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authorJonas Gorski <jogo@openwrt.org>2011-07-25 19:52:47 +0000
committerJonas Gorski <jogo@openwrt.org>2011-07-25 19:52:47 +0000
commit4e6c93bef183e292a1fb83ba1983cba7b3bf1772 (patch)
treecbc580a05433c08ebd4981a65f3d343ef72ef6f8
parentb857433bcb1597f99dfe728c83e6b5e647c406f5 (diff)
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bcm63xx: Fix SPI commands and register offsets for BCM6348
In 240-spi.patch, spi registers for bcm6348 were all messed up. This patch fixes that. It also fixes some spi commands for all bcm63xx. Signed-off-by: Anthony Blakemore <stokie-ant@raverbaby.co.uk> SVN-Revision: 27774
-rw-r--r--target/linux/brcm63xx/patches-2.6.39/240-spi.patch30
-rw-r--r--target/linux/brcm63xx/patches-3.0/240-spi.patch30
2 files changed, 30 insertions, 30 deletions
diff --git a/target/linux/brcm63xx/patches-2.6.39/240-spi.patch b/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
index 848b2f6dc7..437d906388 100644
--- a/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
+++ b/target/linux/brcm63xx/patches-2.6.39/240-spi.patch
@@ -195,17 +195,17 @@
+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
+
+/* BCM 6348 SPI core */
-+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00
-+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
-+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
-+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
-+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
-+#define SPI_BCM_6348_SPI_ST 0x06
-+#define SPI_BCM_6348_SPI_INT_MASK 0x07
-+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
-+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
-+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
-+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
++#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
++#define SPI_BCM_6348_SPI_INT_STATUS 0x02
++#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
++#define SPI_BCM_6348_SPI_INT_MASK 0x04
++#define SPI_BCM_6348_SPI_ST 0x05
++#define SPI_BCM_6348_SPI_CLK_CFG 0x06
++#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
++#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
++#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
++#define SPI_BCM_6348_SPI_MSG_CTL 0x40
++#define SPI_BCM_6348_SPI_MSG_DATA 0x41
+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
+#define SPI_BCM_6348_SPI_RX_DATA 0x80
+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
@@ -244,10 +244,10 @@
+#define SPI_MSG_TYPE_SHIFT 14
+
+/* Command */
-+#define SPI_CMD_NOOP 0x01
-+#define SPI_CMD_SOFT_RESET 0x02
-+#define SPI_CMD_HARD_RESET 0x04
-+#define SPI_CMD_START_IMMEDIATE 0x08
++#define SPI_CMD_NOOP 0x00
++#define SPI_CMD_SOFT_RESET 0x01
++#define SPI_CMD_HARD_RESET 0x02
++#define SPI_CMD_START_IMMEDIATE 0x03
+#define SPI_CMD_COMMAND_SHIFT 0
+#define SPI_CMD_COMMAND_MASK 0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT 4
diff --git a/target/linux/brcm63xx/patches-3.0/240-spi.patch b/target/linux/brcm63xx/patches-3.0/240-spi.patch
index 6de3f3cb0d..5e3f1f51c0 100644
--- a/target/linux/brcm63xx/patches-3.0/240-spi.patch
+++ b/target/linux/brcm63xx/patches-3.0/240-spi.patch
@@ -195,17 +195,17 @@
+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
+
+/* BCM 6348 SPI core */
-+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x00
-+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
-+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
-+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
-+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
-+#define SPI_BCM_6348_SPI_ST 0x06
-+#define SPI_BCM_6348_SPI_INT_MASK 0x07
-+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
-+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
-+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
-+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
++#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
++#define SPI_BCM_6348_SPI_INT_STATUS 0x02
++#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
++#define SPI_BCM_6348_SPI_INT_MASK 0x04
++#define SPI_BCM_6348_SPI_ST 0x05
++#define SPI_BCM_6348_SPI_CLK_CFG 0x06
++#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
++#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
++#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
++#define SPI_BCM_6348_SPI_MSG_CTL 0x40
++#define SPI_BCM_6348_SPI_MSG_DATA 0x41
+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
+#define SPI_BCM_6348_SPI_RX_DATA 0x80
+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
@@ -244,10 +244,10 @@
+#define SPI_MSG_TYPE_SHIFT 14
+
+/* Command */
-+#define SPI_CMD_NOOP 0x01
-+#define SPI_CMD_SOFT_RESET 0x02
-+#define SPI_CMD_HARD_RESET 0x04
-+#define SPI_CMD_START_IMMEDIATE 0x08
++#define SPI_CMD_NOOP 0x00
++#define SPI_CMD_SOFT_RESET 0x01
++#define SPI_CMD_HARD_RESET 0x02
++#define SPI_CMD_START_IMMEDIATE 0x03
+#define SPI_CMD_COMMAND_SHIFT 0
+#define SPI_CMD_COMMAND_MASK 0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT 4