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| author | Lucian Cristian <lucian.cristian@gmail.com> | 2018-06-04 02:09:15 +0300 |
|---|---|---|
| committer | John Crispin <john@phrozen.org> | 2018-06-07 09:38:52 +0200 |
| commit | a0a616e1b8d8f3a0cfe1b91b29eef5a8326769f7 (patch) | |
| tree | bc2109f97a1c49989575c43154f36795f28ad0e0 | |
| parent | e36f8b3f3980903d5cefc51fe274c19c7a0719f2 (diff) | |
| download | upstream-a0a616e1b8d8f3a0cfe1b91b29eef5a8326769f7.tar.gz upstream-a0a616e1b8d8f3a0cfe1b91b29eef5a8326769f7.tar.bz2 upstream-a0a616e1b8d8f3a0cfe1b91b29eef5a8326769f7.zip | |
ath79: fix qca956x SoC boot
based on old ar71xx irq.c driver
Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
| -rw-r--r-- | target/linux/ath79/patches-4.14/0035-MIPS-ath79-fix-QCA956x-boot.patch | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-4.14/0035-MIPS-ath79-fix-QCA956x-boot.patch b/target/linux/ath79/patches-4.14/0035-MIPS-ath79-fix-QCA956x-boot.patch new file mode 100644 index 0000000000..e5b714c442 --- /dev/null +++ b/target/linux/ath79/patches-4.14/0035-MIPS-ath79-fix-QCA956x-boot.patch @@ -0,0 +1,17 @@ +--- a/arch/mips/ath79/clock.c 2018-06-01 13:56:30.376729328 +0300 ++++ b/arch/mips/ath79/clock.c 2018-06-04 02:06:57.039616840 +0300 +@@ -525,6 +525,14 @@ + u32 cpu_pll, ddr_pll; + u32 bootstrap; + ++ /* QCA956x timer init workaround has to be applied right before setting ++ * up the clock. Else, there will be no jiffies */ ++ u32 misc; ++ ++ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); ++ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; ++ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); ++ + bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); + if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) + ref_rate = 40 * 1000 * 1000; |