ipq806x: drop ipq40xx support

Signed-off-by: John Crispin <john@phrozen.org>

48 files changed, 3 insertions, 15076 deletions

diff --git a/target/linux/ipq806x/base-files/etc/board.d/01_leds b/target/linux/ipq806x/base-files/etc/board.d/01_leds
index ea8b7817cb..98aac707d5 100755
--- a/target/linux/ipq806x/base-files/etc/board.d/01_leds
+++ b/target/linux/ipq806x/base-files/etc/board.d/01_leds
@@ -11,14 +11,6 @@ board=$(board_name)
 boardname="${board##*,}"
 
 case "$board" in
-avm,fritzbox-4040)
-	ucidef_set_led_wlan "wlan" "WLAN" "fritz4040:green:wlan" "phy0tpt" "phy1tpt"
-	ucidef_set_led_netdev "wan" "WAN" "fritz4040:green:wan" "eth1"
-	ucidef_set_led_switch "lan" "LAN" "fritz4040:green:lan" "switch0" "0x1e"
-	;;
-glinet,gl-b1300)
-	ucidef_set_led_wlan "wlan" "WLAN" "${boardname}:green:wlan" "phy0tpt"
-	;;
 netgear,d7800 |\
 netgear,r7500 |\
 netgear,r7500v2 |\
diff --git a/target/linux/ipq806x/base-files/etc/board.d/02_network b/target/linux/ipq806x/base-files/etc/board.d/02_network
index 74223e5b47..e279cdd8f6 100755
--- a/target/linux/ipq806x/base-files/etc/board.d/02_network
+++ b/target/linux/ipq806x/base-files/etc/board.d/02_network
@@ -12,11 +12,6 @@ board_config_update
 board=$(board_name)
 
 case "$board" in
-avm,fritzbox-4040)
-	ucidef_set_interfaces_lan_wan "eth0" "eth1"
-	ucidef_add_switch "switch0" \
-		"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
-	;;
 linksys,ea8500)
 	hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
 	ucidef_add_switch "switch0" \
@@ -33,10 +28,6 @@ tplink,vr2600v)
 	ucidef_add_switch "switch0" \
 		"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
 	;;
-glinet,gl-b1300 |\
-openmesh,a42)
-	ucidef_set_interfaces_lan_wan "eth1" "eth0"
-	;;
 qcom,ipq8064-db149)
 	ucidef_set_interface_lan "eth1 eth2 eth3"
 	ucidef_add_switch "switch0" \
diff --git a/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
index fa8eb11857..ed99bd5ea8 100644
--- a/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
+++ b/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
@@ -45,35 +45,6 @@ board=$(board_name)
 
 
 case "$FIRMWARE" in
-"ath10k/pre-cal-ahb-a000000.wifi.bin")
-	case "$board" in
-	avm,fritzbox-4040)
-		/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
-		;;
-	openmesh,a42)
-		ath10kcal_extract "0:ART" 4096 12064
-		;;
-	glinet,gl-b1300 |\
-	qcom,ap-dk01.1-c1)
-		ath10kcal_extract "ART" 4096 12064
-		;;
-	esac
-	;;
-"ath10k/pre-cal-ahb-a800000.wifi.bin")
-	case "$board" in
-	avm,fritzbox-4040)
-		/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev "urlader_config")
-		;;
-	openmesh,a42)
-		ath10kcal_extract "0:ART" 20480 12064
-		;;
-	glinet,gl-b1300 |\
-	qcom,ap-dk01.1-c1)
-		ath10kcal_extract "ART" 20480 12064
-		;;
-	esac
-	;;
-
 "ath10k/pre-cal-pci-0000:01:00.0.bin")
 	case $board in
 	linksys,ea8500)
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh b/target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh
deleted file mode 100644
index a2c79d9e44..0000000000
--- a/target/linux/ipq806x/base-files/lib/upgrade/openmesh.sh
+++ /dev/null
@@ -1,110 +0,0 @@
-# The U-Boot loader of the OpenMesh devices requires image sizes and
-# checksums to be provided in the U-Boot environment.
-# The OpenMesh devices come with 2 main partitions - while one is active
-# sysupgrade will flash the other. The boot order is changed to boot the
-# newly flashed partition. If the new partition can't be booted due to
-# upgrade failures the previously used partition is loaded.
-
-platform_do_upgrade_openmesh() {
-	local tar_file="$1"
-	local restore_backup
-	local primary_kernel_mtd
-
-	local setenv_script="/tmp/fw_env_upgrade"
-
-	local kernel_mtd="$(find_mtd_index $PART_NAME)"
-	local kernel_offset="$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)"
-	local total_size="$(cat /sys/class/mtd/mtd${kernel_mtd}/size)"
-
-	# detect to which flash region the new image is written to.
-	#
-	# 1. check what is the mtd index for the first flash region on this
-	#    device
-	# 2. check if the target partition ("inactive") has the mtd index of
-	#    the first flash region
-	#
-	#    - when it is: the new bootseq will be 1,2 and the first region is
-	#      modified
-	#    - when it isnt: bootseq will be 2,1 and the second region is
-	#      modified
-	#
-	# The detection has to be done via the hardcoded mtd partition because
-	# the current boot might be done with the fallback region. Let us
-	# assume that the current bootseq is 1,2. The bootloader detected that
-	# the image in flash region 1 is corrupt and thus switches to flash
-	# region 2. The bootseq in the u-boot-env is now still the same and
-	# the sysupgrade code can now only rely on the actual mtd indexes and
-	# not the bootseq variable to detect the currently booted flash
-	# region/image.
-	#
-	# In the above example, an implementation which uses bootseq ("1,2") to
-	# detect the currently booted image would assume that region 1 is booted
-	# and then overwrite the variables for the wrong flash region (aka the
-	# one which isn't modified). This could result in a device which doesn't
-	# boot anymore to Linux until it was reflashed with ap51-flash.
-	local next_boot_part="1"
-	case "$(board_name)" in
-	openmesh,a42)
-		primary_kernel_mtd=8
-		;;
-	*)
-		echo "failed to detect primary kernel mtd partition for board"
-		return 1
-		;;
-	esac
-	[ "$kernel_mtd" = "$primary_kernel_mtd" ] || next_boot_part="2"
-
-	local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
-	board_dir=${board_dir%/}
-
-	local kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)
-	local rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
-	# rootfs without EOF marker
-	rootfs_length=$((rootfs_length-4))
-
-	local kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5="${kernel_md5%% *}"
-	# md5 checksum of rootfs with EOF marker
-	local rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5="${rootfs_md5%% *}"
-
-	#
-	# add tar support to get_image() to use default_do_upgrade() instead?
-	#
-
-	# take care of restoring a saved config
-	[ "$SAVE_CONFIG" -eq 1 ] && restore_backup="${MTD_CONFIG_ARGS} -j ${CONF_TAR}"
-
-	# write concatinated kernel + rootfs to flash
-	tar xf $tar_file ${board_dir}/kernel ${board_dir}/root -O | \
-		mtd $restore_backup write - $PART_NAME
-
-	# prepare new u-boot env
-	if [ "$next_boot_part" = "1" ]; then
-		echo "bootseq 1,2" > $setenv_script
-	else
-		echo "bootseq 2,1" > $setenv_script
-	fi
-
-	printf "kernel_size_%i 0x%08x\n" $next_boot_part $kernel_length >> $setenv_script
-	printf "vmlinux_start_addr 0x%08x\n" ${kernel_offset} >> $setenv_script
-	printf "vmlinux_size 0x%08x\n" ${kernel_length} >> $setenv_script
-	printf "vmlinux_checksum %s\n" ${kernel_md5} >> $setenv_script
-
-	printf "rootfs_size_%i 0x%08x\n" $next_boot_part $((total_size-kernel_length)) >> $setenv_script
-	printf "rootfs_start_addr 0x%08x\n" $((kernel_offset+kernel_length)) >> $setenv_script
-	printf "rootfs_size 0x%08x\n" ${rootfs_length} >> $setenv_script
-	printf "rootfs_checksum %s\n" ${rootfs_md5} >> $setenv_script
-
-	# store u-boot env changes
-	fw_setenv -s $setenv_script || {
-		echo "failed to update U-Boot environment"
-		return 1
-	}
-}
-
-# create /var/lock for the lock "fw_setenv.lock" of fw_setenv
-# the rest is copied using ipq806x's RAMFS_COPY_BIN and RAMFS_COPY_DATA
-platform_add_ramfs_ubootenv()
-{
-        mkdir -p $RAM_ROOT/var/lock
-}
-append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv
diff --git a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
index 5561dd538c..c0deeda889 100644
--- a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
+++ b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh
@@ -17,15 +17,10 @@ platform_do_upgrade() {
 	netgear,r7500 |\
 	netgear,r7500v2 |\
 	netgear,r7800 |\
-	qcom,ap-dk04.1-c1 |\
 	qcom,ipq8064-ap148 |\
 	zyxel,nbg6817)
 		nand_do_upgrade "$ARGV"
 		;;
-	openmesh,a42)
-		PART_NAME="inactive"
-		platform_do_upgrade_openmesh "$ARGV"
-		;;
 	tplink,c2600)
 		PART_NAME="os-image:rootfs"
 		MTD_CONFIG_ARGS="-s 0x200000"
diff --git a/target/linux/ipq806x/config-4.9 b/target/linux/ipq806x/config-4.9
index a71b1b819b..6bc3daf277 100644
--- a/target/linux/ipq806x/config-4.9
+++ b/target/linux/ipq806x/config-4.9
@@ -2,7 +2,6 @@ CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_AMBA_PL08X is not set
 CONFIG_APQ_GCC_8084=y
 CONFIG_APQ_MMCC_8084=y
-CONFIG_AR40XX_PHY=y
 CONFIG_AR8216_PHY=y
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
 CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
@@ -11,7 +10,6 @@ CONFIG_ARCH_HAS_SG_CHAIN=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IPQ40XX=y
 # CONFIG_ARCH_MDM9615 is not set
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MSM8960=y
@@ -60,7 +58,6 @@ CONFIG_ARM_THUMB=y
 # CONFIG_ARM_THUMBEE is not set
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
 # CONFIG_BINFMT_FLAT is not set
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_MQ_PCI=y
@@ -164,7 +161,6 @@ CONFIG_DYNAMIC_DEBUG=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
-CONFIG_ESSEDMA=y
 CONFIG_ETHERNET_PACKET_MANGLE=y
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
@@ -190,8 +186,6 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
@@ -257,7 +251,7 @@ CONFIG_IOMMU_HELPER=y
 # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
 # CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
 CONFIG_IOMMU_SUPPORT=y
-CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_4019 is not set
 CONFIG_IPQ_GCC_806X=y
 # CONFIG_IPQ_LCC_806X is not set
 CONFIG_IRQCHIP=y
@@ -277,7 +271,6 @@ CONFIG_LZO_DECOMPRESS=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_BOARDINFO=y
 CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ40XX=y
 # CONFIG_MDM_GCC_9615 is not set
 # CONFIG_MDM_LCC_9615 is not set
 # CONFIG_MFD_MAX77620 is not set
@@ -378,7 +371,7 @@ CONFIG_PHY_QCOM_IPQ806X_SATA=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_APQ8064=y
 # CONFIG_PINCTRL_APQ8084 is not set
-CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ4019 is not set
 CONFIG_PINCTRL_IPQ8064=y
 # CONFIG_PINCTRL_MDM9615 is not set
 CONFIG_PINCTRL_MSM=y
@@ -444,7 +437,6 @@ CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 # CONFIG_SCHED_INFO is not set
 # CONFIG_SCSI_DMA is not set
 CONFIG_SERIAL_8250_FSL=y
-# CONFIG_SERIAL_AMBA_PL010 is not set
 # CONFIG_SERIAL_AMBA_PL011 is not set
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
@@ -483,7 +475,6 @@ CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_USB=y
 CONFIG_USB_COMMON=y
 # CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_IPQ4019_PHY=y
 CONFIG_USB_SUPPORT=y
 # CONFIG_USB_UHCI_HCD is not set
 CONFIG_USE_OF=y
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-a42.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-a42.dts
deleted file mode 100644
index 887be993e8..0000000000
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-a42.dts
+++ /dev/null
@@ -1,244 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include "qcom-ipq4019-bus.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "OpenMesh A42";
-	compatible = "openmesh,a42", "qcom,ipq4019";
-
-	reserved-memory {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		ranges;
-
-		rsvd1@87000000 {
-			reg = <0x87000000 0x500000>;
-			no-map;
-		};
-
-		wifi_dump@87500000 {
-			reg = <0x87500000 0x600000>;
-			no-map;
-		};
-
-		rsvd2@87B00000 {
-			reg = <0x87b00000 0x500000>;
-			no-map;
-		};
-	};
-
-	soc {
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "ok";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		pinctrl@1000000 {
-			serial_pins: serial_pinmux {
-				mux {
-					pins = "gpio60", "gpio61";
-					function = "blsp_uart0";
-					bias-disable;
-				};
-			};
-
-			spi_0_pins: spi_0_pinmux {
-				pinmux {
-					function = "blsp_spi0";
-					pins = "gpio55", "gpio56", "gpio57";
-				};
-				pinmux_cs {
-					function = "gpio";
-					pins = "gpio54";
-				};
-				pinconf {
-					pins = "gpio55", "gpio56", "gpio57";
-					drive-strength = <12>;
-					bias-disable;
-				};
-				pinconf_cs {
-					pins = "gpio54";
-					drive-strength = <2>;
-					bias-disable;
-					output-high;
-				};
-			};
-		};
-
-		blsp_dma: dma@7884000 {
-			status = "ok";
-		};
-
-		spi_0: spi@78b5000 {
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-			cs-gpios = <&tlmm 54 0>;
-
-			m25p80@0 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <24000000>;
-
-				/* partitions are passed via bootloader */
-			};
-		};
-
-		serial@78af000 {
-			pinctrl-0 = <&serial_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-		};
-
-		cryptobam: dma@8e04000 {
-			status = "ok";
-		};
-
-		crypto@8e3a000 {
-			status = "ok";
-		};
-
-		watchdog@b017000 {
-			status = "ok";
-		};
-
-		usb2_hs_phy: hsphy@a8000 {
-			status = "ok";
-		};
-
-		usb2: usb2@60f8800 {
-			status = "ok";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		ess-switch@c000000 {
-			status = "okay";
-		};
-
-		ess-psgmii@98000 {
-			status = "okay";
-		};
-
-		edma@c080000 {
-			status = "okay";
-		};
-
-		wifi@a000000 {
-			status = "okay";
-			qcom,ath10k-calibration-variant = "OM-A42";
-		};
-
-		wifi@a800000 {
-			status = "okay";
-			qcom,ath10k-calibration-variant = "OM-A42";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		reset {
-			label = "reset";
-			gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &power;
-		led-running = &power;
-		led-upgrade = &power;
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		red {
-			label = "a42:red:status";
-			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "default-off";
-		};
-
-		power: green {
-			label = "a42:green:status";
-			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		blue {
-			label = "a42:blue:status";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "default-off";
-		};
-	};
-
-	watchdog {
-		compatible = "linux,wdt-gpio";
-		gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-		hw_algo = "toggle";
-		/* hw_margin_ms is actually 300s but driver limits it to 60s */
-		hw_margin_ms = <60000>;
-		always-running;
-	};
-};
-
-&gmac0 {
-	qcom,phy_mdio_addr = <4>;
-	qcom,poll_required = <1>;
-	qcom,forced_speed = <1000>;
-	qcom,forced_duplex = <1>;
-	vlan_tag = <2 0x20>;
-};
-
-&gmac1 {
-	qcom,phy_mdio_addr = <3>;
-	qcom,poll_required = <1>;
-	qcom,forced_speed = <1000>;
-	qcom,forced_duplex = <1>;
-	vlan_tag = <1 0x10>;
-};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi
deleted file mode 100644
index 169505973f..0000000000
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-bus.dtsi
+++ /dev/null
@@ -1,1142 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include <dt-bindings/msm/msm-bus-ids.h>
-
-/ {
-
-soc {
-	ad_hoc_bus: ad-hoc-bus {
-		compatible = "qcom,msm-bus-device";
-		reg = <0x580000 0x14000>,
-			<0x500000 0x11000>;
-		reg-names = "snoc-base", "pcnoc-base";
-
-		/*Buses*/
-
-		fab_pcnoc: fab-pcnoc {
-			cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
-			label = "fab-pcnoc";
-			qcom,fab-dev;
-			qcom,base-name = "pcnoc-base";
-			qcom,bypass-qos-prg;
-			qcom,bus-type = <1>;
-			qcom,qos-off = <0x1000>;
-			qcom,base-offset = <0x0>;
-			clocks = <>;
-		};
-
-		fab_snoc: fab-snoc {
-			cell-id = <MSM_BUS_FAB_SYS_NOC>;
-			label = "fab-snoc";
-			qcom,fab-dev;
-			qcom,base-name = "snoc-base";
-			qcom,bypass-qos-prg;
-			qcom,bus-type = <1>;
-			qcom,qos-off = <0x80>;
-			qcom,base-offset = <0x0>;
-			clocks = <>;
-		};
-
-		/*Masters*/
-
-		mas_blsp_bam: mas-blsp-bam {
-			cell-id = <MSM_BUS_MASTER_BLSP_BAM>;
-			label = "mas-blsp-bam";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_0>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_BLSP_BAM>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_usb2_bam: mas-usb2-bam {
-			cell-id = <MSM_BUS_MASTER_USB2_BAM>;
-			label = "mas-usb2-bam";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <15>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&slv_pcnoc_snoc>;
-			qcom,prio1 = <1>;
-			qcom,prio0 = <1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_USB2_BAM>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_adss_dma0: mas-adss-dma0 {
-			cell-id = <MSM_BUS_MASTER_ADDS_DMA0>;
-			label = "mas-adss-dma0";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA0>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_adss_dma1: mas-adss-dma1 {
-			cell-id = <MSM_BUS_MASTER_ADDS_DMA1>;
-			label = "mas-adss-dma1";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA1>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_adss_dma2: mas-adss-dma2 {
-			cell-id = <MSM_BUS_MASTER_ADDS_DMA2>;
-			label = "mas-adss-dma2";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA2>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_adss_dma3: mas-adss-dma3 {
-			cell-id = <MSM_BUS_MASTER_ADDS_DMA3>;
-			label = "mas-adss-dma3";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_ADSS_DMA3>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_qpic_bam: mas-qpic-bam {
-			cell-id = <MSM_BUS_MASTER_QPIC_BAM>;
-			label = "mas-qpic-bam";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_0>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_QPIC_BAM>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_spdm: mas-spdm {
-			cell-id = <MSM_BUS_MASTER_SPDM>;
-			label = "mas-spdm";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_m_0>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_SPDM>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_pcnoc_cfg: mas-pcnoc-cfg {
-			cell-id = <MSM_BUS_MASTER_PNOC_CFG>;
-			label = "mas-pcnoc-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&slv_srvc_pcnoc>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_CFG>;
-		};
-
-		mas_tic: mas-tic {
-			cell-id = <MSM_BUS_MASTER_TIC>;
-			label = "mas-tic";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_TIC>;
-		};
-
-		mas_sdcc_bam: mas-sdcc-bam {
-			cell-id = <MSM_BUS_MASTER_SDCC_BAM>;
-			label = "mas-sdcc-bam";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <14>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&slv_pcnoc_snoc>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_SDCC_BAM>;
-			qcom,blacklist = <&slv_tcsr &slv_mdio &slv_adss_cfg
-				 &slv_fephy_cfg &slv_wss1_apu_cfg &slv_ddrc_mpu1_cfg
-				 &slv_ddrc_mpu0_cfg &slv_qpic_cfg &slv_ddrc_cfg
-				 &slv_pcnoc_cfg &slv_ess_apu_cfg &slv_imem_cfg
-				 &slv_srif &slv_prng &slv_qdss_cfg
-				 &slv_wss0_apu_cfg &slv_ddrc_apu_cfg &slv_gcnt
-				 &slv_tlmm &slv_wss0_vmidmt_cfg &slv_prng_apu_cfg
-				 &slv_boot_rom &slv_security &slv_spdm
-				 &slv_pcnoc_mpu_cfg &slv_ddrc_mpu2_cfg &slv_ess_vmidmt_cfg
-				 &slv_qhss_apu_cfg &slv_adss_vmidmt_cfg &slv_clk_ctl
-				 &slv_adss_apu &slv_blsp_cfg &slv_usb2_cfg
-				 &slv_srvc_pcnoc &slv_snoc_mpu_cfg &slv_wss1_vmidmt_cfg
-				 &slv_sdcc_cfg &slv_snoc_cfg>;
-		};
-
-		mas_snoc_pcnoc: mas-snoc-pcnoc {
-			cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
-			label = "mas-snoc-pcnoc";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <16>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&pcnoc_int_0>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>;
-		};
-
-		mas_qdss_dap: mas-qdss-dap {
-			cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
-			label = "mas-qdss-dap";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&pcnoc_int_0 &slv_pcnoc_snoc>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
-		};
-
-		mas_ddrc_snoc: mas-ddrc-snoc {
-			cell-id = <MSM_BUS_MASTER_DDRC_SNOC>;
-			label = "mas-ddrc-snoc";
-			qcom,buswidth = <16>;
-			qcom,ap-owned;
-			qcom,connections = <&snoc_int_0 &snoc_int_1
-				 &slv_pcie>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_DDRC_SNOC>;
-			qcom,blacklist = <&slv_snoc_ddrc_m1 &slv_srvc_snoc>;
-		};
-
-		mas_wss_0: mas-wss-0 {
-			cell-id = <MSM_BUS_MASTER_WSS_0>;
-			label = "mas-wss-0";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <26>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_WSS_0>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
-				 &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
-				 &slv_srvc_snoc>;
-		};
-
-		mas_wss_1: mas-wss-1 {
-			cell-id = <MSM_BUS_MASTER_WSS_1>;
-			label = "mas-wss-1";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <27>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_WSS_1>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
-				 &slv_wss1_cfg &slv_wss0_cfg &slv_crypto_cfg
-				 &slv_srvc_snoc>;
-		};
-
-		mas_crypto: mas-crypto {
-			cell-id = <MSM_BUS_MASTER_CRYPTO>;
-			label = "mas-crypto";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <5>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &snoc_int_1
-				 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-				 &slv_pcie &slv_qdss_stm &slv_crypto_cfg
-				 &slv_srvc_snoc>;
-		};
-
-		mas_ess: mas-ess {
-			cell-id = <MSM_BUS_MASTER_ESS>;
-			label = "mas-ess";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <44>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_ESS>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-				 &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-				 &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-		};
-
-		mas_pcie: mas-pcie {
-			cell-id = <MSM_BUS_MASTER_PCIE>;
-			label = "mas-pcie";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <6>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCIE>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_pcie
-				 &slv_qdss_stm &slv_wss1_cfg &slv_wss0_cfg
-				 &slv_crypto_cfg &slv_srvc_snoc>;
-		};
-
-		mas_usb3: mas-usb3 {
-			cell-id = <MSM_BUS_MASTER_USB3>;
-			label = "mas-usb3";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <7>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-				 &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-				 &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-		};
-
-		mas_qdss_etr: mas-qdss-etr {
-			cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
-			label = "mas-qdss-etr";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,qport = <544>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&qdss_int>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-				 &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-				 &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-		};
-
-		mas_qdss_bamndp: mas-qdss-bamndp {
-			cell-id = <MSM_BUS_MASTER_QDSS_BAMNDP>;
-			label = "mas-qdss-bamndp";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <576>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&qdss_int>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAMNDP>;
-			qcom,blacklist = <&slv_usb3_cfg &slv_ess_cfg &slv_a7ss
-				 &slv_pcie &slv_qdss_stm &slv_wss1_cfg
-				 &slv_wss0_cfg &slv_crypto_cfg &slv_srvc_snoc>;
-		};
-
-		mas_pcnoc_snoc: mas-pcnoc-snoc {
-			cell-id = <MSM_BUS_PNOC_SNOC_MAS>;
-			label = "mas-pcnoc-snoc";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <384>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&snoc_int_0 &snoc_int_1
-				 &slv_snoc_ddrc_m1>;
-			qcom,prio1 = <0>;
-			qcom,prio0 = <0>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>;
-			qcom,blacklist = <&slv_srvc_snoc>;
-		};
-
-		mas_snoc_cfg: mas-snoc-cfg {
-			cell-id = <MSM_BUS_MASTER_QDSS_SNOC_CFG>;
-			label = "mas-snoc-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&slv_srvc_snoc>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_SNOC_CFG>;
-		};
-
-		/*Internal nodes*/
-
-
-		pcnoc_m_0: pcnoc-m-0 {
-			cell-id = <MSM_BUS_PNOC_M_0>;
-			label = "pcnoc-m-0";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <12>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&slv_pcnoc_snoc>;
-			qcom,prio1 = <1>;
-			qcom,prio0 = <1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
-		};
-
-		pcnoc_m_1: pcnoc-m-1 {
-			cell-id = <MSM_BUS_PNOC_M_1>;
-			label = "pcnoc-m-1";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,qport = <13>;
-			qcom,qos-mode = "fixed";
-			qcom,connections = <&slv_pcnoc_snoc>;
-			qcom,prio1 = <1>;
-			qcom,prio0 = <1>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
-		};
-
-		pcnoc_int_0: pcnoc-int-0 {
-			cell-id = <MSM_BUS_PNOC_INT_0>;
-			label = "pcnoc-int-0";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,connections = < &pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0
-				 &pcnoc_s_4 &pcnoc_s_5
-				 &pcnoc_s_6 &pcnoc_s_7
-				 &pcnoc_s_8 &pcnoc_s_9
-				 &pcnoc_s_3>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
-		};
-
-		pcnoc_s_0: pcnoc-s-0 {
-			cell-id = <MSM_BUS_PNOC_SLV_0>;
-			label = "pcnoc-s-0";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&slv_clk_ctl &slv_tcsr &slv_security
-				 &slv_tlmm>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
-		};
-
-		pcnoc_s_1: pcnoc-s-1 {
-			cell-id = <MSM_BUS_PNOC_SLV_1>;
-			label = "pcnoc-s-1";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_prng_apu_cfg &slv_prng&slv_imem_cfg>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
-		};
-
-		pcnoc_s_2: pcnoc-s-2 {
-			cell-id = <MSM_BUS_PNOC_SLV_2>;
-			label = "pcnoc-s-2";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_spdm &slv_pcnoc_mpu_cfg &slv_pcnoc_cfg
-				&slv_boot_rom>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
-		};
-
-		pcnoc_s_3: pcnoc-s-3 {
-			cell-id = <MSM_BUS_PNOC_SLV_3>;
-			label = "pcnoc-s-3";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_qdss_cfg&slv_gcnt &slv_snoc_cfg
-				 &slv_snoc_mpu_cfg>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
-		};
-
-		pcnoc_s_4: pcnoc-s-4 {
-			cell-id = <MSM_BUS_PNOC_SLV_4>;
-			label = "pcnoc-s-4";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&slv_adss_cfg &slv_adss_vmidmt_cfg &slv_adss_apu>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
-		};
-
-		pcnoc_s_5: pcnoc-s-5 {
-			cell-id = <MSM_BUS_PNOC_SLV_5>;
-			label = "pcnoc-s-5";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = <&slv_qhss_apu_cfg &slv_fephy_cfg &slv_mdio
-				 &slv_srif>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>;
-		};
-
-		pcnoc_s_6: pcnoc-s-6 {
-			cell-id = <MSM_BUS_PNOC_SLV_6>;
-			label = "pcnoc-s-6";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_ddrc_mpu0_cfg &slv_ddrc_apu_cfg &slv_ddrc_mpu2_cfg
-				&slv_ddrc_cfg &slv_ddrc_mpu1_cfg>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>;
-		};
-
-		pcnoc_s_7: pcnoc-s-7 {
-			cell-id = <MSM_BUS_PNOC_SLV_7>;
-			label = "pcnoc-s-7";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_ess_apu_cfg &slv_usb2_cfg&slv_ess_vmidmt_cfg>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>;
-		};
-
-		pcnoc_s_8: pcnoc-s-8 {
-			cell-id = <MSM_BUS_PNOC_SLV_8>;
-			label = "pcnoc-s-8";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_sdcc_cfg &slv_qpic_cfg&slv_blsp_cfg>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>;
-		};
-
-		pcnoc_s_9: pcnoc-s-9 {
-			cell-id = <MSM_BUS_PNOC_SLV_9>;
-			label = "pcnoc-s-9";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_wss1_apu_cfg &slv_wss1_vmidmt_cfg&slv_wss0_vmidmt_cfg
-				 &slv_wss0_apu_cfg>;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_9>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_9>;
-		};
-
-		snoc_int_0: snoc-int-0 {
-			cell-id = <MSM_BUS_SNOC_INT_0>;
-			label = "snoc-int-0";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_ocimem&slv_qdss_stm>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>;
-		};
-
-		snoc_int_1: snoc-int-1 {
-			cell-id = <MSM_BUS_SNOC_INT_1>;
-			label = "snoc-int-1";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,connections = < &slv_crypto_cfg &slv_a7ss &slv_ess_cfg
-				 &slv_usb3_cfg &slv_wss1_cfg
-				&slv_wss0_cfg>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>;
-		};
-
-		qdss_int: qdss-int {
-			cell-id = <MSM_BUS_SNOC_QDSS_INT>;
-			label = "qdss-int";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,connections = <&snoc_int_0 &slv_snoc_ddrc_m1>;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
-		};
-		/*Slaves*/
-
-		slv_clk_ctl:slv-clk-ctl {
-			cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
-			label = "slv-clk-ctl";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
-		};
-
-		slv_security:slv-security {
-			cell-id = <MSM_BUS_SLAVE_SECURITY>;
-			label = "slv-security";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SECURITY>;
-		};
-
-		slv_tcsr:slv-tcsr {
-			cell-id = <MSM_BUS_SLAVE_TCSR>;
-			label = "slv-tcsr";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
-		};
-
-		slv_tlmm:slv-tlmm {
-			cell-id = <MSM_BUS_SLAVE_TLMM>;
-			label = "slv-tlmm";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
-		};
-
-		slv_imem_cfg:slv-imem-cfg {
-			cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
-			label = "slv-imem-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
-		};
-
-		slv_prng:slv-prng {
-			cell-id = <MSM_BUS_SLAVE_PRNG>;
-			label = "slv-prng";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
-		};
-
-		slv_prng_apu_cfg:slv-prng-apu-cfg {
-			cell-id = <MSM_BUS_SLAVE_PRNG_APU_CFG>;
-			label = "slv-prng-apu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PRNG_APU_CFG>;
-		};
-
-		slv_boot_rom:slv-boot-rom {
-			cell-id = <MSM_BUS_SLAVE_BOOT_ROM>;
-			label = "slv-boot-rom";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_BOOT_ROM>;
-		};
-
-		slv_spdm:slv-spdm {
-			cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
-			label = "slv-spdm";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
-		};
-
-		slv_pcnoc_cfg:slv-pcnoc-cfg {
-			cell-id = <MSM_BUS_SLAVE_PNOC_CFG>;
-			label = "slv-pcnoc-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PNOC_CFG>;
-		};
-
-		slv_pcnoc_mpu_cfg:slv-pcnoc-mpu-cfg {
-			cell-id = <MSM_BUS_SLAVE_PERIPH_MPU_CFG>;
-			label = "slv-pcnoc-mpu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PERIPH_MPU_CFG>;
-		};
-
-		slv_gcnt:slv-gcnt {
-			cell-id = <MSM_BUS_SLAVE_GCNT>;
-			label = "slv-gcnt";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_GCNT>;
-		};
-
-		slv_qdss_cfg:slv-qdss-cfg {
-			cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
-			label = "slv-qdss-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
-		};
-
-		slv_snoc_cfg:slv-snoc-cfg {
-			cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
-			label = "slv-snoc-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
-		};
-
-		slv_snoc_mpu_cfg:slv-snoc-mpu-cfg {
-			cell-id = <MSM_BUS_SLAVE_SNOC_MPU_CFG>;
-			label = "slv-snoc-mpu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_MPU_CFG>;
-		};
-
-		slv_adss_cfg:slv-adss-cfg {
-			cell-id = <MSM_BUS_SLAVE_ADSS_CFG>;
-			label = "slv-adss-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_CFG>;
-		};
-
-		slv_adss_apu:slv-adss-apu {
-			cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
-			label = "slv-adss-apu";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_APU>;
-		};
-
-		slv_adss_vmidmt_cfg:slv-adss-vmidmt-cfg {
-			cell-id = <MSM_BUS_SLAVE_ADSS_VMIDMT_CFG>;
-			label = "slv-adss-vmidmt-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_ADSS_VMIDMT_CFG>;
-		};
-
-		slv_qhss_apu_cfg:slv-qhss-apu-cfg {
-			cell-id = <MSM_BUS_SLAVE_QHSS_APU_CFG>;
-			label = "slv-qhss-apu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_QHSS_APU_CFG>;
-		};
-
-		slv_mdio:slv-mdio {
-			cell-id = <MSM_BUS_SLAVE_MDIO>;
-			label = "slv-mdio";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_MDIO>;
-		};
-
-		slv_fephy_cfg:slv-fephy-cfg {
-			cell-id = <MSM_BUS_SLAVE_FEPHY_CFG>;
-			label = "slv-fephy-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_FEPHY_CFG>;
-		};
-
-		slv_srif:slv-srif {
-			cell-id = <MSM_BUS_SLAVE_SRIF>;
-			label = "slv-srif";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SRIF>;
-		};
-
-		slv_ddrc_cfg:slv-ddrc-cfg {
-			cell-id = <MSM_BUS_SLAVE_DDRC_CFG>;
-			label = "slv-ddrc-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_CFG>;
-		};
-
-		slv_ddrc_apu_cfg:slv-ddrc-apu-cfg {
-			cell-id = <MSM_BUS_SLAVE_DDRC_APU_CFG>;
-			label = "slv-ddrc-apu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_APU_CFG>;
-		};
-
-		slv_ddrc_mpu0_cfg:slv-ddrc-mpu0-cfg {
-			cell-id = <MSM_BUS_SLAVE_MPU0_CFG>;
-			label = "slv-ddrc-mpu0-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU0_CFG>;
-		};
-
-		slv_ddrc_mpu1_cfg:slv-ddrc-mpu1-cfg {
-			cell-id = <MSM_BUS_SLAVE_MPU1_CFG>;
-			label = "slv-ddrc-mpu1-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU1_CFG>;
-		};
-
-		slv_ddrc_mpu2_cfg:slv-ddrc-mpu2-cfg {
-			cell-id = <MSM_BUS_SLAVE_MPU2_CFG>;
-			label = "slv-ddrc-mpu2-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_DDRC_MPU2_CFG>;
-		};
-
-		slv_ess_vmidmt_cfg:slv-ess-vmidmt-cfg {
-			cell-id = <MSM_BUS_SLAVE_ESS_VMIDMT_CFG>;
-			label = "slv-ess-vmidmt-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_ESS_VMIDMT_CFG>;
-		};
-
-		slv_ess_apu_cfg:slv-ess-apu-cfg {
-			cell-id = <MSM_BUS_SLAVE_ESS_APU_CFG>;
-			label = "slv-ess-apu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_ESS_APU_CFG>;
-		};
-
-		slv_usb2_cfg:slv-usb2-cfg {
-			cell-id = <MSM_BUS_SLAVE_USB2_CFG>;
-			label = "slv-usb2-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_USB2_CFG>;
-		};
-
-		slv_blsp_cfg:slv-blsp-cfg {
-			cell-id = <MSM_BUS_SLAVE_BLSP_CFG>;
-			label = "slv-blsp-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_CFG>;
-		};
-
-		slv_qpic_cfg:slv-qpic-cfg {
-			cell-id = <MSM_BUS_SLAVE_QPIC_CFG>;
-			label = "slv-qpic-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_QPIC_CFG>;
-		};
-
-		slv_sdcc_cfg:slv-sdcc-cfg {
-			cell-id = <MSM_BUS_SLAVE_SDCC_CFG>;
-			label = "slv-sdcc-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_CFG>;
-		};
-
-		slv_wss0_vmidmt_cfg:slv-wss0-vmidmt-cfg {
-			cell-id = <MSM_BUS_SLAVE_WSS0_VMIDMT_CFG>;
-			label = "slv-wss0-vmidmt-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_VMIDMT_CFG>;
-		};
-
-		slv_wss0_apu_cfg:slv-wss0-apu-cfg {
-			cell-id = <MSM_BUS_SLAVE_WSS0_APU_CFG>;
-			label = "slv-wss0-apu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_APU_CFG>;
-		};
-
-		slv_wss1_vmidmt_cfg:slv-wss1-vmidmt-cfg {
-			cell-id = <MSM_BUS_SLAVE_WSS1_VMIDMT_CFG>;
-			label = "slv-wss1-vmidmt-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_VMIDMT_CFG>;
-		};
-
-		slv_wss1_apu_cfg:slv-wss1-apu-cfg {
-			cell-id = <MSM_BUS_SLAVE_WSS1_APU_CFG>;
-			label = "slv-wss1-apu-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_APU_CFG>;
-		};
-
-		slv_pcnoc_snoc:slv-pcnoc-snoc {
-			cell-id = <MSM_BUS_PNOC_SNOC_SLV>;
-			label = "slv-pcnoc-snoc";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>;
-		};
-
-		slv_srvc_pcnoc:slv-srvc-pcnoc {
-			cell-id = <MSM_BUS_SLAVE_SRVC_PCNOC>;
-			label = "slv-srvc-pcnoc";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_pcnoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_PCNOC>;
-		};
-
-		slv_snoc_ddrc_m1:slv-snoc-ddrc-m1 {
-			cell-id = <MSM_BUS_SLAVE_SNOC_DDRC>;
-			label = "slv-snoc-ddrc-m1";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_DDRC>;
-		};
-
-		slv_a7ss:slv-a7ss {
-			cell-id = <MSM_BUS_SLAVE_A7SS>;
-			label = "slv-a7ss";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_A7SS>;
-		};
-
-		slv_ocimem:slv-ocimem {
-			cell-id = <MSM_BUS_SLAVE_OCIMEM>;
-			label = "slv-ocimem";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_OCIMEM>;
-		};
-
-		slv_wss0_cfg:slv-wss0-cfg {
-			cell-id = <MSM_BUS_SLAVE_WSS0_CFG>;
-			label = "slv-wss0-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_WSS0_CFG>;
-		};
-
-		slv_wss1_cfg:slv-wss1-cfg {
-			cell-id = <MSM_BUS_SLAVE_WSS1_CFG>;
-			label = "slv-wss1-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_WSS1_CFG>;
-		};
-
-		slv_pcie:slv-pcie {
-			cell-id = <MSM_BUS_SLAVE_PCIE>;
-			label = "slv-pcie";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE>;
-		};
-
-		slv_usb3_cfg:slv-usb3-cfg {
-			cell-id = <MSM_BUS_SLAVE_USB3_CFG>;
-			label = "slv-usb3-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_USB3_CFG>;
-		};
-
-		slv_crypto_cfg:slv-crypto-cfg {
-			cell-id = <MSM_BUS_SLAVE_CRYPTO_CFG>;
-			label = "slv-crypto-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_CFG>;
-		};
-
-		slv_ess_cfg:slv-ess-cfg {
-			cell-id = <MSM_BUS_SLAVE_ESS_CFG>;
-			label = "slv-ess-cfg";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_ESS_CFG>;
-		};
-
-		slv_qdss_stm:slv-qdss-stm {
-			cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
-			label = "slv-qdss-stm";
-			qcom,buswidth = <4>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
-		};
-
-		slv_srvc_snoc:slv-srvc-snoc {
-			cell-id = <MSM_BUS_SLAVE_SRVC_SNOC>;
-			label = "slv-srvc-snoc";
-			qcom,buswidth = <8>;
-			qcom,ap-owned;
-			qcom,bus-dev = <&fab_snoc>;
-			qcom,slv-rpm-id = <ICBID_SLAVE_SRVC_SNOC>;
-		};
-	};
-};
-
-};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts
deleted file mode 100644
index f5ca3d5c56..0000000000
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-fritz4040.dts
+++ /dev/null
@@ -1,322 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include "qcom-ipq4019-bus.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "AVM FRITZ!Box 4040";
-	compatible = "avm,fritzbox-4040", "qcom,ipq4019";
-
-	aliases {
-		led-boot = &power;
-		led-failsafe = &flash;
-		led-running = &power;
-		led-upgrade = &flash;
-	};
-
-	reserved-memory {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		ranges;
-
-		tz_apps@87b80000 {
-			reg = <0x87b80000 0x280000>;
-			reusable;
-		};
-
-		smem@87e00000 {
-			reg = <0x87e00000 0x080000>;
-			no-map;
-		};
-
-		tz@87e80000 {
-			reg = <0x87e80000 0x180000>;
-			no-map;
-		};
-	};
-
-	soc {
-		mdio@90000 {
-			status = "okay";
-		};
-
-		ess-psgmii@98000 {
-			status = "okay";
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@194b000 {
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		usb2@60f8800 {
-			status = "ok";
-		};
-
-		serial@78af000 {
-			pinctrl-0 = <&serial_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-		};
-
-		usb3@8af8800 {
-			status = "ok";
-		};
-
-		crypto@8e3a000 {
-			status = "ok";
-		};
-
-		wifi@a000000 {
-			status = "okay";
-		};
-
-		wifi@a800000 {
-			status = "okay";
-		};
-
-		watchdog@b017000 {
-			status = "ok";
-		};
-
-		qca8075: ess-switch@c000000 {
-			status = "okay";
-
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			enable-usb-power {
-				gpio-hog;
-				line-name = "enable USB3 power";
-				gpios = <7 GPIO_ACTIVE_HIGH>;
-				output-high;
-			};
-		};
-
-		edma@c080000 {
-			status = "okay";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		wlan {
-			label = "wlan";
-			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RFKILL>;
-		};
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		wlan {
-			label = "fritz4040:green:wlan";
-			gpios = <&qca8075 1 GPIO_ACTIVE_HIGH>;
-		};
-
-		panic: info_red {
-			label = "fritz4040:red:info";
-			gpios = <&qca8075 3 GPIO_ACTIVE_HIGH>;
-			panic-indicator;
-		};
-
-		wan {
-			label = "fritz4040:green:wan";
-			gpios = <&qca8075 5 GPIO_ACTIVE_HIGH>;
-		};
-
-		power: power {
-			label = "fritz4040:green:power";
-			gpios = <&qca8075 11 GPIO_ACTIVE_HIGH>;
-		};
-
-		lan {
-			label = "fritz4040:green:lan";
-			gpios = <&qca8075 13 GPIO_ACTIVE_HIGH>;
-		};
-
-		flash: info_amber {
-			label = "fritz4040:amber:info";
-			gpios = <&qca8075 15 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&tlmm {
-	serial_pins: serial_pinmux {
-		mux {
-			pins = "gpio60", "gpio61";
-			function = "blsp_uart0";
-			bias-disable;
-		};
-	};
-
-	spi_0_pins: spi_0_pinmux {
-		mux {
-			function = "blsp_spi0";
-			pins = "gpio55", "gpio56", "gpio57";
-			drive-strength = <12>;
-			bias-disable;
-		};
-
-		mux_cs {
-			function = "gpio";
-			pins = "gpio54";
-			drive-strength = <2>;
-			bias-disable;
-			output-high;
-		};
-	};
-};
-
-&cryptobam {
-	status = "ok";
-};
-
-&blsp_dma {
-	status = "ok";
-};
-
-&spi_0 { /* BLSP1 QUP1 */
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	status = "ok";
-	cs-gpios = <&tlmm 54 0>;
-
-	mx25l25635f@0 {
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-		status = "ok";
-		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition0@0 {
-				label = "SBL1";
-				reg = <0x00000000 0x00040000>;
-				read-only;
-			};
-			partition1@40000 {
-				label = "MIBIB";
-				reg = <0x00040000 0x00020000>;
-				read-only;
-			};
-			partition2@60000 {
-				label = "QSEE";
-				reg = <0x00060000 0x00060000>;
-				read-only;
-			};
-			partition3@c0000 {
-				label = "CDT";
-				reg = <0x000c0000 0x00010000>;
-				read-only;
-			};
-			partition4@d0000 {
-				label = "DDRPARAMS";
-				reg = <0x000d0000 0x00010000>;
-				read-only;
-			};
-			partition5@e0000 {
-				label = "APPSBLENV"; /* uboot env - empty */
-				reg = <0x000e0000 0x00010000>;
-				read-only;
-			};
-			partition6@f0000 {
-				label = "urlader"; /* APPSBL */
-				reg = <0x000f0000 0x0002dc000>;
-				read-only;
-			};
-			partition7@11dc00 {
-				/* make a backup of this partition! */
-				label = "urlader_config";
-				reg = <0x0011dc00 0x00002400>;
-				read-only;
-			};
-			partition8@120000 {
-				label = "tffs1";
-				reg = <0x00120000 0x00080000>;
-				read-only;
-			};
-			partition9@1a0000 {
-				label = "tffs2";
-				reg = <0x001a0000 0x00080000>;
-				read-only;
-			};
-			partition10@220000 {
-				label = "uboot";
-				reg = <0x00220000 0x00080000>;
-				read-only;
-			};
-			partition11@2A0000 {
-				label = "firmware";
-				reg = <0x002a0000 0x01c60000>;
-			};
-			partition12@1f00000 {
-				label = "jffs2";
-				reg = <0x01f00000 0x00100000>;
-			};
-		};
-	};
-};
-
-&usb3_ss_phy {
-	status = "ok";
-};
-
-&usb3_hs_phy {
-	status = "ok";
-};
-
-&usb2_hs_phy {
-	status = "ok";
-};
diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts
deleted file mode 100644
index 53824e3c8d..0000000000
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq4019-gl-b1300.dts
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-	model = "GL.iNet GL-B1300";
-	compatible = "glinet,gl-b1300", "qcom,ipq4019";
-
-	memory {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <0x1>;
-		#size-cells = <0x1>;
-		ranges;
-
-		apps_bl@87000000 {
-			reg = <0x87000000 0x400000>;
-			no-map;
-		};
-
-		sbl@87400000 {
-			reg = <0x87400000 0x100000>;
-			no-map;
-		};
-
-		cnss_debug@87500000 {
-			reg = <0x87500000 0x600000>;
-			no-map;
-		};
-
-		cpu_context_dump@87b00000 {
-			reg = <0x87b00000 0x080000>;
-			no-map;
-		};
-
-		tz_apps@87b80000 {
-			reg = <0x87b80000 0x280000>;
-			no-map;
-		};
-
-		smem@87e00000 {
-			reg = <0x87e00000 0x080000>;
-			no-map;
-		};
-
-		tz@87e80000 {
-			reg = <0x87e80000 0x180000>;
-			no-map;
-		};
-	};
-
-	soc {
-		tcsr@194b000 {
-			/* select hostmode */
-			compatible = "qcom,tcsr";
-			reg = <0x194b000 0x100>;
-			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-			status = "ok";
-		};
-
-		ess_tcsr@1953000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1953000 0x1000>;
-			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-		};
-
-		tcsr@1949000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1949000 0x100>;
-			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-		};
-
-		tcsr@1957000 {
-			compatible = "qcom,tcsr";
-			reg = <0x1957000 0x100>;
-			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-		};
-
-		pinctrl@1000000 {
-			serial_pins: serial_pinmux {
-				mux {
-					pins = "gpio60", "gpio61";
-					function = "blsp_uart0";
-					bias-disable;
-				};
-			};
-
-			spi_0_pins: spi_0_pinmux {
-				pinmux {
-					function = "blsp_spi0";
-					pins = "gpio55", "gpio56", "gpio57";
-				};
-				pinmux_cs {
-					function = "gpio";
-					pins = "gpio54";
-				};
-				pinconf {
-					pins = "gpio55", "gpio56", "gpio57";
-					drive-strength = <12>;
-					bias-disable;
-				};
-				pinconf_cs {
-					pins = "gpio54";
-					drive-strength = <2>;
-					bias-disable;
-					output-high;
-				};
-			};
-		};
-
-		blsp_dma: dma@7884000 {
-			status = "ok";
-		};
-
-		spi_0: spi@78b5000 {
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-			cs-gpios = <&tlmm 54 0>;
-		};
-
-		serial@78af000 {
-			pinctrl-0 = <&serial_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-		};
-
-		cryptobam: dma@8e04000 {
-			status = "ok";
-		};
-
-		crypto@8e3a000 {
-			status = "ok";
-		};
-
-		watchdog@b017000 {
-			status = "ok";
-		};
-
-		usb3_ss_phy: ssphy@9a000 {
-			status = "ok";
-		};
-
-		usb3_hs_phy: hsphy@a6000 {
-			status = "ok";
-		};
-
-		usb3: usb3@8af8800 {
-			status = "ok";
-		};
-
-		usb2_hs_phy: hsphy@a8000 {
-			status = "ok";
-		};
-
-		usb2: usb2@60f8800 {
-			status = "ok";
-		};
-
-		mdio@90000 {
-			status = "okay";
-		};
-
-		ess-switch@c000000 {
-			status = "okay";
-		};
-
-		ess-psgmii@98000 {
-			status = "okay";
-		};
-
-		edma@c080000 {
-			status = "okay";
-		};
-
-		wifi@a000000 {
-			status = "okay";
-		};
-
-		wifi@a800000 {
-			status = "okay";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		wps {
-			label = "wps";
-			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_WPS_BUTTON>;
-		};
-		reset {
-			label = "reset";
-			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_RESTART>;
-		};
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-
-		power {
-			label = "gl-b1300:green:power";
-			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-		mesh {
-			label = "gl-b1300:green:mesh";
-			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-		};
-		wlan {
-			label = "gl-b1300:green:wlan";
-			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&spi_0 {
-	mx25l25635f@0 {
-		compatible = "mx25l25635f", "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		spi-max-frequency = <24000000>;
-
-		SBL1@0 {
-			label = "SBL1";
-			reg = <0x0 0x40000>;
-			read-only;
-		};
-		MIBIB@40000 {
-			label = "MIBIB";
-			reg = <0x40000 0x20000>;
-			read-only;
-		};
-		QSEE@60000 {
-			label = "QSEE";
-			reg = <0x60000 0x60000>;
-			read-only;
-		};
-		CDT@c0000 {
-			label = "CDT";
-			reg = <0xc0000 0x10000>;
-			read-only;
-		};
-		DDRPARAMS@d0000 {
-			label = "DDRPARAMS";
-			reg = <0xd0000 0x10000>;
-			read-only;
-		};
-		APPSBLENV@e0000 {
-			label = "APPSBLENV";
-			reg = <0xe0000 0x10000>;
-			read-only;
-		};
-		APPSBL@f0000 {
-			label = "APPSBL";
-			reg = <0xf0000 0x80000>;
-			read-only;
-		};
-		ART@170000 {
-			label = "ART";
-			reg = <0x170000 0x10000>;
-			read-only;
-		};
-		kernel@180000 {
-			label = "kernel";
-			reg = <0x180000 0x400000>;
-		};
-		rootfs@580000 {
-			label = "rootfs";
-			reg = <0x580000 0x1a80000>;
-		};
-		firmware@180000 {
-			label = "firmware";
-			reg = <0x180000 0x1e80000>;
-		};
-	};
-};
-
-&gmac0 {
-	qcom,phy_mdio_addr = <4>;
-	qcom,poll_required = <1>;
-	qcom,forced_speed = <1000>;
-	qcom,forced_duplex = <1>;
-	vlan_tag = <2 0x20>;
-};
-
-&gmac1 {
-	qcom,phy_mdio_addr = <3>;
-	qcom,poll_required = <1>;
-	qcom,forced_speed = <1000>;
-	qcom,forced_duplex = <1>;
-	vlan_tag = <1 0x10>;
-};
\ No newline at end of file
diff --git a/target/linux/ipq806x/image/Makefile b/target/linux/ipq806x/image/Makefile
index c2d7255655..d41679ff97 100644
--- a/target/linux/ipq806x/image/Makefile
+++ b/target/linux/ipq806x/image/Makefile
@@ -73,21 +73,6 @@ define Device/ZyXELImage
 	IMAGE/mmcblk0p4-kernel.bin := append-kernel
 endef
 
-define Device/avm_fritzbox-4040
-	$(call Device/FitImageLzma)
-	DEVICE_DTS := qcom-ipq4019-fritz4040
-	KERNEL_LOADADDR := 0x80208000
-	BLOCKSIZE := 4k
-	PAGESIZE := 256
-	BOARD_NAME := fritz4040
-	DEVICE_TITLE := AVM Fritz!Box 4040
-	IMAGE_SIZE := 29753344
-	IMAGES = sysupgrade.bin
-	IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
-	DEVICE_PACKAGES := ipq-wifi-avm_fritzbox-4040 fritz-tffs fritz-caldata u-boot-fritz4040
-endef
-TARGET_DEVICES += avm_fritzbox-4040
-
 define Device/linksys_ea8500
 	$(call Device/LegacyImage)
 	DEVICE_DTS := qcom-ipq8064-ea8500
@@ -165,66 +150,6 @@ define Device/netgear_r7800
 endef
 TARGET_DEVICES += netgear_r7800
 
-define Device/glinet_gl-b1300
-	DEVICE_TITLE := GL.iNet GL-B1300
-	BOARD_NAME := gl-b1300
-	DEVICE_DTS := qcom-ipq4019-gl-b1300
-	KERNEL_LOADADDR := 0x80208000
-	KERNEL_INSTALL := 1
-	KERNEL_SIZE := 4096k
-	IMAGE_SIZE := 26624k
-	$(call Device/FitImage)
-	IMAGES := sysupgrade.bin
-	IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
-	DEVICE_PACKAGES := ipq-wifi-glinet_gl-b1300
-endef
-TARGET_DEVICES += glinet_gl-b1300
-
-define Device/openmesh_a42
-	$(call Device/FitImageLzma)
-	DEVICE_DTS := qcom-ipq4019-a42
-	KERNEL_LOADADDR := 0x80208000
-	BLOCKSIZE := 64k
-	SUPPORTED_DEVICES := openmesh,a42
-	DEVICE_TITLE := OpenMesh A42
-	KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)
-	IMAGE_SIZE := 15616k
-	IMAGES = factory.bin sysupgrade.bin
-	IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42
-	IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata
-	DEVICE_PACKAGES := ath10k-firmware-qca4019 uboot-envtools
-endef
-TARGET_DEVICES += openmesh_a42
-
-define Device/qcom_ap-dk01.1-c1
-	DEVICE_TITLE := QCA AP-DK01.1-C1
-	BOARD_NAME := ap-dk01.1-c1
-	DEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1
-	KERNEL_LOADADDR := 0x80208000
-	KERNEL_INSTALL := 1
-	KERNEL_SIZE := 4096k
-	IMAGE_SIZE := 26624k
-	$(call Device/FitImage)
-	IMAGES := sysupgrade.bin
-	IMAGE/sysupgrade.bin := append-kernel | pad-to $$$${KERNEL_SIZE} | append-rootfs | pad-rootfs | append-metadata
-	DEVICE_PACKAGES := ath10k-firmware-qca4019
-endef
-TARGET_DEVICES += qcom_ap-dk01.1-c1
-
-define Device/qcom_ap-dk04.1-c1
-	$(call Device/FitImage)
-	$(call Device/UbiFit)
-	DEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1
-	KERNEL_LOADADDR := 0x80208000
-	KERNEL_INSTALL := 1
-	KERNEL_SIZE := 4048k
-	BLOCKSIZE := 128k
-	PAGESIZE := 2048
-	BOARD_NAME := ap-dk04.1-c1
-	DEVICE_TITLE := QCA AP-DK04.1-C1
-endef
-TARGET_DEVICES += qcom_ap-dk04.1-c1
-
 define Device/qcom_ipq8064-ap148
 	$(call Device/FitImage)
 	$(call Device/UbiFit)
diff --git a/target/linux/ipq806x/patches-4.9/0015-cpufreq-dt-qcom-ipq4019-Add-compat-for-qcom-ipq4019.patch b/target/linux/ipq806x/patches-4.9/0015-cpufreq-dt-qcom-ipq4019-Add-compat-for-qcom-ipq4019.patch
deleted file mode 100644
index 06b61a07ef..0000000000
--- a/target/linux/ipq806x/patches-4.9/0015-cpufreq-dt-qcom-ipq4019-Add-compat-for-qcom-ipq4019.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 5543e93f51d5e23f9b3a7fe11a722c91fc410485 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Wed, 13 Apr 2016 14:03:14 -0500
-Subject: [PATCH 15/69] cpufreq: dt: qcom: ipq4019: Add compat for qcom ipq4019
-
-Instantiate  cpufreq-dt-platdev driver for ipq4019 to support changing
-CPU frequencies.
-
-This depends on Viresh Kumar's patches in this series:
-http://comments.gmane.org/gmane.linux.power-management.general/73887
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -35,6 +35,8 @@ static const struct of_device_id machine
- 
- 	{ .compatible = "marvell,berlin", },
- 
-+	{ .compatible = "qcom,ipq4019", },
-+
- 	{ .compatible = "samsung,exynos3250", },
- 	{ .compatible = "samsung,exynos4210", },
- 	{ .compatible = "samsung,exynos4212", },
diff --git a/target/linux/ipq806x/patches-4.9/0016-clk-ipq4019-report-accurate-fixed-clock-rates.patch b/target/linux/ipq806x/patches-4.9/0016-clk-ipq4019-report-accurate-fixed-clock-rates.patch
deleted file mode 100644
index be9c4eb1b2..0000000000
--- a/target/linux/ipq806x/patches-4.9/0016-clk-ipq4019-report-accurate-fixed-clock-rates.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 5e2df5f44e35d79fff2ab8bbb8a726ad5de78a3e Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@qca.qualcomm.com>
-Date: Thu, 28 Apr 2016 12:55:08 -0500
-Subject: [PATCH 16/69] clk: ipq4019: report accurate fixed clock rates
-
-This looks like a copy-and-paste gone wrong, but update all
-the fixed clock rates to report the correct values.
-
-Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
----
- drivers/clk/qcom/gcc-ipq4019.c | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1327,12 +1327,12 @@ static int gcc_ipq4019_probe(struct plat
- {
- 	struct device *dev = &pdev->dev;
- 
--	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
--	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
--	clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
--	clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
-+	clk_register_fixed_rate(dev, "fepll125", "xo", 0, 125000000);
-+	clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 125000000);
-+	clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 250000000);
-+	clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 250000000);
- 	clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
--	clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
-+	clk_register_fixed_rate(dev, "fepll500", "xo", 0, 500000000);
- 	clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
- 
- 	return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
diff --git a/target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch b/target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
deleted file mode 100644
index 7cbd6a4551..0000000000
--- a/target/linux/ipq806x/patches-4.9/0017-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 18c3b42575a154343831aec0637aab00e19440e1 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 15:01:09 -0500
-Subject: [PATCH 17/69] qcom: ipq4019: add cpu operating points for cpufreq
- support
-
-This adds some operating points for cpu frequeny scaling
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
- 1 file changed, 26 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -40,14 +40,7 @@
- 			reg = <0x0>;
- 			clocks = <&gcc GCC_APPS_CLK_SRC>;
- 			clock-frequency = <0>;
--			operating-points = <
--				/* kHz	uV (fixed) */
--				48000	1100000
--				200000	1100000
--				500000	1100000
--				666000	1100000
--			>;
--			clock-latency = <256000>;
-+			operating-points-v2 = <&cpu0_opp_table>;
- 		};
- 
- 		cpu@1 {
-@@ -59,6 +52,7 @@
- 			reg = <0x1>;
- 			clocks = <&gcc GCC_APPS_CLK_SRC>;
- 			clock-frequency = <0>;
-+			operating-points-v2 = <&cpu0_opp_table>;
- 		};
- 
- 		cpu@2 {
-@@ -70,6 +64,7 @@
- 			reg = <0x2>;
- 			clocks = <&gcc GCC_APPS_CLK_SRC>;
- 			clock-frequency = <0>;
-+			operating-points-v2 = <&cpu0_opp_table>;
- 		};
- 
- 		cpu@3 {
-@@ -81,6 +76,29 @@
- 			reg = <0x3>;
- 			clocks = <&gcc GCC_APPS_CLK_SRC>;
- 			clock-frequency = <0>;
-+			operating-points-v2 = <&cpu0_opp_table>;
-+		};
-+	};
-+
-+	cpu0_opp_table: opp_table0 {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp@48000000 {
-+			opp-hz = /bits/ 64 <48000000>;
-+			clock-latency-ns = <256000>;
-+		};
-+		opp@200000000 {
-+			opp-hz = /bits/ 64 <200000000>;
-+			clock-latency-ns = <256000>;
-+		};
-+		opp@500000000 {
-+			opp-hz = /bits/ 64 <500000000>;
-+			clock-latency-ns = <256000>;
-+		};
-+		opp@666000000 {
-+			opp-hz = /bits/ 64 <666000000>;
-+			clock-latency-ns = <256000>;
- 		};
- 	};
- 
diff --git a/target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch b/target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch
deleted file mode 100644
index 42bb4a6e3e..0000000000
--- a/target/linux/ipq806x/patches-4.9/0018-qcom-ipq4019-turn-on-DMA-for-i2c.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 71f82049dca86bc89b9da07e051e4ed492820233 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 28 Mar 2016 11:16:51 -0500
-Subject: [PATCH 18/69] qcom: ipq4019: turn on DMA for i2c
-
-These are the required nodes for i2c-qup to use DMA
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -179,6 +179,8 @@
- 			clock-names = "iface", "core";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-+			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
-+			dma-names = "rx", "tx";
- 			status = "disabled";
- 		};
- 
diff --git a/target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch b/target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch
deleted file mode 100644
index 54ee571cbb..0000000000
--- a/target/linux/ipq806x/patches-4.9/0019-qcom-ipq4019-use-correct-clock-for-i2c-bus-0.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 7292bf171cdf2fb48607058f12ddd0d812a87428 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@qca.qualcomm.com>
-Date: Fri, 29 Apr 2016 12:48:02 -0500
-Subject: [PATCH 19/69] qcom: ipq4019: use correct clock for i2c bus 0
-
-For the record the mapping is as follows:
-
-QUP0 = SPI QUP1
-QUP1 = SPI QUP2
-QUP2 = I2C QUP1
-QUP3 = I2C QUP2
-
-Signed-off-by: Matthew McClintock <mmcclint@qca.qualcomm.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -175,7 +175,7 @@
- 			reg = <0x78b7000 0x6000>;
- 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
--				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
-+				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- 			clock-names = "iface", "core";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
diff --git a/target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch b/target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch
deleted file mode 100644
index c1fa5c7298..0000000000
--- a/target/linux/ipq806x/patches-4.9/0020-qcom-ipq4019-enable-DMA-for-spi.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 4593e768393b9589f0a8987eaf57316c214865fe Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 11 Apr 2016 14:49:12 -0500
-Subject: [PATCH 20/69] qcom: ipq4019: enable DMA for spi
-
-These are the required nodes for spi-qup to use DMA
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -167,6 +167,8 @@
- 			clock-names = "core", "iface";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-+			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
-+			dma-names = "rx", "tx";
- 			status = "disabled";
- 		};
- 
diff --git a/target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch b/target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch
deleted file mode 100644
index 8cd3e205d3..0000000000
--- a/target/linux/ipq806x/patches-4.9/0026-dts-ipq4019-Add-support-for-IPQ4019-DK04-board.patch
+++ /dev/null
@@ -1,225 +0,0 @@
-From ec3e465ecf3f7dd26f2e22170e4c5f4b9979df5d Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Mon, 21 Mar 2016 15:55:21 -0500
-Subject: [PATCH 26/69] dts: ipq4019: Add support for IPQ4019 DK04 board
-
-This is pretty similiar to a DK01 but has a bit more IO. Some notable
-differences are listed below however they are not in the device tree yet
-as we continue adding more support
-
-- second serial port
-- PCIe
-- NAND
-- SD/EMMC
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
----
- arch/arm/boot/dts/Makefile                      |   1 +
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   |  12 +-
- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts |  21 +++
- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi   | 163 ++++++++++++++++++++++++
- 4 files changed, 189 insertions(+), 8 deletions(-)
- create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
- create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -617,6 +617,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
- 	qcom-apq8084-ifc6540.dtb \
- 	qcom-apq8084-mtp.dtb \
- 	qcom-ipq4019-ap.dk01.1-c1.dtb \
-+	qcom-ipq4019-ap.dk04.1-c1.dtb \
- 	qcom-ipq8064-ap148.dtb \
- 	qcom-msm8660-surf.dtb \
- 	qcom-msm8960-cdp.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
-@@ -0,0 +1,22 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include "qcom-ipq4019-ap.dk04.1.dtsi"
-+
-+/ {
-+	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
-+	compatible = "qcom,ap-dk04.1-c1", "qcom,ipq4019";
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-@@ -0,0 +1,163 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include "qcom-ipq4019.dtsi"
-+
-+/ {
-+	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
-+	compatible = "qcom,ipq4019";
-+
-+	clocks {
-+                xo: xo {
-+                        compatible = "fixed-clock";
-+                        clock-frequency = <48000000>;
-+                        #clock-cells = <0>;
-+                };
-+	};
-+
-+	soc {
-+		timer {
-+			compatible = "arm,armv7-timer";
-+			interrupts = <1 2 0xf08>,
-+				     <1 3 0xf08>,
-+				     <1 4 0xf08>,
-+				     <1 1 0xf08>;
-+			clock-frequency = <48000000>;
-+		};
-+
-+		pinctrl@0x01000000 {
-+			serial_0_pins: serial_pinmux {
-+				mux {
-+					pins = "gpio16", "gpio17";
-+					function = "blsp_uart0";
-+					bias-disable;
-+				};
-+			};
-+
-+                       serial_1_pins: serial1_pinmux {
-+				mux {
-+					pins = "gpio8", "gpio9";
-+					function = "blsp_uart1";
-+					bias-disable;
-+				};
-+			};
-+
-+			spi_0_pins: spi_0_pinmux {
-+				pinmux {
-+					function = "blsp_spi0";
-+					pins = "gpio13", "gpio14", "gpio15";
-+				};
-+				pinmux_cs {
-+					function = "gpio";
-+					pins = "gpio12";
-+				};
-+				pinconf {
-+					pins = "gpio13", "gpio14", "gpio15";
-+					drive-strength = <12>;
-+					bias-disable;
-+				};
-+				pinconf_cs {
-+					pins = "gpio12";
-+					drive-strength = <2>;
-+					bias-disable;
-+					output-high;
-+				};
-+			};
-+
-+			i2c_0_pins: i2c_0_pinmux {
-+				pinmux {
-+					function = "blsp_i2c0";
-+					pins = "gpio10", "gpio11";
-+				};
-+				pinconf {
-+					pins = "gpio10", "gpio11";
-+					drive-strength = <16>;
-+					bias-disable;
-+				};
-+			};
-+		};
-+
-+		blsp_dma: dma@7884000 {
-+			status = "ok";
-+		};
-+
-+		spi_0: spi@78b5000 {
-+			pinctrl-0 = <&spi_0_pins>;
-+			pinctrl-names = "default";
-+			status = "ok";
-+			cs-gpios = <&tlmm 12 0>;
-+
-+			mx25l25635e@0 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				reg = <0>;
-+				compatible = "mx25l25635e";
-+				spi-max-frequency = <24000000>;
-+			};
-+		};
-+
-+		i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
-+			pinctrl-0 = <&i2c_0_pins>;
-+			pinctrl-names = "default";
-+
-+			status = "ok";
-+		};
-+
-+		serial@78af000 {
-+			pinctrl-0 = <&serial_0_pins>;
-+			pinctrl-names = "default";
-+			status = "ok";
-+		};
-+
-+		serial@78b0000 {
-+			pinctrl-0 = <&serial_1_pins>;
-+			pinctrl-names = "default";
-+			status = "ok";
-+		};
-+
-+		usb3_ss_phy: ssphy@9a000 {
-+			status = "ok";
-+		};
-+
-+		usb3_hs_phy: hsphy@a6000 {
-+			status = "ok";
-+		};
-+
-+		usb3: usb3@8af8800 {
-+			status = "ok";
-+		};
-+
-+		usb2_hs_phy: hsphy@a8000 {
-+			status = "ok";
-+		};
-+
-+		usb2: usb2@60f8800 {
-+			status = "ok";
-+		};
-+
-+		cryptobam: dma@8e04000 {
-+			status = "ok";
-+		};
-+
-+		crypto@8e3a000 {
-+			status = "ok";
-+		};
-+
-+		watchdog@b017000 {
-+			status = "ok";
-+		};
-+	};
-+};
diff --git a/target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch b/target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
index 0f3b20ebe7..bac7c6da4f 100644
--- a/target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
+++ b/target/linux/ipq806x/patches-4.9/0069-arm-boot-add-dts-files.patch
@@ -10,15 +10,9 @@ Signed-off-by: John Crispin <john@phrozen.org>
 
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
-@@ -616,9 +616,20 @@ dtb-$(CONFIG_ARCH_QCOM) += \
- 	qcom-apq8074-dragonboard.dtb \
- 	qcom-apq8084-ifc6540.dtb \
+@@ -618,6 +618,14 @@ dtb-$(CONFIG_ARCH_QCOM) += \
  	qcom-apq8084-mtp.dtb \
-+ 	qcom-ipq4019-a42.dtb \
-+ 	qcom-ipq4019-gl-b1300.dtb \
  	qcom-ipq4019-ap.dk01.1-c1.dtb \
- 	qcom-ipq4019-ap.dk04.1-c1.dtb \
-+	qcom-ipq4019-fritz4040.dtb \
  	qcom-ipq8064-ap148.dtb \
 +	qcom-ipq8064-c2600.dtb \
 +	qcom-ipq8064-d7800.dtb \
diff --git a/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch b/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
deleted file mode 100644
index 40f5e407ba..0000000000
--- a/target/linux/ipq806x/patches-4.9/305-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch
+++ /dev/null
@@ -1,109 +0,0 @@
-From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Fri, 8 Apr 2016 15:26:10 -0500
-Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
-
-v1 was the incorrect choice here and sometimes the board
-would not come up properly.
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
-Changes:
-	- moved L2-Cache to be a subnode of cpu0
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
- 1 file changed, 24 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -34,19 +34,27 @@
- 		cpu@0 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a7";
--			enable-method = "qcom,kpss-acc-v1";
-+			enable-method = "qcom,kpss-acc-v2";
-+			next-level-cache = <&L2>;
- 			qcom,acc = <&acc0>;
- 			qcom,saw = <&saw0>;
- 			reg = <0x0>;
- 			clocks = <&gcc GCC_APPS_CLK_SRC>;
- 			clock-frequency = <0>;
- 			operating-points-v2 = <&cpu0_opp_table>;
-+
-+			L2: l2-cache {
-+				compatible = "qcom,arch-cache";
-+				cache-level = <2>;
-+				qcom,saw = <&saw_l2>;
-+			};
- 		};
- 
- 		cpu@1 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a7";
--			enable-method = "qcom,kpss-acc-v1";
-+			enable-method = "qcom,kpss-acc-v2";
-+			next-level-cache = <&L2>;
- 			qcom,acc = <&acc1>;
- 			qcom,saw = <&saw1>;
- 			reg = <0x1>;
-@@ -58,7 +66,8 @@
- 		cpu@2 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a7";
--			enable-method = "qcom,kpss-acc-v1";
-+			enable-method = "qcom,kpss-acc-v2";
-+			next-level-cache = <&L2>;
- 			qcom,acc = <&acc2>;
- 			qcom,saw = <&saw2>;
- 			reg = <0x2>;
-@@ -70,7 +79,8 @@
- 		cpu@3 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a7";
--			enable-method = "qcom,kpss-acc-v1";
-+			enable-method = "qcom,kpss-acc-v2";
-+			next-level-cache = <&L2>;
- 			qcom,acc = <&acc3>;
- 			qcom,saw = <&saw3>;
- 			reg = <0x3>;
-@@ -212,22 +222,22 @@
- 		};
- 
-                 acc0: clock-controller@b088000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-                 };
- 
-                 acc1: clock-controller@b098000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
-                 };
- 
-                 acc2: clock-controller@b0a8000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
-                 };
- 
-                 acc3: clock-controller@b0b8000 {
--                        compatible = "qcom,kpss-acc-v1";
-+                        compatible = "qcom,kpss-acc-v2";
-                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
-                 };
- 
-@@ -255,6 +265,12 @@
-                         regulator;
-                 };
- 
-+		saw_l2: regulator@b012000 {
-+			compatible = "qcom,saw2";
-+			reg = <0xb012000 0x1000>;
-+			regulator;
-+		};
-+
- 		serial@78af000 {
- 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- 			reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch b/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
deleted file mode 100644
index 3c3fc98a2d..0000000000
--- a/target/linux/ipq806x/patches-4.9/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
-From: Matthew McClintock <mmcclint@codeaurora.org>
-Date: Thu, 17 Mar 2016 16:22:28 -0500
-Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
-
-This adds the SoC nodes to the ipq4019 device tree and
-enable it for the DK01.1 board.
-
-Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
-Changes:
-	- replaced space with tab
-	- added sleep and mock_utmi clocks
-	- added registers for usb2 and usb3 parent node
-	- changed compatible to qca,ipa4019-dwc3
-	- updated usb2 and usb3 names
-	  (included the reg - in case they become necessary later)
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
- arch/arm/boot/dts/qcom-ipq4019.dtsi           | 71 +++++++++++++++++++++++++++
- 2 files changed, 91 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -108,5 +108,25 @@
- 		watchdog@b017000 {
- 			status = "ok";
- 		};
-+
-+		usb3_ss_phy: ssphy@9a000 {
-+			status = "ok";
-+		};
-+
-+		usb3_hs_phy: hsphy@a6000 {
-+			status = "ok";
-+		};
-+
-+		usb3: usb3@8af8800 {
-+			status = "ok";
-+		};
-+
-+		usb2_hs_phy: hsphy@a8000 {
-+			status = "ok";
-+		};
-+
-+		usb2: usb2@60f8800 {
-+			status = "ok";
-+		};
- 	};
- };
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -307,5 +307,76 @@
- 			compatible = "qcom,pshold";
- 			reg = <0x4ab000 0x4>;
- 		};
-+
-+		usb3_ss_phy: ssphy@9a000 {
-+			compatible = "qca,uni-ssphy";
-+			reg = <0x9a000 0x800>;
-+			reg-names = "phy_base";
-+			resets = <&gcc USB3_UNIPHY_PHY_ARES>;
-+			reset-names = "por_rst";
-+			status = "disabled";
-+		};
-+
-+		usb3_hs_phy: hsphy@a6000 {
-+			compatible = "qca,baldur-usb3-hsphy";
-+			reg = <0xa6000 0x40>;
-+			reg-names = "phy_base";
-+			resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
-+			reset-names = "por_rst", "srif_rst";
-+			status = "disabled";
-+		};
-+
-+		usb3@8af8800 {
-+			compatible = "qca,ipq4019-dwc3";
-+			reg = <0x8af8800 0x100>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			clocks = <&gcc GCC_USB3_MASTER_CLK>,
-+				 <&gcc GCC_USB3_SLEEP_CLK>,
-+				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
-+			clock-names = "master", "sleep", "mock_utmi";
-+			ranges;
-+			status = "disabled";
-+
-+			dwc3@8a00000 {
-+				compatible = "snps,dwc3";
-+				reg = <0x8a00000 0xf8000>;
-+				interrupts = <0 132 0>;
-+				usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
-+				phy-names = "usb2-phy", "usb3-phy";
-+				dr_mode = "host";
-+			};
-+		};
-+
-+		usb2_hs_phy: hsphy@a8000 {
-+			compatible = "qca,baldur-usb2-hsphy";
-+			reg = <0xa8000 0x40>;
-+			reg-names = "phy_base";
-+			resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
-+			reset-names = "por_rst", "srif_rst";
-+			status = "disabled";
-+		};
-+
-+		usb2@60f8800 {
-+			compatible = "qca,ipq4019-dwc3";
-+			reg = <0x60f8800 0x100>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			clocks = <&gcc GCC_USB2_MASTER_CLK>,
-+				 <&gcc GCC_USB2_SLEEP_CLK>,
-+				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
-+			clock-names = "master", "sleep", "mock_utmi";
-+			ranges;
-+			status = "disabled";
-+
-+			dwc3@6000000 {
-+				compatible = "snps,dwc3";
-+				reg = <0x6000000 0xf8000>;
-+				interrupts = <0 136 0>;
-+				usb-phy = <&usb2_hs_phy>;
-+				phy-names = "usb2-phy";
-+				dr_mode = "host";
-+			};
-+		};
- 	};
- };
diff --git a/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch b/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch
deleted file mode 100644
index 4cbcc0aea2..0000000000
--- a/target/linux/ipq806x/patches-4.9/307-ARM-qcom-Add-IPQ4019-SoC-support.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From e7748d641ae37081e2034869491f1629461ae13c Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 00:58:18 +0100
-Subject: [PATCH] ARM: qcom: Add IPQ4019 SoC support
-
-Add support for the Qualcomm Atheros IPQ4019 SoC.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/Makefile          | 1 +
- arch/arm/mach-qcom/Kconfig | 5 +++++
- 2 files changed, 6 insertions(+)
-
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -147,6 +147,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
- endif
- textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
- textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
-+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
- textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
- 
- # Machine directory name.  This list is sorted alphanumerically
---- a/arch/arm/mach-qcom/Kconfig
-+++ b/arch/arm/mach-qcom/Kconfig
-@@ -28,4 +28,9 @@ config ARCH_MDM9615
- 	bool "Enable support for MDM9615"
- 	select CLKSRC_QCOM
- 
-+config ARCH_IPQ40XX
-+	bool "Enable support for IPQ40XX"
-+	select CLKSRC_QCOM
-+	select HAVE_ARM_ARCH_TIMER
-+
- endif
diff --git a/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch b/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch
deleted file mode 100644
index d12ca4befe..0000000000
--- a/target/linux/ipq806x/patches-4.9/308-dts-ipq4019-add-both-IPQ4019-wifi-block-definitions.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 6091a49b0b06bf838fed80498c4f5f40d0fbd447 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 01:22:46 +0100
-Subject: [PATCH] dts: ipq4019: add both IPQ4019 wifi block definitions
-
-The IPQ4019 has two ath10k blocks on the AHB. Both wifi's
-are already supported by ath10k.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 84 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -378,5 +378,89 @@
- 				dr_mode = "host";
- 			};
- 		};
-+
-+		wifi0: wifi@a000000 {
-+			compatible = "qcom,ipq4019-wifi";
-+			reg = <0xa000000 0x200000>;
-+			resets = <&gcc WIFI0_CPU_INIT_RESET
-+				  &gcc WIFI0_RADIO_SRIF_RESET
-+				  &gcc WIFI0_RADIO_WARM_RESET
-+				  &gcc WIFI0_RADIO_COLD_RESET
-+				  &gcc WIFI0_CORE_WARM_RESET
-+				  &gcc WIFI0_CORE_COLD_RESET>;
-+			reset-names = "wifi_cpu_init", "wifi_radio_srif",
-+				      "wifi_radio_warm", "wifi_radio_cold",
-+				      "wifi_core_warm", "wifi_core_cold";
-+			clocks = <&gcc GCC_WCSS2G_CLK
-+				  &gcc GCC_WCSS2G_REF_CLK
-+				  &gcc GCC_WCSS2G_RTC_CLK>;
-+			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
-+				      "wifi_wcss_rtc";
-+			interrupts = <0 32 IRQ_TYPE_EDGE_RISING
-+				      0 33 IRQ_TYPE_EDGE_RISING
-+				      0 34 IRQ_TYPE_EDGE_RISING
-+				      0 35 IRQ_TYPE_EDGE_RISING
-+				      0 36 IRQ_TYPE_EDGE_RISING
-+				      0 37 IRQ_TYPE_EDGE_RISING
-+				      0 38 IRQ_TYPE_EDGE_RISING
-+				      0 39 IRQ_TYPE_EDGE_RISING
-+				      0 40 IRQ_TYPE_EDGE_RISING
-+				      0 41 IRQ_TYPE_EDGE_RISING
-+				      0 42 IRQ_TYPE_EDGE_RISING
-+				      0 43 IRQ_TYPE_EDGE_RISING
-+				      0 44 IRQ_TYPE_EDGE_RISING
-+				      0 45 IRQ_TYPE_EDGE_RISING
-+				      0 46 IRQ_TYPE_EDGE_RISING
-+				      0 47 IRQ_TYPE_EDGE_RISING
-+				      0 168 IRQ_TYPE_NONE>;
-+			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
-+					   "msi4",  "msi5",  "msi6",  "msi7",
-+					   "msi8",  "msi9", "msi10", "msi11",
-+					  "msi12", "msi13", "msi14", "msi15",
-+					  "legacy";
-+			status = "disabled";
-+		};
-+
-+		wifi1: wifi@a800000 {
-+			compatible = "qcom,ipq4019-wifi";
-+			reg = <0xa800000 0x200000>;
-+			resets = <&gcc WIFI1_CPU_INIT_RESET
-+				  &gcc WIFI1_RADIO_SRIF_RESET
-+				  &gcc WIFI1_RADIO_WARM_RESET
-+				  &gcc WIFI1_RADIO_COLD_RESET
-+				  &gcc WIFI1_CORE_WARM_RESET
-+				  &gcc WIFI1_CORE_COLD_RESET>;
-+			reset-names = "wifi_cpu_init", "wifi_radio_srif",
-+				      "wifi_radio_warm", "wifi_radio_cold",
-+				      "wifi_core_warm", "wifi_core_cold";
-+			clocks = <&gcc GCC_WCSS5G_CLK
-+				  &gcc GCC_WCSS5G_REF_CLK
-+				  &gcc GCC_WCSS5G_RTC_CLK>;
-+			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
-+				      "wifi_wcss_rtc";
-+			interrupts = <0 48 IRQ_TYPE_EDGE_RISING
-+				      0 49 IRQ_TYPE_EDGE_RISING
-+				      0 50 IRQ_TYPE_EDGE_RISING
-+				      0 51 IRQ_TYPE_EDGE_RISING
-+				      0 52 IRQ_TYPE_EDGE_RISING
-+				      0 53 IRQ_TYPE_EDGE_RISING
-+				      0 54 IRQ_TYPE_EDGE_RISING
-+				      0 55 IRQ_TYPE_EDGE_RISING
-+				      0 56 IRQ_TYPE_EDGE_RISING
-+				      0 57 IRQ_TYPE_EDGE_RISING
-+				      0 58 IRQ_TYPE_EDGE_RISING
-+				      0 59 IRQ_TYPE_EDGE_RISING
-+				      0 60 IRQ_TYPE_EDGE_RISING
-+				      0 61 IRQ_TYPE_EDGE_RISING
-+				      0 62 IRQ_TYPE_EDGE_RISING
-+				      0 63 IRQ_TYPE_EDGE_RISING
-+				      0 169 IRQ_TYPE_NONE>;
-+			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
-+					   "msi4",  "msi5",  "msi6",  "msi7",
-+					   "msi8",  "msi9", "msi10", "msi11",
-+					  "msi12", "msi13", "msi14", "msi15",
-+					  "legacy";
-+			status = "disabled";
-+		};
- 	};
- };
diff --git a/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch b/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch
deleted file mode 100644
index abcbb6ee55..0000000000
--- a/target/linux/ipq806x/patches-4.9/309-dts-ipq4019-add-pseudo-random-number-generator.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 26fa6fdc627b523277c7a79907233596b2f8a3ef Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 03:29:04 +0100
-Subject: [PATCH] dts: ipq4019: add pseudo random number generator
-
-This architecture has a pseudo random number generator
-supported by the existing "qcom,prng" binding.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -271,6 +271,13 @@
- 			regulator;
- 		};
- 
-+		rng@22000 {
-+			compatible = "qcom,prng";
-+			reg = <0x22000 0x140>;
-+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
-+			clock-names = "core";
-+		};
-+
- 		serial@78af000 {
- 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- 			reg = <0x78af000 0x200>;
diff --git a/target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch b/target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch
deleted file mode 100644
index d2721875a2..0000000000
--- a/target/linux/ipq806x/patches-4.9/605-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
-From: Rakesh Nair <ranair@codeaurora.org>
-Date: Wed, 20 Jul 2016 15:02:01 +0530
-Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
- netdev_ops
-
-Add callback support to get default vlan tag and register
-receive flow steering filter.
-
-Used by IPQ4019 ess-edma driver.
-
-BUG=chrome-os-partner:33096
-TEST=none
-
-Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
-Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
-Reviewed-on: https://chromium-review.googlesource.com/362203
-Commit-Ready: Grant Grundler <grundler@chromium.org>
-Tested-by: Grant Grundler <grundler@chromium.org>
-Reviewed-by: Grant Grundler <grundler@chromium.org>
----
- include/linux/netdevice.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -725,6 +725,16 @@ struct xps_map {
- #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
-        - sizeof(struct xps_map)) / sizeof(u16))
- 
-+#ifdef CONFIG_RFS_ACCEL
-+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
-+                                     __be32 src,
-+                                     __be32 dst,
-+                                     __be16 sport,
-+                                     __be16 dport,
-+                                     u8 proto,
-+                                     u16 rxq_index,
-+                                     u32 action);
-+#endif
- /*
-  * This structure holds all XPS maps for device.  Maps are indexed by CPU.
-  */
-@@ -1251,6 +1261,9 @@ struct net_device_ops {
- 						     const struct sk_buff *skb,
- 						     u16 rxq_index,
- 						     u32 flow_id);
-+        int                     (*ndo_register_rfs_filter)(struct net_device *dev,
-+                                                              set_rfs_filter_callback_t set_filter);
-+        int                     (*ndo_get_default_vlan_tag)(struct net_device *net);
- #endif
- 	int			(*ndo_add_slave)(struct net_device *dev,
- 						 struct net_device *slave_dev);
diff --git a/target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch b/target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch
deleted file mode 100644
index 003524312c..0000000000
--- a/target/linux/ipq806x/patches-4.9/700-net-add-qualcomm-mdio-and-phy.patch
+++ /dev/null
@@ -1,2690 +0,0 @@
-From 5a71a2005a2e1e6bbe36f00386c495ad6626beb2 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Thu, 19 Jan 2017 01:59:43 +0100
-Subject: [PATCH 30/38] NET: add qualcomm mdio and PHY
-
----
- drivers/net/phy/Kconfig  | 14 ++++++++++++++
- drivers/net/phy/Makefile |  2 ++
- 2 files changed, 16 insertions(+)
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -408,6 +408,20 @@ config XILINX_GMII2RGMII
-          the Reduced Gigabit Media Independent Interface(RGMII) between
-          Ethernet physical media devices and the Gigabit Ethernet controller.
- 
-+config MDIO_IPQ40XX
-+	tristate "Qualcomm Atheros ipq40xx MDIO interface"
-+	depends on HAS_IOMEM && OF
-+	---help---
-+	  This driver supports the MDIO interface found in Qualcomm
-+	  Atheros ipq40xx Soc chip.
-+
-+config AR40XX_PHY
-+	tristate "Driver for Qualcomm Atheros IPQ40XX switches"
-+	depends on HAS_IOMEM && OF
-+	select SWCONFIG
-+	---help---
-+	   This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
-+
- endif # PHYLIB
- 
- config MICREL_KS8995MA
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -32,6 +32,7 @@ obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += md
- obj-$(CONFIG_MDIO_CAVIUM)	+= mdio-cavium.o
- obj-$(CONFIG_MDIO_GPIO)		+= mdio-gpio.o
- obj-$(CONFIG_MDIO_HISI_FEMAC)	+= mdio-hisi-femac.o
-+obj-$(CONFIG_MDIO_IPQ40XX)	+= mdio-ipq40xx.o
- obj-$(CONFIG_MDIO_MOXART)	+= mdio-moxart.o
- obj-$(CONFIG_MDIO_OCTEON)	+= mdio-octeon.o
- obj-$(CONFIG_MDIO_SUN4I)	+= mdio-sun4i.o
-@@ -40,6 +41,7 @@ obj-$(CONFIG_MDIO_XGENE)	+= mdio-xgene.o
- 
- obj-$(CONFIG_AMD_PHY)		+= amd.o
- obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o
-+obj-$(CONFIG_AR40XX_PHY)	+= ar40xx.o
- obj-$(CONFIG_AT803X_PHY)	+= at803x.o
- obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o
- obj-$(CONFIG_BCM7XXX_PHY)	+= bcm7xxx.o
---- /dev/null
-+++ b/drivers/net/phy/ar40xx.c
-@@ -0,0 +1,2090 @@
-+/*
-+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/list.h>
-+#include <linux/bitops.h>
-+#include <linux/switch.h>
-+#include <linux/delay.h>
-+#include <linux/phy.h>
-+#include <linux/clk.h>
-+#include <linux/reset.h>
-+#include <linux/lockdep.h>
-+#include <linux/workqueue.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/mdio.h>
-+#include <linux/gpio.h>
-+
-+#include "ar40xx.h"
-+
-+static struct ar40xx_priv *ar40xx_priv;
-+
-+#define MIB_DESC(_s , _o, _n)	\
-+	{			\
-+		.size = (_s),	\
-+		.offset = (_o),	\
-+		.name = (_n),	\
-+	}
-+
-+static const struct ar40xx_mib_desc ar40xx_mibs[] = {
-+	MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
-+	MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
-+	MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
-+	MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
-+	MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
-+	MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
-+	MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
-+	MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
-+	MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
-+	MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
-+	MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
-+	MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
-+	MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
-+	MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
-+	MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
-+	MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
-+	MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
-+	MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
-+	MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
-+	MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
-+	MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
-+	MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
-+	MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
-+	MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
-+	MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
-+	MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
-+	MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
-+	MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
-+	MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
-+	MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
-+	MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
-+	MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
-+	MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
-+	MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
-+	MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
-+	MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
-+	MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
-+	MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
-+	MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
-+};
-+
-+static u32
-+ar40xx_read(struct ar40xx_priv *priv, int reg)
-+{
-+	return readl(priv->hw_addr + reg);
-+}
-+
-+static u32
-+ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg)
-+{
-+	return readl(priv->psgmii_hw_addr + reg);
-+}
-+
-+static void
-+ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val)
-+{
-+	writel(val, priv->hw_addr + reg);
-+}
-+
-+static u32
-+ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
-+{
-+	u32 ret;
-+
-+	ret = ar40xx_read(priv, reg);
-+	ret &= ~mask;
-+	ret |= val;
-+	ar40xx_write(priv, reg, ret);
-+	return ret;
-+}
-+
-+static void
-+ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val)
-+{
-+	writel(val, priv->psgmii_hw_addr + reg);
-+}
-+
-+static void
-+ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr,
-+		     u16 dbg_addr, u16 dbg_data)
-+{
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	mutex_lock(&bus->mdio_lock);
-+	bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
-+	bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data);
-+	mutex_unlock(&bus->mdio_lock);
-+}
-+
-+static void
-+ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr,
-+		    u16 dbg_addr, u16 *dbg_data)
-+{
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	mutex_lock(&bus->mdio_lock);
-+	bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
-+	*dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA);
-+	mutex_unlock(&bus->mdio_lock);
-+}
-+
-+static void
-+ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id,
-+		     u16 mmd_num, u16 reg_id, u16 reg_val)
-+{
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	mutex_lock(&bus->mdio_lock);
-+	bus->write(bus, phy_id,
-+			AR40XX_MII_ATH_MMD_ADDR, mmd_num);
-+	bus->write(bus, phy_id,
-+			AR40XX_MII_ATH_MMD_DATA, reg_id);
-+	bus->write(bus, phy_id,
-+			AR40XX_MII_ATH_MMD_ADDR,
-+			0x4000 | mmd_num);
-+	bus->write(bus, phy_id,
-+		AR40XX_MII_ATH_MMD_DATA, reg_val);
-+	mutex_unlock(&bus->mdio_lock);
-+}
-+
-+static u16
-+ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id,
-+		    u16 mmd_num, u16 reg_id)
-+{
-+	u16 value;
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	mutex_lock(&bus->mdio_lock);
-+	bus->write(bus, phy_id,
-+			AR40XX_MII_ATH_MMD_ADDR, mmd_num);
-+	bus->write(bus, phy_id,
-+			AR40XX_MII_ATH_MMD_DATA, reg_id);
-+	bus->write(bus, phy_id,
-+			AR40XX_MII_ATH_MMD_ADDR,
-+			0x4000 | mmd_num);
-+	value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA);
-+	mutex_unlock(&bus->mdio_lock);
-+	return value;
-+}
-+
-+/* Start of swconfig support */
-+
-+static void
-+ar40xx_phy_poll_reset(struct ar40xx_priv *priv)
-+{
-+	u32 i, in_reset, retries = 500;
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	/* Assume RESET was recently issued to some or all of the phys */
-+	in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0);
-+
-+	while (retries--) {
-+		/* 1ms should be plenty of time.
-+		 * 802.3 spec allows for a max wait time of 500ms
-+		 */
-+		usleep_range(1000, 2000);
-+
-+		for (i = 0; i < AR40XX_NUM_PHYS; i++) {
-+			int val;
-+
-+			/* skip devices which have completed reset */
-+			if (!(in_reset & BIT(i)))
-+				continue;
-+
-+			val = mdiobus_read(bus, i, MII_BMCR);
-+			if (val < 0)
-+				continue;
-+
-+			/* mark when phy is no longer in reset state */
-+			if (!(val & BMCR_RESET))
-+				in_reset &= ~BIT(i);
-+		}
-+
-+		if (!in_reset)
-+			return;
-+	}
-+
-+	dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n",
-+		 in_reset);
-+}
-+
-+static void
-+ar40xx_phy_init(struct ar40xx_priv *priv)
-+{
-+	int i;
-+	struct mii_bus *bus;
-+	u16 val;
-+
-+	bus = priv->mii_bus;
-+	for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
-+		ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
-+		val &= ~AR40XX_PHY_MANU_CTRL_EN;
-+		ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
-+		mdiobus_write(bus, i,
-+			      MII_ADVERTISE, ADVERTISE_ALL |
-+			      ADVERTISE_PAUSE_CAP |
-+			      ADVERTISE_PAUSE_ASYM);
-+		mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
-+		mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
-+	}
-+
-+	ar40xx_phy_poll_reset(priv);
-+}
-+
-+static void
-+ar40xx_port_phy_linkdown(struct ar40xx_priv *priv)
-+{
-+	struct mii_bus *bus;
-+	int i;
-+	u16 val;
-+
-+	bus = priv->mii_bus;
-+	for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
-+		mdiobus_write(bus, i, MII_CTRL1000, 0);
-+		mdiobus_write(bus, i, MII_ADVERTISE, 0);
-+		mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
-+		ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
-+		val |= AR40XX_PHY_MANU_CTRL_EN;
-+		ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
-+		/* disable transmit */
-+		ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val);
-+		val &= 0xf00f;
-+		ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val);
-+	}
-+}
-+
-+static void
-+ar40xx_set_mirror_regs(struct ar40xx_priv *priv)
-+{
-+	int port;
-+
-+	/* reset all mirror registers */
-+	ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
-+		   AR40XX_FWD_CTRL0_MIRROR_PORT,
-+		   (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
-+	for (port = 0; port < AR40XX_NUM_PORTS; port++) {
-+		ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port),
-+			   AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0);
-+
-+		ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port),
-+			   AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0);
-+	}
-+
-+	/* now enable mirroring if necessary */
-+	if (priv->source_port >= AR40XX_NUM_PORTS ||
-+	    priv->monitor_port >= AR40XX_NUM_PORTS ||
-+	    priv->source_port == priv->monitor_port) {
-+		return;
-+	}
-+
-+	ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
-+		   AR40XX_FWD_CTRL0_MIRROR_PORT,
-+		   (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
-+
-+	if (priv->mirror_rx)
-+		ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0,
-+			   AR40XX_PORT_LOOKUP_ING_MIRROR_EN);
-+
-+	if (priv->mirror_tx)
-+		ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port),
-+			   0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN);
-+}
-+
-+static int
-+ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	u8 ports = priv->vlan_table[val->port_vlan];
-+	int i;
-+
-+	val->len = 0;
-+	for (i = 0; i < dev->ports; i++) {
-+		struct switch_port *p;
-+
-+		if (!(ports & BIT(i)))
-+			continue;
-+
-+		p = &val->value.ports[val->len++];
-+		p->id = i;
-+		if ((priv->vlan_tagged & BIT(i)) ||
-+		    (priv->pvid[i] != val->port_vlan))
-+			p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
-+		else
-+			p->flags = 0;
-+	}
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	u8 *vt = &priv->vlan_table[val->port_vlan];
-+	int i;
-+
-+	*vt = 0;
-+	for (i = 0; i < val->len; i++) {
-+		struct switch_port *p = &val->value.ports[i];
-+
-+		if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
-+			if (val->port_vlan == priv->pvid[p->id])
-+				priv->vlan_tagged |= BIT(p->id);
-+		} else {
-+			priv->vlan_tagged &= ~BIT(p->id);
-+			priv->pvid[p->id] = val->port_vlan;
-+		}
-+
-+		*vt |= BIT(p->id);
-+	}
-+	return 0;
-+}
-+
-+static int
-+ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val,
-+		unsigned timeout)
-+{
-+	int i;
-+
-+	for (i = 0; i < timeout; i++) {
-+		u32 t;
-+
-+		t = ar40xx_read(priv, reg);
-+		if ((t & mask) == val)
-+			return 0;
-+
-+		usleep_range(1000, 2000);
-+	}
-+
-+	return -ETIMEDOUT;
-+}
-+
-+static int
-+ar40xx_mib_op(struct ar40xx_priv *priv, u32 op)
-+{
-+	int ret;
-+
-+	lockdep_assert_held(&priv->mib_lock);
-+
-+	/* Capture the hardware statistics for all ports */
-+	ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC,
-+		   AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S));
-+
-+	/* Wait for the capturing to complete. */
-+	ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC,
-+			      AR40XX_MIB_BUSY, 0, 10);
-+
-+	return ret;
-+}
-+
-+static void
-+ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush)
-+{
-+	unsigned int base;
-+	u64 *mib_stats;
-+	int i;
-+	u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+
-+	WARN_ON(port >= priv->dev.ports);
-+
-+	lockdep_assert_held(&priv->mib_lock);
-+
-+	base = AR40XX_REG_PORT_STATS_START +
-+	       AR40XX_REG_PORT_STATS_LEN * port;
-+
-+	mib_stats = &priv->mib_stats[port * num_mibs];
-+	if (flush) {
-+		u32 len;
-+
-+		len = num_mibs * sizeof(*mib_stats);
-+		memset(mib_stats, 0, len);
-+		return;
-+	}
-+	for (i = 0; i < num_mibs; i++) {
-+		const struct ar40xx_mib_desc *mib;
-+		u64 t;
-+
-+		mib = &ar40xx_mibs[i];
-+		t = ar40xx_read(priv, base + mib->offset);
-+		if (mib->size == 2) {
-+			u64 hi;
-+
-+			hi = ar40xx_read(priv, base + mib->offset + 4);
-+			t |= hi << 32;
-+		}
-+
-+		mib_stats[i] += t;
-+	}
-+}
-+
-+static int
-+ar40xx_mib_capture(struct ar40xx_priv *priv)
-+{
-+	return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE);
-+}
-+
-+static int
-+ar40xx_mib_flush(struct ar40xx_priv *priv)
-+{
-+	return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH);
-+}
-+
-+static int
-+ar40xx_sw_set_reset_mibs(struct switch_dev *dev,
-+			 const struct switch_attr *attr,
-+			 struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	unsigned int len;
-+	int ret;
-+	u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+
-+	mutex_lock(&priv->mib_lock);
-+
-+	len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats);
-+	memset(priv->mib_stats, 0, len);
-+	ret = ar40xx_mib_flush(priv);
-+
-+	mutex_unlock(&priv->mib_lock);
-+	return ret;
-+}
-+
-+static int
-+ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
-+		   struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	priv->vlan = !!val->value.i;
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
-+		   struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	val->value.i = priv->vlan;
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev,
-+			       const struct switch_attr *attr,
-+			       struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	priv->mirror_rx = !!val->value.i;
-+	ar40xx_set_mirror_regs(priv);
-+	mutex_unlock(&priv->reg_mutex);
-+
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev,
-+			       const struct switch_attr *attr,
-+			       struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	val->value.i = priv->mirror_rx;
-+	mutex_unlock(&priv->reg_mutex);
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev,
-+			       const struct switch_attr *attr,
-+			       struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	priv->mirror_tx = !!val->value.i;
-+	ar40xx_set_mirror_regs(priv);
-+	mutex_unlock(&priv->reg_mutex);
-+
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev,
-+			       const struct switch_attr *attr,
-+			       struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	val->value.i = priv->mirror_tx;
-+	mutex_unlock(&priv->reg_mutex);
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev,
-+				  const struct switch_attr *attr,
-+				  struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	priv->monitor_port = val->value.i;
-+	ar40xx_set_mirror_regs(priv);
-+	mutex_unlock(&priv->reg_mutex);
-+
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev,
-+				  const struct switch_attr *attr,
-+				  struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	val->value.i = priv->monitor_port;
-+	mutex_unlock(&priv->reg_mutex);
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_mirror_source_port(struct switch_dev *dev,
-+				 const struct switch_attr *attr,
-+				 struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	priv->source_port = val->value.i;
-+	ar40xx_set_mirror_regs(priv);
-+	mutex_unlock(&priv->reg_mutex);
-+
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_mirror_source_port(struct switch_dev *dev,
-+				 const struct switch_attr *attr,
-+				 struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	mutex_lock(&priv->reg_mutex);
-+	val->value.i = priv->source_port;
-+	mutex_unlock(&priv->reg_mutex);
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_linkdown(struct switch_dev *dev,
-+		       const struct switch_attr *attr,
-+		       struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	if (val->value.i == 1)
-+		ar40xx_port_phy_linkdown(priv);
-+	else
-+		ar40xx_phy_init(priv);
-+
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_port_reset_mib(struct switch_dev *dev,
-+			     const struct switch_attr *attr,
-+			     struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	int port;
-+	int ret;
-+
-+	port = val->port_vlan;
-+	if (port >= dev->ports)
-+		return -EINVAL;
-+
-+	mutex_lock(&priv->mib_lock);
-+	ret = ar40xx_mib_capture(priv);
-+	if (ret)
-+		goto unlock;
-+
-+	ar40xx_mib_fetch_port_stat(priv, port, true);
-+
-+unlock:
-+	mutex_unlock(&priv->mib_lock);
-+	return ret;
-+}
-+
-+static int
-+ar40xx_sw_get_port_mib(struct switch_dev *dev,
-+		       const struct switch_attr *attr,
-+		       struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	u64 *mib_stats;
-+	int port;
-+	int ret;
-+	char *buf = priv->buf;
-+	int i, len = 0;
-+	u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+
-+	port = val->port_vlan;
-+	if (port >= dev->ports)
-+		return -EINVAL;
-+
-+	mutex_lock(&priv->mib_lock);
-+	ret = ar40xx_mib_capture(priv);
-+	if (ret)
-+		goto unlock;
-+
-+	ar40xx_mib_fetch_port_stat(priv, port, false);
-+
-+	len += snprintf(buf + len, sizeof(priv->buf) - len,
-+			"Port %d MIB counters\n",
-+			port);
-+
-+	mib_stats = &priv->mib_stats[port * num_mibs];
-+	for (i = 0; i < num_mibs; i++)
-+		len += snprintf(buf + len, sizeof(priv->buf) - len,
-+				"%-12s: %llu\n",
-+				ar40xx_mibs[i].name,
-+				mib_stats[i]);
-+
-+	val->value.s = buf;
-+	val->len = len;
-+
-+unlock:
-+	mutex_unlock(&priv->mib_lock);
-+	return ret;
-+}
-+
-+static int
-+ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
-+		  struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	priv->vlan_id[val->port_vlan] = val->value.i;
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
-+		  struct switch_val *val)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	val->value.i = priv->vlan_id[val->port_vlan];
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	*vlan = priv->pvid[port];
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	/* make sure no invalid PVIDs get set */
-+	if (vlan >= dev->vlans)
-+		return -EINVAL;
-+
-+	priv->pvid[port] = vlan;
-+	return 0;
-+}
-+
-+static void
-+ar40xx_read_port_link(struct ar40xx_priv *priv, int port,
-+		      struct switch_port_link *link)
-+{
-+	u32 status;
-+	u32 speed;
-+
-+	memset(link, 0, sizeof(*link));
-+
-+	status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port));
-+
-+	link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN);
-+	if (link->aneg || (port != AR40XX_PORT_CPU))
-+		link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP);
-+	else
-+		link->link = true;
-+
-+	if (!link->link)
-+		return;
-+
-+	link->duplex = !!(status & AR40XX_PORT_DUPLEX);
-+	link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW);
-+	link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW);
-+
-+	speed = (status & AR40XX_PORT_SPEED) >>
-+		 AR40XX_PORT_STATUS_SPEED_S;
-+
-+	switch (speed) {
-+	case AR40XX_PORT_SPEED_10M:
-+		link->speed = SWITCH_PORT_SPEED_10;
-+		break;
-+	case AR40XX_PORT_SPEED_100M:
-+		link->speed = SWITCH_PORT_SPEED_100;
-+		break;
-+	case AR40XX_PORT_SPEED_1000M:
-+		link->speed = SWITCH_PORT_SPEED_1000;
-+		break;
-+	default:
-+		link->speed = SWITCH_PORT_SPEED_UNKNOWN;
-+		break;
-+	}
-+}
-+
-+static int
-+ar40xx_sw_get_port_link(struct switch_dev *dev, int port,
-+			struct switch_port_link *link)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+
-+	ar40xx_read_port_link(priv, port, link);
-+	return 0;
-+}
-+
-+static const struct switch_attr ar40xx_sw_attr_globals[] = {
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "enable_vlan",
-+		.description = "Enable VLAN mode",
-+		.set = ar40xx_sw_set_vlan,
-+		.get = ar40xx_sw_get_vlan,
-+		.max = 1
-+	},
-+	{
-+		.type = SWITCH_TYPE_NOVAL,
-+		.name = "reset_mibs",
-+		.description = "Reset all MIB counters",
-+		.set = ar40xx_sw_set_reset_mibs,
-+	},
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "enable_mirror_rx",
-+		.description = "Enable mirroring of RX packets",
-+		.set = ar40xx_sw_set_mirror_rx_enable,
-+		.get = ar40xx_sw_get_mirror_rx_enable,
-+		.max = 1
-+	},
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "enable_mirror_tx",
-+		.description = "Enable mirroring of TX packets",
-+		.set = ar40xx_sw_set_mirror_tx_enable,
-+		.get = ar40xx_sw_get_mirror_tx_enable,
-+		.max = 1
-+	},
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "mirror_monitor_port",
-+		.description = "Mirror monitor port",
-+		.set = ar40xx_sw_set_mirror_monitor_port,
-+		.get = ar40xx_sw_get_mirror_monitor_port,
-+		.max = AR40XX_NUM_PORTS - 1
-+	},
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "mirror_source_port",
-+		.description = "Mirror source port",
-+		.set = ar40xx_sw_set_mirror_source_port,
-+		.get = ar40xx_sw_get_mirror_source_port,
-+		.max = AR40XX_NUM_PORTS - 1
-+	},
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "linkdown",
-+		.description = "Link down all the PHYs",
-+		.set = ar40xx_sw_set_linkdown,
-+		.max = 1
-+	},
-+};
-+
-+static const struct switch_attr ar40xx_sw_attr_port[] = {
-+	{
-+		.type = SWITCH_TYPE_NOVAL,
-+		.name = "reset_mib",
-+		.description = "Reset single port MIB counters",
-+		.set = ar40xx_sw_set_port_reset_mib,
-+	},
-+	{
-+		.type = SWITCH_TYPE_STRING,
-+		.name = "mib",
-+		.description = "Get port's MIB counters",
-+		.set = NULL,
-+		.get = ar40xx_sw_get_port_mib,
-+	},
-+};
-+
-+const struct switch_attr ar40xx_sw_attr_vlan[] = {
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "vid",
-+		.description = "VLAN ID (0-4094)",
-+		.set = ar40xx_sw_set_vid,
-+		.get = ar40xx_sw_get_vid,
-+		.max = 4094,
-+	},
-+};
-+
-+/* End of swconfig support */
-+
-+static int
-+ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
-+{
-+	int timeout = 20;
-+	u32 t;
-+
-+	while (1) {
-+		t = ar40xx_read(priv, reg);
-+		if ((t & mask) == val)
-+			return 0;
-+
-+		if (timeout-- <= 0)
-+			break;
-+
-+		usleep_range(10, 20);
-+	}
-+
-+	pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n",
-+	       (unsigned int)reg, t, mask, val);
-+	return -ETIMEDOUT;
-+}
-+
-+static int
-+ar40xx_atu_flush(struct ar40xx_priv *priv)
-+{
-+	int ret;
-+
-+	ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC,
-+			      AR40XX_ATU_FUNC_BUSY, 0);
-+	if (!ret)
-+		ar40xx_write(priv, AR40XX_REG_ATU_FUNC,
-+			     AR40XX_ATU_FUNC_OP_FLUSH |
-+			     AR40XX_ATU_FUNC_BUSY);
-+
-+	return ret;
-+}
-+
-+static void
-+ar40xx_ess_reset(struct ar40xx_priv *priv)
-+{
-+	reset_control_assert(priv->ess_rst);
-+	mdelay(10);
-+	reset_control_deassert(priv->ess_rst);
-+	/* Waiting for all inner tables init done.
-+	  * It cost 5~10ms.
-+	  */
-+	mdelay(10);
-+
-+	pr_info("ESS reset ok!\n");
-+}
-+
-+/* Start of psgmii self test */
-+
-+static void
-+ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv)
-+{
-+	u32 n;
-+	struct mii_bus *bus = priv->mii_bus;
-+	/* reset phy psgmii */
-+	/* fix phy psgmii RX 20bit */
-+	mdiobus_write(bus, 5, 0x0, 0x005b);
-+	/* reset phy psgmii */
-+	mdiobus_write(bus, 5, 0x0, 0x001b);
-+	/* release reset phy psgmii */
-+	mdiobus_write(bus, 5, 0x0, 0x005b);
-+
-+	for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
-+		u16 status;
-+
-+		status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28);
-+		if (status & BIT(0))
-+			break;
-+		/* Polling interval to check PSGMII PLL in malibu is ready
-+		  * the worst time is 8.67ms
-+		  * for 25MHz reference clock
-+		  * [512+(128+2048)*49]*80ns+100us
-+		  */
-+		mdelay(2);
-+	}
-+
-+	/*check malibu psgmii calibration done end..*/
-+
-+	/*freeze phy psgmii RX CDR*/
-+	mdiobus_write(bus, 5, 0x1a, 0x2230);
-+
-+	ar40xx_ess_reset(priv);
-+
-+	/*check psgmii calibration done start*/
-+	for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
-+		u32 status;
-+
-+		status = ar40xx_psgmii_read(priv, 0xa0);
-+		if (status & BIT(0))
-+			break;
-+		/* Polling interval to check PSGMII PLL in ESS is ready */
-+		mdelay(2);
-+	}
-+
-+	/* check dakota psgmii calibration done end..*/
-+
-+	/* relesae phy psgmii RX CDR */
-+	mdiobus_write(bus, 5, 0x1a, 0x3230);
-+	/* release phy psgmii RX 20bit */
-+	mdiobus_write(bus, 5, 0x0, 0x005f);
-+}
-+
-+static void
-+ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy)
-+{
-+	int j;
-+	u32 tx_ok, tx_error;
-+	u32 rx_ok, rx_error;
-+	u32 tx_ok_high16;
-+	u32 rx_ok_high16;
-+	u32 tx_all_ok, rx_all_ok;
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	mdiobus_write(bus, phy, 0x0, 0x9000);
-+	mdiobus_write(bus, phy, 0x0, 0x4140);
-+
-+	for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
-+		u16 status;
-+
-+		status = mdiobus_read(bus, phy, 0x11);
-+		if (status & AR40XX_PHY_SPEC_STATUS_LINK)
-+			break;
-+		/* the polling interval to check if the PHY link up or not
-+		  * maxwait_timer: 750 ms +/-10 ms
-+		  * minwait_timer : 1 us +/- 0.1us
-+		  * time resides in minwait_timer ~ maxwait_timer
-+		  * see IEEE 802.3 section 40.4.5.2
-+		  */
-+		mdelay(8);
-+	}
-+
-+	/* enable check */
-+	ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);
-+	ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);
-+
-+	/* start traffic */
-+	ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);
-+	/* wait for all traffic end
-+	  * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
-+	  */
-+	mdelay(50);
-+
-+	/* check counter */
-+	tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
-+	tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
-+	tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
-+	rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
-+	rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
-+	rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
-+	tx_all_ok = tx_ok + (tx_ok_high16 << 16);
-+	rx_all_ok = rx_ok + (rx_ok_high16 << 16);
-+	if (tx_all_ok == 0x1000 && tx_error == 0) {
-+		/* success */
-+		priv->phy_t_status &= (~BIT(phy));
-+	} else {
-+		pr_info("PHY %d single test PSGMII issue happen!\n", phy);
-+		priv->phy_t_status |= BIT(phy);
-+	}
-+
-+	mdiobus_write(bus, phy, 0x0, 0x1840);
-+}
-+
-+static void
-+ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv)
-+{
-+	int phy, j;
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	mdiobus_write(bus, 0x1f, 0x0, 0x9000);
-+	mdiobus_write(bus, 0x1f, 0x0, 0x4140);
-+
-+	for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
-+		for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+			u16 status;
-+
-+			status = mdiobus_read(bus, phy, 0x11);
-+			if (!(status & BIT(10)))
-+				break;
-+		}
-+
-+		if (phy >= (AR40XX_NUM_PORTS - 1))
-+			break;
-+		/* The polling interva to check if the PHY link up or not */
-+		mdelay(8);
-+	}
-+	/* enable check */
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);
-+
-+	/* start traffic */
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);
-+	/* wait for all traffic end
-+	  * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
-+	  */
-+	mdelay(50);
-+
-+	for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+		u32 tx_ok, tx_error;
-+		u32 rx_ok, rx_error;
-+		u32 tx_ok_high16;
-+		u32 rx_ok_high16;
-+		u32 tx_all_ok, rx_all_ok;
-+
-+		/* check counter */
-+		tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
-+		tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
-+		tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
-+		rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
-+		rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
-+		rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
-+		tx_all_ok = tx_ok + (tx_ok_high16<<16);
-+		rx_all_ok = rx_ok + (rx_ok_high16<<16);
-+		if (tx_all_ok == 0x1000 && tx_error == 0) {
-+			/* success */
-+			priv->phy_t_status &= ~BIT(phy + 8);
-+		} else {
-+			pr_info("PHY%d test see issue!\n", phy);
-+			priv->phy_t_status |= BIT(phy + 8);
-+		}
-+	}
-+
-+	pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status);
-+}
-+
-+void
-+ar40xx_psgmii_self_test(struct ar40xx_priv *priv)
-+{
-+	u32 i, phy;
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	ar40xx_malibu_psgmii_ess_reset(priv);
-+
-+	/* switch to access MII reg for copper */
-+	mdiobus_write(bus, 4, 0x1f, 0x8500);
-+	for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+		/*enable phy mdio broadcast write*/
-+		ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);
-+	}
-+	/* force no link by power down */
-+	mdiobus_write(bus, 0x1f, 0x0, 0x1840);
-+	/*packet number*/
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000);
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0);
-+
-+	/*fix mdi status */
-+	mdiobus_write(bus, 0x1f, 0x10, 0x6800);
-+	for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
-+		priv->phy_t_status = 0;
-+
-+		for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+			ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
-+				AR40XX_PORT_LOOKUP_LOOPBACK,
-+				AR40XX_PORT_LOOKUP_LOOPBACK);
-+		}
-+
-+		for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
-+			ar40xx_psgmii_single_phy_testing(priv, phy);
-+
-+		ar40xx_psgmii_all_phy_testing(priv);
-+
-+		if (priv->phy_t_status)
-+			ar40xx_malibu_psgmii_ess_reset(priv);
-+		else
-+			break;
-+	}
-+
-+	if (i >= AR40XX_PSGMII_CALB_NUM)
-+		pr_info("PSGMII cannot recover\n");
-+	else
-+		pr_debug("PSGMII recovered after %d times reset\n", i);
-+
-+	/* configuration recover */
-+	/* packet number */
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);
-+	/* disable check */
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);
-+	/* disable traffic */
-+	ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);
-+}
-+
-+void
-+ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv)
-+{
-+	int phy;
-+	struct mii_bus *bus = priv->mii_bus;
-+
-+	/* disable phy internal loopback */
-+	mdiobus_write(bus, 0x1f, 0x10, 0x6860);
-+	mdiobus_write(bus, 0x1f, 0x0, 0x9040);
-+
-+	for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
-+		/* disable mac loop back */
-+		ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
-+				AR40XX_PORT_LOOKUP_LOOPBACK, 0);
-+		/* disable phy mdio broadcast write */
-+		ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);
-+	}
-+
-+	/* clear fdb entry */
-+	ar40xx_atu_flush(priv);
-+}
-+
-+/* End of psgmii self test */
-+
-+static void
-+ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode)
-+{
-+	if (mode == PORT_WRAPPER_PSGMII) {
-+		ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);
-+		ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);
-+	}
-+}
-+
-+static
-+int ar40xx_cpuport_setup(struct ar40xx_priv *priv)
-+{
-+	u32 t;
-+
-+	t = AR40XX_PORT_STATUS_TXFLOW |
-+	     AR40XX_PORT_STATUS_RXFLOW |
-+	     AR40XX_PORT_TXHALF_FLOW |
-+	     AR40XX_PORT_DUPLEX |
-+	     AR40XX_PORT_SPEED_1000M;
-+	ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
-+	usleep_range(10, 20);
-+
-+	t |= AR40XX_PORT_TX_EN |
-+	       AR40XX_PORT_RX_EN;
-+	ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
-+
-+	return 0;
-+}
-+
-+static void
-+ar40xx_init_port(struct ar40xx_priv *priv, int port)
-+{
-+	u32 t;
-+
-+	ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
-+			AR40XX_PORT_AUTO_LINK_EN, 0);
-+
-+	ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
-+
-+	ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
-+
-+	t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S;
-+	ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
-+
-+	t = AR40XX_PORT_LOOKUP_LEARN;
-+	t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
-+	ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
-+}
-+
-+void
-+ar40xx_init_globals(struct ar40xx_priv *priv)
-+{
-+	u32 t;
-+
-+	/* enable CPU port and disable mirror port */
-+	t = AR40XX_FWD_CTRL0_CPU_PORT_EN |
-+	    AR40XX_FWD_CTRL0_MIRROR_PORT;
-+	ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t);
-+
-+	/* forward multicast and broadcast frames to CPU */
-+	t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) |
-+	    (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) |
-+	    (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);
-+	ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t);
-+
-+	/* enable jumbo frames */
-+	ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE,
-+		   AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
-+
-+	/* Enable MIB counters */
-+	ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0,
-+		   AR40XX_MODULE_EN_MIB);
-+
-+	/* Disable AZ */
-+	ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0);
-+
-+	/* set flowctrl thershold for cpu port */
-+	t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
-+	      AR40XX_PORT0_FC_THRESH_OFF_DFLT;
-+	ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
-+}
-+
-+static void
-+ar40xx_malibu_init(struct ar40xx_priv *priv)
-+{
-+	int i;
-+	struct mii_bus *bus;
-+	u16 val;
-+
-+	bus = priv->mii_bus;
-+
-+	/* war to enable AZ transmitting ability */
-+	ar40xx_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1,
-+			     AR40XX_MALIBU_PSGMII_MODE_CTRL,
-+			     AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL);
-+	for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
-+		/* change malibu control_dac */
-+		val = ar40xx_phy_mmd_read(priv, i, 7,
-+					  AR40XX_MALIBU_PHY_MMD7_DAC_CTRL);
-+		val &= ~AR40XX_MALIBU_DAC_CTRL_MASK;
-+		val |= AR40XX_MALIBU_DAC_CTRL_VALUE;
-+		ar40xx_phy_mmd_write(priv, i, 7,
-+				     AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val);
-+		if (i == AR40XX_MALIBU_PHY_LAST_ADDR) {
-+			/* to avoid goes into hibernation */
-+			val = ar40xx_phy_mmd_read(priv, i, 3,
-+						  AR40XX_MALIBU_PHY_RLP_CTRL);
-+			val &= (~(1<<1));
-+			ar40xx_phy_mmd_write(priv, i, 3,
-+					     AR40XX_MALIBU_PHY_RLP_CTRL, val);
-+		}
-+	}
-+
-+	/* adjust psgmii serdes tx amp */
-+	mdiobus_write(bus, AR40XX_PSGMII_ID, AR40XX_PSGMII_TX_DRIVER_1_CTRL,
-+		      AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
-+}
-+
-+static int
-+ar40xx_hw_init(struct ar40xx_priv *priv)
-+{
-+	u32 i;
-+
-+	ar40xx_ess_reset(priv);
-+
-+	if (priv->mii_bus)
-+		ar40xx_malibu_init(priv);
-+	else
-+		return -1;
-+
-+	ar40xx_psgmii_self_test(priv);
-+	ar40xx_psgmii_self_test_clean(priv);
-+
-+	ar40xx_mac_mode_init(priv, priv->mac_mode);
-+
-+	for (i = 0; i < priv->dev.ports; i++)
-+		ar40xx_init_port(priv, i);
-+
-+	ar40xx_init_globals(priv);
-+
-+	return 0;
-+}
-+
-+/* Start of qm error WAR */
-+
-+static
-+int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id)
-+{
-+	u32 reg;
-+
-+	if (port_id < 0 || port_id > 6)
-+		return -1;
-+
-+	reg = AR40XX_REG_PORT_STATUS(port_id);
-+	return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED,
-+			(AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX));
-+}
-+
-+static
-+int ar40xx_get_qm_status(struct ar40xx_priv *priv,
-+			 u32 port_id, u32 *qm_buffer_err)
-+{
-+	u32 reg;
-+	u32 qm_val;
-+
-+	if (port_id < 1 || port_id > 5) {
-+		*qm_buffer_err = 0;
-+		return -1;
-+	}
-+
-+	if (port_id < 4) {
-+		reg = AR40XX_REG_QM_PORT0_3_QNUM;
-+		ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
-+		qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
-+		/* every 8 bits for each port */
-+		*qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
-+	} else {
-+		reg = AR40XX_REG_QM_PORT4_6_QNUM;
-+		ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
-+		qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
-+		/* every 8 bits for each port */
-+		*qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
-+	}
-+
-+	return 0;
-+}
-+
-+static void
-+ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv)
-+{
-+	static int task_count;
-+	u32 i;
-+	u32 reg, value;
-+	u32 link, speed, duplex;
-+	u32 qm_buffer_err;
-+	u16 port_phy_status[AR40XX_NUM_PORTS];
-+	static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
-+	static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
-+	struct mii_bus *bus = NULL;
-+
-+	if (!priv || !priv->mii_bus)
-+		return;
-+
-+	bus = priv->mii_bus;
-+
-+	++task_count;
-+
-+	for (i = 1; i < AR40XX_NUM_PORTS; ++i) {
-+		port_phy_status[i] =
-+			mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);
-+		speed = link = duplex = port_phy_status[i];
-+		speed &= AR40XX_PHY_SPEC_STATUS_SPEED;
-+		speed >>= 14;
-+		link &= AR40XX_PHY_SPEC_STATUS_LINK;
-+		link >>= 10;
-+		duplex &= AR40XX_PHY_SPEC_STATUS_DUPLEX;
-+		duplex >>= 13;
-+
-+		if (link != priv->ar40xx_port_old_link[i]) {
-+			++link_cnt[i];
-+			/* Up --> Down */
-+			if ((priv->ar40xx_port_old_link[i] ==
-+					AR40XX_PORT_LINK_UP) &&
-+			    (link == AR40XX_PORT_LINK_DOWN)) {
-+				/* LINK_EN disable(MAC force mode)*/
-+				reg = AR40XX_REG_PORT_STATUS(i);
-+				ar40xx_rmw(priv, reg,
-+						AR40XX_PORT_AUTO_LINK_EN, 0);
-+
-+				/* Check queue buffer */
-+				qm_err_cnt[i] = 0;
-+				ar40xx_get_qm_status(priv, i, &qm_buffer_err);
-+				if (qm_buffer_err) {
-+					priv->ar40xx_port_qm_buf[i] =
-+						AR40XX_QM_NOT_EMPTY;
-+				} else {
-+					u16 phy_val = 0;
-+
-+					priv->ar40xx_port_qm_buf[i] =
-+						AR40XX_QM_EMPTY;
-+					ar40xx_force_1g_full(priv, i);
-+					/* Ref:QCA8337 Datasheet,Clearing
-+					 * MENU_CTRL_EN prevents phy to
-+					 * stuck in 100BT mode when
-+					 * bringing up the link
-+					 */
-+					ar40xx_phy_dbg_read(priv, i-1,
-+							    AR40XX_PHY_DEBUG_0,
-+							    &phy_val);
-+					phy_val &= (~AR40XX_PHY_MANU_CTRL_EN);
-+					ar40xx_phy_dbg_write(priv, i-1,
-+							     AR40XX_PHY_DEBUG_0,
-+							     phy_val);
-+				}
-+				priv->ar40xx_port_old_link[i] = link;
-+			} else if ((priv->ar40xx_port_old_link[i] ==
-+						AR40XX_PORT_LINK_DOWN) &&
-+					(link == AR40XX_PORT_LINK_UP)) {
-+				/* Down --> Up */
-+				if (priv->port_link_up[i] < 1) {
-+					++priv->port_link_up[i];
-+				} else {
-+					/* Change port status */
-+					reg = AR40XX_REG_PORT_STATUS(i);
-+					value = ar40xx_read(priv, reg);
-+					priv->port_link_up[i] = 0;
-+
-+					value &= ~(AR40XX_PORT_DUPLEX |
-+						   AR40XX_PORT_SPEED);
-+					value |= speed | (duplex ? BIT(6) : 0);
-+					ar40xx_write(priv, reg, value);
-+					/* clock switch need such time
-+					 * to avoid glitch
-+					 */
-+					usleep_range(100, 200);
-+
-+					value |= AR40XX_PORT_AUTO_LINK_EN;
-+					ar40xx_write(priv, reg, value);
-+					/* HW need such time to make sure link
-+					 * stable before enable MAC
-+					 */
-+					usleep_range(100, 200);
-+
-+					if (speed == AR40XX_PORT_SPEED_100M) {
-+						u16 phy_val = 0;
-+						/* Enable @100M, if down to 10M
-+						 * clock will change smoothly
-+						 */
-+						ar40xx_phy_dbg_read(priv, i-1,
-+								    0,
-+								    &phy_val);
-+						phy_val |=
-+							AR40XX_PHY_MANU_CTRL_EN;
-+						ar40xx_phy_dbg_write(priv, i-1,
-+								     0,
-+								     phy_val);
-+					}
-+					priv->ar40xx_port_old_link[i] = link;
-+				}
-+			}
-+		}
-+
-+		if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {
-+			/* Check QM */
-+			ar40xx_get_qm_status(priv, i, &qm_buffer_err);
-+			if (qm_buffer_err) {
-+				++qm_err_cnt[i];
-+			} else {
-+				priv->ar40xx_port_qm_buf[i] =
-+						AR40XX_QM_EMPTY;
-+				qm_err_cnt[i] = 0;
-+				ar40xx_force_1g_full(priv, i);
-+			}
-+		}
-+	}
-+}
-+
-+static void
-+ar40xx_qm_err_check_work_task(struct work_struct *work)
-+{
-+	struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv,
-+					qm_dwork.work);
-+
-+	mutex_lock(&priv->qm_lock);
-+
-+	ar40xx_sw_mac_polling_task(priv);
-+
-+	mutex_unlock(&priv->qm_lock);
-+
-+	schedule_delayed_work(&priv->qm_dwork,
-+			      msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
-+}
-+
-+static int
-+ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv)
-+{
-+	mutex_init(&priv->qm_lock);
-+
-+	INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);
-+
-+	schedule_delayed_work(&priv->qm_dwork,
-+			      msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
-+
-+	return 0;
-+}
-+
-+/* End of qm error WAR */
-+
-+static int
-+ar40xx_vlan_init(struct ar40xx_priv *priv)
-+{
-+	int port;
-+	unsigned long bmp;
-+
-+	/* By default Enable VLAN */
-+	priv->vlan = 1;
-+	priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp;
-+	priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp;
-+	priv->vlan_tagged = priv->cpu_bmp;
-+	bmp = priv->lan_bmp;
-+	for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
-+			priv->pvid[port] = AR40XX_LAN_VLAN;
-+
-+	bmp = priv->wan_bmp;
-+	for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
-+			priv->pvid[port] = AR40XX_WAN_VLAN;
-+
-+	return 0;
-+}
-+
-+static void
-+ar40xx_mib_work_func(struct work_struct *work)
-+{
-+	struct ar40xx_priv *priv;
-+	int err;
-+
-+	priv = container_of(work, struct ar40xx_priv, mib_work.work);
-+
-+	mutex_lock(&priv->mib_lock);
-+
-+	err = ar40xx_mib_capture(priv);
-+	if (err)
-+		goto next_port;
-+
-+	ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
-+
-+next_port:
-+	priv->mib_next_port++;
-+	if (priv->mib_next_port >= priv->dev.ports)
-+		priv->mib_next_port = 0;
-+
-+	mutex_unlock(&priv->mib_lock);
-+
-+	schedule_delayed_work(&priv->mib_work,
-+			      msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
-+}
-+
-+static void
-+ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
-+{
-+	u32 t;
-+	u32 egress, ingress;
-+	u32 pvid = priv->vlan_id[priv->pvid[port]];
-+
-+	if (priv->vlan) {
-+		egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
-+		ingress = AR40XX_IN_SECURE;
-+	} else {
-+		egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
-+		ingress = AR40XX_IN_PORT_ONLY;
-+	}
-+
-+	t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
-+	t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
-+	ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
-+
-+	t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
-+	t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
-+	ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
-+
-+	t = members;
-+	t |= AR40XX_PORT_LOOKUP_LEARN;
-+	t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;
-+	t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
-+	ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
-+}
-+
-+static void
-+ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val)
-+{
-+	if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1,
-+			    AR40XX_VTU_FUNC1_BUSY, 0))
-+		return;
-+
-+	if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD)
-+		ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val);
-+
-+	op |= AR40XX_VTU_FUNC1_BUSY;
-+	ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op);
-+}
-+
-+static void
-+ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask)
-+{
-+	u32 op;
-+	u32 val;
-+	int i;
-+
-+	op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S);
-+	val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL;
-+	for (i = 0; i < AR40XX_NUM_PORTS; i++) {
-+		u32 mode;
-+
-+		if ((port_mask & BIT(i)) == 0)
-+			mode = AR40XX_VTU_FUNC0_EG_MODE_NOT;
-+		else if (priv->vlan == 0)
-+			mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP;
-+		else if ((priv->vlan_tagged & BIT(i)) ||
-+			 (priv->vlan_id[priv->pvid[i]] != vid))
-+			mode = AR40XX_VTU_FUNC0_EG_MODE_TAG;
-+		else
-+			mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG;
-+
-+		val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i);
-+	}
-+	ar40xx_vtu_op(priv, op, val);
-+}
-+
-+static void
-+ar40xx_vtu_flush(struct ar40xx_priv *priv)
-+{
-+	ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0);
-+}
-+
-+static int
-+ar40xx_sw_hw_apply(struct switch_dev *dev)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	u8 portmask[AR40XX_NUM_PORTS];
-+	int i, j;
-+
-+	mutex_lock(&priv->reg_mutex);
-+	/* flush all vlan entries */
-+	ar40xx_vtu_flush(priv);
-+
-+	memset(portmask, 0, sizeof(portmask));
-+	if (priv->vlan) {
-+		for (j = 0; j < AR40XX_MAX_VLANS; j++) {
-+			u8 vp = priv->vlan_table[j];
-+
-+			if (!vp)
-+				continue;
-+
-+			for (i = 0; i < dev->ports; i++) {
-+				u8 mask = BIT(i);
-+
-+				if (vp & mask)
-+					portmask[i] |= vp & ~mask;
-+			}
-+
-+			ar40xx_vtu_load_vlan(priv, priv->vlan_id[j],
-+					     priv->vlan_table[j]);
-+		}
-+	} else {
-+		/* 8021q vlan disabled */
-+		for (i = 0; i < dev->ports; i++) {
-+			if (i == AR40XX_PORT_CPU)
-+				continue;
-+
-+			portmask[i] = BIT(AR40XX_PORT_CPU);
-+			portmask[AR40XX_PORT_CPU] |= BIT(i);
-+		}
-+	}
-+
-+	/* update the port destination mask registers and tag settings */
-+	for (i = 0; i < dev->ports; i++)
-+		ar40xx_setup_port(priv, i, portmask[i]);
-+
-+	ar40xx_set_mirror_regs(priv);
-+
-+	mutex_unlock(&priv->reg_mutex);
-+	return 0;
-+}
-+
-+static int
-+ar40xx_sw_reset_switch(struct switch_dev *dev)
-+{
-+	struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
-+	int i, rv;
-+
-+	mutex_lock(&priv->reg_mutex);
-+	memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) -
-+		offsetof(struct ar40xx_priv, vlan));
-+
-+	for (i = 0; i < AR40XX_MAX_VLANS; i++)
-+		priv->vlan_id[i] = i;
-+
-+	ar40xx_vlan_init(priv);
-+
-+	priv->mirror_rx = false;
-+	priv->mirror_tx = false;
-+	priv->source_port = 0;
-+	priv->monitor_port = 0;
-+
-+	mutex_unlock(&priv->reg_mutex);
-+
-+	rv = ar40xx_sw_hw_apply(dev);
-+	return rv;
-+}
-+
-+static int
-+ar40xx_start(struct ar40xx_priv *priv)
-+{
-+	int ret;
-+
-+	ret = ar40xx_hw_init(priv);
-+	if (ret)
-+		return ret;
-+
-+	ret = ar40xx_sw_reset_switch(&priv->dev);
-+	if (ret)
-+		return ret;
-+
-+	/* at last, setup cpu port */
-+	ret = ar40xx_cpuport_setup(priv);
-+	if (ret)
-+		return ret;
-+
-+	schedule_delayed_work(&priv->mib_work,
-+			      msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
-+
-+	ar40xx_qm_err_check_work_start(priv);
-+
-+	return 0;
-+}
-+
-+static const struct switch_dev_ops ar40xx_sw_ops = {
-+	.attr_global = {
-+		.attr = ar40xx_sw_attr_globals,
-+		.n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals),
-+	},
-+	.attr_port = {
-+		.attr = ar40xx_sw_attr_port,
-+		.n_attr = ARRAY_SIZE(ar40xx_sw_attr_port),
-+	},
-+	.attr_vlan = {
-+		.attr = ar40xx_sw_attr_vlan,
-+		.n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan),
-+	},
-+	.get_port_pvid = ar40xx_sw_get_pvid,
-+	.set_port_pvid = ar40xx_sw_set_pvid,
-+	.get_vlan_ports = ar40xx_sw_get_ports,
-+	.set_vlan_ports = ar40xx_sw_set_ports,
-+	.apply_config = ar40xx_sw_hw_apply,
-+	.reset_switch = ar40xx_sw_reset_switch,
-+	.get_port_link = ar40xx_sw_get_port_link,
-+};
-+
-+/* Start of phy driver support */
-+
-+static const u32 ar40xx_phy_ids[] = {
-+	0x004dd0b1,
-+	0x004dd0b2, /* AR40xx */
-+};
-+
-+static bool
-+ar40xx_phy_match(u32 phy_id)
-+{
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(ar40xx_phy_ids); i++)
-+		if (phy_id == ar40xx_phy_ids[i])
-+			return true;
-+
-+	return false;
-+}
-+
-+static bool
-+is_ar40xx_phy(struct mii_bus *bus)
-+{
-+	unsigned i;
-+
-+	for (i = 0; i < 4; i++) {
-+		u32 phy_id;
-+
-+		phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
-+		phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
-+		if (!ar40xx_phy_match(phy_id))
-+			return false;
-+	}
-+
-+	return true;
-+}
-+
-+static int
-+ar40xx_phy_probe(struct phy_device *phydev)
-+{
-+	if (!is_ar40xx_phy(phydev->mdio.bus))
-+		return -ENODEV;
-+
-+	ar40xx_priv->mii_bus = phydev->mdio.bus;
-+	phydev->priv = ar40xx_priv;
-+	if (phydev->mdio.addr == 0)
-+		ar40xx_priv->phy = phydev;
-+
-+	phydev->supported |= SUPPORTED_1000baseT_Full;
-+	phydev->advertising |= ADVERTISED_1000baseT_Full;
-+	return 0;
-+}
-+
-+static void
-+ar40xx_phy_remove(struct phy_device *phydev)
-+{
-+	ar40xx_priv->mii_bus = NULL;
-+	phydev->priv = NULL;
-+}
-+
-+static int
-+ar40xx_phy_config_init(struct phy_device *phydev)
-+{
-+	return 0;
-+}
-+
-+static int
-+ar40xx_phy_read_status(struct phy_device *phydev)
-+{
-+	if (phydev->mdio.addr != 0)
-+		return genphy_read_status(phydev);
-+
-+	return 0;
-+}
-+
-+static int
-+ar40xx_phy_config_aneg(struct phy_device *phydev)
-+{
-+	if (phydev->mdio.addr == 0)
-+		return 0;
-+
-+	return genphy_config_aneg(phydev);
-+}
-+
-+static struct phy_driver ar40xx_phy_driver = {
-+	.phy_id		= 0x004d0000,
-+	.name		= "QCA Malibu",
-+	.phy_id_mask	= 0xffff0000,
-+	.features	= PHY_BASIC_FEATURES,
-+	.probe		= ar40xx_phy_probe,
-+	.remove		= ar40xx_phy_remove,
-+	.config_init	= ar40xx_phy_config_init,
-+	.config_aneg	= ar40xx_phy_config_aneg,
-+	.read_status	= ar40xx_phy_read_status,
-+};
-+
-+static uint16_t ar40xx_gpio_get_phy(unsigned int offset)
-+{
-+	return offset / 4;
-+}
-+
-+static uint16_t ar40xx_gpio_get_reg(unsigned int offset)
-+{
-+	return 0x8074 + offset % 4;
-+}
-+
-+static void ar40xx_gpio_set(struct gpio_chip *gc, unsigned int offset,
-+			    int value)
-+{
-+	struct ar40xx_priv *priv = gpiochip_get_data(gc);
-+
-+	ar40xx_phy_mmd_write(priv, ar40xx_gpio_get_phy(offset), 0x7,
-+			     ar40xx_gpio_get_reg(offset),
-+			     value ? 0xA000 : 0x8000);
-+}
-+
-+static int ar40xx_gpio_get(struct gpio_chip *gc, unsigned offset)
-+{
-+	struct ar40xx_priv *priv = gpiochip_get_data(gc);
-+
-+	return ar40xx_phy_mmd_read(priv, ar40xx_gpio_get_phy(offset), 0x7,
-+				   ar40xx_gpio_get_reg(offset)) == 0xA000;
-+}
-+
-+static int ar40xx_gpio_get_dir(struct gpio_chip *gc, unsigned offset)
-+{
-+	return 0; /* only out direction */
-+}
-+
-+static int ar40xx_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
-+			       int value)
-+{
-+	/*
-+	 * the direction out value is used to set the initial value.
-+	 * support of this function is required by leds-gpio.c
-+	 */
-+	ar40xx_gpio_set(gc, offset, value);
-+	return 0;
-+}
-+
-+static void ar40xx_register_gpio(struct device *pdev,
-+				 struct ar40xx_priv *priv,
-+				 struct device_node *switch_node)
-+{
-+	struct gpio_chip *gc;
-+	int err;
-+
-+	gc = devm_kzalloc(pdev, sizeof(*gc), GFP_KERNEL);
-+	if (!gc)
-+		return;
-+
-+	gc->label = "ar40xx_gpio",
-+	gc->base = -1,
-+	gc->ngpio = 5 /* mmd 0 - 4 */ * 4 /* 0x8074 - 0x8077 */,
-+	gc->parent = pdev;
-+	gc->owner = THIS_MODULE;
-+
-+	gc->get_direction = ar40xx_gpio_get_dir;
-+	gc->direction_output = ar40xx_gpio_dir_out;
-+	gc->get = ar40xx_gpio_get;
-+	gc->set = ar40xx_gpio_set;
-+	gc->can_sleep = true;
-+	gc->label = priv->dev.name;
-+	gc->of_node = switch_node;
-+
-+	err = devm_gpiochip_add_data(pdev, gc, priv);
-+	if (err != 0)
-+		dev_err(pdev, "Failed to register gpio %d.\n", err);
-+}
-+
-+/* End of phy driver support */
-+
-+/* Platform driver probe function */
-+
-+static int ar40xx_probe(struct platform_device *pdev)
-+{
-+	struct device_node *switch_node;
-+	struct device_node *psgmii_node;
-+	const __be32 *mac_mode;
-+	struct clk *ess_clk;
-+	struct switch_dev *swdev;
-+	struct ar40xx_priv *priv;
-+	u32 len;
-+	u32 num_mibs;
-+	struct resource psgmii_base = {0};
-+	struct resource switch_base = {0};
-+	int ret;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, priv);
-+	ar40xx_priv = priv;
-+
-+	switch_node = of_node_get(pdev->dev.of_node);
-+	if (of_address_to_resource(switch_node, 0, &switch_base) != 0)
-+		return -EIO;
-+
-+	priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base);
-+	if (IS_ERR(priv->hw_addr)) {
-+		dev_err(&pdev->dev, "Failed to ioremap switch_base!\n");
-+		return PTR_ERR(priv->hw_addr);
-+	}
-+
-+	/*psgmii dts get*/
-+	psgmii_node = of_find_node_by_name(NULL, "ess-psgmii");
-+	if (!psgmii_node) {
-+		dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n");
-+		return -EINVAL;
-+	}
-+
-+	if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0)
-+		return -EIO;
-+
-+	priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base);
-+	if (IS_ERR(priv->psgmii_hw_addr)) {
-+		dev_err(&pdev->dev, "psgmii ioremap fail!\n");
-+		return PTR_ERR(priv->psgmii_hw_addr);
-+	}
-+
-+	mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
-+	if (!mac_mode) {
-+		dev_err(&pdev->dev, "Failed to read switch_mac_mode\n");
-+		return -EINVAL;
-+	}
-+	priv->mac_mode = be32_to_cpup(mac_mode);
-+
-+	ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
-+	if (ess_clk)
-+		clk_prepare_enable(ess_clk);
-+
-+	priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
-+	if (IS_ERR(priv->ess_rst)) {
-+		dev_err(&pdev->dev, "Failed to get ess_rst control!\n");
-+		return PTR_ERR(priv->ess_rst);
-+	}
-+
-+	if (of_property_read_u32(switch_node, "switch_cpu_bmp",
-+				 &priv->cpu_bmp) ||
-+	    of_property_read_u32(switch_node, "switch_lan_bmp",
-+				 &priv->lan_bmp) ||
-+	    of_property_read_u32(switch_node, "switch_wan_bmp",
-+				 &priv->wan_bmp)) {
-+		dev_err(&pdev->dev, "Failed to read port properties\n");
-+		return -EIO;
-+	}
-+
-+	ret = phy_driver_register(&ar40xx_phy_driver, THIS_MODULE);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to register ar40xx phy driver!\n");
-+		return -EIO;
-+	}
-+
-+	mutex_init(&priv->reg_mutex);
-+	mutex_init(&priv->mib_lock);
-+	INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);
-+
-+	/* register switch */
-+	swdev = &priv->dev;
-+
-+	swdev->alias = dev_name(&priv->mii_bus->dev);
-+
-+	swdev->cpu_port = AR40XX_PORT_CPU;
-+	swdev->name = "QCA AR40xx";
-+	swdev->vlans = AR40XX_MAX_VLANS;
-+	swdev->ports = AR40XX_NUM_PORTS;
-+	swdev->ops = &ar40xx_sw_ops;
-+	ret = register_switch(swdev, NULL);
-+	if (ret)
-+		goto err_unregister_phy;
-+
-+	num_mibs = ARRAY_SIZE(ar40xx_mibs);
-+	len = priv->dev.ports * num_mibs *
-+	      sizeof(*priv->mib_stats);
-+	priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
-+	if (!priv->mib_stats) {
-+		ret = -ENOMEM;
-+		goto err_unregister_switch;
-+	}
-+
-+	ar40xx_start(priv);
-+
-+	if (of_property_read_bool(switch_node, "gpio-controller"))
-+		ar40xx_register_gpio(&pdev->dev, ar40xx_priv, switch_node);
-+
-+	return 0;
-+
-+err_unregister_switch:
-+	unregister_switch(&priv->dev);
-+err_unregister_phy:
-+	phy_driver_unregister(&ar40xx_phy_driver);
-+	platform_set_drvdata(pdev, NULL);
-+	return ret;
-+}
-+
-+static int ar40xx_remove(struct platform_device *pdev)
-+{
-+	struct ar40xx_priv *priv = platform_get_drvdata(pdev);
-+
-+	cancel_delayed_work_sync(&priv->qm_dwork);
-+	cancel_delayed_work_sync(&priv->mib_work);
-+
-+	unregister_switch(&priv->dev);
-+
-+	phy_driver_unregister(&ar40xx_phy_driver);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id ar40xx_of_mtable[] = {
-+	{.compatible = "qcom,ess-switch" },
-+	{}
-+};
-+
-+struct platform_driver ar40xx_drv = {
-+	.probe = ar40xx_probe,
-+	.remove = ar40xx_remove,
-+	.driver = {
-+		.name    = "ar40xx",
-+		.of_match_table = ar40xx_of_mtable,
-+	},
-+};
-+
-+module_platform_driver(ar40xx_drv);
-+
-+MODULE_DESCRIPTION("IPQ40XX ESS driver");
-+MODULE_LICENSE("Dual BSD/GPL");
---- /dev/null
-+++ b/drivers/net/phy/ar40xx.h
-@@ -0,0 +1,337 @@
-+/*
-+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+ #ifndef __AR40XX_H
-+#define __AR40XX_H
-+
-+#define AR40XX_MAX_VLANS	128
-+#define AR40XX_NUM_PORTS	6
-+#define AR40XX_NUM_PHYS	5
-+
-+#define BITS(_s, _n)	(((1UL << (_n)) - 1) << _s)
-+
-+struct ar40xx_priv {
-+	struct switch_dev dev;
-+
-+	u8  __iomem      *hw_addr;
-+	u8  __iomem      *psgmii_hw_addr;
-+	u32 mac_mode;
-+	struct reset_control *ess_rst;
-+	u32 cpu_bmp;
-+	u32 lan_bmp;
-+	u32 wan_bmp;
-+
-+	struct mii_bus *mii_bus;
-+	struct phy_device *phy;
-+
-+	/* mutex for qm task */
-+	struct mutex qm_lock;
-+	struct delayed_work qm_dwork;
-+	u32 port_link_up[AR40XX_NUM_PORTS];
-+	u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
-+	u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
-+
-+	u32 phy_t_status;
-+
-+	/* mutex for switch reg access */
-+	struct mutex reg_mutex;
-+
-+	/* mutex for mib task */
-+	struct mutex mib_lock;
-+	struct delayed_work mib_work;
-+	int mib_next_port;
-+	u64 *mib_stats;
-+
-+	char buf[2048];
-+
-+	/* all fields below will be cleared on reset */
-+	bool vlan;
-+	u16 vlan_id[AR40XX_MAX_VLANS];
-+	u8 vlan_table[AR40XX_MAX_VLANS];
-+	u8 vlan_tagged;
-+	u16 pvid[AR40XX_NUM_PORTS];
-+
-+	/* mirror */
-+	bool mirror_rx;
-+	bool mirror_tx;
-+	int source_port;
-+	int monitor_port;
-+};
-+
-+#define AR40XX_PORT_LINK_UP 1
-+#define AR40XX_PORT_LINK_DOWN 0
-+#define AR40XX_QM_NOT_EMPTY  1
-+#define AR40XX_QM_EMPTY  0
-+
-+#define AR40XX_LAN_VLAN	1
-+#define AR40XX_WAN_VLAN	2
-+
-+enum ar40xx_port_wrapper_cfg {
-+	PORT_WRAPPER_PSGMII = 0,
-+};
-+
-+struct ar40xx_mib_desc {
-+	u32 size;
-+	u32 offset;
-+	const char *name;
-+};
-+
-+#define AR40XX_PORT_CPU	0
-+
-+#define AR40XX_PSGMII_MODE_CONTROL	0x1b4
-+#define   AR40XX_PSGMII_ATHR_CSCO_MODE_25M	BIT(0)
-+
-+#define AR40XX_PSGMIIPHY_TX_CONTROL	 0x288
-+
-+#define AR40XX_MII_ATH_MMD_ADDR		0x0d
-+#define AR40XX_MII_ATH_MMD_DATA		0x0e
-+#define AR40XX_MII_ATH_DBG_ADDR		0x1d
-+#define AR40XX_MII_ATH_DBG_DATA		0x1e
-+
-+#define AR40XX_STATS_RXBROAD		0x00
-+#define AR40XX_STATS_RXPAUSE		0x04
-+#define AR40XX_STATS_RXMULTI		0x08
-+#define AR40XX_STATS_RXFCSERR		0x0c
-+#define AR40XX_STATS_RXALIGNERR		0x10
-+#define AR40XX_STATS_RXRUNT		0x14
-+#define AR40XX_STATS_RXFRAGMENT		0x18
-+#define AR40XX_STATS_RX64BYTE		0x1c
-+#define AR40XX_STATS_RX128BYTE		0x20
-+#define AR40XX_STATS_RX256BYTE		0x24
-+#define AR40XX_STATS_RX512BYTE		0x28
-+#define AR40XX_STATS_RX1024BYTE		0x2c
-+#define AR40XX_STATS_RX1518BYTE		0x30
-+#define AR40XX_STATS_RXMAXBYTE		0x34
-+#define AR40XX_STATS_RXTOOLONG		0x38
-+#define AR40XX_STATS_RXGOODBYTE		0x3c
-+#define AR40XX_STATS_RXBADBYTE		0x44
-+#define AR40XX_STATS_RXOVERFLOW		0x4c
-+#define AR40XX_STATS_FILTERED		0x50
-+#define AR40XX_STATS_TXBROAD		0x54
-+#define AR40XX_STATS_TXPAUSE		0x58
-+#define AR40XX_STATS_TXMULTI		0x5c
-+#define AR40XX_STATS_TXUNDERRUN		0x60
-+#define AR40XX_STATS_TX64BYTE		0x64
-+#define AR40XX_STATS_TX128BYTE		0x68
-+#define AR40XX_STATS_TX256BYTE		0x6c
-+#define AR40XX_STATS_TX512BYTE		0x70
-+#define AR40XX_STATS_TX1024BYTE		0x74
-+#define AR40XX_STATS_TX1518BYTE		0x78
-+#define AR40XX_STATS_TXMAXBYTE		0x7c
-+#define AR40XX_STATS_TXOVERSIZE		0x80
-+#define AR40XX_STATS_TXBYTE		0x84
-+#define AR40XX_STATS_TXCOLLISION	0x8c
-+#define AR40XX_STATS_TXABORTCOL		0x90
-+#define AR40XX_STATS_TXMULTICOL		0x94
-+#define AR40XX_STATS_TXSINGLECOL	0x98
-+#define AR40XX_STATS_TXEXCDEFER		0x9c
-+#define AR40XX_STATS_TXDEFER		0xa0
-+#define AR40XX_STATS_TXLATECOL		0xa4
-+
-+#define AR40XX_REG_MODULE_EN			0x030
-+#define   AR40XX_MODULE_EN_MIB			BIT(0)
-+
-+#define AR40XX_REG_MIB_FUNC			0x034
-+#define   AR40XX_MIB_BUSY		BIT(17)
-+#define   AR40XX_MIB_CPU_KEEP			BIT(20)
-+#define   AR40XX_MIB_FUNC		BITS(24, 3)
-+#define   AR40XX_MIB_FUNC_S		24
-+#define   AR40XX_MIB_FUNC_NO_OP		0x0
-+#define   AR40XX_MIB_FUNC_FLUSH		0x1
-+
-+#define AR40XX_REG_PORT_STATUS(_i)		(0x07c + (_i) * 4)
-+#define   AR40XX_PORT_SPEED			BITS(0, 2)
-+#define   AR40XX_PORT_STATUS_SPEED_S	0
-+#define   AR40XX_PORT_TX_EN			BIT(2)
-+#define   AR40XX_PORT_RX_EN			BIT(3)
-+#define   AR40XX_PORT_STATUS_TXFLOW	BIT(4)
-+#define   AR40XX_PORT_STATUS_RXFLOW	BIT(5)
-+#define   AR40XX_PORT_DUPLEX			BIT(6)
-+#define   AR40XX_PORT_TXHALF_FLOW		BIT(7)
-+#define   AR40XX_PORT_STATUS_LINK_UP	BIT(8)
-+#define   AR40XX_PORT_AUTO_LINK_EN		BIT(9)
-+#define   AR40XX_PORT_STATUS_FLOW_CONTROL  BIT(12)
-+
-+#define AR40XX_REG_MAX_FRAME_SIZE		0x078
-+#define   AR40XX_MAX_FRAME_SIZE_MTU		BITS(0, 14)
-+
-+#define AR40XX_REG_PORT_HEADER(_i)		(0x09c + (_i) * 4)
-+
-+#define AR40XX_REG_EEE_CTRL			0x100
-+#define   AR40XX_EEE_CTRL_DISABLE_PHY(_i)	BIT(4 + (_i) * 2)
-+
-+#define AR40XX_REG_PORT_VLAN0(_i)		(0x420 + (_i) * 0x8)
-+#define   AR40XX_PORT_VLAN0_DEF_SVID		BITS(0, 12)
-+#define   AR40XX_PORT_VLAN0_DEF_SVID_S		0
-+#define   AR40XX_PORT_VLAN0_DEF_CVID		BITS(16, 12)
-+#define   AR40XX_PORT_VLAN0_DEF_CVID_S		16
-+
-+#define AR40XX_REG_PORT_VLAN1(_i)		(0x424 + (_i) * 0x8)
-+#define   AR40XX_PORT_VLAN1_PORT_VLAN_PROP	BIT(6)
-+#define   AR40XX_PORT_VLAN1_OUT_MODE		BITS(12, 2)
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_S		12
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_UNMOD	0
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_UNTAG	1
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_TAG		2
-+#define   AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH	3
-+
-+#define AR40XX_REG_VTU_FUNC0			0x0610
-+#define   AR40XX_VTU_FUNC0_EG_MODE		BITS(4, 14)
-+#define   AR40XX_VTU_FUNC0_EG_MODE_S(_i)	(4 + (_i) * 2)
-+#define   AR40XX_VTU_FUNC0_EG_MODE_KEEP		0
-+#define   AR40XX_VTU_FUNC0_EG_MODE_UNTAG	1
-+#define   AR40XX_VTU_FUNC0_EG_MODE_TAG		2
-+#define   AR40XX_VTU_FUNC0_EG_MODE_NOT		3
-+#define   AR40XX_VTU_FUNC0_IVL			BIT(19)
-+#define   AR40XX_VTU_FUNC0_VALID		BIT(20)
-+
-+#define AR40XX_REG_VTU_FUNC1			0x0614
-+#define   AR40XX_VTU_FUNC1_OP			BITS(0, 3)
-+#define   AR40XX_VTU_FUNC1_OP_NOOP		0
-+#define   AR40XX_VTU_FUNC1_OP_FLUSH		1
-+#define   AR40XX_VTU_FUNC1_OP_LOAD		2
-+#define   AR40XX_VTU_FUNC1_OP_PURGE		3
-+#define   AR40XX_VTU_FUNC1_OP_REMOVE_PORT	4
-+#define   AR40XX_VTU_FUNC1_OP_GET_NEXT		5
-+#define   AR40XX7_VTU_FUNC1_OP_GET_ONE		6
-+#define   AR40XX_VTU_FUNC1_FULL			BIT(4)
-+#define   AR40XX_VTU_FUNC1_PORT			BIT(8, 4)
-+#define   AR40XX_VTU_FUNC1_PORT_S		8
-+#define   AR40XX_VTU_FUNC1_VID			BIT(16, 12)
-+#define   AR40XX_VTU_FUNC1_VID_S		16
-+#define   AR40XX_VTU_FUNC1_BUSY			BIT(31)
-+
-+#define AR40XX_REG_FWD_CTRL0			0x620
-+#define   AR40XX_FWD_CTRL0_CPU_PORT_EN		BIT(10)
-+#define   AR40XX_FWD_CTRL0_MIRROR_PORT		BITS(4, 4)
-+#define   AR40XX_FWD_CTRL0_MIRROR_PORT_S	4
-+
-+#define AR40XX_REG_FWD_CTRL1			0x624
-+#define   AR40XX_FWD_CTRL1_UC_FLOOD		BITS(0, 7)
-+#define   AR40XX_FWD_CTRL1_UC_FLOOD_S		0
-+#define   AR40XX_FWD_CTRL1_MC_FLOOD		BITS(8, 7)
-+#define   AR40XX_FWD_CTRL1_MC_FLOOD_S		8
-+#define   AR40XX_FWD_CTRL1_BC_FLOOD		BITS(16, 7)
-+#define   AR40XX_FWD_CTRL1_BC_FLOOD_S		16
-+#define   AR40XX_FWD_CTRL1_IGMP			BITS(24, 7)
-+#define   AR40XX_FWD_CTRL1_IGMP_S		24
-+
-+#define AR40XX_REG_PORT_LOOKUP(_i)		(0x660 + (_i) * 0xc)
-+#define   AR40XX_PORT_LOOKUP_MEMBER		BITS(0, 7)
-+#define   AR40XX_PORT_LOOKUP_IN_MODE		BITS(8, 2)
-+#define   AR40XX_PORT_LOOKUP_IN_MODE_S		8
-+#define   AR40XX_PORT_LOOKUP_STATE		BITS(16, 3)
-+#define   AR40XX_PORT_LOOKUP_STATE_S		16
-+#define   AR40XX_PORT_LOOKUP_LEARN		BIT(20)
-+#define   AR40XX_PORT_LOOKUP_LOOPBACK		BIT(21)
-+#define   AR40XX_PORT_LOOKUP_ING_MIRROR_EN	BIT(25)
-+
-+#define AR40XX_REG_ATU_FUNC			0x60c
-+#define   AR40XX_ATU_FUNC_OP			BITS(0, 4)
-+#define   AR40XX_ATU_FUNC_OP_NOOP		0x0
-+#define   AR40XX_ATU_FUNC_OP_FLUSH		0x1
-+#define   AR40XX_ATU_FUNC_OP_LOAD		0x2
-+#define   AR40XX_ATU_FUNC_OP_PURGE		0x3
-+#define   AR40XX_ATU_FUNC_OP_FLUSH_LOCKED	0x4
-+#define   AR40XX_ATU_FUNC_OP_FLUSH_UNICAST	0x5
-+#define   AR40XX_ATU_FUNC_OP_GET_NEXT		0x6
-+#define   AR40XX_ATU_FUNC_OP_SEARCH_MAC		0x7
-+#define   AR40XX_ATU_FUNC_OP_CHANGE_TRUNK	0x8
-+#define   AR40XX_ATU_FUNC_BUSY			BIT(31)
-+
-+#define AR40XX_REG_QM_DEBUG_ADDR		0x820
-+#define AR40XX_REG_QM_DEBUG_VALUE		0x824
-+#define   AR40XX_REG_QM_PORT0_3_QNUM		0x1d
-+#define   AR40XX_REG_QM_PORT4_6_QNUM		0x1e
-+
-+#define AR40XX_REG_PORT_HOL_CTRL1(_i)		(0x974 + (_i) * 0x8)
-+#define   AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN	BIT(16)
-+
-+#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i)	(0x9b0 + (_i) * 0x4)
-+#define   AR40XX_PORT0_FC_THRESH_ON_DFLT	0x60
-+#define   AR40XX_PORT0_FC_THRESH_OFF_DFLT	0x90
-+
-+#define AR40XX_PHY_DEBUG_0   0
-+#define AR40XX_PHY_MANU_CTRL_EN  BIT(12)
-+
-+#define AR40XX_PHY_DEBUG_2   2
-+
-+#define AR40XX_PHY_SPEC_STATUS 0x11
-+#define   AR40XX_PHY_SPEC_STATUS_LINK		BIT(10)
-+#define   AR40XX_PHY_SPEC_STATUS_DUPLEX		BIT(13)
-+#define   AR40XX_PHY_SPEC_STATUS_SPEED		BITS(14, 2)
-+
-+/* port forwarding state */
-+enum {
-+	AR40XX_PORT_STATE_DISABLED = 0,
-+	AR40XX_PORT_STATE_BLOCK = 1,
-+	AR40XX_PORT_STATE_LISTEN = 2,
-+	AR40XX_PORT_STATE_LEARN = 3,
-+	AR40XX_PORT_STATE_FORWARD = 4
-+};
-+
-+/* ingress 802.1q mode */
-+enum {
-+	AR40XX_IN_PORT_ONLY = 0,
-+	AR40XX_IN_PORT_FALLBACK = 1,
-+	AR40XX_IN_VLAN_ONLY = 2,
-+	AR40XX_IN_SECURE = 3
-+};
-+
-+/* egress 802.1q mode */
-+enum {
-+	AR40XX_OUT_KEEP = 0,
-+	AR40XX_OUT_STRIP_VLAN = 1,
-+	AR40XX_OUT_ADD_VLAN = 2
-+};
-+
-+/* port speed */
-+enum {
-+	AR40XX_PORT_SPEED_10M = 0,
-+	AR40XX_PORT_SPEED_100M = 1,
-+	AR40XX_PORT_SPEED_1000M = 2,
-+	AR40XX_PORT_SPEED_ERR = 3,
-+};
-+
-+#define AR40XX_MIB_WORK_DELAY	2000 /* msecs */
-+
-+#define AR40XX_QM_WORK_DELAY    100
-+
-+#define   AR40XX_MIB_FUNC_CAPTURE	0x3
-+
-+#define AR40XX_REG_PORT_STATS_START	0x1000
-+#define AR40XX_REG_PORT_STATS_LEN		0x100
-+
-+#define AR40XX_PORTS_ALL	0x3f
-+
-+#define AR40XX_PSGMII_ID	5
-+#define AR40XX_PSGMII_CALB_NUM	100
-+#define AR40XX_MALIBU_PSGMII_MODE_CTRL	0x6d
-+#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL	0x220c
-+#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL	0x801a
-+#define AR40XX_MALIBU_DAC_CTRL_MASK	0x380
-+#define AR40XX_MALIBU_DAC_CTRL_VALUE	0x280
-+#define AR40XX_MALIBU_PHY_RLP_CTRL       0x805a
-+#define AR40XX_PSGMII_TX_DRIVER_1_CTRL	0xb
-+#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP	0x8a
-+#define AR40XX_MALIBU_PHY_LAST_ADDR	4
-+
-+static inline struct ar40xx_priv *
-+swdev_to_ar40xx(struct switch_dev *swdev)
-+{
-+	return container_of(swdev, struct ar40xx_priv, dev);
-+}
-+
-+#endif
---- /dev/null
-+++ b/drivers/net/phy/mdio-ipq40xx.c
-@@ -0,0 +1,203 @@
-+/*
-+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/io.h>
-+#include <linux/of_address.h>
-+#include <linux/of_mdio.h>
-+#include <linux/phy.h>
-+#include <linux/platform_device.h>
-+
-+#define MDIO_CTRL_0_REG		0x40
-+#define MDIO_CTRL_1_REG		0x44
-+#define MDIO_CTRL_2_REG		0x48
-+#define MDIO_CTRL_3_REG		0x4c
-+#define MDIO_CTRL_4_REG		0x50
-+#define MDIO_CTRL_4_ACCESS_BUSY		BIT(16)
-+#define MDIO_CTRL_4_ACCESS_START		BIT(8)
-+#define MDIO_CTRL_4_ACCESS_CODE_READ		0
-+#define MDIO_CTRL_4_ACCESS_CODE_WRITE	1
-+#define CTRL_0_REG_DEFAULT_VALUE	0x150FF
-+
-+#define IPQ40XX_MDIO_RETRY	1000
-+#define IPQ40XX_MDIO_DELAY	10
-+
-+struct ipq40xx_mdio_data {
-+	struct mii_bus	*mii_bus;
-+	void __iomem	*membase;
-+	int		phy_irq[PHY_MAX_ADDR];
-+	struct device	*dev;
-+};
-+
-+static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am)
-+{
-+	int i;
-+
-+	for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) {
-+		unsigned int busy;
-+
-+		busy = readl(am->membase + MDIO_CTRL_4_REG) &
-+			MDIO_CTRL_4_ACCESS_BUSY;
-+		if (!busy)
-+			return 0;
-+
-+		/* BUSY might take to be cleard by 15~20 times of loop */
-+		udelay(IPQ40XX_MDIO_DELAY);
-+	}
-+
-+	dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name);
-+
-+	return -ETIMEDOUT;
-+}
-+
-+static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-+{
-+	struct ipq40xx_mdio_data *am = bus->priv;
-+	int value = 0;
-+	unsigned int cmd = 0;
-+
-+	lockdep_assert_held(&bus->mdio_lock);
-+
-+	if (ipq40xx_mdio_wait_busy(am))
-+		return -ETIMEDOUT;
-+
-+	/* issue the phy address and reg */
-+	writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
-+
-+	cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ;
-+
-+	/* issue read command */
-+	writel(cmd, am->membase + MDIO_CTRL_4_REG);
-+
-+	/* Wait read complete */
-+	if (ipq40xx_mdio_wait_busy(am))
-+		return -ETIMEDOUT;
-+
-+	/* Read data */
-+	value = readl(am->membase + MDIO_CTRL_3_REG);
-+
-+	return value;
-+}
-+
-+static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
-+			    u16 value)
-+{
-+	struct ipq40xx_mdio_data *am = bus->priv;
-+	unsigned int cmd = 0;
-+
-+	lockdep_assert_held(&bus->mdio_lock);
-+
-+	if (ipq40xx_mdio_wait_busy(am))
-+		return -ETIMEDOUT;
-+
-+	/* issue the phy address and reg */
-+	writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
-+
-+	/* issue write data */
-+	writel(value, am->membase + MDIO_CTRL_2_REG);
-+
-+	cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE;
-+	/* issue write command */
-+	writel(cmd, am->membase + MDIO_CTRL_4_REG);
-+
-+	/* Wait write complete */
-+	if (ipq40xx_mdio_wait_busy(am))
-+		return -ETIMEDOUT;
-+
-+	return 0;
-+}
-+
-+static int ipq40xx_mdio_probe(struct platform_device *pdev)
-+{
-+	struct ipq40xx_mdio_data *am;
-+	struct resource *res;
-+	int i;
-+
-+	am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL);
-+	if (!am)
-+		return -ENOMEM;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!res) {
-+		dev_err(&pdev->dev, "no iomem resource found\n");
-+		return -ENXIO;
-+	}
-+
-+	am->membase = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(am->membase)) {
-+		dev_err(&pdev->dev, "unable to ioremap registers\n");
-+		return PTR_ERR(am->membase);
-+	}
-+
-+	am->mii_bus = devm_mdiobus_alloc(&pdev->dev);
-+	if (!am->mii_bus)
-+		return  -ENOMEM;
-+
-+	writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
-+
-+	am->mii_bus->name = "ipq40xx_mdio";
-+	am->mii_bus->read = ipq40xx_mdio_read;
-+	am->mii_bus->write = ipq40xx_mdio_write;
-+	memcpy(am->mii_bus->irq, am->phy_irq, sizeof(am->phy_irq));
-+	am->mii_bus->priv = am;
-+	am->mii_bus->parent = &pdev->dev;
-+	snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
-+
-+	for (i = 0; i < PHY_MAX_ADDR; i++)
-+		am->phy_irq[i] = PHY_POLL;
-+
-+	am->dev = &pdev->dev;
-+	platform_set_drvdata(pdev, am);
-+
-+	/* edma_axi_probe() use "am" drvdata.
-+	 * ipq40xx_mdio_probe() must be called first.
-+	 */
-+	return of_mdiobus_register(am->mii_bus, pdev->dev.of_node);
-+}
-+
-+static int ipq40xx_mdio_remove(struct platform_device *pdev)
-+{
-+	struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev);
-+
-+	mdiobus_unregister(am->mii_bus);
-+	return 0;
-+}
-+
-+static const struct of_device_id ipq40xx_mdio_dt_ids[] = {
-+	{ .compatible = "qcom,ipq4019-mdio" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids);
-+
-+static struct platform_driver ipq40xx_mdio_driver = {
-+	.probe = ipq40xx_mdio_probe,
-+	.remove = ipq40xx_mdio_remove,
-+	.driver = {
-+		.name = "ipq40xx-mdio",
-+		.of_match_table = ipq40xx_mdio_dt_ids,
-+	},
-+};
-+
-+module_platform_driver(ipq40xx_mdio_driver);
-+
-+#define DRV_VERSION     "1.0"
-+
-+MODULE_DESCRIPTION("IPQ40XX MDIO interface driver");
-+MODULE_AUTHOR("Qualcomm Atheros");
-+MODULE_VERSION(DRV_VERSION);
-+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch b/target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch
deleted file mode 100644
index 676da72147..0000000000
--- a/target/linux/ipq806x/patches-4.9/701-dts-ipq4019-add-mdio-node.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 09ed737593f71bcca08a537a6c15264a1a6add08 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 01:10:33 +0100
-Subject: [PATCH] dts: ipq4019: add mdio node for ethernet
-
-This patch adds the mdio device-tree node.
-This is where the switch is connected to, so it's needed
-for the ethernet interfaces.
-
-Note: The driver isn't anywhere close to be upstream,
-so the info might change.
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -315,6 +315,34 @@
- 			reg = <0x4ab000 0x4>;
- 		};
- 
-+		mdio@90000 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			compatible = "qcom,ipq4019-mdio";
-+			reg = <0x90000 0x64>;
-+			status = "disabled";
-+
-+			ethernet-phy@0 {
-+				reg = <0>;
-+			};
-+
-+			ethernet-phy@1 {
-+				reg = <1>;
-+			};
-+
-+			ethernet-phy@2 {
-+				reg = <2>;
-+			};
-+
-+			ethernet-phy@3 {
-+				reg = <3>;
-+			};
-+
-+			ethernet-phy@4 {
-+				reg = <4>;
-+			};
-+		};
-+
- 		usb3_ss_phy: ssphy@9a000 {
- 			compatible = "qca,uni-ssphy";
- 			reg = <0x9a000 0x800>;
diff --git a/target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch b/target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch
deleted file mode 100644
index 79031d398a..0000000000
--- a/target/linux/ipq806x/patches-4.9/702-dts-ipq4019-add-PHY-switch-nodes.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 02:20:54 +0100
-Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
-
-This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
-nodes which are needed for the ar40xx.c driver to initialize the
-switch.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -343,6 +343,29 @@
- 			};
- 		};
- 
-+		ess-switch@c000000 {
-+			compatible = "qcom,ess-switch";
-+			reg = <0xc000000 0x80000>;
-+			switch_access_mode = "local bus";
-+			resets = <&gcc ESS_RESET>;
-+			reset-names = "ess_rst";
-+			clocks = <&gcc GCC_ESS_CLK>;
-+			clock-names = "ess_clk";
-+			switch_cpu_bmp = <0x1>;
-+			switch_lan_bmp = <0x1e>;
-+			switch_wan_bmp = <0x20>;
-+			switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
-+			switch_initvlas = <0x7c 0x54>;
-+			status = "disabled";
-+		};
-+
-+		ess-psgmii@98000 {
-+			compatible = "qcom,ess-psgmii";
-+			reg = <0x98000 0x800>;
-+			psgmii_access_mode = "local bus";
-+			status = "disabled";
-+		};
-+
- 		usb3_ss_phy: ssphy@9a000 {
- 			compatible = "qca,uni-ssphy";
- 			reg = <0x9a000 0x800>;
diff --git a/target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch b/target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch
deleted file mode 100644
index eb84124b54..0000000000
--- a/target/linux/ipq806x/patches-4.9/710-net-add-qualcomm-essedma-ethernet-driver.patch
+++ /dev/null
@@ -1,4602 +0,0 @@
-From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Thu, 19 Jan 2017 02:01:31 +0100
-Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- drivers/net/ethernet/qualcomm/Kconfig  | 9 +++++++++
- drivers/net/ethernet/qualcomm/Makefile | 1 +
- 2 files changed, 10 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -37,4 +37,13 @@ config QCOM_EMAC
- 	  low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- 	  Precision Clock Synchronization Protocol.
- 
-+config ESSEDMA
-+	tristate "Qualcomm Atheros ESS Edma support"
-+	---help---
-+	  This driver supports ethernet edma adapter.
-+	  Say Y to build this driver.
-+
-+	  To compile this driver as a module, choose M here. The module
-+	  will be called essedma.ko.
-+
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -6,3 +6,4 @@ obj-$(CONFIG_QCA7000) += qcaspi.o
- qcaspi-objs := qca_spi.o qca_framing.o qca_7k.o qca_debug.o
- 
- obj-y += emac/
-+obj-$(CONFIG_ESSEDMA) += essedma/
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/Makefile
-@@ -0,0 +1,9 @@
-+#
-+## Makefile for the Qualcomm Atheros ethernet edma driver
-+#
-+
-+
-+obj-$(CONFIG_ESSEDMA) += essedma.o
-+
-+essedma-objs := edma_axi.o edma.o edma_ethtool.o
-+
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/edma.c
-@@ -0,0 +1,2168 @@
-+/*
-+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/if_vlan.h>
-+#include "ess_edma.h"
-+#include "edma.h"
-+
-+extern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
-+bool edma_stp_rstp;
-+u16 edma_ath_eth_type;
-+
-+/* edma_skb_priority_offset()
-+ * 	get edma skb priority
-+ */
-+static unsigned int edma_skb_priority_offset(struct sk_buff *skb)
-+{
-+	return (skb->priority >> 2) & 1;
-+}
-+
-+/* edma_alloc_tx_ring()
-+ *	Allocate Tx descriptors ring
-+ */
-+static int edma_alloc_tx_ring(struct edma_common_info *edma_cinfo,
-+			      struct edma_tx_desc_ring *etdr)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+
-+	/* Initialize ring */
-+	etdr->size = sizeof(struct edma_sw_desc) * etdr->count;
-+	etdr->sw_next_to_fill = 0;
-+	etdr->sw_next_to_clean = 0;
-+
-+	/* Allocate SW descriptors */
-+	etdr->sw_desc = vzalloc(etdr->size);
-+	if (!etdr->sw_desc) {
-+		dev_err(&pdev->dev, "buffer alloc of tx ring failed=%p", etdr);
-+		return -ENOMEM;
-+	}
-+
-+	/* Allocate HW descriptors */
-+	etdr->hw_desc = dma_alloc_coherent(&pdev->dev, etdr->size, &etdr->dma,
-+					  GFP_KERNEL);
-+	if (!etdr->hw_desc) {
-+		dev_err(&pdev->dev, "descriptor allocation for tx ring failed");
-+		vfree(etdr->sw_desc);
-+		return -ENOMEM;
-+	}
-+
-+	return 0;
-+}
-+
-+/* edma_free_tx_ring()
-+ *	Free tx rings allocated by edma_alloc_tx_rings
-+ */
-+static void edma_free_tx_ring(struct edma_common_info *edma_cinfo,
-+			      struct edma_tx_desc_ring *etdr)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+
-+	if (likely(etdr->dma))
-+		dma_free_coherent(&pdev->dev, etdr->size, etdr->hw_desc,
-+				 etdr->dma);
-+
-+	vfree(etdr->sw_desc);
-+	etdr->sw_desc = NULL;
-+}
-+
-+/* edma_alloc_rx_ring()
-+ *	allocate rx descriptor ring
-+ */
-+static int edma_alloc_rx_ring(struct edma_common_info *edma_cinfo,
-+			     struct edma_rfd_desc_ring *erxd)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+
-+	erxd->size = sizeof(struct edma_sw_desc) * erxd->count;
-+	erxd->sw_next_to_fill = 0;
-+	erxd->sw_next_to_clean = 0;
-+
-+	/* Allocate SW descriptors */
-+	erxd->sw_desc = vzalloc(erxd->size);
-+	if (!erxd->sw_desc)
-+		return -ENOMEM;
-+
-+	/* Alloc HW descriptors */
-+	erxd->hw_desc = dma_alloc_coherent(&pdev->dev, erxd->size, &erxd->dma,
-+			GFP_KERNEL);
-+	if (!erxd->hw_desc) {
-+		vfree(erxd->sw_desc);
-+		return -ENOMEM;
-+	}
-+
-+	return 0;
-+}
-+
-+/* edma_free_rx_ring()
-+ *	Free rx ring allocated by alloc_rx_ring
-+ */
-+static void edma_free_rx_ring(struct edma_common_info *edma_cinfo,
-+			     struct edma_rfd_desc_ring *rxdr)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+
-+	if (likely(rxdr->dma))
-+		dma_free_coherent(&pdev->dev, rxdr->size, rxdr->hw_desc,
-+				 rxdr->dma);
-+
-+	vfree(rxdr->sw_desc);
-+	rxdr->sw_desc = NULL;
-+}
-+
-+/* edma_configure_tx()
-+ *	Configure transmission control data
-+ */
-+static void edma_configure_tx(struct edma_common_info *edma_cinfo)
-+{
-+	u32 txq_ctrl_data;
-+
-+	txq_ctrl_data = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT);
-+	txq_ctrl_data |= EDMA_TXQ_CTRL_TPD_BURST_EN;
-+	txq_ctrl_data |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT);
-+	edma_write_reg(EDMA_REG_TXQ_CTRL, txq_ctrl_data);
-+}
-+
-+
-+/* edma_configure_rx()
-+ *	configure reception control data
-+ */
-+static void edma_configure_rx(struct edma_common_info *edma_cinfo)
-+{
-+	struct edma_hw *hw = &edma_cinfo->hw;
-+	u32 rss_type, rx_desc1, rxq_ctrl_data;
-+
-+	/* Set RSS type */
-+	rss_type = hw->rss_type;
-+	edma_write_reg(EDMA_REG_RSS_TYPE, rss_type);
-+
-+	/* Set RFD burst number */
-+	rx_desc1 = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT);
-+
-+	/* Set RFD prefetch threshold */
-+	rx_desc1 |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT);
-+
-+	/* Set RFD in host ring low threshold to generte interrupt */
-+	rx_desc1 |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT);
-+	edma_write_reg(EDMA_REG_RX_DESC1, rx_desc1);
-+
-+	/* Set Rx FIFO threshold to start to DMA data to host */
-+	rxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE;
-+
-+	/* Set RX remove vlan bit */
-+	rxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;
-+
-+	edma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data);
-+}
-+
-+/* edma_alloc_rx_buf()
-+ *	does skb allocation for the received packets.
-+ */
-+static int edma_alloc_rx_buf(struct edma_common_info
-+			     *edma_cinfo,
-+			     struct edma_rfd_desc_ring *erdr,
-+			     int cleaned_count, int queue_id)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	struct edma_rx_free_desc *rx_desc;
-+	struct edma_sw_desc *sw_desc;
-+	struct sk_buff *skb;
-+	unsigned int i;
-+	u16 prod_idx, length;
-+	u32 reg_data;
-+
-+	if (cleaned_count > erdr->count) {
-+		dev_err(&pdev->dev, "Incorrect cleaned_count %d",
-+		       cleaned_count);
-+		return -1;
-+	}
-+
-+	i = erdr->sw_next_to_fill;
-+
-+	while (cleaned_count) {
-+		sw_desc = &erdr->sw_desc[i];
-+		length = edma_cinfo->rx_head_buffer_len;
-+
-+		if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_REUSE) {
-+			skb = sw_desc->skb;
-+		} else {
-+			/* alloc skb */
-+			skb = netdev_alloc_skb(edma_netdev[0], length);
-+			if (!skb) {
-+				/* Better luck next round */
-+				break;
-+			}
-+		}
-+
-+		if (edma_cinfo->page_mode) {
-+			struct page *pg = alloc_page(GFP_ATOMIC);
-+
-+			if (!pg) {
-+				dev_kfree_skb_any(skb);
-+				break;
-+			}
-+
-+			sw_desc->dma = dma_map_page(&pdev->dev, pg, 0,
-+						   edma_cinfo->rx_page_buffer_len,
-+						   DMA_FROM_DEVICE);
-+			if (dma_mapping_error(&pdev->dev,
-+				    sw_desc->dma)) {
-+				__free_page(pg);
-+				dev_kfree_skb_any(skb);
-+				break;
-+			}
-+
-+			skb_fill_page_desc(skb, 0, pg, 0,
-+					   edma_cinfo->rx_page_buffer_len);
-+			sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_FRAG;
-+			sw_desc->length = edma_cinfo->rx_page_buffer_len;
-+		} else {
-+			sw_desc->dma = dma_map_single(&pdev->dev, skb->data,
-+						     length, DMA_FROM_DEVICE);
-+			if (dma_mapping_error(&pdev->dev,
-+			   sw_desc->dma)) {
-+				dev_kfree_skb_any(skb);
-+				break;
-+			}
-+
-+			sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_HEAD;
-+			sw_desc->length = length;
-+		}
-+
-+		/* Update the buffer info */
-+		sw_desc->skb = skb;
-+		rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[i]);
-+		rx_desc->buffer_addr = cpu_to_le64(sw_desc->dma);
-+		if (++i == erdr->count)
-+			i = 0;
-+		cleaned_count--;
-+	}
-+
-+	erdr->sw_next_to_fill = i;
-+
-+	if (i == 0)
-+		prod_idx = erdr->count - 1;
-+	else
-+		prod_idx = i - 1;
-+
-+	/* Update the producer index */
-+	edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &reg_data);
-+	reg_data &= ~EDMA_RFD_PROD_IDX_BITS;
-+	reg_data |= prod_idx;
-+	edma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data);
-+	return cleaned_count;
-+}
-+
-+/* edma_init_desc()
-+ *	update descriptor ring size, buffer and producer/consumer index
-+ */
-+static void edma_init_desc(struct edma_common_info *edma_cinfo)
-+{
-+	struct edma_rfd_desc_ring *rfd_ring;
-+	struct edma_tx_desc_ring *etdr;
-+	int i = 0, j = 0;
-+	u32 data = 0;
-+	u16 hw_cons_idx = 0;
-+
-+	/* Set the base address of every TPD ring. */
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+		etdr = edma_cinfo->tpd_ring[i];
-+
-+		/* Update descriptor ring base address */
-+		edma_write_reg(EDMA_REG_TPD_BASE_ADDR_Q(i), (u32)etdr->dma);
-+		edma_read_reg(EDMA_REG_TPD_IDX_Q(i), &data);
-+
-+		/* Calculate hardware consumer index */
-+		hw_cons_idx = (data >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff;
-+		etdr->sw_next_to_fill = hw_cons_idx;
-+		etdr->sw_next_to_clean = hw_cons_idx;
-+		data &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT);
-+		data |= hw_cons_idx;
-+
-+		/* update producer index */
-+		edma_write_reg(EDMA_REG_TPD_IDX_Q(i), data);
-+
-+		/* update SW consumer index register */
-+		edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(i), hw_cons_idx);
-+
-+		/* Set TPD ring size */
-+		edma_write_reg(EDMA_REG_TPD_RING_SIZE,
-+			       edma_cinfo->tx_ring_count &
-+				    EDMA_TPD_RING_SIZE_MASK);
-+	}
-+
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		rfd_ring = edma_cinfo->rfd_ring[j];
-+		/* Update Receive Free descriptor ring base address */
-+		edma_write_reg(EDMA_REG_RFD_BASE_ADDR_Q(j),
-+			(u32)(rfd_ring->dma));
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+
-+	data = edma_cinfo->rx_head_buffer_len;
-+	if (edma_cinfo->page_mode)
-+		data = edma_cinfo->rx_page_buffer_len;
-+
-+	data &= EDMA_RX_BUF_SIZE_MASK;
-+	data <<= EDMA_RX_BUF_SIZE_SHIFT;
-+
-+	/* Update RFD ring size and RX buffer size */
-+	data |= (edma_cinfo->rx_ring_count & EDMA_RFD_RING_SIZE_MASK)
-+		<< EDMA_RFD_RING_SIZE_SHIFT;
-+
-+	edma_write_reg(EDMA_REG_RX_DESC0, data);
-+
-+	/* Disable TX FIFO low watermark and high watermark */
-+	edma_write_reg(EDMA_REG_TXF_WATER_MARK, 0);
-+
-+	/* Load all of base address above */
-+	edma_read_reg(EDMA_REG_TX_SRAM_PART, &data);
-+	data |= 1 << EDMA_LOAD_PTR_SHIFT;
-+	edma_write_reg(EDMA_REG_TX_SRAM_PART, data);
-+}
-+
-+/* edma_receive_checksum
-+ *	Api to check checksum on receive packets
-+ */
-+static void edma_receive_checksum(struct edma_rx_return_desc *rd,
-+						 struct sk_buff *skb)
-+{
-+	skb_checksum_none_assert(skb);
-+
-+	/* check the RRD IP/L4 checksum bit to see if
-+	 * its set, which in turn indicates checksum
-+	 * failure.
-+	 */
-+	if (rd->rrd6 & EDMA_RRD_CSUM_FAIL_MASK)
-+		return;
-+
-+	skb->ip_summed = CHECKSUM_UNNECESSARY;
-+}
-+
-+/* edma_clean_rfd()
-+ *	clean up rx resourcers on error
-+ */
-+static void edma_clean_rfd(struct edma_rfd_desc_ring *erdr, u16 index)
-+{
-+	struct edma_rx_free_desc *rx_desc;
-+	struct edma_sw_desc *sw_desc;
-+
-+	rx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[index]);
-+	sw_desc = &erdr->sw_desc[index];
-+	if (sw_desc->skb) {
-+		dev_kfree_skb_any(sw_desc->skb);
-+		sw_desc->skb = NULL;
-+	}
-+
-+	memset(rx_desc, 0, sizeof(struct edma_rx_free_desc));
-+}
-+
-+/* edma_rx_complete_fraglist()
-+ *	Complete Rx processing for fraglist skbs
-+ */
-+static void edma_rx_complete_stp_rstp(struct sk_buff *skb, int port_id, struct edma_rx_return_desc *rd)
-+{
-+	int i;
-+	u32 priority;
-+	u16 port_type;
-+	u8 mac_addr[EDMA_ETH_HDR_LEN];
-+
-+	port_type = (rd->rrd1 >> EDMA_RRD_PORT_TYPE_SHIFT)
-+		                & EDMA_RRD_PORT_TYPE_MASK;
-+	/* if port type is 0x4, then only proceed with
-+	 * other stp/rstp calculation
-+	 */
-+	if (port_type == EDMA_RX_ATH_HDR_RSTP_PORT_TYPE) {
-+		u8 bpdu_mac[6] = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x00};
-+
-+		/* calculate the frame priority */
-+		priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)
-+			& EDMA_RRD_PRIORITY_MASK;
-+
-+		for (i = 0; i < EDMA_ETH_HDR_LEN; i++)
-+			mac_addr[i] = skb->data[i];
-+
-+		/* Check if destination mac addr is bpdu addr */
-+		if (!memcmp(mac_addr, bpdu_mac, 6)) {
-+			/* destination mac address is BPDU
-+			 * destination mac address, then add
-+			 * atheros header to the packet.
-+			 */
-+			u16 athr_hdr = (EDMA_RX_ATH_HDR_VERSION << EDMA_RX_ATH_HDR_VERSION_SHIFT) |
-+				(priority << EDMA_RX_ATH_HDR_PRIORITY_SHIFT) |
-+				(EDMA_RX_ATH_HDR_RSTP_PORT_TYPE << EDMA_RX_ATH_PORT_TYPE_SHIFT) | port_id;
-+			skb_push(skb, 4);
-+			memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);
-+			*(uint16_t *)&skb->data[12] = htons(edma_ath_eth_type);
-+			*(uint16_t *)&skb->data[14] = htons(athr_hdr);
-+		}
-+	}
-+}
-+
-+/*
-+ * edma_rx_complete_fraglist()
-+ *	Complete Rx processing for fraglist skbs
-+ */
-+static int edma_rx_complete_fraglist(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,
-+					u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	struct edma_hw *hw = &edma_cinfo->hw;
-+	struct sk_buff *skb_temp;
-+	struct edma_sw_desc *sw_desc;
-+	int i;
-+	u16 size_remaining;
-+
-+	skb->data_len = 0;
-+	skb->tail += (hw->rx_head_buff_size - 16);
-+	skb->len = skb->truesize = length;
-+	size_remaining = length - (hw->rx_head_buff_size - 16);
-+
-+	/* clean-up all related sw_descs */
-+	for (i = 1; i < num_rfds; i++) {
-+		struct sk_buff *skb_prev;
-+		sw_desc = &erdr->sw_desc[sw_next_to_clean];
-+		skb_temp = sw_desc->skb;
-+
-+		dma_unmap_single(&pdev->dev, sw_desc->dma,
-+			sw_desc->length, DMA_FROM_DEVICE);
-+
-+		if (size_remaining < hw->rx_head_buff_size)
-+			skb_put(skb_temp, size_remaining);
-+		else
-+			skb_put(skb_temp, hw->rx_head_buff_size);
-+
-+		/*
-+		 * If we are processing the first rfd, we link
-+		 * skb->frag_list to the skb corresponding to the
-+		 * first RFD
-+		 */
-+		if (i == 1)
-+			skb_shinfo(skb)->frag_list = skb_temp;
-+		else
-+			skb_prev->next = skb_temp;
-+		skb_prev = skb_temp;
-+		skb_temp->next = NULL;
-+
-+		skb->data_len += skb_temp->len;
-+		size_remaining -= skb_temp->len;
-+
-+		/* Increment SW index */
-+		sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+		(*cleaned_count)++;
-+	}
-+
-+	return sw_next_to_clean;
-+}
-+
-+/* edma_rx_complete_paged()
-+ *	Complete Rx processing for paged skbs
-+ */
-+static int edma_rx_complete_paged(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,
-+					u16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	struct sk_buff *skb_temp;
-+	struct edma_sw_desc *sw_desc;
-+	int i;
-+	u16 size_remaining;
-+
-+	skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
-+
-+	/* Setup skbuff fields */
-+	skb->len = length;
-+
-+	if (likely(num_rfds <= 1)) {
-+		skb->data_len = length;
-+		skb->truesize += edma_cinfo->rx_page_buffer_len;
-+		skb_fill_page_desc(skb, 0, skb_frag_page(frag),
-+				16, length);
-+	} else {
-+		frag->size -= 16;
-+		skb->data_len = frag->size;
-+		skb->truesize += edma_cinfo->rx_page_buffer_len;
-+		size_remaining = length - frag->size;
-+
-+		skb_fill_page_desc(skb, 0, skb_frag_page(frag),
-+				16, frag->size);
-+
-+		/* clean-up all related sw_descs */
-+		for (i = 1; i < num_rfds; i++) {
-+			sw_desc = &erdr->sw_desc[sw_next_to_clean];
-+			skb_temp = sw_desc->skb;
-+			frag = &skb_shinfo(skb_temp)->frags[0];
-+			dma_unmap_page(&pdev->dev, sw_desc->dma,
-+				sw_desc->length, DMA_FROM_DEVICE);
-+
-+			if (size_remaining < edma_cinfo->rx_page_buffer_len)
-+				frag->size = size_remaining;
-+
-+			skb_fill_page_desc(skb, i, skb_frag_page(frag),
-+					0, frag->size);
-+
-+			skb_shinfo(skb_temp)->nr_frags = 0;
-+			dev_kfree_skb_any(skb_temp);
-+
-+			skb->data_len += frag->size;
-+			skb->truesize += edma_cinfo->rx_page_buffer_len;
-+			size_remaining -= frag->size;
-+
-+			/* Increment SW index */
-+			sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+			(*cleaned_count)++;
-+		}
-+	}
-+
-+	return sw_next_to_clean;
-+}
-+
-+/*
-+ * edma_rx_complete()
-+ *	Main api called from the poll function to process rx packets.
-+ */
-+static void edma_rx_complete(struct edma_common_info *edma_cinfo,
-+			    int *work_done, int work_to_do, int queue_id,
-+			    struct napi_struct *napi)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	struct edma_rfd_desc_ring *erdr = edma_cinfo->rfd_ring[queue_id];
-+	struct net_device *netdev;
-+	struct edma_adapter *adapter;
-+	struct edma_sw_desc *sw_desc;
-+	struct sk_buff *skb;
-+	struct edma_rx_return_desc *rd;
-+	u16 hash_type, rrd[8], cleaned_count = 0, length = 0, num_rfds = 1,
-+	    sw_next_to_clean, hw_next_to_clean = 0, vlan = 0, ret_count = 0;
-+	u32 data = 0;
-+	u8 *vaddr;
-+	int port_id, i, drop_count = 0;
-+	u32 priority;
-+	u16 count = erdr->count, rfd_avail;
-+	u8 queue_to_rxid[8] = {0, 0, 1, 1, 2, 2, 3, 3};
-+
-+	sw_next_to_clean = erdr->sw_next_to_clean;
-+
-+	edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);
-+	hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &
-+			   EDMA_RFD_CONS_IDX_MASK;
-+
-+	do {
-+		while (sw_next_to_clean != hw_next_to_clean) {
-+			if (!work_to_do)
-+				break;
-+
-+			sw_desc = &erdr->sw_desc[sw_next_to_clean];
-+			skb = sw_desc->skb;
-+
-+			/* Unmap the allocated buffer */
-+			if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD))
-+				dma_unmap_single(&pdev->dev, sw_desc->dma,
-+					        sw_desc->length, DMA_FROM_DEVICE);
-+			else
-+				dma_unmap_page(&pdev->dev, sw_desc->dma,
-+					      sw_desc->length, DMA_FROM_DEVICE);
-+
-+			/* Get RRD */
-+			if (edma_cinfo->page_mode) {
-+				vaddr = kmap_atomic(skb_frag_page(&skb_shinfo(skb)->frags[0]));
-+				memcpy((uint8_t *)&rrd[0], vaddr, 16);
-+				rd = (struct edma_rx_return_desc *)rrd;
-+				kunmap_atomic(vaddr);
-+			} else {
-+				rd = (struct edma_rx_return_desc *)skb->data;
-+			}
-+
-+			/* Check if RRD is valid */
-+			if (!(rd->rrd7 & EDMA_RRD_DESC_VALID)) {
-+				edma_clean_rfd(erdr, sw_next_to_clean);
-+				sw_next_to_clean = (sw_next_to_clean + 1) &
-+						   (erdr->count - 1);
-+				cleaned_count++;
-+				continue;
-+			}
-+
-+			/* Get the number of RFDs from RRD */
-+			num_rfds = rd->rrd1 & EDMA_RRD_NUM_RFD_MASK;
-+
-+			/* Get Rx port ID from switch */
-+			port_id = (rd->rrd1 >> EDMA_PORT_ID_SHIFT) & EDMA_PORT_ID_MASK;
-+			if ((!port_id) || (port_id > EDMA_MAX_PORTID_SUPPORTED)) {
-+				dev_err(&pdev->dev, "Invalid RRD source port bit set");
-+				for (i = 0; i < num_rfds; i++) {
-+					edma_clean_rfd(erdr, sw_next_to_clean);
-+					sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+					cleaned_count++;
-+				}
-+				continue;
-+			}
-+
-+			/* check if we have a sink for the data we receive.
-+			 * If the interface isn't setup, we have to drop the
-+			 * incoming data for now.
-+			 */
-+			netdev = edma_cinfo->portid_netdev_lookup_tbl[port_id];
-+			if (!netdev) {
-+				edma_clean_rfd(erdr, sw_next_to_clean);
-+				sw_next_to_clean = (sw_next_to_clean + 1) &
-+						   (erdr->count - 1);
-+				cleaned_count++;
-+				continue;
-+			}
-+			adapter = netdev_priv(netdev);
-+
-+			/* This code is added to handle a usecase where high
-+			 * priority stream and a low priority stream are
-+			 * received simultaneously on DUT. The problem occurs
-+			 * if one of the  Rx rings is full and the corresponding
-+			 * core is busy with other stuff. This causes ESS CPU
-+			 * port to backpressure all incoming traffic including
-+			 * high priority one. We monitor free descriptor count
-+			 * on each CPU and whenever it reaches threshold (< 80),
-+			 * we drop all low priority traffic and let only high
-+			 * priotiy traffic pass through. We can hence avoid
-+			 * ESS CPU port to send backpressure on high priroity
-+			 * stream.
-+			 */
-+			priority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)
-+				& EDMA_RRD_PRIORITY_MASK;
-+			if (likely(!priority && !edma_cinfo->page_mode && (num_rfds <= 1))) {
-+				rfd_avail = (count + sw_next_to_clean - hw_next_to_clean - 1) & (count - 1);
-+				if (rfd_avail < EDMA_RFD_AVAIL_THR) {
-+					sw_desc->flags = EDMA_SW_DESC_FLAG_SKB_REUSE;
-+					sw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);
-+					adapter->stats.rx_dropped++;
-+					cleaned_count++;
-+					drop_count++;
-+					if (drop_count == 3) {
-+						work_to_do--;
-+						(*work_done)++;
-+						drop_count = 0;
-+					}
-+					if (cleaned_count == EDMA_RX_BUFFER_WRITE) {
-+						/* If buffer clean count reaches 16, we replenish HW buffers. */
-+						ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
-+						edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
-+							      sw_next_to_clean);
-+						cleaned_count = ret_count;
-+					}
-+					continue;
-+				}
-+			}
-+
-+			work_to_do--;
-+			(*work_done)++;
-+
-+			/* Increment SW index */
-+			sw_next_to_clean = (sw_next_to_clean + 1) &
-+					   (erdr->count - 1);
-+
-+			cleaned_count++;
-+
-+			/* Get the packet size and allocate buffer */
-+			length = rd->rrd6 & EDMA_RRD_PKT_SIZE_MASK;
-+
-+			if (edma_cinfo->page_mode) {
-+				/* paged skb */
-+				sw_next_to_clean = edma_rx_complete_paged(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);
-+				if (!pskb_may_pull(skb, ETH_HLEN)) {
-+					dev_kfree_skb_any(skb);
-+					continue;
-+				}
-+			} else {
-+				/* single or fraglist skb */
-+
-+				/* Addition of 16 bytes is required, as in the packet
-+				 * first 16 bytes are rrd descriptors, so actual data
-+				 * starts from an offset of 16.
-+				 */
-+				skb_reserve(skb, 16);
-+				if (likely((num_rfds <= 1) || !edma_cinfo->fraglist_mode)) {
-+					skb_put(skb, length);
-+				} else {
-+					sw_next_to_clean = edma_rx_complete_fraglist(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);
-+				}
-+			}
-+
-+			if (edma_stp_rstp) {
-+				edma_rx_complete_stp_rstp(skb, port_id, rd);
-+			}
-+
-+			skb->protocol = eth_type_trans(skb, netdev);
-+
-+			/* Record Rx queue for RFS/RPS and fill flow hash from HW */
-+			skb_record_rx_queue(skb, queue_to_rxid[queue_id]);
-+			if (netdev->features & NETIF_F_RXHASH) {
-+				hash_type = (rd->rrd5 >> EDMA_HASH_TYPE_SHIFT);
-+				if ((hash_type > EDMA_HASH_TYPE_START) && (hash_type < EDMA_HASH_TYPE_END))
-+					skb_set_hash(skb, rd->rrd2, PKT_HASH_TYPE_L4);
-+			}
-+
-+#ifdef CONFIG_NF_FLOW_COOKIE
-+			skb->flow_cookie = rd->rrd3 & EDMA_RRD_FLOW_COOKIE_MASK;
-+#endif
-+			edma_receive_checksum(rd, skb);
-+
-+			/* Process VLAN HW acceleration indication provided by HW */
-+			if (unlikely(adapter->default_vlan_tag != rd->rrd4)) {
-+				vlan = rd->rrd4;
-+				if (likely(rd->rrd7 & EDMA_RRD_CVLAN))
-+					__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
-+				else if (rd->rrd1 & EDMA_RRD_SVLAN)
-+					__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);
-+			}
-+
-+			/* Update rx statistics */
-+			adapter->stats.rx_packets++;
-+			adapter->stats.rx_bytes += length;
-+
-+			/* Check if we reached refill threshold */
-+			if (cleaned_count == EDMA_RX_BUFFER_WRITE) {
-+				ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
-+				edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
-+					      sw_next_to_clean);
-+				cleaned_count = ret_count;
-+			}
-+
-+			/* At this point skb should go to stack */
-+			napi_gro_receive(napi, skb);
-+		}
-+
-+		/* Check if we still have NAPI budget */
-+		if (!work_to_do)
-+			break;
-+
-+		/* Read index once again since we still have NAPI budget */
-+		edma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);
-+		hw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &
-+			EDMA_RFD_CONS_IDX_MASK;
-+	} while (hw_next_to_clean != sw_next_to_clean);
-+
-+	erdr->sw_next_to_clean = sw_next_to_clean;
-+
-+	/* Refill here in case refill threshold wasn't reached */
-+	if (likely(cleaned_count)) {
-+		ret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);
-+		if (ret_count)
-+			dev_dbg(&pdev->dev, "Not all buffers was reallocated");
-+		edma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),
-+			      erdr->sw_next_to_clean);
-+	}
-+}
-+
-+/* edma_delete_rfs_filter()
-+ *	Remove RFS filter from switch
-+ */
-+static int edma_delete_rfs_filter(struct edma_adapter *adapter,
-+				 struct edma_rfs_filter_node *filter_node)
-+{
-+	int res = -1;
-+
-+	struct flow_keys *keys = &filter_node->keys;
-+
-+	if (likely(adapter->set_rfs_rule))
-+		res = (*adapter->set_rfs_rule)(adapter->netdev,
-+			flow_get_u32_src(keys), flow_get_u32_dst(keys),
-+			keys->ports.src, keys->ports.dst,
-+			keys->basic.ip_proto, filter_node->rq_id, 0);
-+
-+	return res;
-+}
-+
-+/* edma_add_rfs_filter()
-+ *	Add RFS filter to switch
-+ */
-+static int edma_add_rfs_filter(struct edma_adapter *adapter,
-+			       struct flow_keys *keys, u16 rq,
-+			       struct edma_rfs_filter_node *filter_node)
-+{
-+	int res = -1;
-+
-+	struct flow_keys *dest_keys = &filter_node->keys;
-+
-+	memcpy(dest_keys, &filter_node->keys, sizeof(*dest_keys));
-+/*
-+	dest_keys->control = keys->control;
-+	dest_keys->basic = keys->basic;
-+	dest_keys->addrs = keys->addrs;
-+	dest_keys->ports = keys->ports;
-+	dest_keys.ip_proto = keys->ip_proto;
-+*/
-+	/* Call callback registered by ESS driver */
-+	if (likely(adapter->set_rfs_rule))
-+		res = (*adapter->set_rfs_rule)(adapter->netdev, flow_get_u32_src(keys),
-+		      flow_get_u32_dst(keys), keys->ports.src, keys->ports.dst,
-+		      keys->basic.ip_proto, rq, 1);
-+
-+	return res;
-+}
-+
-+/* edma_rfs_key_search()
-+ *	Look for existing RFS entry
-+ */
-+static struct edma_rfs_filter_node *edma_rfs_key_search(struct hlist_head *h,
-+						       struct flow_keys *key)
-+{
-+	struct edma_rfs_filter_node *p;
-+
-+	hlist_for_each_entry(p, h, node)
-+		if (flow_get_u32_src(&p->keys) == flow_get_u32_src(key) &&
-+		    flow_get_u32_dst(&p->keys) == flow_get_u32_dst(key) &&
-+		    p->keys.ports.src == key->ports.src &&
-+		    p->keys.ports.dst == key->ports.dst &&
-+		    p->keys.basic.ip_proto == key->basic.ip_proto)
-+			return p;
-+	return NULL;
-+}
-+
-+/* edma_initialise_rfs_flow_table()
-+ * 	Initialise EDMA RFS flow table
-+ */
-+static void edma_initialise_rfs_flow_table(struct edma_adapter *adapter)
-+{
-+	int i;
-+
-+	spin_lock_init(&adapter->rfs.rfs_ftab_lock);
-+
-+	/* Initialize EDMA flow hash table */
-+	for (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++)
-+		INIT_HLIST_HEAD(&adapter->rfs.hlist_head[i]);
-+
-+	adapter->rfs.max_num_filter = EDMA_RFS_FLOW_ENTRIES;
-+	adapter->rfs.filter_available = adapter->rfs.max_num_filter;
-+	adapter->rfs.hashtoclean = 0;
-+
-+	/* Add timer to get periodic RFS updates from OS */
-+	init_timer(&adapter->rfs.expire_rfs);
-+	adapter->rfs.expire_rfs.function = edma_flow_may_expire;
-+	adapter->rfs.expire_rfs.data = (unsigned long)adapter;
-+	mod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4);
-+}
-+
-+/* edma_free_rfs_flow_table()
-+ * 	Free EDMA RFS flow table
-+ */
-+static void edma_free_rfs_flow_table(struct edma_adapter *adapter)
-+{
-+	int i;
-+
-+	/* Remove sync timer */
-+	del_timer_sync(&adapter->rfs.expire_rfs);
-+	spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
-+
-+	/* Free EDMA RFS table entries */
-+	adapter->rfs.filter_available = 0;
-+
-+	/* Clean-up EDMA flow hash table */
-+	for (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++) {
-+		struct hlist_head *hhead;
-+		struct hlist_node *tmp;
-+		struct edma_rfs_filter_node *filter_node;
-+		int res;
-+
-+		hhead = &adapter->rfs.hlist_head[i];
-+		hlist_for_each_entry_safe(filter_node, tmp, hhead, node) {
-+			res  = edma_delete_rfs_filter(adapter, filter_node);
-+			if (res < 0)
-+				dev_warn(&adapter->netdev->dev,
-+					"EDMA going down but RFS entry %d not allowed to be flushed by Switch",
-+				        filter_node->flow_id);
-+			hlist_del(&filter_node->node);
-+			kfree(filter_node);
-+		}
-+	}
-+	spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
-+}
-+
-+/* edma_tx_unmap_and_free()
-+ *	clean TX buffer
-+ */
-+static inline void edma_tx_unmap_and_free(struct platform_device *pdev,
-+					 struct edma_sw_desc *sw_desc)
-+{
-+	struct sk_buff *skb = sw_desc->skb;
-+
-+	if (likely((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD) ||
-+			(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAGLIST)))
-+		/* unmap_single for skb head area */
-+		dma_unmap_single(&pdev->dev, sw_desc->dma,
-+				sw_desc->length, DMA_TO_DEVICE);
-+	else if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)
-+		/* unmap page for paged fragments */
-+		dma_unmap_page(&pdev->dev, sw_desc->dma,
-+		  	      sw_desc->length, DMA_TO_DEVICE);
-+
-+	if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_LAST))
-+		dev_kfree_skb_any(skb);
-+
-+	sw_desc->flags = 0;
-+}
-+
-+/* edma_tx_complete()
-+ *	Used to clean tx queues and update hardware and consumer index
-+ */
-+static void edma_tx_complete(struct edma_common_info *edma_cinfo, int queue_id)
-+{
-+	struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
-+	struct edma_sw_desc *sw_desc;
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	int i;
-+
-+	u16 sw_next_to_clean = etdr->sw_next_to_clean;
-+	u16 hw_next_to_clean;
-+	u32 data = 0;
-+
-+	edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &data);
-+	hw_next_to_clean = (data >> EDMA_TPD_CONS_IDX_SHIFT) & EDMA_TPD_CONS_IDX_MASK;
-+
-+	/* clean the buffer here */
-+	while (sw_next_to_clean != hw_next_to_clean) {
-+		sw_desc = &etdr->sw_desc[sw_next_to_clean];
-+		edma_tx_unmap_and_free(pdev, sw_desc);
-+		sw_next_to_clean = (sw_next_to_clean + 1) & (etdr->count - 1);
-+	}
-+
-+	etdr->sw_next_to_clean = sw_next_to_clean;
-+
-+	/* update the TPD consumer index register */
-+	edma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(queue_id), sw_next_to_clean);
-+
-+	/* Wake the queue if queue is stopped and netdev link is up */
-+	for (i = 0; i < EDMA_MAX_NETDEV_PER_QUEUE && etdr->nq[i] ; i++) {
-+		if (netif_tx_queue_stopped(etdr->nq[i])) {
-+			if ((etdr->netdev[i]) && netif_carrier_ok(etdr->netdev[i]))
-+				netif_tx_wake_queue(etdr->nq[i]);
-+		}
-+	}
-+}
-+
-+/* edma_get_tx_buffer()
-+ *	Get sw_desc corresponding to the TPD
-+ */
-+static struct edma_sw_desc *edma_get_tx_buffer(struct edma_common_info *edma_cinfo,
-+					       struct edma_tx_desc *tpd, int queue_id)
-+{
-+	struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
-+	return &etdr->sw_desc[tpd - (struct edma_tx_desc *)etdr->hw_desc];
-+}
-+
-+/* edma_get_next_tpd()
-+ *	Return a TPD descriptor for transfer
-+ */
-+static struct edma_tx_desc *edma_get_next_tpd(struct edma_common_info *edma_cinfo,
-+					     int queue_id)
-+{
-+	struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
-+	u16 sw_next_to_fill = etdr->sw_next_to_fill;
-+	struct edma_tx_desc *tpd_desc =
-+		(&((struct edma_tx_desc *)(etdr->hw_desc))[sw_next_to_fill]);
-+
-+	etdr->sw_next_to_fill = (etdr->sw_next_to_fill + 1) & (etdr->count - 1);
-+
-+	return tpd_desc;
-+}
-+
-+/* edma_tpd_available()
-+ *	Check number of free TPDs
-+ */
-+static inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo,
-+				    int queue_id)
-+{
-+	struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
-+
-+	u16 sw_next_to_fill;
-+	u16 sw_next_to_clean;
-+	u16 count = 0;
-+
-+	sw_next_to_clean = etdr->sw_next_to_clean;
-+	sw_next_to_fill = etdr->sw_next_to_fill;
-+
-+	if (likely(sw_next_to_clean <= sw_next_to_fill))
-+		count = etdr->count;
-+
-+	return count + sw_next_to_clean - sw_next_to_fill - 1;
-+}
-+
-+/* edma_tx_queue_get()
-+ *	Get the starting number of  the queue
-+ */
-+static inline int edma_tx_queue_get(struct edma_adapter *adapter,
-+				   struct sk_buff *skb, int txq_id)
-+{
-+	/* skb->priority is used as an index to skb priority table
-+	 * and based on packet priority, correspong queue is assigned.
-+	 */
-+	return adapter->tx_start_offset[txq_id] + edma_skb_priority_offset(skb);
-+}
-+
-+/* edma_tx_update_hw_idx()
-+ *	update the producer index for the ring transmitted
-+ */
-+static void edma_tx_update_hw_idx(struct edma_common_info *edma_cinfo,
-+			         struct sk_buff *skb, int queue_id)
-+{
-+	struct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];
-+	u32 tpd_idx_data;
-+
-+	/* Read and update the producer index */
-+	edma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &tpd_idx_data);
-+	tpd_idx_data &= ~EDMA_TPD_PROD_IDX_BITS;
-+	tpd_idx_data |= (etdr->sw_next_to_fill & EDMA_TPD_PROD_IDX_MASK)
-+		<< EDMA_TPD_PROD_IDX_SHIFT;
-+
-+	edma_write_reg(EDMA_REG_TPD_IDX_Q(queue_id), tpd_idx_data);
-+}
-+
-+/* edma_rollback_tx()
-+ *	Function to retrieve tx resources in case of error
-+ */
-+static void edma_rollback_tx(struct edma_adapter *adapter,
-+			    struct edma_tx_desc *start_tpd, int queue_id)
-+{
-+	struct edma_tx_desc_ring *etdr = adapter->edma_cinfo->tpd_ring[queue_id];
-+	struct edma_sw_desc *sw_desc;
-+	struct edma_tx_desc *tpd = NULL;
-+	u16 start_index, index;
-+
-+	start_index = start_tpd - (struct edma_tx_desc *)(etdr->hw_desc);
-+
-+	index = start_index;
-+	while (index != etdr->sw_next_to_fill) {
-+		tpd = (&((struct edma_tx_desc *)(etdr->hw_desc))[index]);
-+		sw_desc = &etdr->sw_desc[index];
-+		edma_tx_unmap_and_free(adapter->pdev, sw_desc);
-+		memset(tpd, 0, sizeof(struct edma_tx_desc));
-+		if (++index == etdr->count)
-+			index = 0;
-+	}
-+	etdr->sw_next_to_fill = start_index;
-+}
-+
-+/* edma_tx_map_and_fill()
-+ *	gets called from edma_xmit_frame
-+ *
-+ * This is where the dma of the buffer to be transmitted
-+ * gets mapped
-+ */
-+static int edma_tx_map_and_fill(struct edma_common_info *edma_cinfo,
-+			       struct edma_adapter *adapter, struct sk_buff *skb, int queue_id,
-+			       unsigned int flags_transmit, u16 from_cpu, u16 dp_bitmap,
-+			       bool packet_is_rstp, int nr_frags)
-+{
-+	struct edma_sw_desc *sw_desc = NULL;
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	struct edma_tx_desc *tpd = NULL, *start_tpd = NULL;
-+	struct sk_buff *iter_skb;
-+	int i = 0;
-+	u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0;
-+	u16 buf_len, lso_desc_len = 0;
-+
-+	/* It should either be a nr_frags skb or fraglist skb but not both */
-+	BUG_ON(nr_frags && skb_has_frag_list(skb));
-+
-+	if (skb_is_gso(skb)) {
-+		/* TODO: What additional checks need to be performed here */
-+		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
-+			lso_word1 |= EDMA_TPD_IPV4_EN;
-+			ip_hdr(skb)->check = 0;
-+			tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
-+				ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
-+		} else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
-+			lso_word1 |= EDMA_TPD_LSO_V2_EN;
-+			ipv6_hdr(skb)->payload_len = 0;
-+			tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
-+				&ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);
-+		} else
-+			return -EINVAL;
-+
-+		lso_word1 |= EDMA_TPD_LSO_EN | ((skb_shinfo(skb)->gso_size & EDMA_TPD_MSS_MASK) << EDMA_TPD_MSS_SHIFT) |
-+				(skb_transport_offset(skb) << EDMA_TPD_HDR_SHIFT);
-+	} else if (flags_transmit & EDMA_HW_CHECKSUM) {
-+			u8 css, cso;
-+			cso = skb_checksum_start_offset(skb);
-+			css = cso  + skb->csum_offset;
-+
-+			word1 |= (EDMA_TPD_CUSTOM_CSUM_EN);
-+			word1 |= (cso >> 1) << EDMA_TPD_HDR_SHIFT;
-+			word1 |= ((css >> 1) << EDMA_TPD_CUSTOM_CSUM_SHIFT);
-+	}
-+
-+	if (skb->protocol == htons(ETH_P_PPP_SES))
-+		word1 |= EDMA_TPD_PPPOE_EN;
-+
-+	if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_FLAG) {
-+		switch(skb->vlan_proto) {
-+		case htons(ETH_P_8021Q):
-+			word3 |= (1 << EDMA_TX_INS_CVLAN);
-+			word3 |= skb_vlan_tag_get(skb) << EDMA_TX_CVLAN_TAG_SHIFT;
-+			break;
-+		case htons(ETH_P_8021AD):
-+			word1 |= (1 << EDMA_TX_INS_SVLAN);
-+			svlan_tag = skb_vlan_tag_get(skb) << EDMA_TX_SVLAN_TAG_SHIFT;
-+			break;
-+		default:
-+			dev_err(&pdev->dev, "no ctag or stag present\n");
-+			goto vlan_tag_error;
-+		}
-+	} else if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG) {
-+		word3 |= (1 << EDMA_TX_INS_CVLAN);
-+		word3 |= (adapter->default_vlan_tag) << EDMA_TX_CVLAN_TAG_SHIFT;
-+	}
-+
-+	if (packet_is_rstp) {
-+		word3 |= dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT;
-+		word3 |= from_cpu << EDMA_TPD_FROM_CPU_SHIFT;
-+	} else {
-+		word3 |= adapter->dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT;
-+	}
-+
-+	buf_len = skb_headlen(skb);
-+
-+	if (lso_word1) {
-+		if (lso_word1 & EDMA_TPD_LSO_V2_EN) {
-+
-+			/* IPv6 LSOv2 descriptor */
-+			start_tpd = tpd = edma_get_next_tpd(edma_cinfo, queue_id);
-+			sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
-+			sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_NONE;
-+
-+			/* LSOv2 descriptor overrides addr field to pass length */
-+			tpd->addr = cpu_to_le16(skb->len);
-+			tpd->svlan_tag = svlan_tag;
-+			tpd->word1 = word1 | lso_word1;
-+			tpd->word3 = word3;
-+		}
-+
-+		tpd = edma_get_next_tpd(edma_cinfo, queue_id);
-+		if (!start_tpd)
-+			start_tpd = tpd;
-+		sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
-+
-+		/* The last buffer info contain the skb address,
-+		 * so skb will be freed after unmap
-+		 */
-+		sw_desc->length = lso_desc_len;
-+		sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;
-+
-+		sw_desc->dma = dma_map_single(&adapter->pdev->dev,
-+					skb->data, buf_len, DMA_TO_DEVICE);
-+		if (dma_mapping_error(&pdev->dev, sw_desc->dma))
-+			goto dma_error;
-+
-+		tpd->addr = cpu_to_le32(sw_desc->dma);
-+		tpd->len  = cpu_to_le16(buf_len);
-+
-+		tpd->svlan_tag = svlan_tag;
-+		tpd->word1 = word1 | lso_word1;
-+		tpd->word3 = word3;
-+
-+		/* The last buffer info contain the skb address,
-+		 * so it will be freed after unmap
-+		 */
-+		sw_desc->length = lso_desc_len;
-+		sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;
-+
-+		buf_len = 0;
-+	}
-+
-+	if (likely(buf_len)) {
-+
-+		/* TODO Do not dequeue descriptor if there is a potential error */
-+		tpd = edma_get_next_tpd(edma_cinfo, queue_id);
-+
-+		if (!start_tpd)
-+			start_tpd = tpd;
-+
-+		sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
-+
-+		/* The last buffer info contain the skb address,
-+		 * so it will be free after unmap
-+		 */
-+		sw_desc->length = buf_len;
-+		sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;
-+		sw_desc->dma = dma_map_single(&adapter->pdev->dev,
-+			skb->data, buf_len, DMA_TO_DEVICE);
-+		if (dma_mapping_error(&pdev->dev, sw_desc->dma))
-+			goto dma_error;
-+
-+		tpd->addr = cpu_to_le32(sw_desc->dma);
-+		tpd->len  = cpu_to_le16(buf_len);
-+
-+		tpd->svlan_tag = svlan_tag;
-+		tpd->word1 = word1 | lso_word1;
-+		tpd->word3 = word3;
-+	}
-+
-+	/* Walk through all paged fragments */
-+	while (nr_frags--) {
-+		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-+		buf_len = skb_frag_size(frag);
-+		tpd = edma_get_next_tpd(edma_cinfo, queue_id);
-+		sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
-+		sw_desc->length = buf_len;
-+		sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAG;
-+
-+		sw_desc->dma = skb_frag_dma_map(&pdev->dev, frag, 0, buf_len, DMA_TO_DEVICE);
-+
-+		if (dma_mapping_error(NULL, sw_desc->dma))
-+			goto dma_error;
-+
-+		tpd->addr = cpu_to_le32(sw_desc->dma);
-+		tpd->len  = cpu_to_le16(buf_len);
-+
-+		tpd->svlan_tag = svlan_tag;
-+		tpd->word1 = word1 | lso_word1;
-+		tpd->word3 = word3;
-+		i++;
-+	}
-+
-+	/* Walk through all fraglist skbs */
-+	skb_walk_frags(skb, iter_skb) {
-+		buf_len = iter_skb->len;
-+		tpd = edma_get_next_tpd(edma_cinfo, queue_id);
-+		sw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);
-+		sw_desc->length = buf_len;
-+		sw_desc->dma =  dma_map_single(&adapter->pdev->dev,
-+				iter_skb->data, buf_len, DMA_TO_DEVICE);
-+
-+		if (dma_mapping_error(NULL, sw_desc->dma))
-+			goto dma_error;
-+
-+		tpd->addr = cpu_to_le32(sw_desc->dma);
-+		tpd->len  = cpu_to_le16(buf_len);
-+		tpd->svlan_tag = svlan_tag;
-+		tpd->word1 = word1 | lso_word1;
-+		tpd->word3 = word3;
-+		sw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAGLIST;
-+	}
-+
-+	if (tpd)
-+		tpd->word1 |= 1 << EDMA_TPD_EOP_SHIFT;
-+
-+	sw_desc->skb = skb;
-+	sw_desc->flags |= EDMA_SW_DESC_FLAG_LAST;
-+
-+	return 0;
-+
-+dma_error:
-+	edma_rollback_tx(adapter, start_tpd, queue_id);
-+	dev_err(&pdev->dev, "TX DMA map failed\n");
-+vlan_tag_error:
-+	return -ENOMEM;
-+}
-+
-+/* edma_check_link()
-+ *	check Link status
-+ */
-+static int edma_check_link(struct edma_adapter *adapter)
-+{
-+	struct phy_device *phydev = adapter->phydev;
-+
-+	if (!(adapter->poll_required))
-+		return __EDMA_LINKUP;
-+
-+	if (phydev->link)
-+		return __EDMA_LINKUP;
-+
-+	return __EDMA_LINKDOWN;
-+}
-+
-+/* edma_adjust_link()
-+ *	check for edma link status
-+ */
-+void edma_adjust_link(struct net_device *netdev)
-+{
-+	int status;
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+	struct phy_device *phydev = adapter->phydev;
-+
-+	if (!test_bit(__EDMA_UP, &adapter->state_flags))
-+		return;
-+
-+	status = edma_check_link(adapter);
-+
-+	if (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) {
-+		dev_info(&adapter->pdev->dev, "%s: GMAC Link is up with phy_speed=%d\n", netdev->name, phydev->speed);
-+		adapter->link_state = __EDMA_LINKUP;
-+		netif_carrier_on(netdev);
-+		if (netif_running(netdev))
-+			netif_tx_wake_all_queues(netdev);
-+	} else if (status == __EDMA_LINKDOWN && adapter->link_state == __EDMA_LINKUP) {
-+		dev_info(&adapter->pdev->dev, "%s: GMAC Link is down\n", netdev->name);
-+		adapter->link_state = __EDMA_LINKDOWN;
-+		netif_carrier_off(netdev);
-+		netif_tx_stop_all_queues(netdev);
-+	}
-+}
-+
-+/* edma_get_stats()
-+ *	Statistics api used to retreive the tx/rx statistics
-+ */
-+struct net_device_stats *edma_get_stats(struct net_device *netdev)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+
-+	return &adapter->stats;
-+}
-+
-+/* edma_xmit()
-+ *	Main api to be called by the core for packet transmission
-+ */
-+netdev_tx_t edma_xmit(struct sk_buff *skb,
-+		     struct net_device *net_dev)
-+{
-+	struct edma_adapter *adapter = netdev_priv(net_dev);
-+	struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
-+	struct edma_tx_desc_ring *etdr;
-+	u16 from_cpu, dp_bitmap, txq_id;
-+	int ret, nr_frags = 0, num_tpds_needed = 1, queue_id;
-+	unsigned int flags_transmit = 0;
-+	bool packet_is_rstp = false;
-+	struct netdev_queue *nq = NULL;
-+
-+	if (skb_shinfo(skb)->nr_frags) {
-+		nr_frags = skb_shinfo(skb)->nr_frags;
-+		num_tpds_needed += nr_frags;
-+	} else if (skb_has_frag_list(skb)) {
-+		struct sk_buff *iter_skb;
-+
-+		skb_walk_frags(skb, iter_skb)
-+			num_tpds_needed++;
-+	}
-+
-+	if (num_tpds_needed > EDMA_MAX_SKB_FRAGS) {
-+		dev_err(&net_dev->dev,
-+			"skb received with fragments %d which is more than %lu",
-+			num_tpds_needed, EDMA_MAX_SKB_FRAGS);
-+		dev_kfree_skb_any(skb);
-+		adapter->stats.tx_errors++;
-+		return NETDEV_TX_OK;
-+	}
-+
-+	if (edma_stp_rstp) {
-+		u16 ath_hdr, ath_eth_type;
-+		u8 mac_addr[EDMA_ETH_HDR_LEN];
-+		ath_eth_type = ntohs(*(uint16_t *)&skb->data[12]);
-+		if (ath_eth_type == edma_ath_eth_type) {
-+			packet_is_rstp = true;
-+			ath_hdr = htons(*(uint16_t *)&skb->data[14]);
-+			dp_bitmap = ath_hdr & EDMA_TX_ATH_HDR_PORT_BITMAP_MASK;
-+			from_cpu = (ath_hdr & EDMA_TX_ATH_HDR_FROM_CPU_MASK) >> EDMA_TX_ATH_HDR_FROM_CPU_SHIFT;
-+			memcpy(mac_addr, skb->data, EDMA_ETH_HDR_LEN);
-+
-+			skb_pull(skb, 4);
-+
-+			memcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);
-+		}
-+	}
-+
-+	/* this will be one of the 4 TX queues exposed to linux kernel */
-+	txq_id = skb_get_queue_mapping(skb);
-+	queue_id = edma_tx_queue_get(adapter, skb, txq_id);
-+	etdr = edma_cinfo->tpd_ring[queue_id];
-+	nq = netdev_get_tx_queue(net_dev, txq_id);
-+
-+	local_bh_disable();
-+	/* Tx is not handled in bottom half context. Hence, we need to protect
-+	 * Tx from tasks and bottom half
-+	 */
-+
-+	if (num_tpds_needed > edma_tpd_available(edma_cinfo, queue_id)) {
-+		/* not enough descriptor, just stop queue */
-+		netif_tx_stop_queue(nq);
-+		local_bh_enable();
-+		dev_dbg(&net_dev->dev, "Not enough descriptors available");
-+		edma_cinfo->edma_ethstats.tx_desc_error++;
-+		return NETDEV_TX_BUSY;
-+	}
-+
-+	/* Check and mark VLAN tag offload */
-+	if (skb_vlan_tag_present(skb))
-+		flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;
-+	else if (adapter->default_vlan_tag)
-+		flags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;
-+
-+	/* Check and mark checksum offload */
-+	if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
-+		flags_transmit |= EDMA_HW_CHECKSUM;
-+
-+	/* Map and fill descriptor for Tx */
-+	ret = edma_tx_map_and_fill(edma_cinfo, adapter, skb, queue_id,
-+		flags_transmit, from_cpu, dp_bitmap, packet_is_rstp, nr_frags);
-+	if (ret) {
-+		dev_kfree_skb_any(skb);
-+		adapter->stats.tx_errors++;
-+		goto netdev_okay;
-+	}
-+
-+	/* Update SW producer index */
-+	edma_tx_update_hw_idx(edma_cinfo, skb, queue_id);
-+
-+	/* update tx statistics */
-+	adapter->stats.tx_packets++;
-+	adapter->stats.tx_bytes += skb->len;
-+
-+netdev_okay:
-+	local_bh_enable();
-+	return NETDEV_TX_OK;
-+}
-+
-+/*
-+ * edma_flow_may_expire()
-+ * 	Timer function called periodically to delete the node
-+ */
-+void edma_flow_may_expire(unsigned long data)
-+{
-+	struct edma_adapter *adapter = (struct edma_adapter *)data;
-+	int j;
-+
-+	spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
-+	for (j = 0; j < EDMA_RFS_EXPIRE_COUNT_PER_CALL; j++) {
-+		struct hlist_head *hhead;
-+		struct hlist_node *tmp;
-+		struct edma_rfs_filter_node *n;
-+		bool res;
-+
-+		hhead = &adapter->rfs.hlist_head[adapter->rfs.hashtoclean++];
-+		hlist_for_each_entry_safe(n, tmp, hhead, node) {
-+			res = rps_may_expire_flow(adapter->netdev, n->rq_id,
-+					n->flow_id, n->filter_id);
-+			if (res) {
-+				int ret;
-+				ret = edma_delete_rfs_filter(adapter, n);
-+				if (ret < 0)
-+					dev_dbg(&adapter->netdev->dev,
-+							"RFS entry %d not allowed to be flushed by Switch",
-+							n->flow_id);
-+				else {
-+					hlist_del(&n->node);
-+					kfree(n);
-+					adapter->rfs.filter_available++;
-+				}
-+			}
-+		}
-+	}
-+
-+	adapter->rfs.hashtoclean = adapter->rfs.hashtoclean & (EDMA_RFS_FLOW_ENTRIES - 1);
-+	spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
-+	mod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4);
-+}
-+
-+/* edma_rx_flow_steer()
-+ *	Called by core to to steer the flow to CPU
-+ */
-+int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
-+		       u16 rxq, u32 flow_id)
-+{
-+	struct flow_keys keys;
-+	struct edma_rfs_filter_node *filter_node;
-+	struct edma_adapter *adapter = netdev_priv(dev);
-+	u16 hash_tblid;
-+	int res;
-+
-+	if (skb->protocol == htons(ETH_P_IPV6)) {
-+		dev_err(&adapter->pdev->dev, "IPv6 not supported\n");
-+		res = -EINVAL;
-+		goto no_protocol_err;
-+	}
-+
-+	/* Dissect flow parameters
-+	 * We only support IPv4 + TCP/UDP
-+	 */
-+	res = skb_flow_dissect_flow_keys(skb, &keys, 0);
-+	if (!((keys.basic.ip_proto == IPPROTO_TCP) || (keys.basic.ip_proto == IPPROTO_UDP))) {
-+		res = -EPROTONOSUPPORT;
-+		goto no_protocol_err;
-+	}
-+
-+	/* Check if table entry exists */
-+	hash_tblid = skb_get_hash_raw(skb) & EDMA_RFS_FLOW_ENTRIES_MASK;
-+
-+	spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
-+	filter_node = edma_rfs_key_search(&adapter->rfs.hlist_head[hash_tblid], &keys);
-+
-+	if (filter_node) {
-+		if (rxq == filter_node->rq_id) {
-+			res = -EEXIST;
-+			goto out;
-+		} else {
-+			res = edma_delete_rfs_filter(adapter, filter_node);
-+			if (res < 0)
-+				dev_warn(&adapter->netdev->dev,
-+						"Cannot steer flow %d to different queue",
-+						filter_node->flow_id);
-+			else {
-+				adapter->rfs.filter_available++;
-+				res = edma_add_rfs_filter(adapter, &keys, rxq, filter_node);
-+				if (res < 0) {
-+					dev_warn(&adapter->netdev->dev,
-+							"Cannot steer flow %d to different queue",
-+							filter_node->flow_id);
-+				} else {
-+					adapter->rfs.filter_available--;
-+					filter_node->rq_id = rxq;
-+					filter_node->filter_id = res;
-+				}
-+			}
-+		}
-+	} else {
-+		if (adapter->rfs.filter_available == 0) {
-+			res = -EBUSY;
-+			goto out;
-+		}
-+
-+		filter_node = kmalloc(sizeof(*filter_node), GFP_ATOMIC);
-+		if (!filter_node) {
-+			res = -ENOMEM;
-+			goto out;
-+		}
-+
-+		res = edma_add_rfs_filter(adapter, &keys, rxq, filter_node);
-+		if (res < 0) {
-+			kfree(filter_node);
-+			goto out;
-+		}
-+
-+		adapter->rfs.filter_available--;
-+		filter_node->rq_id = rxq;
-+		filter_node->filter_id = res;
-+		filter_node->flow_id = flow_id;
-+		filter_node->keys = keys;
-+		INIT_HLIST_NODE(&filter_node->node);
-+		hlist_add_head(&filter_node->node, &adapter->rfs.hlist_head[hash_tblid]);
-+	}
-+
-+out:
-+	spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
-+no_protocol_err:
-+	return res;
-+}
-+
-+/* edma_register_rfs_filter()
-+ *	Add RFS filter callback
-+ */
-+int edma_register_rfs_filter(struct net_device *netdev,
-+			    set_rfs_filter_callback_t set_filter)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+
-+	spin_lock_bh(&adapter->rfs.rfs_ftab_lock);
-+
-+	if (adapter->set_rfs_rule) {
-+		spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
-+		return -1;
-+	}
-+
-+	adapter->set_rfs_rule = set_filter;
-+	spin_unlock_bh(&adapter->rfs.rfs_ftab_lock);
-+
-+	return 0;
-+}
-+
-+/* edma_alloc_tx_rings()
-+ *	Allocate rx rings
-+ */
-+int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	int i, err = 0;
-+
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+		err = edma_alloc_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]);
-+		if (err) {
-+			dev_err(&pdev->dev, "Tx Queue alloc %u failed\n", i);
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/* edma_free_tx_rings()
-+ *	Free tx rings
-+ */
-+void edma_free_tx_rings(struct edma_common_info *edma_cinfo)
-+{
-+	int i;
-+
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++)
-+		edma_free_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]);
-+}
-+
-+/* edma_free_tx_resources()
-+ *	Free buffers associated with tx rings
-+ */
-+void edma_free_tx_resources(struct edma_common_info *edma_cinfo)
-+{
-+	struct edma_tx_desc_ring *etdr;
-+	struct edma_sw_desc *sw_desc;
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	int i, j;
-+
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+		etdr = edma_cinfo->tpd_ring[i];
-+		for (j = 0; j < EDMA_TX_RING_SIZE; j++) {
-+			sw_desc = &etdr->sw_desc[j];
-+			if (sw_desc->flags & (EDMA_SW_DESC_FLAG_SKB_HEAD |
-+				EDMA_SW_DESC_FLAG_SKB_FRAG | EDMA_SW_DESC_FLAG_SKB_FRAGLIST))
-+				edma_tx_unmap_and_free(pdev, sw_desc);
-+		}
-+	}
-+}
-+
-+/* edma_alloc_rx_rings()
-+ *	Allocate rx rings
-+ */
-+int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo)
-+{
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	int i, j, err = 0;
-+
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		err = edma_alloc_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]);
-+		if (err) {
-+			dev_err(&pdev->dev, "Rx Queue alloc%u failed\n", i);
-+			return err;
-+		}
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+
-+	return 0;
-+}
-+
-+/* edma_free_rx_rings()
-+ *	free rx rings
-+ */
-+void edma_free_rx_rings(struct edma_common_info *edma_cinfo)
-+{
-+	int i, j;
-+
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		edma_free_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]);
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+}
-+
-+/* edma_free_queues()
-+ *	Free the queues allocaated
-+ */
-+void edma_free_queues(struct edma_common_info *edma_cinfo)
-+{
-+	int i , j;
-+
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+		if (edma_cinfo->tpd_ring[i])
-+			kfree(edma_cinfo->tpd_ring[i]);
-+		edma_cinfo->tpd_ring[i] = NULL;
-+	}
-+
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		if (edma_cinfo->rfd_ring[j])
-+			kfree(edma_cinfo->rfd_ring[j]);
-+		edma_cinfo->rfd_ring[j] = NULL;
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+
-+	edma_cinfo->num_rx_queues = 0;
-+	edma_cinfo->num_tx_queues = 0;
-+
-+	return;
-+}
-+
-+/* edma_free_rx_resources()
-+ *	Free buffers associated with tx rings
-+ */
-+void edma_free_rx_resources(struct edma_common_info *edma_cinfo)
-+{
-+        struct edma_rfd_desc_ring *erdr;
-+	struct edma_sw_desc *sw_desc;
-+	struct platform_device *pdev = edma_cinfo->pdev;
-+	int i, j, k;
-+
-+	for (i = 0, k = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		erdr = edma_cinfo->rfd_ring[k];
-+		for (j = 0; j < EDMA_RX_RING_SIZE; j++) {
-+			sw_desc = &erdr->sw_desc[j];
-+			if (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD)) {
-+				dma_unmap_single(&pdev->dev, sw_desc->dma,
-+					sw_desc->length, DMA_FROM_DEVICE);
-+				edma_clean_rfd(erdr, j);
-+			} else if ((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)) {
-+				dma_unmap_page(&pdev->dev, sw_desc->dma,
-+					sw_desc->length, DMA_FROM_DEVICE);
-+				edma_clean_rfd(erdr, j);
-+			}
-+		}
-+		k += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+
-+	}
-+}
-+
-+/* edma_alloc_queues_tx()
-+ *	Allocate memory for all rings
-+ */
-+int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo)
-+{
-+	int i;
-+
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+		struct edma_tx_desc_ring *etdr;
-+		etdr = kzalloc(sizeof(struct edma_tx_desc_ring), GFP_KERNEL);
-+		if (!etdr)
-+			goto err;
-+		etdr->count = edma_cinfo->tx_ring_count;
-+		edma_cinfo->tpd_ring[i] = etdr;
-+	}
-+
-+	return 0;
-+err:
-+	edma_free_queues(edma_cinfo);
-+	return -1;
-+}
-+
-+/* edma_alloc_queues_rx()
-+ *	Allocate memory for all rings
-+ */
-+int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo)
-+{
-+	int i, j;
-+
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		struct edma_rfd_desc_ring *rfd_ring;
-+		rfd_ring = kzalloc(sizeof(struct edma_rfd_desc_ring),
-+				GFP_KERNEL);
-+		if (!rfd_ring)
-+			goto err;
-+		rfd_ring->count = edma_cinfo->rx_ring_count;
-+		edma_cinfo->rfd_ring[j] = rfd_ring;
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+	return 0;
-+err:
-+	edma_free_queues(edma_cinfo);
-+	return -1;
-+}
-+
-+/* edma_clear_irq_status()
-+ *	Clear interrupt status
-+ */
-+void edma_clear_irq_status()
-+{
-+	edma_write_reg(EDMA_REG_RX_ISR, 0xff);
-+	edma_write_reg(EDMA_REG_TX_ISR, 0xffff);
-+	edma_write_reg(EDMA_REG_MISC_ISR, 0x1fff);
-+	edma_write_reg(EDMA_REG_WOL_ISR, 0x1);
-+};
-+
-+/* edma_configure()
-+ *	Configure skb, edma interrupts and control register.
-+ */
-+int edma_configure(struct edma_common_info *edma_cinfo)
-+{
-+	struct edma_hw *hw = &edma_cinfo->hw;
-+	u32 intr_modrt_data;
-+	u32 intr_ctrl_data = 0;
-+	int i, j, ret_count;
-+
-+	edma_read_reg(EDMA_REG_INTR_CTRL, &intr_ctrl_data);
-+	intr_ctrl_data &= ~(1 << EDMA_INTR_SW_IDX_W_TYP_SHIFT);
-+	intr_ctrl_data |= hw->intr_sw_idx_w << EDMA_INTR_SW_IDX_W_TYP_SHIFT;
-+	edma_write_reg(EDMA_REG_INTR_CTRL, intr_ctrl_data);
-+
-+	edma_clear_irq_status();
-+
-+	/* Clear any WOL status */
-+	edma_write_reg(EDMA_REG_WOL_CTRL, 0);
-+	intr_modrt_data = (EDMA_TX_IMT << EDMA_IRQ_MODRT_TX_TIMER_SHIFT);
-+	intr_modrt_data |= (EDMA_RX_IMT << EDMA_IRQ_MODRT_RX_TIMER_SHIFT);
-+	edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
-+	edma_configure_tx(edma_cinfo);
-+	edma_configure_rx(edma_cinfo);
-+
-+	/* Allocate the RX buffer */
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		struct edma_rfd_desc_ring *ring = edma_cinfo->rfd_ring[j];
-+		ret_count = edma_alloc_rx_buf(edma_cinfo, ring, ring->count, j);
-+		if (ret_count) {
-+			dev_dbg(&edma_cinfo->pdev->dev, "not all rx buffers allocated\n");
-+		}
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+
-+	/* Configure descriptor Ring */
-+	edma_init_desc(edma_cinfo);
-+	return 0;
-+}
-+
-+/* edma_irq_enable()
-+ *	Enable default interrupt generation settings
-+ */
-+void edma_irq_enable(struct edma_common_info *edma_cinfo)
-+{
-+	struct edma_hw *hw = &edma_cinfo->hw;
-+	int i, j;
-+
-+	edma_write_reg(EDMA_REG_RX_ISR, 0xff);
-+	for (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {
-+		edma_write_reg(EDMA_REG_RX_INT_MASK_Q(j), hw->rx_intr_mask);
-+		j += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);
-+	}
-+	edma_write_reg(EDMA_REG_TX_ISR, 0xffff);
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++)
-+		edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), hw->tx_intr_mask);
-+}
-+
-+/* edma_irq_disable()
-+ *	Disable Interrupt
-+ */
-+void edma_irq_disable(struct edma_common_info *edma_cinfo)
-+{
-+	int i;
-+
-+	for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++)
-+		edma_write_reg(EDMA_REG_RX_INT_MASK_Q(i), 0x0);
-+
-+	for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++)
-+		edma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), 0x0);
-+	edma_write_reg(EDMA_REG_MISC_IMR, 0);
-+	edma_write_reg(EDMA_REG_WOL_IMR, 0);
-+}
-+
-+/* edma_free_irqs()
-+ *	Free All IRQs
-+ */
-+void edma_free_irqs(struct edma_adapter *adapter)
-+{
-+	struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
-+	int i, j;
-+	int k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2);
-+
-+	for (i = 0; i < CONFIG_NR_CPUS; i++) {
-+		for (j = edma_cinfo->edma_percpu_info[i].tx_start; j < (edma_cinfo->edma_percpu_info[i].tx_start + 4); j++)
-+			free_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]);
-+
-+		for (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++)
-+			free_irq(edma_cinfo->rx_irq[j], &edma_cinfo->edma_percpu_info[i]);
-+	}
-+}
-+
-+/* edma_enable_rx_ctrl()
-+ *	Enable RX queue control
-+ */
-+void edma_enable_rx_ctrl(struct edma_hw *hw)
-+{
-+	u32 data;
-+
-+	edma_read_reg(EDMA_REG_RXQ_CTRL, &data);
-+	data |= EDMA_RXQ_CTRL_EN;
-+	edma_write_reg(EDMA_REG_RXQ_CTRL, data);
-+}
-+
-+
-+/* edma_enable_tx_ctrl()
-+ *	Enable TX queue control
-+ */
-+void edma_enable_tx_ctrl(struct edma_hw *hw)
-+{
-+	u32 data;
-+
-+	edma_read_reg(EDMA_REG_TXQ_CTRL, &data);
-+	data |= EDMA_TXQ_CTRL_TXQ_EN;
-+	edma_write_reg(EDMA_REG_TXQ_CTRL, data);
-+}
-+
-+/* edma_stop_rx_tx()
-+ *	Disable RX/TQ Queue control
-+ */
-+void edma_stop_rx_tx(struct edma_hw *hw)
-+{
-+	u32 data;
-+
-+	edma_read_reg(EDMA_REG_RXQ_CTRL, &data);
-+	data &= ~EDMA_RXQ_CTRL_EN;
-+	edma_write_reg(EDMA_REG_RXQ_CTRL, data);
-+	edma_read_reg(EDMA_REG_TXQ_CTRL, &data);
-+	data &= ~EDMA_TXQ_CTRL_TXQ_EN;
-+	edma_write_reg(EDMA_REG_TXQ_CTRL, data);
-+}
-+
-+/* edma_reset()
-+ *	Reset the EDMA
-+ */
-+int edma_reset(struct edma_common_info *edma_cinfo)
-+{
-+	struct edma_hw *hw = &edma_cinfo->hw;
-+
-+	edma_irq_disable(edma_cinfo);
-+
-+	edma_clear_irq_status();
-+
-+	edma_stop_rx_tx(hw);
-+
-+	return 0;
-+}
-+
-+/* edma_fill_netdev()
-+ * 	Fill netdev for each etdr
-+ */
-+int edma_fill_netdev(struct edma_common_info *edma_cinfo, int queue_id,
-+		    int dev, int txq_id)
-+{
-+	struct edma_tx_desc_ring *etdr;
-+	int i = 0;
-+
-+	etdr = edma_cinfo->tpd_ring[queue_id];
-+
-+	while (etdr->netdev[i])
-+		i++;
-+
-+	if (i >= EDMA_MAX_NETDEV_PER_QUEUE)
-+		return -1;
-+
-+	/* Populate the netdev associated with the tpd ring */
-+	etdr->netdev[i] = edma_netdev[dev];
-+	etdr->nq[i] = netdev_get_tx_queue(edma_netdev[dev], txq_id);
-+
-+	return 0;
-+}
-+
-+/* edma_change_mtu()
-+ *	change the MTU of the NIC.
-+ */
-+int edma_change_mtu(struct net_device *netdev, int new_mtu)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+	struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
-+	int old_mtu = netdev->mtu;
-+	int max_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + (2 * VLAN_HLEN);
-+
-+	if ((max_frame_size < ETH_ZLEN + ETH_FCS_LEN) ||
-+		(max_frame_size > EDMA_MAX_JUMBO_FRAME_SIZE)) {
-+			dev_err(&edma_cinfo->pdev->dev, "MTU setting not correct\n");
-+			return -EINVAL;
-+	}
-+
-+	/* set MTU */
-+	if (old_mtu != new_mtu) {
-+		netdev->mtu = new_mtu;
-+		netdev_update_features(netdev);
-+	}
-+
-+	return 0;
-+}
-+
-+/* edma_set_mac()
-+ *	Change the Ethernet Address of the NIC
-+ */
-+int edma_set_mac_addr(struct net_device *netdev, void *p)
-+{
-+	struct sockaddr *addr = p;
-+
-+	if (!is_valid_ether_addr(addr->sa_data))
-+		return -EINVAL;
-+
-+	if (netif_running(netdev))
-+		return -EBUSY;
-+
-+	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
-+	return 0;
-+}
-+
-+/* edma_set_stp_rstp()
-+ *	set stp/rstp
-+ */
-+void edma_set_stp_rstp(bool rstp)
-+{
-+	edma_stp_rstp = rstp;
-+}
-+
-+/* edma_assign_ath_hdr_type()
-+ *	assign atheros header eth type
-+ */
-+void edma_assign_ath_hdr_type(int eth_type)
-+{
-+	edma_ath_eth_type = eth_type & EDMA_ETH_TYPE_MASK;
-+}
-+
-+/* edma_get_default_vlan_tag()
-+ *	Used by other modules to get the default vlan tag
-+ */
-+int edma_get_default_vlan_tag(struct net_device *netdev)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+
-+	if (adapter->default_vlan_tag)
-+		return adapter->default_vlan_tag;
-+
-+	return 0;
-+}
-+
-+/* edma_open()
-+ *	gets called when netdevice is up, start the queue.
-+ */
-+int edma_open(struct net_device *netdev)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+	struct platform_device *pdev = adapter->edma_cinfo->pdev;
-+
-+	netif_tx_start_all_queues(netdev);
-+	edma_initialise_rfs_flow_table(adapter);
-+	set_bit(__EDMA_UP, &adapter->state_flags);
-+
-+	/* if Link polling is enabled, in our case enabled for WAN, then
-+	 * do a phy start, else always set link as UP
-+	 */
-+	if (adapter->poll_required) {
-+		if (!IS_ERR(adapter->phydev)) {
-+			phy_start(adapter->phydev);
-+			phy_start_aneg(adapter->phydev);
-+			adapter->link_state = __EDMA_LINKDOWN;
-+		} else {
-+			dev_dbg(&pdev->dev, "Invalid PHY device for a link polled interface\n");
-+		}
-+	} else {
-+		adapter->link_state = __EDMA_LINKUP;
-+		netif_carrier_on(netdev);
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/* edma_close()
-+ *	gets called when netdevice is down, stops the queue.
-+ */
-+int edma_close(struct net_device *netdev)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+
-+	edma_free_rfs_flow_table(adapter);
-+	netif_carrier_off(netdev);
-+	netif_tx_stop_all_queues(netdev);
-+
-+	if (adapter->poll_required) {
-+		if (!IS_ERR(adapter->phydev))
-+			phy_stop(adapter->phydev);
-+	}
-+
-+	adapter->link_state = __EDMA_LINKDOWN;
-+
-+	/* Set GMAC state to UP before link state is checked
-+	 */
-+	clear_bit(__EDMA_UP, &adapter->state_flags);
-+
-+	return 0;
-+}
-+
-+/* edma_poll
-+ *	polling function that gets called when the napi gets scheduled.
-+ *
-+ * Main sequence of task performed in this api
-+ * is clear irq status -> clear_tx_irq -> clean_rx_irq->
-+ * enable interrupts.
-+ */
-+int edma_poll(struct napi_struct *napi, int budget)
-+{
-+	struct edma_per_cpu_queues_info *edma_percpu_info = container_of(napi,
-+		struct edma_per_cpu_queues_info, napi);
-+	struct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo;
-+	u32 reg_data;
-+	u32 shadow_rx_status, shadow_tx_status;
-+	int queue_id;
-+	int i, work_done = 0;
-+
-+	/* Store the Rx/Tx status by ANDing it with
-+	 * appropriate CPU RX?TX mask
-+	 */
-+	edma_read_reg(EDMA_REG_RX_ISR, &reg_data);
-+	edma_percpu_info->rx_status |= reg_data & edma_percpu_info->rx_mask;
-+	shadow_rx_status = edma_percpu_info->rx_status;
-+	edma_read_reg(EDMA_REG_TX_ISR, &reg_data);
-+	edma_percpu_info->tx_status |= reg_data & edma_percpu_info->tx_mask;
-+	shadow_tx_status = edma_percpu_info->tx_status;
-+
-+	/* Every core will have a start, which will be computed
-+	 * in probe and stored in edma_percpu_info->tx_start variable.
-+	 * We will shift the status bit by tx_start to obtain
-+	 * status bits for the core on which the current processing
-+	 * is happening. Since, there are 4 tx queues per core,
-+	 * we will run the loop till we get the correct queue to clear.
-+	 */
-+	while (edma_percpu_info->tx_status) {
-+		queue_id = ffs(edma_percpu_info->tx_status) - 1;
-+		edma_tx_complete(edma_cinfo, queue_id);
-+		edma_percpu_info->tx_status &= ~(1 << queue_id);
-+	}
-+
-+	/* Every core will have a start, which will be computed
-+	 * in probe and stored in edma_percpu_info->tx_start variable.
-+	 * We will shift the status bit by tx_start to obtain
-+	 * status bits for the core on which the current processing
-+	 * is happening. Since, there are 4 tx queues per core, we
-+	 * will run the loop till we get the correct queue to clear.
-+	 */
-+	while (edma_percpu_info->rx_status) {
-+		queue_id = ffs(edma_percpu_info->rx_status) - 1;
-+		edma_rx_complete(edma_cinfo, &work_done,
-+			        budget, queue_id, napi);
-+
-+		if (likely(work_done < budget))
-+			edma_percpu_info->rx_status &= ~(1 << queue_id);
-+		else
-+			break;
-+	}
-+
-+	/* Clear the status register, to avoid the interrupts to
-+	 * reoccur.This clearing of interrupt status register is
-+	 * done here as writing to status register only takes place
-+	 * once the  producer/consumer index has been updated to
-+	 * reflect that the packet transmission/reception went fine.
-+	 */
-+	edma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status);
-+	edma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status);
-+
-+	/* If budget not fully consumed, exit the polling mode */
-+	if (likely(work_done < budget)) {
-+		napi_complete(napi);
-+
-+		/* re-enable the interrupts */
-+		for (i = 0; i < edma_cinfo->num_rxq_per_core; i++)
-+			edma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x1);
-+		for (i = 0; i < edma_cinfo->num_txq_per_core; i++)
-+			edma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x1);
-+	}
-+
-+	return work_done;
-+}
-+
-+/* edma interrupt()
-+ *	interrupt handler
-+ */
-+irqreturn_t edma_interrupt(int irq, void *dev)
-+{
-+	struct edma_per_cpu_queues_info *edma_percpu_info = (struct edma_per_cpu_queues_info *) dev;
-+	struct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo;
-+	int i;
-+
-+	/* Unmask the TX/RX interrupt register */
-+	for (i = 0; i < edma_cinfo->num_rxq_per_core; i++)
-+		edma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x0);
-+
-+	for (i = 0; i < edma_cinfo->num_txq_per_core; i++)
-+		edma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x0);
-+
-+	napi_schedule(&edma_percpu_info->napi);
-+
-+	return IRQ_HANDLED;
-+}
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/edma.h
-@@ -0,0 +1,447 @@
-+/*
-+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#ifndef _EDMA_H_
-+#define _EDMA_H_
-+
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/module.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/skbuff.h>
-+#include <linux/io.h>
-+#include <linux/vmalloc.h>
-+#include <linux/pagemap.h>
-+#include <linux/smp.h>
-+#include <linux/platform_device.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/kernel.h>
-+#include <linux/device.h>
-+#include <linux/sysctl.h>
-+#include <linux/phy.h>
-+#include <linux/of_net.h>
-+#include <net/checksum.h>
-+#include <net/ip6_checksum.h>
-+#include <asm-generic/bug.h>
-+#include "ess_edma.h"
-+
-+#define EDMA_CPU_CORES_SUPPORTED 4
-+#define EDMA_MAX_PORTID_SUPPORTED 5
-+#define EDMA_MAX_VLAN_SUPPORTED  EDMA_MAX_PORTID_SUPPORTED
-+#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
-+#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f	/* 0001_1111 = 0x1f */
-+#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
-+
-+#define EDMA_MAX_RECEIVE_QUEUE 8
-+#define EDMA_MAX_TRANSMIT_QUEUE 16
-+
-+/* WAN/LAN adapter number */
-+#define EDMA_WAN 0
-+#define EDMA_LAN 1
-+
-+/* VLAN tag */
-+#define EDMA_LAN_DEFAULT_VLAN 1
-+#define EDMA_WAN_DEFAULT_VLAN 2
-+
-+#define EDMA_DEFAULT_GROUP1_VLAN 1
-+#define EDMA_DEFAULT_GROUP2_VLAN 2
-+#define EDMA_DEFAULT_GROUP3_VLAN 3
-+#define EDMA_DEFAULT_GROUP4_VLAN 4
-+#define EDMA_DEFAULT_GROUP5_VLAN 5
-+
-+/* Queues exposed to linux kernel */
-+#define EDMA_NETDEV_TX_QUEUE 4
-+#define EDMA_NETDEV_RX_QUEUE 4
-+
-+/* Number of queues per core */
-+#define EDMA_NUM_TXQ_PER_CORE 4
-+#define EDMA_NUM_RXQ_PER_CORE 2
-+
-+#define EDMA_TPD_EOP_SHIFT 31
-+
-+#define EDMA_PORT_ID_SHIFT 12
-+#define EDMA_PORT_ID_MASK 0x7
-+
-+/* tpd word 3 bit 18-28 */
-+#define EDMA_TPD_PORT_BITMAP_SHIFT 18
-+
-+#define EDMA_TPD_FROM_CPU_SHIFT 25
-+
-+#define EDMA_FROM_CPU_MASK 0x80
-+#define EDMA_SKB_PRIORITY_MASK 0x38
-+
-+/* TX/RX descriptor ring count */
-+/* should be a power of 2 */
-+#define EDMA_RX_RING_SIZE 128
-+#define EDMA_TX_RING_SIZE 128
-+
-+/* Flags used in paged/non paged mode */
-+#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
-+#define EDMA_RX_HEAD_BUFF_SIZE 1540
-+
-+/* MAX frame size supported by switch */
-+#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
-+
-+/* Configurations */
-+#define EDMA_INTR_CLEAR_TYPE 0
-+#define EDMA_INTR_SW_IDX_W_TYPE 0
-+#define EDMA_FIFO_THRESH_TYPE 0
-+#define EDMA_RSS_TYPE 0
-+#define EDMA_RX_IMT 0x0020
-+#define EDMA_TX_IMT 0x0050
-+#define EDMA_TPD_BURST 5
-+#define EDMA_TXF_BURST 0x100
-+#define EDMA_RFD_BURST 8
-+#define EDMA_RFD_THR 16
-+#define EDMA_RFD_LTHR 0
-+
-+/* RX/TX per CPU based mask/shift */
-+#define EDMA_TX_PER_CPU_MASK 0xF
-+#define EDMA_RX_PER_CPU_MASK 0x3
-+#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
-+#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
-+#define EDMA_TX_CPU_START_SHIFT 0x2
-+#define EDMA_RX_CPU_START_SHIFT 0x1
-+
-+/* FLags used in transmit direction */
-+#define EDMA_HW_CHECKSUM 0x00000001
-+#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
-+#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
-+
-+#define EDMA_SW_DESC_FLAG_LAST 0x1
-+#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
-+#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
-+#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
-+#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
-+#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
-+
-+
-+#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
-+
-+/* Ethtool specific list of EDMA supported features */
-+#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
-+					| SUPPORTED_10baseT_Full \
-+					| SUPPORTED_100baseT_Half \
-+					| SUPPORTED_100baseT_Full \
-+					| SUPPORTED_1000baseT_Full)
-+
-+/* Recevie side atheros Header */
-+#define EDMA_RX_ATH_HDR_VERSION 0x2
-+#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
-+#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
-+#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
-+#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
-+
-+/* Transmit side atheros Header */
-+#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
-+#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
-+#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
-+
-+#define EDMA_TXQ_START_CORE0 8
-+#define EDMA_TXQ_START_CORE1 12
-+#define EDMA_TXQ_START_CORE2 0
-+#define EDMA_TXQ_START_CORE3 4
-+
-+#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
-+#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
-+#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
-+#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
-+
-+#define EDMA_ETH_HDR_LEN 12
-+#define EDMA_ETH_TYPE_MASK 0xFFFF
-+
-+#define EDMA_RX_BUFFER_WRITE 16
-+#define EDMA_RFD_AVAIL_THR 80
-+
-+#define EDMA_GMAC_NO_MDIO_PHY	PHY_MAX_ADDR
-+
-+extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
-+				  __be16 sport, __be16 dport,
-+				  uint8_t proto, u16 loadbalance, bool action);
-+struct edma_ethtool_statistics {
-+	u32 tx_q0_pkt;
-+	u32 tx_q1_pkt;
-+	u32 tx_q2_pkt;
-+	u32 tx_q3_pkt;
-+	u32 tx_q4_pkt;
-+	u32 tx_q5_pkt;
-+	u32 tx_q6_pkt;
-+	u32 tx_q7_pkt;
-+	u32 tx_q8_pkt;
-+	u32 tx_q9_pkt;
-+	u32 tx_q10_pkt;
-+	u32 tx_q11_pkt;
-+	u32 tx_q12_pkt;
-+	u32 tx_q13_pkt;
-+	u32 tx_q14_pkt;
-+	u32 tx_q15_pkt;
-+	u32 tx_q0_byte;
-+	u32 tx_q1_byte;
-+	u32 tx_q2_byte;
-+	u32 tx_q3_byte;
-+	u32 tx_q4_byte;
-+	u32 tx_q5_byte;
-+	u32 tx_q6_byte;
-+	u32 tx_q7_byte;
-+	u32 tx_q8_byte;
-+	u32 tx_q9_byte;
-+	u32 tx_q10_byte;
-+	u32 tx_q11_byte;
-+	u32 tx_q12_byte;
-+	u32 tx_q13_byte;
-+	u32 tx_q14_byte;
-+	u32 tx_q15_byte;
-+	u32 rx_q0_pkt;
-+	u32 rx_q1_pkt;
-+	u32 rx_q2_pkt;
-+	u32 rx_q3_pkt;
-+	u32 rx_q4_pkt;
-+	u32 rx_q5_pkt;
-+	u32 rx_q6_pkt;
-+	u32 rx_q7_pkt;
-+	u32 rx_q0_byte;
-+	u32 rx_q1_byte;
-+	u32 rx_q2_byte;
-+	u32 rx_q3_byte;
-+	u32 rx_q4_byte;
-+	u32 rx_q5_byte;
-+	u32 rx_q6_byte;
-+	u32 rx_q7_byte;
-+	u32 tx_desc_error;
-+};
-+
-+struct edma_mdio_data {
-+	struct mii_bus	*mii_bus;
-+	void __iomem	*membase;
-+	int phy_irq[PHY_MAX_ADDR];
-+};
-+
-+/* EDMA LINK state */
-+enum edma_link_state {
-+	__EDMA_LINKUP, /* Indicate link is UP */
-+	__EDMA_LINKDOWN /* Indicate link is down */
-+};
-+
-+/* EDMA GMAC state */
-+enum edma_gmac_state {
-+	__EDMA_UP /* use to indicate GMAC is up */
-+};
-+
-+/* edma transmit descriptor */
-+struct edma_tx_desc {
-+	__le16  len; /* full packet including CRC */
-+	__le16  svlan_tag; /* vlan tag */
-+	__le32  word1; /* byte 4-7 */
-+	__le32  addr; /* address of buffer */
-+	__le32  word3; /* byte 12 */
-+};
-+
-+/* edma receive return descriptor */
-+struct edma_rx_return_desc {
-+	u16 rrd0;
-+	u16 rrd1;
-+	u16 rrd2;
-+	u16 rrd3;
-+	u16 rrd4;
-+	u16 rrd5;
-+	u16 rrd6;
-+	u16 rrd7;
-+};
-+
-+/* RFD descriptor */
-+struct edma_rx_free_desc {
-+	__le32  buffer_addr; /* buffer address */
-+};
-+
-+/* edma hw specific data */
-+struct edma_hw {
-+	u32  __iomem *hw_addr; /* inner register address */
-+	struct edma_adapter *adapter; /* netdevice adapter */
-+	u32 rx_intr_mask; /*rx interrupt mask */
-+	u32 tx_intr_mask; /* tx interrupt nask */
-+	u32 misc_intr_mask; /* misc interrupt mask */
-+	u32 wol_intr_mask; /* wake on lan interrupt mask */
-+	bool intr_clear_type; /* interrupt clear */
-+	bool intr_sw_idx_w; /* interrupt software index */
-+	u32 rx_head_buff_size; /* Rx buffer size */
-+	u8 rss_type; /* rss protocol type */
-+};
-+
-+/* edma_sw_desc stores software descriptor
-+ * SW descriptor has 1:1 map with HW descriptor
-+ */
-+struct edma_sw_desc {
-+	struct sk_buff *skb;
-+	dma_addr_t dma; /* dma address */
-+	u16 length; /* Tx/Rx buffer length */
-+	u32 flags;
-+};
-+
-+/* per core related information */
-+struct edma_per_cpu_queues_info {
-+	struct napi_struct napi; /* napi associated with the core */
-+	u32 tx_mask; /* tx interrupt mask */
-+	u32 rx_mask; /* rx interrupt mask */
-+	u32 tx_status; /* tx interrupt status */
-+	u32 rx_status; /* rx interrupt status */
-+	u32 tx_start; /* tx queue start */
-+	u32 rx_start; /* rx queue start */
-+	struct edma_common_info *edma_cinfo; /* edma common info */
-+};
-+
-+/* edma specific common info */
-+struct edma_common_info {
-+	struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
-+	struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
-+	struct platform_device *pdev; /* device structure */
-+	struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
-+	struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
-+	struct ctl_table_header *edma_ctl_table_hdr;
-+	int num_gmac;
-+	struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
-+	int num_rx_queues; /* number of rx queue */
-+	u32 num_tx_queues; /* number of tx queue */
-+	u32 tx_irq[16]; /* number of tx irq */
-+	u32 rx_irq[8]; /* number of rx irq */
-+	u32 from_cpu; /* from CPU TPD field */
-+	u32 num_rxq_per_core; /* Rx queues per core */
-+	u32 num_txq_per_core; /* Tx queues per core */
-+	u16 tx_ring_count; /* Tx ring count */
-+	u16 rx_ring_count; /* Rx ring*/
-+	u16 rx_head_buffer_len; /* rx buffer length */
-+	u16 rx_page_buffer_len; /* rx buffer length */
-+	u32 page_mode; /* Jumbo frame supported flag */
-+	u32 fraglist_mode; /* fraglist supported flag */
-+	struct edma_hw hw; /* edma hw specific structure */
-+	struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
-+	spinlock_t stats_lock; /* protect edma stats area for updation */
-+};
-+
-+/* transimit packet descriptor (tpd) ring */
-+struct edma_tx_desc_ring {
-+	struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
-+	struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
-+			/* Array of netdevs associated with the tpd ring */
-+	void *hw_desc; /* descriptor ring virtual address */
-+	struct edma_sw_desc *sw_desc; /* buffer associated with ring */
-+	int netdev_bmp; /* Bitmap for per-ring netdevs */
-+	u32 size; /* descriptor ring length in bytes */
-+	u16 count; /* number of descriptors in the ring */
-+	dma_addr_t dma; /* descriptor ring physical address */
-+	u16 sw_next_to_fill; /* next Tx descriptor to fill */
-+	u16 sw_next_to_clean; /* next Tx descriptor to clean */
-+};
-+
-+/* receive free descriptor (rfd) ring */
-+struct edma_rfd_desc_ring {
-+	void *hw_desc; /* descriptor ring virtual address */
-+	struct edma_sw_desc *sw_desc; /* buffer associated with ring */
-+	u16 size; /* bytes allocated to sw_desc */
-+	u16 count; /* number of descriptors in the ring */
-+	dma_addr_t dma; /* descriptor ring physical address */
-+	u16 sw_next_to_fill; /* next descriptor to fill */
-+	u16 sw_next_to_clean; /* next descriptor to clean */
-+};
-+
-+/* edma_rfs_flter_node - rfs filter node in hash table */
-+struct edma_rfs_filter_node {
-+	struct flow_keys keys;
-+	u32 flow_id; /* flow_id of filter provided by kernel */
-+	u16 filter_id; /* filter id of filter returned by adaptor */
-+	u16 rq_id; /* desired rq index */
-+	struct hlist_node node; /* edma rfs list node */
-+};
-+
-+/* edma_rfs_flow_tbl - rfs flow table */
-+struct edma_rfs_flow_table {
-+	u16 max_num_filter; /* Maximum number of filters edma supports */
-+	u16 hashtoclean; /* hash table index to clean next */
-+	int filter_available; /* Number of free filters available */
-+	struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
-+	spinlock_t rfs_ftab_lock;
-+	struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
-+};
-+
-+/* EDMA net device structure */
-+struct edma_adapter {
-+	struct net_device *netdev; /* netdevice */
-+	struct platform_device *pdev; /* platform device */
-+	struct edma_common_info *edma_cinfo; /* edma common info */
-+	struct phy_device *phydev; /* Phy device */
-+	struct edma_rfs_flow_table rfs; /* edma rfs flow table */
-+	struct net_device_stats stats; /* netdev statistics */
-+	set_rfs_filter_callback_t set_rfs_rule;
-+	u32 flags;/* status flags */
-+	unsigned long state_flags; /* GMAC up/down flags */
-+	u32 forced_speed; /* link force speed */
-+	u32 forced_duplex; /* link force duplex */
-+	u32 link_state; /* phy link state */
-+	u32 phy_mdio_addr; /* PHY device address on MII interface */
-+	u32 poll_required; /* check if link polling is required */
-+	u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
-+	u32 default_vlan_tag; /* vlan tag */
-+	u32 dp_bitmap;
-+	uint8_t phy_id[MII_BUS_ID_SIZE + 3];
-+};
-+
-+int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
-+int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
-+int edma_open(struct net_device *netdev);
-+int edma_close(struct net_device *netdev);
-+void edma_free_tx_resources(struct edma_common_info *edma_c_info);
-+void edma_free_rx_resources(struct edma_common_info *edma_c_info);
-+int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
-+int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
-+void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
-+void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
-+void edma_free_queues(struct edma_common_info *edma_cinfo);
-+void edma_irq_disable(struct edma_common_info *edma_cinfo);
-+int edma_reset(struct edma_common_info *edma_cinfo);
-+int edma_poll(struct napi_struct *napi, int budget);
-+netdev_tx_t edma_xmit(struct sk_buff *skb,
-+		struct net_device *netdev);
-+int edma_configure(struct edma_common_info *edma_cinfo);
-+void edma_irq_enable(struct edma_common_info *edma_cinfo);
-+void edma_enable_tx_ctrl(struct edma_hw *hw);
-+void edma_enable_rx_ctrl(struct edma_hw *hw);
-+void edma_stop_rx_tx(struct edma_hw *hw);
-+void edma_free_irqs(struct edma_adapter *adapter);
-+irqreturn_t edma_interrupt(int irq, void *dev);
-+void edma_write_reg(u16 reg_addr, u32 reg_value);
-+void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
-+struct net_device_stats *edma_get_stats(struct net_device *netdev);
-+int edma_set_mac_addr(struct net_device *netdev, void *p);
-+int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
-+		u16 rxq, u32 flow_id);
-+int edma_register_rfs_filter(struct net_device *netdev,
-+		set_rfs_filter_callback_t set_filter);
-+void edma_flow_may_expire(unsigned long data);
-+void edma_set_ethtool_ops(struct net_device *netdev);
-+int edma_change_mtu(struct net_device *netdev, int new_mtu);
-+void edma_set_stp_rstp(bool tag);
-+void edma_assign_ath_hdr_type(int tag);
-+int edma_get_default_vlan_tag(struct net_device *netdev);
-+void edma_adjust_link(struct net_device *netdev);
-+int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
-+void edma_read_append_stats(struct edma_common_info *edma_cinfo);
-+void edma_change_tx_coalesce(int usecs);
-+void edma_change_rx_coalesce(int usecs);
-+void edma_get_tx_rx_coalesce(u32 *reg_val);
-+void edma_clear_irq_status(void);
-+#endif /* _EDMA_H_ */
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/edma_axi.c
-@@ -0,0 +1,1220 @@
-+/*
-+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/cpu_rmap.h>
-+#include <linux/of.h>
-+#include <linux/of_net.h>
-+#include <linux/timer.h>
-+#include "edma.h"
-+#include "ess_edma.h"
-+
-+/* Weight round robin and virtual QID mask */
-+#define EDMA_WRR_VID_SCTL_MASK 0xffff
-+
-+/* Weight round robin and virtual QID shift */
-+#define EDMA_WRR_VID_SCTL_SHIFT 16
-+
-+char edma_axi_driver_name[] = "ess_edma";
-+static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
-+	NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
-+
-+static u32 edma_hw_addr;
-+
-+struct timer_list edma_stats_timer;
-+
-+char edma_tx_irq[16][64];
-+char edma_rx_irq[8][64];
-+struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];
-+static u16 tx_start[4] = {EDMA_TXQ_START_CORE0, EDMA_TXQ_START_CORE1,
-+			EDMA_TXQ_START_CORE2, EDMA_TXQ_START_CORE3};
-+static u32 tx_mask[4] = {EDMA_TXQ_IRQ_MASK_CORE0, EDMA_TXQ_IRQ_MASK_CORE1,
-+			EDMA_TXQ_IRQ_MASK_CORE2, EDMA_TXQ_IRQ_MASK_CORE3};
-+
-+static u32 edma_default_ltag  __read_mostly = EDMA_LAN_DEFAULT_VLAN;
-+static u32 edma_default_wtag  __read_mostly = EDMA_WAN_DEFAULT_VLAN;
-+static u32 edma_default_group1_vtag  __read_mostly = EDMA_DEFAULT_GROUP1_VLAN;
-+static u32 edma_default_group2_vtag  __read_mostly = EDMA_DEFAULT_GROUP2_VLAN;
-+static u32 edma_default_group3_vtag  __read_mostly = EDMA_DEFAULT_GROUP3_VLAN;
-+static u32 edma_default_group4_vtag  __read_mostly = EDMA_DEFAULT_GROUP4_VLAN;
-+static u32 edma_default_group5_vtag  __read_mostly = EDMA_DEFAULT_GROUP5_VLAN;
-+static u32 edma_rss_idt_val = EDMA_RSS_IDT_VALUE;
-+static u32 edma_rss_idt_idx;
-+
-+static int edma_weight_assigned_to_q __read_mostly;
-+static int edma_queue_to_virtual_q __read_mostly;
-+static bool edma_enable_rstp  __read_mostly;
-+static int edma_athr_hdr_eth_type __read_mostly;
-+
-+static int page_mode;
-+module_param(page_mode, int, 0);
-+MODULE_PARM_DESC(page_mode, "enable page mode");
-+
-+static int overwrite_mode;
-+module_param(overwrite_mode, int, 0);
-+MODULE_PARM_DESC(overwrite_mode, "overwrite default page_mode setting");
-+
-+static int jumbo_mru = EDMA_RX_HEAD_BUFF_SIZE;
-+module_param(jumbo_mru, int, 0);
-+MODULE_PARM_DESC(jumbo_mru, "enable fraglist support");
-+
-+static int num_rxq = 4;
-+module_param(num_rxq, int, 0);
-+MODULE_PARM_DESC(num_rxq, "change the number of rx queues");
-+
-+void edma_write_reg(u16 reg_addr, u32 reg_value)
-+{
-+	writel(reg_value, ((void __iomem *)(edma_hw_addr + reg_addr)));
-+}
-+
-+void edma_read_reg(u16 reg_addr, volatile u32 *reg_value)
-+{
-+	*reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr));
-+}
-+
-+/* edma_change_tx_coalesce()
-+ *	change tx interrupt moderation timer
-+ */
-+void edma_change_tx_coalesce(int usecs)
-+{
-+	u32 reg_value;
-+
-+	/* Here, we right shift the value from the user by 1, this is
-+	 * done because IMT resolution timer is 2usecs. 1 count
-+	 * of this register corresponds to 2 usecs.
-+	 */
-+	edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, &reg_value);
-+	reg_value = ((reg_value & 0xffff) | ((usecs >> 1) << 16));
-+	edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value);
-+}
-+
-+/* edma_change_rx_coalesce()
-+ *	change rx interrupt moderation timer
-+ */
-+void edma_change_rx_coalesce(int usecs)
-+{
-+	u32 reg_value;
-+
-+	/* Here, we right shift the value from the user by 1, this is
-+	 * done because IMT resolution timer is 2usecs. 1 count
-+	 * of this register corresponds to 2 usecs.
-+	 */
-+	edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, &reg_value);
-+	reg_value = ((reg_value & 0xffff0000) | (usecs >> 1));
-+	edma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value);
-+}
-+
-+/* edma_get_tx_rx_coalesce()
-+ *	Get tx/rx interrupt moderation value
-+ */
-+void edma_get_tx_rx_coalesce(u32 *reg_val)
-+{
-+	edma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_val);
-+}
-+
-+void edma_read_append_stats(struct edma_common_info *edma_cinfo)
-+{
-+	uint32_t *p;
-+	int i;
-+	u32 stat;
-+
-+	spin_lock(&edma_cinfo->stats_lock);
-+	p = (uint32_t *)&(edma_cinfo->edma_ethstats);
-+
-+	for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) {
-+		edma_read_reg(EDMA_REG_TX_STAT_PKT_Q(i), &stat);
-+		*p += stat;
-+		p++;
-+	}
-+
-+	for (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) {
-+		edma_read_reg(EDMA_REG_TX_STAT_BYTE_Q(i), &stat);
-+		*p += stat;
-+		p++;
-+	}
-+
-+	for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) {
-+		edma_read_reg(EDMA_REG_RX_STAT_PKT_Q(i), &stat);
-+		*p += stat;
-+		p++;
-+	}
-+
-+	for (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) {
-+		edma_read_reg(EDMA_REG_RX_STAT_BYTE_Q(i), &stat);
-+		*p += stat;
-+		p++;
-+	}
-+
-+	spin_unlock(&edma_cinfo->stats_lock);
-+}
-+
-+static void edma_statistics_timer(unsigned long data)
-+{
-+	struct edma_common_info *edma_cinfo = (struct edma_common_info *)data;
-+
-+	edma_read_append_stats(edma_cinfo);
-+
-+	mod_timer(&edma_stats_timer, jiffies + 1*HZ);
-+}
-+
-+static int edma_enable_stp_rstp(struct ctl_table *table, int write,
-+				void __user *buffer, size_t *lenp,
-+				loff_t *ppos)
-+{
-+	int ret;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+	if (write)
-+		edma_set_stp_rstp(edma_enable_rstp);
-+
-+	return ret;
-+}
-+
-+static int edma_ath_hdr_eth_type(struct ctl_table *table, int write,
-+				 void __user *buffer, size_t *lenp,
-+				 loff_t *ppos)
-+{
-+	int ret;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+	if (write)
-+		edma_assign_ath_hdr_type(edma_athr_hdr_eth_type);
-+
-+	return ret;
-+}
-+
-+static int edma_change_default_lan_vlan(struct ctl_table *table, int write,
-+					void __user *buffer, size_t *lenp,
-+					loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	int ret;
-+
-+	if (!edma_netdev[1]) {
-+		pr_err("Netdevice for default_lan does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[1]);
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_ltag;
-+
-+	return ret;
-+}
-+
-+static int edma_change_default_wan_vlan(struct ctl_table *table, int write,
-+					void __user *buffer, size_t *lenp,
-+					loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	int ret;
-+
-+	if (!edma_netdev[0]) {
-+		pr_err("Netdevice for default_wan does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[0]);
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_wtag;
-+
-+	return ret;
-+}
-+
-+static int edma_change_group1_vtag(struct ctl_table *table, int write,
-+				   void __user *buffer, size_t *lenp,
-+				   loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	struct edma_common_info *edma_cinfo;
-+	int ret;
-+
-+	if (!edma_netdev[0]) {
-+		pr_err("Netdevice for Group 1 does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[0]);
-+	edma_cinfo = adapter->edma_cinfo;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_group1_vtag;
-+
-+	return ret;
-+}
-+
-+static int edma_change_group2_vtag(struct ctl_table *table, int write,
-+				   void __user *buffer, size_t *lenp,
-+				   loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	struct edma_common_info *edma_cinfo;
-+	int ret;
-+
-+	if (!edma_netdev[1]) {
-+		pr_err("Netdevice for Group 2 does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[1]);
-+	edma_cinfo = adapter->edma_cinfo;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_group2_vtag;
-+
-+	return ret;
-+}
-+
-+static int edma_change_group3_vtag(struct ctl_table *table, int write,
-+				   void __user *buffer, size_t *lenp,
-+				   loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	struct edma_common_info *edma_cinfo;
-+	int ret;
-+
-+	if (!edma_netdev[2]) {
-+		pr_err("Netdevice for Group 3 does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[2]);
-+	edma_cinfo = adapter->edma_cinfo;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_group3_vtag;
-+
-+	return ret;
-+}
-+
-+static int edma_change_group4_vtag(struct ctl_table *table, int write,
-+				   void __user *buffer, size_t *lenp,
-+				   loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	struct edma_common_info *edma_cinfo;
-+	int ret;
-+
-+	if (!edma_netdev[3]) {
-+		pr_err("Netdevice for Group 4 does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[3]);
-+	edma_cinfo = adapter->edma_cinfo;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_group4_vtag;
-+
-+	return ret;
-+}
-+
-+static int edma_change_group5_vtag(struct ctl_table *table, int write,
-+				   void __user *buffer, size_t *lenp,
-+				   loff_t *ppos)
-+{
-+	struct edma_adapter *adapter;
-+	struct edma_common_info *edma_cinfo;
-+	int ret;
-+
-+	if (!edma_netdev[4]) {
-+		pr_err("Netdevice for Group 5 does not exist\n");
-+		return -1;
-+	}
-+
-+	adapter = netdev_priv(edma_netdev[4]);
-+	edma_cinfo = adapter->edma_cinfo;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+
-+	if (write)
-+		adapter->default_vlan_tag = edma_default_group5_vtag;
-+
-+	return ret;
-+}
-+
-+static int edma_set_rss_idt_value(struct ctl_table *table, int write,
-+				  void __user *buffer, size_t *lenp,
-+				  loff_t *ppos)
-+{
-+	int ret;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+	if (write && !ret)
-+		edma_write_reg(EDMA_REG_RSS_IDT(edma_rss_idt_idx),
-+			       edma_rss_idt_val);
-+	return ret;
-+}
-+
-+static int edma_set_rss_idt_idx(struct ctl_table *table, int write,
-+				void __user *buffer, size_t *lenp,
-+				loff_t *ppos)
-+{
-+	int ret;
-+	u32 old_value = edma_rss_idt_idx;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+	if (!write || ret)
-+		return ret;
-+
-+	if (edma_rss_idt_idx >= EDMA_NUM_IDT) {
-+		pr_err("Invalid RSS indirection table index %d\n",
-+		       edma_rss_idt_idx);
-+		edma_rss_idt_idx = old_value;
-+		return -EINVAL;
-+	}
-+	return ret;
-+}
-+
-+static int edma_weight_assigned_to_queues(struct ctl_table *table, int write,
-+					  void __user *buffer, size_t *lenp,
-+					  loff_t *ppos)
-+{
-+	int ret, queue_id, weight;
-+	u32 reg_data, data, reg_addr;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+	if (write) {
-+		queue_id = edma_weight_assigned_to_q & EDMA_WRR_VID_SCTL_MASK;
-+		if (queue_id < 0 || queue_id > 15) {
-+			pr_err("queue_id not within desired range\n");
-+			return -EINVAL;
-+		}
-+
-+		weight = edma_weight_assigned_to_q >> EDMA_WRR_VID_SCTL_SHIFT;
-+		if (weight < 0 || weight > 0xF) {
-+			pr_err("queue_id not within desired range\n");
-+			return -EINVAL;
-+		}
-+
-+		data = weight << EDMA_WRR_SHIFT(queue_id);
-+
-+		reg_addr = EDMA_REG_WRR_CTRL_Q0_Q3 + (queue_id & ~0x3);
-+		edma_read_reg(reg_addr, &reg_data);
-+		reg_data &= ~(1 << EDMA_WRR_SHIFT(queue_id));
-+		edma_write_reg(reg_addr, data | reg_data);
-+	}
-+
-+	return ret;
-+}
-+
-+static int edma_queue_to_virtual_queue_map(struct ctl_table *table, int write,
-+					   void __user *buffer, size_t *lenp,
-+					   loff_t *ppos)
-+{
-+	int ret, queue_id, virtual_qid;
-+	u32 reg_data, data, reg_addr;
-+
-+	ret = proc_dointvec(table, write, buffer, lenp, ppos);
-+	if (write) {
-+		queue_id = edma_queue_to_virtual_q & EDMA_WRR_VID_SCTL_MASK;
-+		if (queue_id < 0 || queue_id > 15) {
-+			pr_err("queue_id not within desired range\n");
-+			return -EINVAL;
-+		}
-+
-+		virtual_qid = edma_queue_to_virtual_q >>
-+			EDMA_WRR_VID_SCTL_SHIFT;
-+		if (virtual_qid < 0 || virtual_qid > 8) {
-+			pr_err("queue_id not within desired range\n");
-+			return -EINVAL;
-+		}
-+
-+		data = virtual_qid << EDMA_VQ_ID_SHIFT(queue_id);
-+
-+		reg_addr = EDMA_REG_VQ_CTRL0 + (queue_id & ~0x3);
-+		edma_read_reg(reg_addr, &reg_data);
-+		reg_data &= ~(1 << EDMA_VQ_ID_SHIFT(queue_id));
-+		edma_write_reg(reg_addr, data | reg_data);
-+	}
-+
-+	return ret;
-+}
-+
-+static struct ctl_table edma_table[] = {
-+	{
-+		.procname       = "default_lan_tag",
-+		.data           = &edma_default_ltag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_default_lan_vlan
-+	},
-+	{
-+		.procname       = "default_wan_tag",
-+		.data           = &edma_default_wtag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_default_wan_vlan
-+	},
-+	{
-+		.procname       = "weight_assigned_to_queues",
-+		.data           = &edma_weight_assigned_to_q,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_weight_assigned_to_queues
-+	},
-+	{
-+		.procname       = "queue_to_virtual_queue_map",
-+		.data           = &edma_queue_to_virtual_q,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_queue_to_virtual_queue_map
-+	},
-+	{
-+		.procname       = "enable_stp_rstp",
-+		.data           = &edma_enable_rstp,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_enable_stp_rstp
-+	},
-+	{
-+		.procname       = "athr_hdr_eth_type",
-+		.data           = &edma_athr_hdr_eth_type,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_ath_hdr_eth_type
-+	},
-+	{
-+		.procname       = "default_group1_vlan_tag",
-+		.data           = &edma_default_group1_vtag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_group1_vtag
-+	},
-+	{
-+		.procname       = "default_group2_vlan_tag",
-+		.data           = &edma_default_group2_vtag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_group2_vtag
-+	},
-+	{
-+		.procname       = "default_group3_vlan_tag",
-+		.data           = &edma_default_group3_vtag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_group3_vtag
-+	},
-+	{
-+		.procname       = "default_group4_vlan_tag",
-+		.data           = &edma_default_group4_vtag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_group4_vtag
-+	},
-+	{
-+		.procname       = "default_group5_vlan_tag",
-+		.data           = &edma_default_group5_vtag,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_change_group5_vtag
-+	},
-+	{
-+		.procname       = "edma_rss_idt_value",
-+		.data           = &edma_rss_idt_val,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_set_rss_idt_value
-+	},
-+	{
-+		.procname       = "edma_rss_idt_idx",
-+		.data           = &edma_rss_idt_idx,
-+		.maxlen         = sizeof(int),
-+		.mode           = 0644,
-+		.proc_handler   = edma_set_rss_idt_idx
-+	},
-+	{}
-+};
-+
-+/* edma_axi_netdev_ops
-+ *	Describe the operations supported by registered netdevices
-+ *
-+ * static const struct net_device_ops edma_axi_netdev_ops = {
-+ *	.ndo_open               = edma_open,
-+ *	.ndo_stop               = edma_close,
-+ *	.ndo_start_xmit         = edma_xmit_frame,
-+ *	.ndo_set_mac_address    = edma_set_mac_addr,
-+ * }
-+ */
-+static const struct net_device_ops edma_axi_netdev_ops = {
-+	.ndo_open               = edma_open,
-+	.ndo_stop               = edma_close,
-+	.ndo_start_xmit         = edma_xmit,
-+	.ndo_set_mac_address    = edma_set_mac_addr,
-+#ifdef CONFIG_RFS_ACCEL
-+	.ndo_rx_flow_steer      = edma_rx_flow_steer,
-+	.ndo_register_rfs_filter = edma_register_rfs_filter,
-+	.ndo_get_default_vlan_tag = edma_get_default_vlan_tag,
-+#endif
-+	.ndo_get_stats          = edma_get_stats,
-+	.ndo_change_mtu		= edma_change_mtu,
-+};
-+
-+/* edma_axi_probe()
-+ *	Initialise an adapter identified by a platform_device structure.
-+ *
-+ * The OS initialization, configuring of the adapter private structure,
-+ * and a hardware reset occur in the probe.
-+ */
-+static int edma_axi_probe(struct platform_device *pdev)
-+{
-+	struct edma_common_info *edma_cinfo;
-+	struct edma_hw *hw;
-+	struct edma_adapter *adapter[EDMA_MAX_PORTID_SUPPORTED];
-+	struct resource *res;
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device_node *pnp;
-+	struct device_node *mdio_node = NULL;
-+	struct platform_device *mdio_plat = NULL;
-+	struct mii_bus *miibus = NULL;
-+	struct edma_mdio_data *mdio_data = NULL;
-+	int i, j, k, err = 0;
-+	int portid_bmp;
-+	int idx = 0, idx_mac = 0;
-+
-+	if (CONFIG_NR_CPUS != EDMA_CPU_CORES_SUPPORTED) {
-+		dev_err(&pdev->dev, "Invalid CPU Cores\n");
-+		return -EINVAL;
-+	}
-+
-+	if ((num_rxq != 4) && (num_rxq != 8)) {
-+		dev_err(&pdev->dev, "Invalid RX queue, edma probe failed\n");
-+		return -EINVAL;
-+	}
-+	edma_cinfo = kzalloc(sizeof(struct edma_common_info), GFP_KERNEL);
-+	if (!edma_cinfo) {
-+		err = -ENOMEM;
-+		goto err_alloc;
-+	}
-+
-+	edma_cinfo->pdev = pdev;
-+
-+	of_property_read_u32(np, "qcom,num_gmac", &edma_cinfo->num_gmac);
-+	if (edma_cinfo->num_gmac > EDMA_MAX_PORTID_SUPPORTED) {
-+		pr_err("Invalid DTSI Entry for qcom,num_gmac\n");
-+		err = -EINVAL;
-+		goto err_cinfo;
-+	}
-+
-+	/* Initialize the netdev array before allocation
-+	 * to avoid double free
-+	 */
-+	for (i = 0 ; i < edma_cinfo->num_gmac ; i++)
-+		edma_netdev[i] = NULL;
-+
-+	for (i = 0 ; i < edma_cinfo->num_gmac ; i++) {
-+		edma_netdev[i] = alloc_etherdev_mqs(sizeof(struct edma_adapter),
-+			EDMA_NETDEV_TX_QUEUE, EDMA_NETDEV_RX_QUEUE);
-+
-+		if (!edma_netdev[i]) {
-+			dev_err(&pdev->dev,
-+				"net device alloc fails for index=%d\n", i);
-+			err = -ENODEV;
-+			goto err_ioremap;
-+		}
-+
-+		SET_NETDEV_DEV(edma_netdev[i], &pdev->dev);
-+		platform_set_drvdata(pdev, edma_netdev[i]);
-+		edma_cinfo->netdev[i] = edma_netdev[i];
-+	}
-+
-+	/* Fill ring details */
-+	edma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE;
-+	edma_cinfo->num_txq_per_core = (EDMA_MAX_TRANSMIT_QUEUE / 4);
-+	edma_cinfo->tx_ring_count = EDMA_TX_RING_SIZE;
-+
-+	/* Update num rx queues based on module parameter */
-+	edma_cinfo->num_rx_queues = num_rxq;
-+	edma_cinfo->num_rxq_per_core = ((num_rxq == 4) ? 1 : 2);
-+
-+	edma_cinfo->rx_ring_count = EDMA_RX_RING_SIZE;
-+
-+	hw = &edma_cinfo->hw;
-+
-+	/* Fill HW defaults */
-+	hw->tx_intr_mask = EDMA_TX_IMR_NORMAL_MASK;
-+	hw->rx_intr_mask = EDMA_RX_IMR_NORMAL_MASK;
-+
-+	of_property_read_u32(np, "qcom,page-mode", &edma_cinfo->page_mode);
-+	of_property_read_u32(np, "qcom,rx_head_buf_size",
-+			     &hw->rx_head_buff_size);
-+
-+	if (overwrite_mode) {
-+		dev_info(&pdev->dev, "page mode overwritten");
-+		edma_cinfo->page_mode = page_mode;
-+	}
-+
-+	if (jumbo_mru)
-+		edma_cinfo->fraglist_mode = 1;
-+
-+	if (edma_cinfo->page_mode)
-+		hw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE_JUMBO;
-+	else if (edma_cinfo->fraglist_mode)
-+		hw->rx_head_buff_size = jumbo_mru;
-+	else if (!hw->rx_head_buff_size)
-+		hw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE;
-+
-+	hw->misc_intr_mask = 0;
-+	hw->wol_intr_mask = 0;
-+
-+	hw->intr_clear_type = EDMA_INTR_CLEAR_TYPE;
-+	hw->intr_sw_idx_w = EDMA_INTR_SW_IDX_W_TYPE;
-+
-+	/* configure RSS type to the different protocol that can be
-+	 * supported
-+	 */
-+	hw->rss_type = EDMA_RSS_TYPE_IPV4TCP | EDMA_RSS_TYPE_IPV6_TCP |
-+		EDMA_RSS_TYPE_IPV4_UDP | EDMA_RSS_TYPE_IPV6UDP |
-+		EDMA_RSS_TYPE_IPV4 | EDMA_RSS_TYPE_IPV6;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+
-+	edma_cinfo->hw.hw_addr = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(edma_cinfo->hw.hw_addr)) {
-+		err = PTR_ERR(edma_cinfo->hw.hw_addr);
-+		goto err_ioremap;
-+	}
-+
-+	edma_hw_addr = (u32)edma_cinfo->hw.hw_addr;
-+
-+	/* Parse tx queue interrupt number from device tree */
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++)
-+		edma_cinfo->tx_irq[i] = platform_get_irq(pdev, i);
-+
-+	/* Parse rx queue interrupt number from device tree
-+	 * Here we are setting j to point to the point where we
-+	 * left tx interrupt parsing(i.e 16) and run run the loop
-+	 * from 0 to 7 to parse rx interrupt number.
-+	 */
-+	for (i = 0, j = edma_cinfo->num_tx_queues, k = 0;
-+			i < edma_cinfo->num_rx_queues; i++) {
-+		edma_cinfo->rx_irq[k] = platform_get_irq(pdev, j);
-+		k += ((num_rxq == 4) ?  2 : 1);
-+		j += ((num_rxq == 4) ?  2 : 1);
-+	}
-+
-+	edma_cinfo->rx_head_buffer_len = edma_cinfo->hw.rx_head_buff_size;
-+	edma_cinfo->rx_page_buffer_len = PAGE_SIZE;
-+
-+	err = edma_alloc_queues_tx(edma_cinfo);
-+	if (err) {
-+		dev_err(&pdev->dev, "Allocation of TX queue failed\n");
-+		goto err_tx_qinit;
-+	}
-+
-+	err = edma_alloc_queues_rx(edma_cinfo);
-+	if (err) {
-+		dev_err(&pdev->dev, "Allocation of RX queue failed\n");
-+		goto err_rx_qinit;
-+	}
-+
-+	err = edma_alloc_tx_rings(edma_cinfo);
-+	if (err) {
-+		dev_err(&pdev->dev, "Allocation of TX resources failed\n");
-+		goto err_tx_rinit;
-+	}
-+
-+	err = edma_alloc_rx_rings(edma_cinfo);
-+	if (err) {
-+		dev_err(&pdev->dev, "Allocation of RX resources failed\n");
-+		goto err_rx_rinit;
-+	}
-+
-+	/* Initialize netdev and netdev bitmap for transmit descriptor rings */
-+	for (i = 0; i < edma_cinfo->num_tx_queues; i++) {
-+		struct edma_tx_desc_ring *etdr =  edma_cinfo->tpd_ring[i];
-+		int j;
-+
-+		etdr->netdev_bmp = 0;
-+		for (j = 0; j < EDMA_MAX_NETDEV_PER_QUEUE; j++) {
-+			etdr->netdev[j] = NULL;
-+			etdr->nq[j] = NULL;
-+		}
-+	}
-+
-+	if (of_property_read_bool(np, "qcom,mdio_supported")) {
-+		mdio_node = of_find_compatible_node(NULL, NULL,
-+						    "qcom,ipq4019-mdio");
-+		if (!mdio_node) {
-+			dev_err(&pdev->dev, "cannot find mdio node by phandle");
-+			err = -EIO;
-+			goto err_mdiobus_init_fail;
-+		}
-+
-+		mdio_plat = of_find_device_by_node(mdio_node);
-+		if (!mdio_plat) {
-+			dev_err(&pdev->dev,
-+				"cannot find platform device from mdio node");
-+			of_node_put(mdio_node);
-+			err = -EIO;
-+			goto err_mdiobus_init_fail;
-+		}
-+
-+		mdio_data = dev_get_drvdata(&mdio_plat->dev);
-+		if (!mdio_data) {
-+			dev_err(&pdev->dev,
-+				"cannot get mii bus reference from device data");
-+			of_node_put(mdio_node);
-+			err = -EIO;
-+			goto err_mdiobus_init_fail;
-+		}
-+
-+		miibus = mdio_data->mii_bus;
-+	}
-+
-+	for_each_available_child_of_node(np, pnp) {
-+		const char *mac_addr;
-+
-+		/* this check is needed if parent and daughter dts have
-+		 * different number of gmac nodes
-+		 */
-+		if (idx_mac == edma_cinfo->num_gmac) {
-+			of_node_put(np);
-+			break;
-+		}
-+
-+		mac_addr = of_get_mac_address(pnp);
-+		if (mac_addr)
-+			memcpy(edma_netdev[idx_mac]->dev_addr, mac_addr, ETH_ALEN);
-+
-+		idx_mac++;
-+	}
-+
-+	/* Populate the adapter structure register the netdevice */
-+	for (i = 0; i < edma_cinfo->num_gmac; i++) {
-+		int k, m;
-+
-+		adapter[i] = netdev_priv(edma_netdev[i]);
-+		adapter[i]->netdev = edma_netdev[i];
-+		adapter[i]->pdev = pdev;
-+		for (j = 0; j < CONFIG_NR_CPUS; j++) {
-+			m = i % 2;
-+			adapter[i]->tx_start_offset[j] =
-+				((j << EDMA_TX_CPU_START_SHIFT) + (m << 1));
-+			/* Share the queues with available net-devices.
-+			 * For instance , with 5 net-devices
-+			 * eth0/eth2/eth4 will share q0,q1,q4,q5,q8,q9,q12,q13
-+			 * and eth1/eth3 will get the remaining.
-+			 */
-+			for (k = adapter[i]->tx_start_offset[j]; k <
-+			     (adapter[i]->tx_start_offset[j] + 2); k++) {
-+				if (edma_fill_netdev(edma_cinfo, k, i, j)) {
-+					pr_err("Netdev overflow Error\n");
-+					goto err_register;
-+				}
-+			}
-+		}
-+
-+		adapter[i]->edma_cinfo = edma_cinfo;
-+		edma_netdev[i]->netdev_ops = &edma_axi_netdev_ops;
-+		edma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM
-+				      | NETIF_F_HW_VLAN_CTAG_TX
-+				      | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |
-+				      NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GRO;
-+		edma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
-+				NETIF_F_HW_VLAN_CTAG_RX
-+				| NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
-+				NETIF_F_GRO;
-+		edma_netdev[i]->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG |
-+					   NETIF_F_TSO | NETIF_F_TSO6 |
-+					   NETIF_F_GRO;
-+		edma_netdev[i]->wanted_features = NETIF_F_HW_CSUM | NETIF_F_SG |
-+					     NETIF_F_TSO | NETIF_F_TSO6 |
-+					     NETIF_F_GRO;
-+
-+#ifdef CONFIG_RFS_ACCEL
-+		edma_netdev[i]->features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;
-+		edma_netdev[i]->hw_features |=  NETIF_F_RXHASH | NETIF_F_NTUPLE;
-+		edma_netdev[i]->vlan_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
-+		edma_netdev[i]->wanted_features |= NETIF_F_RXHASH | NETIF_F_NTUPLE;
-+#endif
-+		edma_set_ethtool_ops(edma_netdev[i]);
-+
-+		/* This just fill in some default MAC address
-+		 */
-+		if (!is_valid_ether_addr(edma_netdev[i]->dev_addr)) {
-+			random_ether_addr(edma_netdev[i]->dev_addr);
-+			pr_info("EDMA using MAC@ - using");
-+			pr_info("%02x:%02x:%02x:%02x:%02x:%02x\n",
-+			*(edma_netdev[i]->dev_addr),
-+			*(edma_netdev[i]->dev_addr + 1),
-+			*(edma_netdev[i]->dev_addr + 2),
-+			*(edma_netdev[i]->dev_addr + 3),
-+			*(edma_netdev[i]->dev_addr + 4),
-+			*(edma_netdev[i]->dev_addr + 5));
-+		}
-+
-+		err = register_netdev(edma_netdev[i]);
-+		if (err)
-+			goto err_register;
-+
-+		/* carrier off reporting is important to
-+		 * ethtool even BEFORE open
-+		 */
-+		netif_carrier_off(edma_netdev[i]);
-+
-+		/* Allocate reverse irq cpu mapping structure for
-+		* receive queues
-+		*/
-+#ifdef CONFIG_RFS_ACCEL
-+		edma_netdev[i]->rx_cpu_rmap =
-+			alloc_irq_cpu_rmap(EDMA_NETDEV_RX_QUEUE);
-+		if (!edma_netdev[i]->rx_cpu_rmap) {
-+			err = -ENOMEM;
-+			goto err_rmap_alloc_fail;
-+		}
-+#endif
-+	}
-+
-+	for (i = 0; i < EDMA_MAX_PORTID_BITMAP_INDEX; i++)
-+		edma_cinfo->portid_netdev_lookup_tbl[i] = NULL;
-+
-+	for_each_available_child_of_node(np, pnp) {
-+		const uint32_t *vlan_tag = NULL;
-+		int len;
-+
-+		/* this check is needed if parent and daughter dts have
-+		 * different number of gmac nodes
-+		 */
-+		if (idx == edma_cinfo->num_gmac)
-+			break;
-+
-+		/* Populate port-id to netdev lookup table */
-+		vlan_tag = of_get_property(pnp, "vlan_tag", &len);
-+		if (!vlan_tag) {
-+			pr_err("Vlan tag parsing Failed.\n");
-+			goto err_rmap_alloc_fail;
-+		}
-+
-+		adapter[idx]->default_vlan_tag = of_read_number(vlan_tag, 1);
-+		vlan_tag++;
-+		portid_bmp = of_read_number(vlan_tag, 1);
-+		adapter[idx]->dp_bitmap = portid_bmp;
-+
-+		portid_bmp = portid_bmp >> 1; /* We ignore CPU Port bit 0 */
-+		while (portid_bmp) {
-+			int port_bit = ffs(portid_bmp);
-+
-+			if (port_bit > EDMA_MAX_PORTID_SUPPORTED)
-+				goto err_rmap_alloc_fail;
-+			edma_cinfo->portid_netdev_lookup_tbl[port_bit] =
-+				edma_netdev[idx];
-+			portid_bmp &= ~(1 << (port_bit - 1));
-+		}
-+
-+		if (!of_property_read_u32(pnp, "qcom,poll_required",
-+					  &adapter[idx]->poll_required)) {
-+			if (adapter[idx]->poll_required) {
-+				of_property_read_u32(pnp, "qcom,phy_mdio_addr",
-+						     &adapter[idx]->phy_mdio_addr);
-+				of_property_read_u32(pnp, "qcom,forced_speed",
-+						     &adapter[idx]->forced_speed);
-+				of_property_read_u32(pnp, "qcom,forced_duplex",
-+						     &adapter[idx]->forced_duplex);
-+
-+				/* create a phyid using MDIO bus id
-+				 * and MDIO bus address
-+				 */
-+				snprintf(adapter[idx]->phy_id,
-+					 MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
-+					 miibus->id,
-+					 adapter[idx]->phy_mdio_addr);
-+			}
-+		} else {
-+			adapter[idx]->poll_required = 0;
-+			adapter[idx]->forced_speed = SPEED_1000;
-+			adapter[idx]->forced_duplex = DUPLEX_FULL;
-+		}
-+
-+		idx++;
-+	}
-+
-+	edma_cinfo->edma_ctl_table_hdr = register_net_sysctl(&init_net,
-+							     "net/edma",
-+							     edma_table);
-+	if (!edma_cinfo->edma_ctl_table_hdr) {
-+		dev_err(&pdev->dev, "edma sysctl table hdr not registered\n");
-+		goto err_unregister_sysctl_tbl;
-+	}
-+
-+	/* Disable all 16 Tx and 8 rx irqs */
-+	edma_irq_disable(edma_cinfo);
-+
-+	err = edma_reset(edma_cinfo);
-+	if (err) {
-+		err = -EIO;
-+		goto err_reset;
-+	}
-+
-+	/* populate per_core_info, do a napi_Add, request 16 TX irqs,
-+	 * 8 RX irqs, do a napi enable
-+	 */
-+	for (i = 0; i < CONFIG_NR_CPUS; i++) {
-+		u8 rx_start;
-+
-+		edma_cinfo->edma_percpu_info[i].napi.state = 0;
-+
-+		netif_napi_add(edma_netdev[0],
-+			       &edma_cinfo->edma_percpu_info[i].napi,
-+			       edma_poll, 64);
-+		napi_enable(&edma_cinfo->edma_percpu_info[i].napi);
-+		edma_cinfo->edma_percpu_info[i].tx_mask = tx_mask[i];
-+		edma_cinfo->edma_percpu_info[i].rx_mask = EDMA_RX_PER_CPU_MASK
-+				<< (i << EDMA_RX_PER_CPU_MASK_SHIFT);
-+		edma_cinfo->edma_percpu_info[i].tx_start = tx_start[i];
-+		edma_cinfo->edma_percpu_info[i].rx_start =
-+			i << EDMA_RX_CPU_START_SHIFT;
-+		rx_start = i << EDMA_RX_CPU_START_SHIFT;
-+		edma_cinfo->edma_percpu_info[i].tx_status = 0;
-+		edma_cinfo->edma_percpu_info[i].rx_status = 0;
-+		edma_cinfo->edma_percpu_info[i].edma_cinfo = edma_cinfo;
-+
-+		/* Request irq per core */
-+		for (j = edma_cinfo->edma_percpu_info[i].tx_start;
-+		     j < tx_start[i] + 4; j++) {
-+			sprintf(&edma_tx_irq[j][0], "edma_eth_tx%d", j);
-+			err = request_irq(edma_cinfo->tx_irq[j],
-+					  edma_interrupt,
-+					  0,
-+					  &edma_tx_irq[j][0],
-+					  &edma_cinfo->edma_percpu_info[i]);
-+			if (err)
-+				goto err_reset;
-+		}
-+
-+		for (j = edma_cinfo->edma_percpu_info[i].rx_start;
-+		     j < (rx_start +
-+		     ((edma_cinfo->num_rx_queues == 4) ? 1 : 2));
-+		     j++) {
-+			sprintf(&edma_rx_irq[j][0], "edma_eth_rx%d", j);
-+			err = request_irq(edma_cinfo->rx_irq[j],
-+					  edma_interrupt,
-+					  0,
-+					  &edma_rx_irq[j][0],
-+					  &edma_cinfo->edma_percpu_info[i]);
-+			if (err)
-+				goto err_reset;
-+		}
-+
-+#ifdef CONFIG_RFS_ACCEL
-+		for (j = edma_cinfo->edma_percpu_info[i].rx_start;
-+		     j < rx_start + 2; j += 2) {
-+			err = irq_cpu_rmap_add(edma_netdev[0]->rx_cpu_rmap,
-+					       edma_cinfo->rx_irq[j]);
-+			if (err)
-+				goto err_rmap_add_fail;
-+		}
-+#endif
-+	}
-+
-+	/* Used to clear interrupt status, allocate rx buffer,
-+	 * configure edma descriptors registers
-+	 */
-+	err = edma_configure(edma_cinfo);
-+	if (err) {
-+		err = -EIO;
-+		goto err_configure;
-+	}
-+
-+	/* Configure RSS indirection table.
-+	 * 128 hash will be configured in the following
-+	 * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively
-+	 * and so on
-+	 */
-+	for (i = 0; i < EDMA_NUM_IDT; i++)
-+		edma_write_reg(EDMA_REG_RSS_IDT(i), EDMA_RSS_IDT_VALUE);
-+
-+	/* Configure load balance mapping table.
-+	 * 4 table entry will be configured according to the
-+	 * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4}
-+	 * respectively.
-+	 */
-+	edma_write_reg(EDMA_REG_LB_RING, EDMA_LB_REG_VALUE);
-+
-+	/* Configure Virtual queue for Tx rings
-+	 * User can also change this value runtime through
-+	 * a sysctl
-+	 */
-+	edma_write_reg(EDMA_REG_VQ_CTRL0, EDMA_VQ_REG_VALUE);
-+	edma_write_reg(EDMA_REG_VQ_CTRL1, EDMA_VQ_REG_VALUE);
-+
-+	/* Configure Max AXI Burst write size to 128 bytes*/
-+	edma_write_reg(EDMA_REG_AXIW_CTRL_MAXWRSIZE,
-+		       EDMA_AXIW_MAXWRSIZE_VALUE);
-+
-+	/* Enable All 16 tx and 8 rx irq mask */
-+	edma_irq_enable(edma_cinfo);
-+	edma_enable_tx_ctrl(&edma_cinfo->hw);
-+	edma_enable_rx_ctrl(&edma_cinfo->hw);
-+
-+	for (i = 0; i < edma_cinfo->num_gmac; i++) {
-+		if (adapter[i]->poll_required) {
-+			adapter[i]->phydev =
-+				phy_connect(edma_netdev[i],
-+					    (const char *)adapter[i]->phy_id,
-+					    &edma_adjust_link,
-+					    PHY_INTERFACE_MODE_SGMII);
-+			if (IS_ERR(adapter[i]->phydev)) {
-+				dev_dbg(&pdev->dev, "PHY attach FAIL");
-+				err = -EIO;
-+				goto edma_phy_attach_fail;
-+			} else {
-+				adapter[i]->phydev->advertising |=
-+					ADVERTISED_Pause |
-+					ADVERTISED_Asym_Pause;
-+				adapter[i]->phydev->supported |=
-+					SUPPORTED_Pause |
-+					SUPPORTED_Asym_Pause;
-+			}
-+		} else {
-+			adapter[i]->phydev = NULL;
-+		}
-+	}
-+
-+	spin_lock_init(&edma_cinfo->stats_lock);
-+
-+	init_timer(&edma_stats_timer);
-+	edma_stats_timer.expires = jiffies + 1*HZ;
-+	edma_stats_timer.data = (unsigned long)edma_cinfo;
-+	edma_stats_timer.function = edma_statistics_timer; /* timer handler */
-+	add_timer(&edma_stats_timer);
-+
-+	return 0;
-+
-+edma_phy_attach_fail:
-+	miibus = NULL;
-+err_configure:
-+#ifdef CONFIG_RFS_ACCEL
-+	for (i = 0; i < edma_cinfo->num_gmac; i++) {
-+		free_irq_cpu_rmap(adapter[i]->netdev->rx_cpu_rmap);
-+		adapter[i]->netdev->rx_cpu_rmap = NULL;
-+	}
-+#endif
-+err_rmap_add_fail:
-+	edma_free_irqs(adapter[0]);
-+	for (i = 0; i < CONFIG_NR_CPUS; i++)
-+		napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
-+err_reset:
-+err_unregister_sysctl_tbl:
-+err_rmap_alloc_fail:
-+	for (i = 0; i < edma_cinfo->num_gmac; i++)
-+		unregister_netdev(edma_netdev[i]);
-+err_register:
-+err_mdiobus_init_fail:
-+	edma_free_rx_rings(edma_cinfo);
-+err_rx_rinit:
-+	edma_free_tx_rings(edma_cinfo);
-+err_tx_rinit:
-+	edma_free_queues(edma_cinfo);
-+err_rx_qinit:
-+err_tx_qinit:
-+	iounmap(edma_cinfo->hw.hw_addr);
-+err_ioremap:
-+	for (i = 0; i < edma_cinfo->num_gmac; i++) {
-+		if (edma_netdev[i])
-+			free_netdev(edma_netdev[i]);
-+	}
-+err_cinfo:
-+	kfree(edma_cinfo);
-+err_alloc:
-+	return err;
-+}
-+
-+/* edma_axi_remove()
-+ *	Device Removal Routine
-+ *
-+ * edma_axi_remove is called by the platform subsystem to alert the driver
-+ * that it should release a platform device.
-+ */
-+static int edma_axi_remove(struct platform_device *pdev)
-+{
-+	struct edma_adapter *adapter = netdev_priv(edma_netdev[0]);
-+	struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
-+	struct edma_hw *hw = &edma_cinfo->hw;
-+	int i;
-+
-+	for (i = 0; i < edma_cinfo->num_gmac; i++)
-+		unregister_netdev(edma_netdev[i]);
-+
-+	edma_stop_rx_tx(hw);
-+	for (i = 0; i < CONFIG_NR_CPUS; i++)
-+		napi_disable(&edma_cinfo->edma_percpu_info[i].napi);
-+
-+	edma_irq_disable(edma_cinfo);
-+	edma_write_reg(EDMA_REG_RX_ISR, 0xff);
-+	edma_write_reg(EDMA_REG_TX_ISR, 0xffff);
-+#ifdef CONFIG_RFS_ACCEL
-+	for (i = 0; i < edma_cinfo->num_gmac; i++) {
-+		free_irq_cpu_rmap(edma_netdev[i]->rx_cpu_rmap);
-+		edma_netdev[i]->rx_cpu_rmap = NULL;
-+	}
-+#endif
-+
-+	for (i = 0; i < edma_cinfo->num_gmac; i++) {
-+		struct edma_adapter *adapter = netdev_priv(edma_netdev[i]);
-+
-+		if (adapter->phydev)
-+			phy_disconnect(adapter->phydev);
-+	}
-+
-+	del_timer_sync(&edma_stats_timer);
-+	edma_free_irqs(adapter);
-+	unregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr);
-+	edma_free_tx_resources(edma_cinfo);
-+	edma_free_rx_resources(edma_cinfo);
-+	edma_free_tx_rings(edma_cinfo);
-+	edma_free_rx_rings(edma_cinfo);
-+	edma_free_queues(edma_cinfo);
-+	for (i = 0; i < edma_cinfo->num_gmac; i++)
-+		free_netdev(edma_netdev[i]);
-+
-+	kfree(edma_cinfo);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id edma_of_mtable[] = {
-+	{.compatible = "qcom,ess-edma" },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, edma_of_mtable);
-+
-+static struct platform_driver edma_axi_driver = {
-+	.driver = {
-+		.name    = edma_axi_driver_name,
-+		.of_match_table = edma_of_mtable,
-+	},
-+	.probe    = edma_axi_probe,
-+	.remove   = edma_axi_remove,
-+};
-+
-+module_platform_driver(edma_axi_driver);
-+
-+MODULE_AUTHOR("Qualcomm Atheros Inc");
-+MODULE_DESCRIPTION("QCA ESS EDMA driver");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c
-@@ -0,0 +1,374 @@
-+/*
-+ * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/ethtool.h>
-+#include <linux/netdevice.h>
-+#include <linux/string.h>
-+#include "edma.h"
-+
-+struct edma_ethtool_stats {
-+	uint8_t stat_string[ETH_GSTRING_LEN];
-+	uint32_t stat_offset;
-+};
-+
-+#define EDMA_STAT(m)    offsetof(struct edma_ethtool_statistics, m)
-+#define DRVINFO_LEN	32
-+
-+/* Array of strings describing statistics
-+ */
-+static const struct edma_ethtool_stats edma_gstrings_stats[] = {
-+	{"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
-+	{"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
-+	{"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
-+	{"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
-+	{"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
-+	{"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
-+	{"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
-+	{"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
-+	{"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
-+	{"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
-+	{"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
-+	{"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
-+	{"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
-+	{"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
-+	{"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
-+	{"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
-+	{"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
-+	{"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
-+	{"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
-+	{"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
-+	{"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
-+	{"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
-+	{"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
-+	{"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
-+	{"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
-+	{"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
-+	{"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
-+	{"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
-+	{"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
-+	{"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
-+	{"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
-+	{"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
-+	{"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
-+	{"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
-+	{"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
-+	{"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
-+	{"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
-+	{"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
-+	{"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
-+	{"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
-+	{"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
-+	{"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
-+	{"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
-+	{"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
-+	{"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
-+	{"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
-+	{"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
-+	{"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
-+	{"tx_desc_error", EDMA_STAT(tx_desc_error)},
-+};
-+
-+#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
-+
-+/* edma_get_strset_count()
-+ *	Get strset count
-+ */
-+static int edma_get_strset_count(struct net_device *netdev,
-+				 int sset)
-+{
-+	switch (sset) {
-+	case ETH_SS_STATS:
-+		return EDMA_STATS_LEN;
-+	default:
-+		netdev_dbg(netdev, "%s: Invalid string set", __func__);
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+
-+/* edma_get_strings()
-+ *	get stats string
-+ */
-+static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
-+			     uint8_t *data)
-+{
-+	uint8_t *p = data;
-+	uint32_t i;
-+
-+	switch (stringset) {
-+	case ETH_SS_STATS:
-+		for (i = 0; i < EDMA_STATS_LEN; i++) {
-+			memcpy(p, edma_gstrings_stats[i].stat_string,
-+				min((size_t)ETH_GSTRING_LEN,
-+				    strlen(edma_gstrings_stats[i].stat_string)
-+				    + 1));
-+			p += ETH_GSTRING_LEN;
-+		}
-+		break;
-+	}
-+}
-+
-+/* edma_get_ethtool_stats()
-+ *	Get ethtool statistics
-+ */
-+static void edma_get_ethtool_stats(struct net_device *netdev,
-+				   struct ethtool_stats *stats, uint64_t *data)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+	struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
-+	int i;
-+	uint8_t *p = NULL;
-+
-+	edma_read_append_stats(edma_cinfo);
-+
-+	for(i = 0; i < EDMA_STATS_LEN; i++) {
-+		p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
-+			edma_gstrings_stats[i].stat_offset;
-+		data[i] = *(uint32_t *)p;
-+	}
-+}
-+
-+/* edma_get_drvinfo()
-+ *	get edma driver info
-+ */
-+static void edma_get_drvinfo(struct net_device *dev,
-+			     struct ethtool_drvinfo *info)
-+{
-+	strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
-+	strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
-+}
-+
-+/* edma_nway_reset()
-+ *	Reset the phy, if available.
-+ */
-+static int edma_nway_reset(struct net_device *netdev)
-+{
-+	return -EINVAL;
-+}
-+
-+/* edma_get_wol()
-+ *	get wake on lan info
-+ */
-+static void edma_get_wol(struct net_device *netdev,
-+			 struct ethtool_wolinfo *wol)
-+{
-+	wol->supported = 0;
-+	wol->wolopts = 0;
-+}
-+
-+/* edma_get_msglevel()
-+ *	get message level.
-+ */
-+static uint32_t edma_get_msglevel(struct net_device *netdev)
-+{
-+	return 0;
-+}
-+
-+/* edma_get_settings()
-+ *	Get edma settings
-+ */
-+static int edma_get_settings(struct net_device *netdev,
-+			     struct ethtool_cmd *ecmd)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+
-+	if (adapter->poll_required) {
-+		struct phy_device *phydev = NULL;
-+		uint16_t phyreg;
-+
-+		if ((adapter->forced_speed != SPEED_UNKNOWN)
-+			&& !(adapter->poll_required))
-+			return -EPERM;
-+
-+		phydev = adapter->phydev;
-+
-+		ecmd->advertising = phydev->advertising;
-+		ecmd->autoneg = phydev->autoneg;
-+
-+		if (adapter->link_state == __EDMA_LINKDOWN) {
-+			ecmd->speed =  SPEED_UNKNOWN;
-+			ecmd->duplex = DUPLEX_UNKNOWN;
-+		} else {
-+			ecmd->speed = phydev->speed;
-+			ecmd->duplex = phydev->duplex;
-+		}
-+
-+		ecmd->phy_address = adapter->phy_mdio_addr;
-+
-+		phyreg = (uint16_t)phy_read(adapter->phydev, MII_LPA);
-+		if (phyreg & LPA_10HALF)
-+			ecmd->lp_advertising |= ADVERTISED_10baseT_Half;
-+
-+		if (phyreg & LPA_10FULL)
-+			ecmd->lp_advertising |= ADVERTISED_10baseT_Full;
-+
-+		if (phyreg & LPA_100HALF)
-+			ecmd->lp_advertising |= ADVERTISED_100baseT_Half;
-+
-+		if (phyreg & LPA_100FULL)
-+			ecmd->lp_advertising |= ADVERTISED_100baseT_Full;
-+
-+		phyreg = (uint16_t)phy_read(adapter->phydev, MII_STAT1000);
-+		if (phyreg & LPA_1000HALF)
-+			ecmd->lp_advertising |= ADVERTISED_1000baseT_Half;
-+
-+		if (phyreg & LPA_1000FULL)
-+			ecmd->lp_advertising |= ADVERTISED_1000baseT_Full;
-+	} else {
-+		/* If the speed/duplex for this GMAC is forced and we
-+		 * are not polling for link state changes, return the
-+		 * values as specified by platform. This will be true
-+		 * for GMACs connected to switch, and interfaces that
-+		 * do not use a PHY.
-+		 */
-+		if (!(adapter->poll_required)) {
-+			if (adapter->forced_speed != SPEED_UNKNOWN) {
-+				/* set speed and duplex */
-+				ethtool_cmd_speed_set(ecmd, SPEED_1000);
-+				ecmd->duplex = DUPLEX_FULL;
-+
-+				/* Populate capabilities advertised by self */
-+				ecmd->advertising = 0;
-+				ecmd->autoneg = 0;
-+				ecmd->port = PORT_TP;
-+				ecmd->transceiver = XCVR_EXTERNAL;
-+			} else {
-+				/* non link polled and non
-+				 * forced speed/duplex interface
-+				 */
-+				return -EIO;
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+/* edma_set_settings()
-+ *	Set EDMA settings
-+ */
-+static int edma_set_settings(struct net_device *netdev,
-+			     struct ethtool_cmd *ecmd)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+	struct phy_device *phydev = NULL;
-+
-+	if ((adapter->forced_speed != SPEED_UNKNOWN) &&
-+	     !adapter->poll_required)
-+		return -EPERM;
-+
-+	phydev = adapter->phydev;
-+	phydev->advertising = ecmd->advertising;
-+	phydev->autoneg = ecmd->autoneg;
-+	phydev->speed = ethtool_cmd_speed(ecmd);
-+	phydev->duplex = ecmd->duplex;
-+
-+	genphy_config_aneg(phydev);
-+
-+	return 0;
-+}
-+
-+/* edma_get_coalesce
-+ *	get interrupt mitigation
-+ */
-+static int edma_get_coalesce(struct net_device *netdev,
-+			     struct ethtool_coalesce *ec)
-+{
-+	u32 reg_val;
-+
-+	edma_get_tx_rx_coalesce(&reg_val);
-+
-+	/* We read the Interrupt Moderation Timer(IMT) register value,
-+	 * use lower 16 bit for rx and higher 16 bit for Tx. We do a
-+	 * left shift by 1, because IMT resolution timer is 2usecs.
-+	 * Hence the value given by the register is multiplied by 2 to
-+	 * get the actual time in usecs.
-+	 */
-+	ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
-+	ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
-+
-+	return 0;
-+}
-+
-+/* edma_set_coalesce
-+ *	set interrupt mitigation
-+ */
-+static int edma_set_coalesce(struct net_device *netdev,
-+			     struct ethtool_coalesce *ec)
-+{
-+	if (ec->tx_coalesce_usecs)
-+		edma_change_tx_coalesce(ec->tx_coalesce_usecs);
-+	if (ec->rx_coalesce_usecs)
-+		edma_change_rx_coalesce(ec->rx_coalesce_usecs);
-+
-+	return 0;
-+}
-+
-+/* edma_set_priv_flags()
-+ *	Set EDMA private flags
-+ */
-+static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
-+{
-+	return 0;
-+}
-+
-+/* edma_get_priv_flags()
-+ *	get edma driver flags
-+ */
-+static u32 edma_get_priv_flags(struct net_device *netdev)
-+{
-+	return 0;
-+}
-+
-+/* edma_get_ringparam()
-+ *	get ring size
-+ */
-+static void edma_get_ringparam(struct net_device *netdev,
-+			       struct ethtool_ringparam *ring)
-+{
-+	struct edma_adapter *adapter = netdev_priv(netdev);
-+	struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
-+
-+	ring->tx_max_pending = edma_cinfo->tx_ring_count;
-+	ring->rx_max_pending = edma_cinfo->rx_ring_count;
-+}
-+
-+/* Ethtool operations
-+ */
-+static const struct ethtool_ops edma_ethtool_ops = {
-+	.get_drvinfo = &edma_get_drvinfo,
-+	.get_link = &ethtool_op_get_link,
-+	.get_msglevel = &edma_get_msglevel,
-+	.nway_reset = &edma_nway_reset,
-+	.get_wol = &edma_get_wol,
-+	.get_settings = &edma_get_settings,
-+	.set_settings = &edma_set_settings,
-+	.get_strings = &edma_get_strings,
-+	.get_sset_count = &edma_get_strset_count,
-+	.get_ethtool_stats = &edma_get_ethtool_stats,
-+	.get_coalesce = &edma_get_coalesce,
-+	.set_coalesce = &edma_set_coalesce,
-+	.get_priv_flags = edma_get_priv_flags,
-+	.set_priv_flags = edma_set_priv_flags,
-+	.get_ringparam = edma_get_ringparam,
-+};
-+
-+/* edma_set_ethtool_ops
-+ *	Set ethtool operations
-+ */
-+void edma_set_ethtool_ops(struct net_device *netdev)
-+{
-+	netdev->ethtool_ops = &edma_ethtool_ops;
-+}
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/essedma/ess_edma.h
-@@ -0,0 +1,332 @@
-+/*
-+ * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for
-+ * any purpose with or without fee is hereby granted, provided that the
-+ * above copyright notice and this permission notice appear in all copies.
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#ifndef _ESS_EDMA_H_
-+#define _ESS_EDMA_H_
-+
-+#include <linux/types.h>
-+
-+struct edma_adapter;
-+struct edma_hw;
-+
-+/* register definition */
-+#define EDMA_REG_MAS_CTRL 0x0
-+#define EDMA_REG_TIMEOUT_CTRL 0x004
-+#define EDMA_REG_DBG0 0x008
-+#define EDMA_REG_DBG1 0x00C
-+#define EDMA_REG_SW_CTRL0 0x100
-+#define EDMA_REG_SW_CTRL1 0x104
-+
-+/* Interrupt Status Register */
-+#define EDMA_REG_RX_ISR 0x200
-+#define EDMA_REG_TX_ISR 0x208
-+#define EDMA_REG_MISC_ISR 0x210
-+#define EDMA_REG_WOL_ISR 0x218
-+
-+#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
-+
-+#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
-+#define EDMA_MISC_ISR_AXIR_ERR 0x00000200
-+#define EDMA_MISC_ISR_TXF_DEAD 0x00000400
-+#define EDMA_MISC_ISR_AXIW_ERR 0x00000800
-+#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
-+
-+#define EDMA_WOL_ISR 0x00000001
-+
-+/* Interrupt Mask Register */
-+#define EDMA_REG_MISC_IMR 0x214
-+#define EDMA_REG_WOL_IMR 0x218
-+
-+#define EDMA_RX_IMR_NORMAL_MASK 0x1
-+#define EDMA_TX_IMR_NORMAL_MASK 0x1
-+#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
-+#define EDMA_WOL_IMR_NORMAL_MASK 0x1
-+
-+/* Edma receive consumer index */
-+#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
-+/* Edma transmit consumer index */
-+#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
-+
-+/* IRQ Moderator Initial Timer Register */
-+#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
-+#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
-+#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
-+#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
-+
-+/* Interrupt Control Register */
-+#define EDMA_REG_INTR_CTRL 0x284
-+#define EDMA_INTR_CLR_TYP_SHIFT 0
-+#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
-+#define EDMA_INTR_CLEAR_TYPE_W1 0
-+#define EDMA_INTR_CLEAR_TYPE_R 1
-+
-+/* RX Interrupt Mask Register */
-+#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
-+
-+/* TX Interrupt mask register */
-+#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
-+
-+/* Load Ptr Register
-+ * Software sets this bit after the initialization of the head and tail
-+ */
-+#define EDMA_REG_TX_SRAM_PART 0x400
-+#define EDMA_LOAD_PTR_SHIFT 16
-+
-+/* TXQ Control Register */
-+#define EDMA_REG_TXQ_CTRL 0x404
-+#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
-+#define EDMA_TXQ_CTRL_TXQ_EN 0x20
-+#define EDMA_TXQ_CTRL_ENH_MODE 0x40
-+#define EDMA_TXQ_CTRL_LS_8023_EN 0x80
-+#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
-+#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
-+#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
-+#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
-+#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
-+#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
-+
-+#define	EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
-+#define EDMA_TXF_WATER_MARK_MASK 0x0FFF
-+#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
-+#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
-+#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
-+
-+/* WRR Control Register */
-+#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
-+#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
-+#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
-+#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
-+
-+/* Weight round robin(WRR), it takes queue as input, and computes
-+ * starting bits where we need to write the weight for a particular
-+ * queue
-+ */
-+#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
-+
-+/* Tx Descriptor Control Register */
-+#define EDMA_REG_TPD_RING_SIZE 0x41C
-+#define EDMA_TPD_RING_SIZE_SHIFT 0
-+#define EDMA_TPD_RING_SIZE_MASK 0xFFFF
-+
-+/* Transmit descriptor base address */
-+#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
-+
-+/* TPD Index Register */
-+#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
-+
-+#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
-+#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
-+#define EDMA_TPD_PROD_IDX_MASK 0xFFFF
-+#define EDMA_TPD_CONS_IDX_MASK 0xFFFF
-+#define EDMA_TPD_PROD_IDX_SHIFT 0
-+#define EDMA_TPD_CONS_IDX_SHIFT 16
-+
-+/* TX Virtual Queue Mapping Control Register */
-+#define EDMA_REG_VQ_CTRL0 0x4A0
-+#define EDMA_REG_VQ_CTRL1 0x4A4
-+
-+/* Virtual QID shift, it takes queue as input, and computes
-+ * Virtual QID position in virtual qid control register
-+ */
-+#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
-+
-+/* Virtual Queue Default Value */
-+#define EDMA_VQ_REG_VALUE 0x240240
-+
-+/* Tx side Port Interface Control Register */
-+#define EDMA_REG_PORT_CTRL 0x4A8
-+#define EDMA_PAD_EN_SHIFT 15
-+
-+/* Tx side VLAN Configuration Register */
-+#define EDMA_REG_VLAN_CFG 0x4AC
-+
-+#define EDMA_TX_CVLAN 16
-+#define EDMA_TX_INS_CVLAN 17
-+#define EDMA_TX_CVLAN_TAG_SHIFT 0
-+
-+#define EDMA_TX_SVLAN 14
-+#define EDMA_TX_INS_SVLAN 15
-+#define EDMA_TX_SVLAN_TAG_SHIFT 16
-+
-+/* Tx Queue Packet Statistic Register */
-+#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
-+
-+#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
-+
-+/* Tx Queue Byte Statistic Register */
-+#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
-+
-+/* Load Balance Based Ring Offset Register */
-+#define EDMA_REG_LB_RING 0x800
-+#define EDMA_LB_RING_ENTRY_MASK 0xff
-+#define EDMA_LB_RING_ID_MASK 0x7
-+#define EDMA_LB_RING_PROFILE_ID_MASK 0x3
-+#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
-+#define EDMA_LB_RING_ID_OFFSET 0
-+#define EDMA_LB_RING_PROFILE_ID_OFFSET 3
-+#define EDMA_LB_REG_VALUE 0x6040200
-+
-+/* Load Balance Priority Mapping Register */
-+#define EDMA_REG_LB_PRI_START 0x804
-+#define EDMA_REG_LB_PRI_END 0x810
-+#define EDMA_LB_PRI_REG_INC 4
-+#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
-+#define EDMA_LB_PRI_ENTRY_MASK 0xf
-+
-+/* RSS Priority Mapping Register */
-+#define EDMA_REG_RSS_PRI 0x820
-+#define EDMA_RSS_PRI_ENTRY_MASK 0xf
-+#define EDMA_RSS_RING_ID_MASK 0x7
-+#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
-+
-+/* RSS Indirection Register */
-+#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
-+#define EDMA_NUM_IDT 16
-+#define EDMA_RSS_IDT_VALUE 0x64206420
-+
-+/* Default RSS Ring Register */
-+#define EDMA_REG_DEF_RSS 0x890
-+#define EDMA_DEF_RSS_MASK 0x7
-+
-+/* RSS Hash Function Type Register */
-+#define EDMA_REG_RSS_TYPE 0x894
-+#define EDMA_RSS_TYPE_NONE 0x01
-+#define EDMA_RSS_TYPE_IPV4TCP 0x02
-+#define EDMA_RSS_TYPE_IPV6_TCP 0x04
-+#define EDMA_RSS_TYPE_IPV4_UDP 0x08
-+#define EDMA_RSS_TYPE_IPV6UDP 0x10
-+#define EDMA_RSS_TYPE_IPV4 0x20
-+#define EDMA_RSS_TYPE_IPV6 0x40
-+#define EDMA_RSS_HASH_MODE_MASK 0x7f
-+
-+#define EDMA_REG_RSS_HASH_VALUE 0x8C0
-+
-+#define EDMA_REG_RSS_TYPE_RESULT 0x8C4
-+
-+#define EDMA_HASH_TYPE_START 0
-+#define EDMA_HASH_TYPE_END 5
-+#define EDMA_HASH_TYPE_SHIFT 12
-+
-+#define EDMA_RFS_FLOW_ENTRIES 1024
-+#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
-+#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
-+
-+/* RFD Base Address Register */
-+#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
-+
-+/* RFD Index Register */
-+#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
-+
-+#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
-+#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
-+#define EDMA_RFD_PROD_IDX_MASK 0xFFF
-+#define EDMA_RFD_CONS_IDX_MASK 0xFFF
-+#define EDMA_RFD_PROD_IDX_SHIFT 0
-+#define EDMA_RFD_CONS_IDX_SHIFT 16
-+
-+/* Rx Descriptor Control Register */
-+#define EDMA_REG_RX_DESC0 0xA10
-+#define EDMA_RFD_RING_SIZE_MASK 0xFFF
-+#define EDMA_RX_BUF_SIZE_MASK 0xFFFF
-+#define EDMA_RFD_RING_SIZE_SHIFT 0
-+#define EDMA_RX_BUF_SIZE_SHIFT 16
-+
-+#define EDMA_REG_RX_DESC1 0xA14
-+#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
-+#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
-+#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
-+#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
-+#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
-+#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
-+
-+/* RXQ Control Register */
-+#define EDMA_REG_RXQ_CTRL 0xA18
-+#define EDMA_FIFO_THRESH_TYPE_SHIF 0
-+#define EDMA_FIFO_THRESH_128_BYTE 0x0
-+#define EDMA_FIFO_THRESH_64_BYTE 0x1
-+#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
-+#define EDMA_RXQ_CTRL_EN 0x0000FF00
-+
-+/* AXI Burst Size Config */
-+#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
-+#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
-+
-+/* Rx Statistics Register */
-+#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
-+#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
-+
-+/* WoL Pattern Length Register */
-+#define EDMA_REG_WOL_PATTERN_LEN0 0xC00
-+#define EDMA_WOL_PT_LEN_MASK 0xFF
-+#define EDMA_WOL_PT0_LEN_SHIFT 0
-+#define EDMA_WOL_PT1_LEN_SHIFT 8
-+#define EDMA_WOL_PT2_LEN_SHIFT 16
-+#define EDMA_WOL_PT3_LEN_SHIFT 24
-+
-+#define EDMA_REG_WOL_PATTERN_LEN1 0xC04
-+#define EDMA_WOL_PT4_LEN_SHIFT 0
-+#define EDMA_WOL_PT5_LEN_SHIFT 8
-+#define EDMA_WOL_PT6_LEN_SHIFT 16
-+
-+/* WoL Control Register */
-+#define EDMA_REG_WOL_CTRL 0xC08
-+#define EDMA_WOL_WK_EN 0x00000001
-+#define EDMA_WOL_MG_EN 0x00000002
-+#define EDMA_WOL_PT0_EN 0x00000004
-+#define EDMA_WOL_PT1_EN 0x00000008
-+#define EDMA_WOL_PT2_EN 0x00000010
-+#define EDMA_WOL_PT3_EN 0x00000020
-+#define EDMA_WOL_PT4_EN 0x00000040
-+#define EDMA_WOL_PT5_EN 0x00000080
-+#define EDMA_WOL_PT6_EN 0x00000100
-+
-+/* MAC Control Register */
-+#define EDMA_REG_MAC_CTRL0 0xC20
-+#define EDMA_REG_MAC_CTRL1 0xC24
-+
-+/* WoL Pattern Register */
-+#define EDMA_REG_WOL_PATTERN_START 0x5000
-+#define EDMA_PATTERN_PART_REG_OFFSET 0x40
-+
-+
-+/* TX descriptor fields */
-+#define EDMA_TPD_HDR_SHIFT 0
-+#define EDMA_TPD_PPPOE_EN 0x00000100
-+#define EDMA_TPD_IP_CSUM_EN 0x00000200
-+#define EDMA_TPD_TCP_CSUM_EN 0x0000400
-+#define EDMA_TPD_UDP_CSUM_EN 0x00000800
-+#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
-+#define EDMA_TPD_LSO_EN 0x00001000
-+#define EDMA_TPD_LSO_V2_EN 0x00002000
-+#define EDMA_TPD_IPV4_EN 0x00010000
-+#define EDMA_TPD_MSS_MASK 0x1FFF
-+#define EDMA_TPD_MSS_SHIFT 18
-+#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
-+
-+/* RRD descriptor fields */
-+#define EDMA_RRD_NUM_RFD_MASK 0x000F
-+#define EDMA_RRD_SVLAN 0x8000
-+#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
-+
-+#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
-+#define EDMA_RRD_CSUM_FAIL_MASK 0xC000
-+#define EDMA_RRD_CVLAN 0x0001
-+#define EDMA_RRD_DESC_VALID 0x8000
-+
-+#define EDMA_RRD_PRIORITY_SHIFT 4
-+#define EDMA_RRD_PRIORITY_MASK 0x7
-+#define EDMA_RRD_PORT_TYPE_SHIFT 7
-+#define EDMA_RRD_PORT_TYPE_MASK 0x1F
-+#endif /* _ESS_EDMA_H_ */
diff --git a/target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch b/target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch
deleted file mode 100644
index 771ff22753..0000000000
--- a/target/linux/ipq806x/patches-4.9/711-dts-ipq4019-add-ethernet-essedma-node.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sun, 20 Nov 2016 01:01:10 +0100
-Subject: [PATCH] dts: ipq4019: add ethernet essedma node
-
-This patch adds the device-tree node for the ethernet
-interfaces.
-
-Note: The driver isn't anywhere close to be upstream,
-so the info might change.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 60 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -26,6 +26,8 @@
- 	aliases {
- 		spi0 = &spi_0;
- 		i2c0 = &i2c_0;
-+		ethernet0 = &gmac0;
-+		ethernet1 = &gmac1;
- 	};
- 
- 	cpus {
-@@ -366,6 +368,64 @@
- 			status = "disabled";
- 		};
- 
-+		edma@c080000 {
-+			compatible = "qcom,ess-edma";
-+			reg = <0xc080000 0x8000>;
-+			qcom,page-mode = <0>;
-+			qcom,rx_head_buf_size = <1540>;
-+			qcom,mdio_supported;
-+			qcom,poll_required = <1>;
-+			qcom,num_gmac = <2>;
-+			interrupts = <0  65 IRQ_TYPE_EDGE_RISING
-+				      0  66 IRQ_TYPE_EDGE_RISING
-+				      0  67 IRQ_TYPE_EDGE_RISING
-+				      0  68 IRQ_TYPE_EDGE_RISING
-+				      0  69 IRQ_TYPE_EDGE_RISING
-+				      0  70 IRQ_TYPE_EDGE_RISING
-+				      0  71 IRQ_TYPE_EDGE_RISING
-+				      0  72 IRQ_TYPE_EDGE_RISING
-+				      0  73 IRQ_TYPE_EDGE_RISING
-+				      0  74 IRQ_TYPE_EDGE_RISING
-+				      0  75 IRQ_TYPE_EDGE_RISING
-+				      0  76 IRQ_TYPE_EDGE_RISING
-+				      0  77 IRQ_TYPE_EDGE_RISING
-+				      0  78 IRQ_TYPE_EDGE_RISING
-+				      0  79 IRQ_TYPE_EDGE_RISING
-+				      0  80 IRQ_TYPE_EDGE_RISING
-+				      0 240 IRQ_TYPE_EDGE_RISING
-+				      0 241 IRQ_TYPE_EDGE_RISING
-+				      0 242 IRQ_TYPE_EDGE_RISING
-+				      0 243 IRQ_TYPE_EDGE_RISING
-+				      0 244 IRQ_TYPE_EDGE_RISING
-+				      0 245 IRQ_TYPE_EDGE_RISING
-+				      0 246 IRQ_TYPE_EDGE_RISING
-+				      0 247 IRQ_TYPE_EDGE_RISING
-+				      0 248 IRQ_TYPE_EDGE_RISING
-+				      0 249 IRQ_TYPE_EDGE_RISING
-+				      0 250 IRQ_TYPE_EDGE_RISING
-+				      0 251 IRQ_TYPE_EDGE_RISING
-+				      0 252 IRQ_TYPE_EDGE_RISING
-+				      0 253 IRQ_TYPE_EDGE_RISING
-+				      0 254 IRQ_TYPE_EDGE_RISING
-+				      0 255 IRQ_TYPE_EDGE_RISING>;
-+
-+			status = "disabled";
-+
-+			gmac0: gmac0 {
-+				local-mac-address = [00 00 00 00 00 00];
-+				vlan_tag = <1 0x1f>;
-+			};
-+
-+			gmac1: gmac1 {
-+				local-mac-address = [00 00 00 00 00 00];
-+				qcom,phy_mdio_addr = <4>;
-+				qcom,poll_required = <1>;
-+				qcom,forced_speed = <1000>;
-+				qcom,forced_duplex = <1>;
-+				vlan_tag = <2 0x20>;
-+			};
-+		};
-+
- 		usb3_ss_phy: ssphy@9a000 {
- 			compatible = "qca,uni-ssphy";
- 			reg = <0x9a000 0x800>;
diff --git a/target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch b/target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch
deleted file mode 100644
index 6f5b6616d1..0000000000
--- a/target/linux/ipq806x/patches-4.9/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch
+++ /dev/null
@@ -1,429 +0,0 @@
-From e73682ec4455c34f3f3edc7f40d90ed297521012 Mon Sep 17 00:00:00 2001
-From: Senthilkumar N L <snlakshm@codeaurora.org>
-Date: Tue, 6 Jan 2015 12:52:23 +0530
-Subject: [PATCH] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
-
-These drivers handles control and configuration of the HS
-and SS USB PHY transceivers.
-
-Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-
----
-Changed:
-	- replaced spaces with tabs
-	- remove emulation and host variables
----
- drivers/usb/phy/Kconfig          |  11 ++
- drivers/usb/phy/Makefile         |   2 +
- drivers/usb/phy/phy-qca-baldur.c | 233 +++++++++++++++++++++++++++++++++++++++
- drivers/usb/phy/phy-qca-uniphy.c | 141 +++++++++++++++++++++++
- 4 files changed, 387 insertions(+)
- create mode 100644 drivers/usb/phy/phy-qca-baldur.c
- create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
-
---- a/drivers/usb/phy/Kconfig
-+++ b/drivers/usb/phy/Kconfig
-@@ -195,6 +195,17 @@ config USB_MXS_PHY
- 
- 	  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
- 
-+config USB_IPQ4019_PHY
-+	tristate "IPQ4019 PHY wrappers support"
-+	depends on (USB || USB_GADGET) && ARCH_QCOM
-+	select USB_PHY
-+	help
-+	  Enable this to support the USB PHY transceivers on QCA961x chips.
-+	  It handles PHY initialization, clock management required after
-+	  resetting the hardware and power management.
-+	  This driver is required even for peripheral only or host only
-+	  mode configurations.
-+
- config USB_ULPI
- 	bool "Generic ULPI Transceiver Driver"
- 	depends on ARM || ARM64
---- a/drivers/usb/phy/Makefile
-+++ b/drivers/usb/phy/Makefile
-@@ -21,6 +21,8 @@ obj-$(CONFIG_USB_GPIO_VBUS)		+= phy-gpio
- obj-$(CONFIG_USB_ISP1301)		+= phy-isp1301.o
- obj-$(CONFIG_USB_MSM_OTG)		+= phy-msm-usb.o
- obj-$(CONFIG_USB_QCOM_8X16_PHY)	+= phy-qcom-8x16-usb.o
-+obj-$(CONFIG_USB_IPQ4019_PHY)		+= phy-qca-baldur.o
-+obj-$(CONFIG_USB_IPQ4019_PHY)		+= phy-qca-uniphy.o
- obj-$(CONFIG_USB_MV_OTG)		+= phy-mv-usb.o
- obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o
- obj-$(CONFIG_USB_ULPI)			+= phy-ulpi.o
---- /dev/null
-+++ b/drivers/usb/phy/phy-qca-baldur.c
-@@ -0,0 +1,233 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/usb/phy.h>
-+#include <linux/reset.h>
-+#include <linux/of_device.h>
-+
-+/**
-+ *  USB Hardware registers
-+ */
-+#define PHY_CTRL0_ADDR	0x000
-+#define PHY_CTRL1_ADDR	0x004
-+#define PHY_CTRL2_ADDR	0x008
-+#define PHY_CTRL3_ADDR	0x00C
-+#define PHY_CTRL4_ADDR	0x010
-+#define PHY_MISC_ADDR	0x024
-+#define PHY_IPG_ADDR	0x030
-+
-+#define PHY_CTRL0_VAL	0xA4600015
-+#define PHY_CTRL1_VAL	0x09500000
-+#define PHY_CTRL2_VAL	0x00058180
-+#define PHY_CTRL3_VAL	0x6DB6DCD6
-+#define PHY_CTRL4_VAL	0x836DB6DB
-+#define PHY_MISC_VAL	0x3803FB0C
-+#define PHY_IPG_VAL	0x47323232
-+
-+#define USB30_HS_PHY_HOST_MODE	(0x01 << 21)
-+#define USB20_HS_PHY_HOST_MODE	(0x01 << 5)
-+
-+/* used to differentiate between USB3 HS and USB2 HS PHY */
-+struct qca_baldur_hs_data {
-+	unsigned int usb3_hs_phy;
-+	unsigned int phy_config_offset;
-+};
-+
-+struct qca_baldur_hs_phy {
-+	struct device *dev;
-+	struct usb_phy phy;
-+
-+	void __iomem *base;
-+	void __iomem *qscratch_base;
-+
-+	struct reset_control *por_rst;
-+	struct reset_control *srif_rst;
-+
-+	const struct qca_baldur_hs_data *data;
-+};
-+
-+#define phy_to_dw_phy(x) container_of((x), struct qca_baldur_hs_phy, phy)
-+
-+static int qca_baldur_phy_read(struct usb_phy *x, u32 reg)
-+{
-+	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
-+
-+	return readl(phy->base + reg);
-+}
-+
-+static int qca_baldur_phy_write(struct usb_phy *x, u32 val, u32 reg)
-+{
-+	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
-+
-+	writel(val, phy->base + reg);
-+	return 0;
-+}
-+
-+static int qca_baldur_hs_phy_init(struct usb_phy *x)
-+{
-+	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
-+
-+	/* assert HS PHY POR reset */
-+	reset_control_assert(phy->por_rst);
-+	msleep(10);
-+
-+	/* assert HS PHY SRIF reset */
-+	reset_control_assert(phy->srif_rst);
-+	msleep(10);
-+
-+	/* deassert HS PHY SRIF reset and program HS PHY registers */
-+	reset_control_deassert(phy->srif_rst);
-+	msleep(10);
-+
-+	/* perform PHY register writes */
-+	writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
-+	writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
-+	writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
-+	writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
-+	writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
-+	writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
-+	writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
-+
-+	msleep(10);
-+
-+	/* de-assert USB3 HS PHY POR reset */
-+	reset_control_deassert(phy->por_rst);
-+
-+	return 0;
-+}
-+
-+static int qca_baldur_hs_get_resources(struct qca_baldur_hs_phy *phy)
-+{
-+	struct platform_device *pdev = to_platform_device(phy->dev);
-+	struct resource *res;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	phy->base = devm_ioremap_resource(phy->dev, res);
-+	if (IS_ERR(phy->base))
-+		return PTR_ERR(phy->base);
-+
-+	phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
-+	if (IS_ERR(phy->por_rst))
-+		return PTR_ERR(phy->por_rst);
-+
-+	phy->srif_rst = devm_reset_control_get(phy->dev, "srif_rst");
-+	if (IS_ERR(phy->srif_rst))
-+		return PTR_ERR(phy->srif_rst);
-+
-+	return 0;
-+}
-+
-+static void qca_baldur_hs_put_resources(struct qca_baldur_hs_phy *phy)
-+{
-+	reset_control_assert(phy->srif_rst);
-+	reset_control_assert(phy->por_rst);
-+}
-+
-+static int qca_baldur_hs_remove(struct platform_device *pdev)
-+{
-+	struct qca_baldur_hs_phy *phy = platform_get_drvdata(pdev);
-+
-+	usb_remove_phy(&phy->phy);
-+	return 0;
-+}
-+
-+static void qca_baldur_hs_phy_shutdown(struct usb_phy *x)
-+{
-+	struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
-+
-+	qca_baldur_hs_put_resources(phy);
-+}
-+
-+static struct usb_phy_io_ops qca_baldur_io_ops = {
-+	.read = qca_baldur_phy_read,
-+	.write = qca_baldur_phy_write,
-+};
-+
-+static const struct qca_baldur_hs_data usb3_hs_data = {
-+	.usb3_hs_phy = 1,
-+	.phy_config_offset = USB30_HS_PHY_HOST_MODE,
-+};
-+
-+static const struct qca_baldur_hs_data usb2_hs_data = {
-+	.usb3_hs_phy = 0,
-+	.phy_config_offset = USB20_HS_PHY_HOST_MODE,
-+};
-+
-+static const struct of_device_id qca_baldur_hs_id_table[] = {
-+	{ .compatible = "qca,baldur-usb3-hsphy", .data = &usb3_hs_data },
-+	{ .compatible = "qca,baldur-usb2-hsphy", .data = &usb2_hs_data },
-+	{ /* Sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, qca_baldur_hs_id_table);
-+
-+static int qca_baldur_hs_probe(struct platform_device *pdev)
-+{
-+	const struct of_device_id *match;
-+	struct qca_baldur_hs_phy *phy;
-+	int err;
-+
-+	match = of_match_device(qca_baldur_hs_id_table, &pdev->dev);
-+	if (!match)
-+		return -ENODEV;
-+
-+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
-+	if (!phy)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, phy);
-+	phy->dev = &pdev->dev;
-+
-+	phy->data = match->data;
-+
-+	err = qca_baldur_hs_get_resources(phy);
-+	if (err < 0) {
-+		dev_err(&pdev->dev, "failed to request resources: %d\n", err);
-+		return err;
-+	}
-+
-+	phy->phy.dev = phy->dev;
-+	phy->phy.label = "qca-baldur-hsphy";
-+	phy->phy.init = qca_baldur_hs_phy_init;
-+	phy->phy.shutdown = qca_baldur_hs_phy_shutdown;
-+	phy->phy.type = USB_PHY_TYPE_USB2;
-+	phy->phy.io_ops = &qca_baldur_io_ops;
-+
-+	err = usb_add_phy_dev(&phy->phy);
-+	return err;
-+}
-+
-+static struct platform_driver qca_baldur_hs_driver = {
-+	.probe		= qca_baldur_hs_probe,
-+	.remove		= qca_baldur_hs_remove,
-+	.driver		= {
-+		.name	= "qca-baldur-hsphy",
-+		.owner	= THIS_MODULE,
-+		.of_match_table = qca_baldur_hs_id_table,
-+	},
-+};
-+
-+module_platform_driver(qca_baldur_hs_driver);
-+
-+MODULE_ALIAS("platform:qca-baldur-hsphy");
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
---- /dev/null
-+++ b/drivers/usb/phy/phy-qca-uniphy.c
-@@ -0,0 +1,135 @@
-+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/usb/phy.h>
-+#include <linux/reset.h>
-+#include <linux/of_device.h>
-+
-+struct qca_uni_ss_phy {
-+	struct usb_phy phy;
-+	struct device *dev;
-+
-+	void __iomem *base;
-+
-+	struct reset_control *por_rst;
-+};
-+
-+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_ss_phy, phy)
-+
-+static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
-+{
-+	struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
-+
-+	/* assert SS PHY POR reset */
-+	reset_control_assert(phy->por_rst);
-+}
-+
-+static int qca_uni_ss_phy_init(struct usb_phy *x)
-+{
-+	struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
-+
-+	/* assert SS PHY POR reset */
-+	reset_control_assert(phy->por_rst);
-+
-+	msleep(20);
-+
-+	/* deassert SS PHY POR reset */
-+	reset_control_deassert(phy->por_rst);
-+
-+	return 0;
-+}
-+
-+static int qca_uni_ss_get_resources(struct platform_device *pdev,
-+		struct qca_uni_ss_phy *phy)
-+{
-+	struct resource *res;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	phy->base = devm_ioremap_resource(phy->dev, res);
-+	if (IS_ERR(phy->base))
-+		return PTR_ERR(phy->base);
-+
-+	phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
-+	if (IS_ERR(phy->por_rst))
-+		return PTR_ERR(phy->por_rst);
-+
-+	return 0;
-+}
-+
-+static int qca_uni_ss_remove(struct platform_device *pdev)
-+{
-+	struct qca_uni_ss_phy *phy = platform_get_drvdata(pdev);
-+
-+	usb_remove_phy(&phy->phy);
-+	return 0;
-+}
-+
-+static const struct of_device_id qca_uni_ss_id_table[] = {
-+	{ .compatible = "qca,uni-ssphy" },
-+	{ /* Sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, qca_uni_ss_id_table);
-+
-+static int qca_uni_ss_probe(struct platform_device *pdev)
-+{
-+	struct qca_uni_ss_phy *phy;
-+	int ret;
-+
-+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
-+	if (!phy)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, phy);
-+	phy->dev = &pdev->dev;
-+
-+	ret = qca_uni_ss_get_resources(pdev, phy);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
-+		return ret;
-+	}
-+
-+	phy->phy.dev = phy->dev;
-+	phy->phy.label = "qca-uni-ssphy";
-+	phy->phy.init = qca_uni_ss_phy_init;
-+	phy->phy.shutdown = qca_uni_ss_phy_shutdown;
-+	phy->phy.type = USB_PHY_TYPE_USB3;
-+
-+	ret = usb_add_phy_dev(&phy->phy);
-+	return ret;
-+}
-+
-+static struct platform_driver qca_uni_ss_driver = {
-+	.probe = qca_uni_ss_probe,
-+	.remove	= qca_uni_ss_remove,
-+	.driver = {
-+		.name = "qca-uni-ssphy",
-+		.owner = THIS_MODULE,
-+		.of_match_table = qca_uni_ss_id_table,
-+	},
-+};
-+
-+module_platform_driver(qca_uni_ss_driver);
-+
-+MODULE_ALIAS("platform:qca-uni-ssphy");
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("USB3 QCA UNI SSPHY driver");
diff --git a/target/linux/ipq806x/patches-4.9/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch b/target/linux/ipq806x/patches-4.9/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch
deleted file mode 100644
index 5e183dbad7..0000000000
--- a/target/linux/ipq806x/patches-4.9/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 08c18ab774368feb610d1eb952957bb1bb35129f Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@gmail.com>
-Date: Sat, 19 Nov 2016 00:52:35 +0100
-Subject: [PATCH 37/38] usb: dwc3: register qca,ipq4019-dwc3 in dwc3-of-simple
-
-For host mode, the dwc3 found in the IPQ4019 can be driven
-by the dwc3-of-simple module. It will get more tricky for
-OTG since they'll need to enable VBUS and reconfigure the
-registers.
-
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
----
- drivers/usb/dwc3/dwc3-of-simple.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/usb/dwc3/dwc3-of-simple.c
-+++ b/drivers/usb/dwc3/dwc3-of-simple.c
-@@ -199,6 +199,7 @@ static const struct dev_pm_ops dwc3_of_s
- 
- static const struct of_device_id of_dwc3_simple_match[] = {
- 	{ .compatible = "qcom,dwc3" },
-+	{ .compatible = "qca,ipq4019-dwc3" },
- 	{ .compatible = "rockchip,rk3399-dwc3" },
- 	{ .compatible = "xlnx,zynqmp-dwc3" },
- 	{ .compatible = "cavium,octeon-7130-usb-uctl" },
diff --git a/target/linux/ipq806x/patches-4.9/852-ipq4019-pinctrl-Updated-various-Pin-definitions.patch b/target/linux/ipq806x/patches-4.9/852-ipq4019-pinctrl-Updated-various-Pin-definitions.patch
deleted file mode 100644
index d0a6a26a56..0000000000
--- a/target/linux/ipq806x/patches-4.9/852-ipq4019-pinctrl-Updated-various-Pin-definitions.patch
+++ /dev/null
@@ -1,1328 +0,0 @@
-From fc6cf61517b8b4ab4678659936fc7572f699d6e7 Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Tue, 28 Mar 2017 14:00:00 +0530
-Subject: [PATCH] ipq4019: pinctrl: Updated various Pin definitions
-
-Populate default values for various GPIO functions
-
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1189 +++++++++++++++++++++++++++++---
- 1 file changed, 1111 insertions(+), 78 deletions(-)
-
---- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
-+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
-@@ -276,16 +276,531 @@ DECLARE_QCA_GPIO_PINS(99);
- 
- 
- enum ipq4019_functions {
-+	qca_mux_rmii0_refclk,
-+	qca_mux_wifi0_rfsilient0,
-+	qca_mux_wifi1_rfsilient0,
-+	qca_mux_smart2,
-+	qca_mux_led4,
-+	qca_mux_wifi0_cal,
-+	qca_mux_wifi1_cal,
-+	qca_mux_wifi_wci0,
-+	qca_mux_rmii0_dv,
-+	qca_mux_wifi_wci1,
-+	qca_mux_rmii1_refclk,
-+	qca_mux_blsp_spi1,
-+	qca_mux_led5,
-+	qca_mux_rmii10,
-+	qca_mux_led6,
-+	qca_mux_rmii11,
-+	qca_mux_led7,
-+	qca_mux_rmii1_dv,
-+	qca_mux_led8,
-+	qca_mux_rmii1_tx,
-+	qca_mux_aud_pin,
-+	qca_mux_led9,
-+	qca_mux_rmii1_rx,
-+	qca_mux_led10,
-+	qca_mux_wifi0_rfsilient1,
-+	qca_mux_wifi1_rfsilient1,
-+	qca_mux_led11,
-+	qca_mux_boot7,
-+	qca_mux_qpic_pad,
-+	qca_mux_pcie_clk,
-+	qca_mux_tm_clk0,
-+	qca_mux_wifi00,
-+	qca_mux_wifi10,
-+	qca_mux_mdio1,
-+	qca_mux_prng_rosc,
-+	qca_mux_dbg_out,
-+	qca_mux_tm0,
-+	qca_mux_wifi01,
-+	qca_mux_wifi11,
-+	qca_mux_atest_char3,
-+	qca_mux_pmu0,
-+	qca_mux_boot8,
-+	qca_mux_tm1,
-+	qca_mux_atest_char2,
-+	qca_mux_pmu1,
-+	qca_mux_boot9,
-+	qca_mux_tm2,
-+	qca_mux_atest_char1,
-+	qca_mux_tm_ack,
-+	qca_mux_wifi03,
-+	qca_mux_wifi13,
-+	qca_mux_qpic_pad4,
-+	qca_mux_atest_char0,
-+	qca_mux_tm3,
-+	qca_mux_wifi02,
-+	qca_mux_wifi12,
-+	qca_mux_qpic_pad5,
-+	qca_mux_smart3,
-+	qca_mux_wcss0_dbg14,
-+	qca_mux_tm4,
-+	qca_mux_wifi04,
-+	qca_mux_wifi14,
-+	qca_mux_qpic_pad6,
-+	qca_mux_wcss0_dbg15,
-+	qca_mux_qdss_tracectl_a,
-+	qca_mux_boot18,
-+	qca_mux_tm5,
-+	qca_mux_qpic_pad7,
-+	qca_mux_atest_char,
-+	qca_mux_wcss0_dbg4,
-+	qca_mux_qdss_traceclk_a,
-+	qca_mux_boot19,
-+	qca_mux_tm6,
-+	qca_mux_wcss0_dbg5,
-+	qca_mux_qdss_cti_trig_out_a0,
-+	qca_mux_boot14,
-+	qca_mux_tm7,
-+	qca_mux_chip_rst,
-+	qca_mux_wcss0_dbg6,
-+	qca_mux_qdss_cti_trig_out_b0,
-+	qca_mux_boot11,
-+	qca_mux_tm8,
-+	qca_mux_wcss0_dbg7,
-+	qca_mux_wcss1_dbg7,
-+	qca_mux_boot20,
-+	qca_mux_tm9,
-+	qca_mux_qpic_pad1,
-+	qca_mux_wcss0_dbg8,
-+	qca_mux_wcss1_dbg8,
-+	qca_mux_qpic_pad2,
-+	qca_mux_wcss0_dbg9,
-+	qca_mux_wcss1_dbg9,
-+	qca_mux_qpic_pad3,
-+	qca_mux_wcss0_dbg10,
-+	qca_mux_wcss1_dbg10,
-+	qca_mux_qpic_pad0,
-+	qca_mux_wcss0_dbg11,
-+	qca_mux_wcss1_dbg11,
-+	qca_mux_qpic_pad8,
-+	qca_mux_wcss0_dbg12,
-+	qca_mux_wcss1_dbg12,
-+	qca_mux_wifi034,
-+	qca_mux_wifi134,
-+	qca_mux_jtag_tdi,
- 	qca_mux_gpio,
-+	qca_mux_i2s_rx_bclk,
-+	qca_mux_jtag_tck,
-+	qca_mux_i2s_rx_fsync,
-+	qca_mux_jtag_tms,
-+	qca_mux_i2s_rxd,
-+	qca_mux_smart0,
-+	qca_mux_jtag_tdo,
-+	qca_mux_jtag_rst,
-+	qca_mux_jtag_trst,
-+	qca_mux_mdio0,
-+	qca_mux_wcss0_dbg18,
-+	qca_mux_wcss1_dbg18,
-+	qca_mux_qdss_tracedata_a,
-+	qca_mux_mdc,
-+	qca_mux_wcss0_dbg19,
-+	qca_mux_wcss1_dbg19,
- 	qca_mux_blsp_uart1,
-+	qca_mux_wifi0_uart,
-+	qca_mux_wifi1_uart,
-+	qca_mux_smart1,
-+	qca_mux_wcss0_dbg20,
-+	qca_mux_wcss1_dbg20,
-+	qca_mux_wifi0_uart0,
-+	qca_mux_wifi1_uart0,
-+	qca_mux_wcss0_dbg21,
-+	qca_mux_wcss1_dbg21,
- 	qca_mux_blsp_i2c0,
-+	qca_mux_wcss0_dbg22,
-+	qca_mux_wcss1_dbg22,
-+	qca_mux_wcss0_dbg23,
-+	qca_mux_wcss1_dbg23,
-+	qca_mux_blsp_spi0,
- 	qca_mux_blsp_i2c1,
-+	qca_mux_wcss0_dbg24,
-+	qca_mux_wcss1_dbg24,
-+	qca_mux_wcss0_dbg25,
-+	qca_mux_wcss1_dbg25,
-+	qca_mux_wcss0_dbg26,
-+	qca_mux_wcss1_dbg26,
-+	qca_mux_wcss0_dbg,
-+	qca_mux_wcss1_dbg,
- 	qca_mux_blsp_uart0,
--	qca_mux_blsp_spi1,
--	qca_mux_blsp_spi0,
-+	qca_mux_led0,
-+	qca_mux_wcss0_dbg28,
-+	qca_mux_wcss1_dbg28,
-+	qca_mux_led1,
-+	qca_mux_wcss0_dbg29,
-+	qca_mux_wcss1_dbg29,
-+	qca_mux_wifi0_uart1,
-+	qca_mux_wifi1_uart1,
-+	qca_mux_wcss0_dbg30,
-+	qca_mux_wcss1_dbg30,
-+	qca_mux_wcss0_dbg31,
-+	qca_mux_wcss1_dbg31,
-+	qca_mux_i2s_rx_mclk,
-+	qca_mux_wcss0_dbg16,
-+	qca_mux_wcss1_dbg16,
-+	qca_mux_wcss0_dbg17,
-+	qca_mux_wcss1_dbg17,
-+	qca_mux_rgmii0,
-+	qca_mux_sdio0,
-+	qca_mux_rgmii1,
-+	qca_mux_sdio1,
-+	qca_mux_rgmii2,
-+	qca_mux_i2s_tx_mclk,
-+	qca_mux_sdio2,
-+	qca_mux_rgmii3,
-+	qca_mux_i2s_tx_bclk,
-+	qca_mux_sdio3,
-+	qca_mux_rgmii_rx,
-+	qca_mux_i2s_tx_fsync,
-+	qca_mux_sdio_clk,
-+	qca_mux_rgmii_txc,
-+	qca_mux_i2s_td1,
-+	qca_mux_sdio_cmd,
-+	qca_mux_i2s_td2,
-+	qca_mux_sdio4,
-+	qca_mux_i2s_td3,
-+	qca_mux_sdio5,
-+	qca_mux_audio_pwm0,
-+	qca_mux_sdio6,
-+	qca_mux_audio_pwm1,
-+	qca_mux_wcss0_dbg27,
-+	qca_mux_wcss1_dbg27,
-+	qca_mux_sdio7,
-+	qca_mux_rgmii_rxc,
-+	qca_mux_audio_pwm2,
-+	qca_mux_rgmii_tx,
-+	qca_mux_audio_pwm3,
-+	qca_mux_boot2,
-+	qca_mux_i2s_spdif_in,
-+	qca_mux_i2s_spdif_out,
-+	qca_mux_rmii00,
-+	qca_mux_led2,
-+	qca_mux_rmii01,
-+	qca_mux_wifi0_wci,
-+	qca_mux_wifi1_wci,
-+	qca_mux_boot4,
-+	qca_mux_rmii0_tx,
-+	qca_mux_boot5,
-+	qca_mux_rmii0_rx,
-+	qca_mux_pcie_clk1,
-+	qca_mux_led3,
-+	qca_mux_sdio_cd,
- 	qca_mux_NA,
- };
- 
-+static const char * const rmii0_refclk_groups[] = {
-+	"gpio40",
-+};
-+static const char * const wifi0_rfsilient0_groups[] = {
-+	"gpio40",
-+};
-+static const char * const wifi1_rfsilient0_groups[] = {
-+	"gpio40",
-+};
-+static const char * const smart2_groups[] = {
-+	"gpio40", "gpio41", "gpio48", "gpio49",
-+};
-+static const char * const led4_groups[] = {
-+	"gpio40",
-+};
-+static const char * const wifi0_cal_groups[] = {
-+	"gpio41", "gpio51",
-+};
-+static const char * const wifi1_cal_groups[] = {
-+	"gpio41", "gpio51",
-+};
-+static const char * const wifi_wci0_groups[] = {
-+	"gpio42",
-+};
-+static const char * const rmii0_dv_groups[] = {
-+	"gpio43",
-+};
-+static const char * const wifi_wci1_groups[] = {
-+	"gpio43",
-+};
-+static const char * const rmii1_refclk_groups[] = {
-+	"gpio44",
-+};
-+static const char * const blsp_spi1_groups[] = {
-+	"gpio44", "gpio45", "gpio46", "gpio47",
-+};
-+static const char * const led5_groups[] = {
-+	"gpio44",
-+};
-+static const char * const rmii10_groups[] = {
-+	"gpio45", "gpio50",
-+};
-+static const char * const led6_groups[] = {
-+	"gpio45",
-+};
-+static const char * const rmii11_groups[] = {
-+	"gpio46", "gpio51",
-+};
-+static const char * const led7_groups[] = {
-+	"gpio46",
-+};
-+static const char * const rmii1_dv_groups[] = {
-+	"gpio47",
-+};
-+static const char * const led8_groups[] = {
-+	"gpio47",
-+};
-+static const char * const rmii1_tx_groups[] = {
-+	"gpio48",
-+};
-+static const char * const aud_pin_groups[] = {
-+	"gpio48", "gpio49", "gpio50", "gpio51",
-+};
-+static const char * const led9_groups[] = {
-+	"gpio48",
-+};
-+static const char * const rmii1_rx_groups[] = {
-+	"gpio49",
-+};
-+static const char * const led10_groups[] = {
-+	"gpio49",
-+};
-+static const char * const wifi0_rfsilient1_groups[] = {
-+	"gpio50",
-+};
-+static const char * const wifi1_rfsilient1_groups[] = {
-+	"gpio50",
-+};
-+static const char * const led11_groups[] = {
-+	"gpio50",
-+};
-+static const char * const boot7_groups[] = {
-+	"gpio51",
-+};
-+static const char * const qpic_pad_groups[] = {
-+	"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio61", "gpio62",
-+	"gpio63", "gpio69",
-+};
-+static const char * const pcie_clk_groups[] = {
-+	"gpio52",
-+};
-+static const char * const tm_clk0_groups[] = {
-+	"gpio52",
-+};
-+static const char * const wifi00_groups[] = {
-+	"gpio52",
-+};
-+static const char * const wifi10_groups[] = {
-+	"gpio52",
-+};
-+static const char * const mdio1_groups[] = {
-+	"gpio53",
-+};
-+static const char * const prng_rosc_groups[] = {
-+	"gpio53",
-+};
-+static const char * const dbg_out_groups[] = {
-+	"gpio53",
-+};
-+static const char * const tm0_groups[] = {
-+	"gpio53",
-+};
-+static const char * const wifi01_groups[] = {
-+	"gpio53",
-+};
-+static const char * const wifi11_groups[] = {
-+	"gpio53",
-+};
-+static const char * const atest_char3_groups[] = {
-+	"gpio54",
-+};
-+static const char * const pmu0_groups[] = {
-+	"gpio54",
-+};
-+static const char * const boot8_groups[] = {
-+	"gpio54",
-+};
-+static const char * const tm1_groups[] = {
-+	"gpio54",
-+};
-+static const char * const atest_char2_groups[] = {
-+	"gpio55",
-+};
-+static const char * const pmu1_groups[] = {
-+	"gpio55",
-+};
-+static const char * const boot9_groups[] = {
-+	"gpio55",
-+};
-+static const char * const tm2_groups[] = {
-+	"gpio55",
-+};
-+static const char * const atest_char1_groups[] = {
-+	"gpio56",
-+};
-+static const char * const tm_ack_groups[] = {
-+	"gpio56",
-+};
-+static const char * const wifi03_groups[] = {
-+	"gpio56",
-+};
-+static const char * const wifi13_groups[] = {
-+	"gpio56",
-+};
-+static const char * const qpic_pad4_groups[] = {
-+	"gpio57",
-+};
-+static const char * const atest_char0_groups[] = {
-+	"gpio57",
-+};
-+static const char * const tm3_groups[] = {
-+	"gpio57",
-+};
-+static const char * const wifi02_groups[] = {
-+	"gpio57",
-+};
-+static const char * const wifi12_groups[] = {
-+	"gpio57",
-+};
-+static const char * const qpic_pad5_groups[] = {
-+	"gpio58",
-+};
-+static const char * const smart3_groups[] = {
-+	"gpio58", "gpio59", "gpio60", "gpio61",
-+};
-+static const char * const wcss0_dbg14_groups[] = {
-+	"gpio58",
-+};
-+static const char * const tm4_groups[] = {
-+	"gpio58",
-+};
-+static const char * const wifi04_groups[] = {
-+	"gpio58",
-+};
-+static const char * const wifi14_groups[] = {
-+	"gpio58",
-+};
-+static const char * const qpic_pad6_groups[] = {
-+	"gpio59",
-+};
-+static const char * const wcss0_dbg15_groups[] = {
-+	"gpio59",
-+};
-+static const char * const qdss_tracectl_a_groups[] = {
-+	"gpio59",
-+};
-+static const char * const boot18_groups[] = {
-+	"gpio59",
-+};
-+static const char * const tm5_groups[] = {
-+	"gpio59",
-+};
-+static const char * const qpic_pad7_groups[] = {
-+	"gpio60",
-+};
-+static const char * const atest_char_groups[] = {
-+	"gpio60",
-+};
-+static const char * const wcss0_dbg4_groups[] = {
-+	"gpio60",
-+};
-+static const char * const qdss_traceclk_a_groups[] = {
-+	"gpio60",
-+};
-+static const char * const boot19_groups[] = {
-+	"gpio60",
-+};
-+static const char * const tm6_groups[] = {
-+	"gpio60",
-+};
-+static const char * const wcss0_dbg5_groups[] = {
-+	"gpio61",
-+};
-+static const char * const qdss_cti_trig_out_a0_groups[] = {
-+	"gpio61",
-+};
-+static const char * const boot14_groups[] = {
-+	"gpio61",
-+};
-+static const char * const tm7_groups[] = {
-+	"gpio61",
-+};
-+static const char * const chip_rst_groups[] = {
-+	"gpio62",
-+};
-+static const char * const wcss0_dbg6_groups[] = {
-+	"gpio62",
-+};
-+static const char * const qdss_cti_trig_out_b0_groups[] = {
-+	"gpio62",
-+};
-+static const char * const boot11_groups[] = {
-+	"gpio62",
-+};
-+static const char * const tm8_groups[] = {
-+	"gpio62",
-+};
-+static const char * const wcss0_dbg7_groups[] = {
-+	"gpio63",
-+};
-+static const char * const wcss1_dbg7_groups[] = {
-+	"gpio63",
-+};
-+static const char * const boot20_groups[] = {
-+	"gpio63",
-+};
-+static const char * const tm9_groups[] = {
-+	"gpio63",
-+};
-+static const char * const qpic_pad1_groups[] = {
-+	"gpio64",
-+};
-+static const char * const wcss0_dbg8_groups[] = {
-+	"gpio64",
-+};
-+static const char * const wcss1_dbg8_groups[] = {
-+	"gpio64",
-+};
-+static const char * const qpic_pad2_groups[] = {
-+	"gpio65",
-+};
-+static const char * const wcss0_dbg9_groups[] = {
-+	"gpio65",
-+};
-+static const char * const wcss1_dbg9_groups[] = {
-+	"gpio65",
-+};
-+static const char * const qpic_pad3_groups[] = {
-+	"gpio66",
-+};
-+static const char * const wcss0_dbg10_groups[] = {
-+	"gpio66",
-+};
-+static const char * const wcss1_dbg10_groups[] = {
-+	"gpio66",
-+};
-+static const char * const qpic_pad0_groups[] = {
-+	"gpio67",
-+};
-+static const char * const wcss0_dbg11_groups[] = {
-+	"gpio67",
-+};
-+static const char * const wcss1_dbg11_groups[] = {
-+	"gpio67",
-+};
-+static const char * const qpic_pad8_groups[] = {
-+	"gpio68",
-+};
-+static const char * const wcss0_dbg12_groups[] = {
-+	"gpio68",
-+};
-+static const char * const wcss1_dbg12_groups[] = {
-+	"gpio68",
-+};
-+static const char * const wifi034_groups[] = {
-+	"gpio98",
-+};
-+static const char * const wifi134_groups[] = {
-+	"gpio98",
-+};
-+static const char * const jtag_tdi_groups[] = {
-+	"gpio0",
-+};
- static const char * const gpio_groups[] = {
- 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
- 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
-@@ -303,13 +818,103 @@ static const char * const gpio_groups[]
- 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
- 	"gpio99",
- };
--
-+static const char * const i2s_rx_bclk_groups[] = {
-+	"gpio0", "gpio21", "gpio60",
-+};
-+static const char * const jtag_tck_groups[] = {
-+	"gpio1",
-+};
-+static const char * const i2s_rx_fsync_groups[] = {
-+	"gpio1", "gpio22", "gpio61",
-+};
-+static const char * const jtag_tms_groups[] = {
-+	"gpio2",
-+};
-+static const char * const i2s_rxd_groups[] = {
-+	"gpio2", "gpio23", "gpio63",
-+};
-+static const char * const smart0_groups[] = {
-+	"gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46",
-+	"gpio47",
-+};
-+static const char * const jtag_tdo_groups[] = {
-+	"gpio3",
-+};
-+static const char * const jtag_rst_groups[] = {
-+	"gpio4",
-+};
-+static const char * const jtag_trst_groups[] = {
-+	"gpio5",
-+};
-+static const char * const mdio0_groups[] = {
-+	"gpio6",
-+};
-+static const char * const wcss0_dbg18_groups[] = {
-+	"gpio6", "gpio22", "gpio39",
-+};
-+static const char * const wcss1_dbg18_groups[] = {
-+	"gpio6", "gpio22", "gpio39",
-+};
-+static const char * const qdss_tracedata_a_groups[] = {
-+	"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio16",
-+	"gpio17", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
-+	"gpio43",
-+};
-+static const char * const mdc_groups[] = {
-+	"gpio7", "gpio52",
-+};
-+static const char * const wcss0_dbg19_groups[] = {
-+	"gpio7", "gpio23", "gpio40",
-+};
-+static const char * const wcss1_dbg19_groups[] = {
-+	"gpio7", "gpio23", "gpio40",
-+};
- static const char * const blsp_uart1_groups[] = {
- 	"gpio8", "gpio9", "gpio10", "gpio11",
- };
-+static const char * const wifi0_uart_groups[] = {
-+	"gpio8", "gpio9", "gpio11", "gpio19", "gpio62",
-+};
-+static const char * const wifi1_uart_groups[] = {
-+	"gpio8", "gpio11", "gpio19", "gpio62", "gpio63",
-+};
-+static const char * const smart1_groups[] = {
-+	"gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60",
-+	"gpio61",
-+};
-+static const char * const wcss0_dbg20_groups[] = {
-+	"gpio8", "gpio24", "gpio41",
-+};
-+static const char * const wcss1_dbg20_groups[] = {
-+	"gpio8", "gpio24", "gpio41",
-+};
-+static const char * const wifi0_uart0_groups[] = {
-+	"gpio9", "gpio10",
-+};
-+static const char * const wifi1_uart0_groups[] = {
-+	"gpio9", "gpio10",
-+};
-+static const char * const wcss0_dbg21_groups[] = {
-+	"gpio9", "gpio25", "gpio42",
-+};
-+static const char * const wcss1_dbg21_groups[] = {
-+	"gpio9", "gpio25", "gpio42",
-+};
- static const char * const blsp_i2c0_groups[] = {
- 	"gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
- };
-+static const char * const wcss0_dbg22_groups[] = {
-+	"gpio10", "gpio26", "gpio43",
-+};
-+static const char * const wcss1_dbg22_groups[] = {
-+	"gpio10", "gpio26", "gpio43",
-+};
-+static const char * const wcss0_dbg23_groups[] = {
-+	"gpio11", "gpio27", "gpio44",
-+};
-+static const char * const wcss1_dbg23_groups[] = {
-+	"gpio11", "gpio27", "gpio44",
-+};
- static const char * const blsp_spi0_groups[] = {
- 	"gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
- 	"gpio54", "gpio55", "gpio56", "gpio57",
-@@ -317,94 +922,582 @@ static const char * const blsp_spi0_grou
- static const char * const blsp_i2c1_groups[] = {
- 	"gpio12", "gpio13", "gpio34", "gpio35",
- };
-+static const char * const wcss0_dbg24_groups[] = {
-+	"gpio12", "gpio28", "gpio45",
-+};
-+static const char * const wcss1_dbg24_groups[] = {
-+	"gpio12", "gpio28", "gpio45",
-+};
-+static const char * const wcss0_dbg25_groups[] = {
-+	"gpio13", "gpio29", "gpio46",
-+};
-+static const char * const wcss1_dbg25_groups[] = {
-+	"gpio13", "gpio29", "gpio46",
-+};
-+static const char * const wcss0_dbg26_groups[] = {
-+	"gpio14", "gpio30", "gpio47",
-+};
-+static const char * const wcss1_dbg26_groups[] = {
-+	"gpio14", "gpio30", "gpio47",
-+};
-+static const char * const wcss0_dbg_groups[] = {
-+	"gpio15", "gpio69",
-+};
-+static const char * const wcss1_dbg_groups[] = {
-+	"gpio15",
-+};
- static const char * const blsp_uart0_groups[] = {
- 	"gpio16", "gpio17", "gpio60", "gpio61",
- };
--static const char * const blsp_spi1_groups[] = {
--	"gpio44", "gpio45", "gpio46", "gpio47",
-+static const char * const led0_groups[] = {
-+	"gpio16", "gpio36", "gpio60",
-+};
-+static const char * const wcss0_dbg28_groups[] = {
-+	"gpio16", "gpio32", "gpio49",
-+};
-+static const char * const wcss1_dbg28_groups[] = {
-+	"gpio16", "gpio32", "gpio49",
-+};
-+static const char * const led1_groups[] = {
-+	"gpio17", "gpio37", "gpio61",
-+};
-+static const char * const wcss0_dbg29_groups[] = {
-+	"gpio17", "gpio33", "gpio50",
-+};
-+static const char * const wcss1_dbg29_groups[] = {
-+	"gpio17", "gpio33", "gpio50",
-+};
-+static const char * const wifi0_uart1_groups[] = {
-+	"gpio18", "gpio63",
-+};
-+static const char * const wifi1_uart1_groups[] = {
-+	"gpio18", "gpio63",
-+};
-+static const char * const wcss0_dbg30_groups[] = {
-+	"gpio18", "gpio34", "gpio51",
-+};
-+static const char * const wcss1_dbg30_groups[] = {
-+	"gpio18", "gpio34", "gpio51",
-+};
-+static const char * const wcss0_dbg31_groups[] = {
-+	"gpio19", "gpio35", "gpio52",
-+};
-+static const char * const wcss1_dbg31_groups[] = {
-+	"gpio19", "gpio35",
-+};
-+static const char * const i2s_rx_mclk_groups[] = {
-+	"gpio20", "gpio58",
-+};
-+static const char * const wcss0_dbg16_groups[] = {
-+	"gpio20", "gpio37",
-+};
-+static const char * const wcss1_dbg16_groups[] = {
-+	"gpio20", "gpio37",
-+};
-+static const char * const wcss0_dbg17_groups[] = {
-+	"gpio21", "gpio38",
-+};
-+static const char * const wcss1_dbg17_groups[] = {
-+	"gpio21", "gpio38",
-+};
-+static const char * const rgmii0_groups[] = {
-+	"gpio22", "gpio28",
-+};
-+static const char * const sdio0_groups[] = {
-+	"gpio23",
-+};
-+static const char * const rgmii1_groups[] = {
-+	"gpio23", "gpio29",
-+};
-+static const char * const sdio1_groups[] = {
-+	"gpio24",
-+};
-+static const char * const rgmii2_groups[] = {
-+	"gpio24", "gpio30",
-+};
-+static const char * const i2s_tx_mclk_groups[] = {
-+	"gpio24", "gpio52",
-+};
-+static const char * const sdio2_groups[] = {
-+	"gpio25",
-+};
-+static const char * const rgmii3_groups[] = {
-+	"gpio25", "gpio31",
-+};
-+static const char * const i2s_tx_bclk_groups[] = {
-+	"gpio25", "gpio53", "gpio60",
-+};
-+static const char * const sdio3_groups[] = {
-+	"gpio26",
-+};
-+static const char * const rgmii_rx_groups[] = {
-+	"gpio26",
-+};
-+static const char * const i2s_tx_fsync_groups[] = {
-+	"gpio26", "gpio57", "gpio61",
-+};
-+static const char * const sdio_clk_groups[] = {
-+	"gpio27",
-+};
-+static const char * const rgmii_txc_groups[] = {
-+	"gpio27",
-+};
-+static const char * const i2s_td1_groups[] = {
-+	"gpio27", "gpio54", "gpio63",
-+};
-+static const char * const sdio_cmd_groups[] = {
-+	"gpio28",
-+};
-+static const char * const i2s_td2_groups[] = {
-+	"gpio28", "gpio55",
-+};
-+static const char * const sdio4_groups[] = {
-+	"gpio29",
-+};
-+static const char * const i2s_td3_groups[] = {
-+	"gpio29", "gpio56",
-+};
-+static const char * const sdio5_groups[] = {
-+	"gpio30",
-+};
-+static const char * const audio_pwm0_groups[] = {
-+	"gpio30", "gpio64",
-+};
-+static const char * const sdio6_groups[] = {
-+	"gpio31",
-+};
-+static const char * const audio_pwm1_groups[] = {
-+	"gpio31", "gpio65",
-+};
-+static const char * const wcss0_dbg27_groups[] = {
-+	"gpio31", "gpio48",
-+};
-+static const char * const wcss1_dbg27_groups[] = {
-+	"gpio31", "gpio48",
-+};
-+static const char * const sdio7_groups[] = {
-+	"gpio32",
-+};
-+static const char * const rgmii_rxc_groups[] = {
-+	"gpio32",
-+};
-+static const char * const audio_pwm2_groups[] = {
-+	"gpio32", "gpio66",
-+};
-+static const char * const rgmii_tx_groups[] = {
-+	"gpio33",
-+};
-+static const char * const audio_pwm3_groups[] = {
-+	"gpio33", "gpio67",
-+};
-+static const char * const boot2_groups[] = {
-+	"gpio33",
-+};
-+static const char * const i2s_spdif_in_groups[] = {
-+	"gpio34", "gpio59", "gpio63",
-+};
-+static const char * const i2s_spdif_out_groups[] = {
-+	"gpio35", "gpio62", "gpio63",
-+};
-+static const char * const rmii00_groups[] = {
-+	"gpio36", "gpio41",
-+};
-+static const char * const led2_groups[] = {
-+	"gpio36", "gpio38", "gpio58",
-+};
-+static const char * const rmii01_groups[] = {
-+	"gpio37", "gpio42",
-+};
-+static const char * const wifi0_wci_groups[] = {
-+	"gpio37",
-+};
-+static const char * const wifi1_wci_groups[] = {
-+	"gpio37",
-+};
-+static const char * const boot4_groups[] = {
-+	"gpio37",
-+};
-+static const char * const rmii0_tx_groups[] = {
-+	"gpio38",
-+};
-+static const char * const boot5_groups[] = {
-+	"gpio38",
-+};
-+static const char * const rmii0_rx_groups[] = {
-+	"gpio39",
-+};
-+static const char * const pcie_clk1_groups[] = {
-+	"gpio39",
-+};
-+static const char * const led3_groups[] = {
-+	"gpio39",
-+};
-+static const char * const sdio_cd_groups[] = {
-+	"gpio22",
- };
- 
- static const struct msm_function ipq4019_functions[] = {
-+	FUNCTION(rmii0_refclk),
-+	FUNCTION(wifi0_rfsilient0),
-+	FUNCTION(wifi1_rfsilient0),
-+	FUNCTION(smart2),
-+	FUNCTION(led4),
-+	FUNCTION(wifi0_cal),
-+	FUNCTION(wifi1_cal),
-+	FUNCTION(wifi_wci0),
-+	FUNCTION(rmii0_dv),
-+	FUNCTION(wifi_wci1),
-+	FUNCTION(rmii1_refclk),
-+	FUNCTION(blsp_spi1),
-+	FUNCTION(led5),
-+	FUNCTION(rmii10),
-+	FUNCTION(led6),
-+	FUNCTION(rmii11),
-+	FUNCTION(led7),
-+	FUNCTION(rmii1_dv),
-+	FUNCTION(led8),
-+	FUNCTION(rmii1_tx),
-+	FUNCTION(aud_pin),
-+	FUNCTION(led9),
-+	FUNCTION(rmii1_rx),
-+	FUNCTION(led10),
-+	FUNCTION(wifi0_rfsilient1),
-+	FUNCTION(wifi1_rfsilient1),
-+	FUNCTION(led11),
-+	FUNCTION(boot7),
-+	FUNCTION(qpic_pad),
-+	FUNCTION(pcie_clk),
-+	FUNCTION(tm_clk0),
-+	FUNCTION(wifi00),
-+	FUNCTION(wifi10),
-+	FUNCTION(mdio1),
-+	FUNCTION(prng_rosc),
-+	FUNCTION(dbg_out),
-+	FUNCTION(tm0),
-+	FUNCTION(wifi01),
-+	FUNCTION(wifi11),
-+	FUNCTION(atest_char3),
-+	FUNCTION(pmu0),
-+	FUNCTION(boot8),
-+	FUNCTION(tm1),
-+	FUNCTION(atest_char2),
-+	FUNCTION(pmu1),
-+	FUNCTION(boot9),
-+	FUNCTION(tm2),
-+	FUNCTION(atest_char1),
-+	FUNCTION(tm_ack),
-+	FUNCTION(wifi03),
-+	FUNCTION(wifi13),
-+	FUNCTION(qpic_pad4),
-+	FUNCTION(atest_char0),
-+	FUNCTION(tm3),
-+	FUNCTION(wifi02),
-+	FUNCTION(wifi12),
-+	FUNCTION(qpic_pad5),
-+	FUNCTION(smart3),
-+	FUNCTION(wcss0_dbg14),
-+	FUNCTION(tm4),
-+	FUNCTION(wifi04),
-+	FUNCTION(wifi14),
-+	FUNCTION(qpic_pad6),
-+	FUNCTION(wcss0_dbg15),
-+	FUNCTION(qdss_tracectl_a),
-+	FUNCTION(boot18),
-+	FUNCTION(tm5),
-+	FUNCTION(qpic_pad7),
-+	FUNCTION(atest_char),
-+	FUNCTION(wcss0_dbg4),
-+	FUNCTION(qdss_traceclk_a),
-+	FUNCTION(boot19),
-+	FUNCTION(tm6),
-+	FUNCTION(wcss0_dbg5),
-+	FUNCTION(qdss_cti_trig_out_a0),
-+	FUNCTION(boot14),
-+	FUNCTION(tm7),
-+	FUNCTION(chip_rst),
-+	FUNCTION(wcss0_dbg6),
-+	FUNCTION(qdss_cti_trig_out_b0),
-+	FUNCTION(boot11),
-+	FUNCTION(tm8),
-+	FUNCTION(wcss0_dbg7),
-+	FUNCTION(wcss1_dbg7),
-+	FUNCTION(boot20),
-+	FUNCTION(tm9),
-+	FUNCTION(qpic_pad1),
-+	FUNCTION(wcss0_dbg8),
-+	FUNCTION(wcss1_dbg8),
-+	FUNCTION(qpic_pad2),
-+	FUNCTION(wcss0_dbg9),
-+	FUNCTION(wcss1_dbg9),
-+	FUNCTION(qpic_pad3),
-+	FUNCTION(wcss0_dbg10),
-+	FUNCTION(wcss1_dbg10),
-+	FUNCTION(qpic_pad0),
-+	FUNCTION(wcss0_dbg11),
-+	FUNCTION(wcss1_dbg11),
-+	FUNCTION(qpic_pad8),
-+	FUNCTION(wcss0_dbg12),
-+	FUNCTION(wcss1_dbg12),
-+	FUNCTION(wifi034),
-+	FUNCTION(wifi134),
-+	FUNCTION(jtag_tdi),
- 	FUNCTION(gpio),
-+	FUNCTION(i2s_rx_bclk),
-+	FUNCTION(jtag_tck),
-+	FUNCTION(i2s_rx_fsync),
-+	FUNCTION(jtag_tms),
-+	FUNCTION(i2s_rxd),
-+	FUNCTION(smart0),
-+	FUNCTION(jtag_tdo),
-+	FUNCTION(jtag_rst),
-+	FUNCTION(jtag_trst),
-+	FUNCTION(mdio0),
-+	FUNCTION(wcss0_dbg18),
-+	FUNCTION(wcss1_dbg18),
-+	FUNCTION(qdss_tracedata_a),
-+	FUNCTION(mdc),
-+	FUNCTION(wcss0_dbg19),
-+	FUNCTION(wcss1_dbg19),
- 	FUNCTION(blsp_uart1),
-+	FUNCTION(wifi0_uart),
-+	FUNCTION(wifi1_uart),
-+	FUNCTION(smart1),
-+	FUNCTION(wcss0_dbg20),
-+	FUNCTION(wcss1_dbg20),
-+	FUNCTION(wifi0_uart0),
-+	FUNCTION(wifi1_uart0),
-+	FUNCTION(wcss0_dbg21),
-+	FUNCTION(wcss1_dbg21),
- 	FUNCTION(blsp_i2c0),
-+	FUNCTION(wcss0_dbg22),
-+	FUNCTION(wcss1_dbg22),
-+	FUNCTION(wcss0_dbg23),
-+	FUNCTION(wcss1_dbg23),
-+	FUNCTION(blsp_spi0),
- 	FUNCTION(blsp_i2c1),
-+	FUNCTION(wcss0_dbg24),
-+	FUNCTION(wcss1_dbg24),
-+	FUNCTION(wcss0_dbg25),
-+	FUNCTION(wcss1_dbg25),
-+	FUNCTION(wcss0_dbg26),
-+	FUNCTION(wcss1_dbg26),
-+	FUNCTION(wcss0_dbg),
-+	FUNCTION(wcss1_dbg),
- 	FUNCTION(blsp_uart0),
--	FUNCTION(blsp_spi1),
--	FUNCTION(blsp_spi0),
-+	FUNCTION(led0),
-+	FUNCTION(wcss0_dbg28),
-+	FUNCTION(wcss1_dbg28),
-+	FUNCTION(led1),
-+	FUNCTION(wcss0_dbg29),
-+	FUNCTION(wcss1_dbg29),
-+	FUNCTION(wifi0_uart1),
-+	FUNCTION(wifi1_uart1),
-+	FUNCTION(wcss0_dbg30),
-+	FUNCTION(wcss1_dbg30),
-+	FUNCTION(wcss0_dbg31),
-+	FUNCTION(wcss1_dbg31),
-+	FUNCTION(i2s_rx_mclk),
-+	FUNCTION(wcss0_dbg16),
-+	FUNCTION(wcss1_dbg16),
-+	FUNCTION(wcss0_dbg17),
-+	FUNCTION(wcss1_dbg17),
-+	FUNCTION(rgmii0),
-+	FUNCTION(sdio0),
-+	FUNCTION(rgmii1),
-+	FUNCTION(sdio1),
-+	FUNCTION(rgmii2),
-+	FUNCTION(i2s_tx_mclk),
-+	FUNCTION(sdio2),
-+	FUNCTION(rgmii3),
-+	FUNCTION(i2s_tx_bclk),
-+	FUNCTION(sdio3),
-+	FUNCTION(rgmii_rx),
-+	FUNCTION(i2s_tx_fsync),
-+	FUNCTION(sdio_clk),
-+	FUNCTION(rgmii_txc),
-+	FUNCTION(i2s_td1),
-+	FUNCTION(sdio_cmd),
-+	FUNCTION(i2s_td2),
-+	FUNCTION(sdio4),
-+	FUNCTION(i2s_td3),
-+	FUNCTION(sdio5),
-+	FUNCTION(audio_pwm0),
-+	FUNCTION(sdio6),
-+	FUNCTION(audio_pwm1),
-+	FUNCTION(wcss0_dbg27),
-+	FUNCTION(wcss1_dbg27),
-+	FUNCTION(sdio7),
-+	FUNCTION(rgmii_rxc),
-+	FUNCTION(audio_pwm2),
-+	FUNCTION(rgmii_tx),
-+	FUNCTION(audio_pwm3),
-+	FUNCTION(boot2),
-+	FUNCTION(i2s_spdif_in),
-+	FUNCTION(i2s_spdif_out),
-+	FUNCTION(rmii00),
-+	FUNCTION(led2),
-+	FUNCTION(rmii01),
-+	FUNCTION(wifi0_wci),
-+	FUNCTION(wifi1_wci),
-+	FUNCTION(boot4),
-+	FUNCTION(rmii0_tx),
-+	FUNCTION(boot5),
-+	FUNCTION(rmii0_rx),
-+	FUNCTION(pcie_clk1),
-+	FUNCTION(led3),
-+	FUNCTION(sdio_cd),
- };
- 
- static const struct msm_pingroup ipq4019_groups[] = {
--	PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(0, jtag_tdi, smart0, i2s_rx_bclk, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA, NA, NA),
-+	PINGROUP(1, jtag_tck, smart0, i2s_rx_fsync, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA, NA, NA),
-+	PINGROUP(2, jtag_tms, smart0, i2s_rxd, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA, NA),
-+	PINGROUP(3, jtag_tdo, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA),
-+	PINGROUP(4, jtag_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA),
-+	PINGROUP(5, jtag_trst, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA),
-+	PINGROUP(6, mdio0, NA, wcss0_dbg18, wcss1_dbg18, NA, qdss_tracedata_a,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(7, mdc, NA, wcss0_dbg19, wcss1_dbg19, NA, qdss_tracedata_a,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(8, blsp_uart1, wifi0_uart, wifi1_uart, smart1, NA,
-+		 wcss0_dbg20, wcss1_dbg20, NA, qdss_tracedata_a, NA, NA, NA,
-+		 NA, NA),
-+	PINGROUP(9, blsp_uart1, wifi0_uart0, wifi1_uart0, smart1, wifi0_uart,
-+		 NA, wcss0_dbg21, wcss1_dbg21, NA, qdss_tracedata_a, NA, NA,
-+		 NA, NA),
-+	PINGROUP(10, blsp_uart1, wifi0_uart0, wifi1_uart0, blsp_i2c0, NA,
-+		 wcss0_dbg22, wcss1_dbg22, NA, qdss_tracedata_a, NA, NA, NA,
-+		 NA, NA),
-+	PINGROUP(11, blsp_uart1, wifi0_uart, wifi1_uart, blsp_i2c0, NA,
-+		 wcss0_dbg23, wcss1_dbg23, NA, qdss_tracedata_a, NA, NA, NA,
-+		 NA, NA),
-+	PINGROUP(12, blsp_spi0, blsp_i2c1, NA, wcss0_dbg24, wcss1_dbg24, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(13, blsp_spi0, blsp_i2c1, NA, wcss0_dbg25, wcss1_dbg25, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(14, blsp_spi0, NA, wcss0_dbg26, wcss1_dbg26, NA, NA, NA, NA,
-+		 NA, NA, NA, NA, NA, NA),
-+	PINGROUP(15, blsp_spi0, NA, wcss0_dbg, wcss1_dbg, NA, NA, NA, NA, NA,
-+		 NA, NA, NA, NA, NA),
-+	PINGROUP(16, blsp_uart0, led0, smart1, NA, wcss0_dbg28, wcss1_dbg28,
-+		 NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(17, blsp_uart0, led1, smart1, NA, wcss0_dbg29, wcss1_dbg29,
-+		 NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(18, wifi0_uart1, wifi1_uart1, NA, wcss0_dbg30, wcss1_dbg30,
-+		 NA, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(19, wifi0_uart, wifi1_uart, NA, wcss0_dbg31, wcss1_dbg31, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(20, blsp_i2c0, i2s_rx_mclk, NA, wcss0_dbg16, wcss1_dbg16, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(21, blsp_i2c0, i2s_rx_bclk, NA, wcss0_dbg17, wcss1_dbg17, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(22, rgmii0, i2s_rx_fsync, NA, wcss0_dbg18, wcss1_dbg18, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(23, sdio0, rgmii1, i2s_rxd, NA, wcss0_dbg19, wcss1_dbg19, NA,
-+		 NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(24, sdio1, rgmii2, i2s_tx_mclk, NA, wcss0_dbg20, wcss1_dbg20,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(25, sdio2, rgmii3, i2s_tx_bclk, NA, wcss0_dbg21, wcss1_dbg21,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(26, sdio3, rgmii_rx, i2s_tx_fsync, NA, wcss0_dbg22,
-+		 wcss1_dbg22, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(27, sdio_clk, rgmii_txc, i2s_td1, NA, wcss0_dbg23,
-+		 wcss1_dbg23, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(28, sdio_cmd, rgmii0, i2s_td2, NA, wcss0_dbg24, wcss1_dbg24,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(29, sdio4, rgmii1, i2s_td3, NA, wcss0_dbg25, wcss1_dbg25, NA,
-+		 NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(30, sdio5, rgmii2, audio_pwm0, NA, wcss0_dbg26, wcss1_dbg26,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(31, sdio6, rgmii3, audio_pwm1, NA, wcss0_dbg27, wcss1_dbg27,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(32, sdio7, rgmii_rxc, audio_pwm2, NA, wcss0_dbg28,
-+		 wcss1_dbg28, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(33, rgmii_tx, audio_pwm3, NA, wcss0_dbg29, wcss1_dbg29, NA,
-+		 boot2, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, wcss0_dbg30, wcss1_dbg30, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, wcss0_dbg31, wcss1_dbg31,
-+		 NA, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(36, rmii00, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA),
-+	PINGROUP(37, rmii01, wifi0_wci, wifi1_wci, led1, NA, NA, wcss0_dbg16,
-+		 wcss1_dbg16, NA, qdss_tracedata_a, boot4, NA, NA, NA),
-+	PINGROUP(38, rmii0_tx, led2, NA, NA, wcss0_dbg17, wcss1_dbg17, NA,
-+		 qdss_tracedata_a, boot5, NA, NA, NA, NA, NA),
-+	PINGROUP(39, rmii0_rx, pcie_clk1, led3, NA, NA, wcss0_dbg18,
-+		 wcss1_dbg18, NA, NA, qdss_tracedata_a, NA, NA, NA, NA),
-+	PINGROUP(40, rmii0_refclk, wifi0_rfsilient0, wifi1_rfsilient0, smart2,
-+		 led4, NA, NA, wcss0_dbg19, wcss1_dbg19, NA, NA,
-+		 qdss_tracedata_a, NA, NA),
-+	PINGROUP(41, rmii00, wifi0_cal, wifi1_cal, smart2, NA, NA, wcss0_dbg20,
-+		 wcss1_dbg20, NA, NA, qdss_tracedata_a, NA, NA, NA),
-+	PINGROUP(42, rmii01, wifi_wci0, NA, NA, wcss0_dbg21, wcss1_dbg21, NA,
-+		 NA, qdss_tracedata_a, NA, NA, NA, NA, NA),
-+	PINGROUP(43, rmii0_dv, wifi_wci1, NA, NA, wcss0_dbg22, wcss1_dbg22, NA,
-+		 NA, qdss_tracedata_a, NA, NA, NA, NA, NA),
-+	PINGROUP(44, rmii1_refclk, blsp_spi1, smart0, led5, NA, NA,
-+		 wcss0_dbg23, wcss1_dbg23, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(45, rmii10, blsp_spi1, blsp_spi0, smart0, led6, NA, NA,
-+		 wcss0_dbg24, wcss1_dbg24, NA, NA, NA, NA, NA),
-+	PINGROUP(46, rmii11, blsp_spi1, smart0, led7, NA, NA, wcss0_dbg25,
-+		 wcss1_dbg25, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(47, rmii1_dv, blsp_spi1, smart0, led8, NA, NA, wcss0_dbg26,
-+		 wcss1_dbg26, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(48, rmii1_tx, aud_pin, smart2, led9, NA, NA, wcss0_dbg27,
-+		 wcss1_dbg27, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(49, rmii1_rx, aud_pin, smart2, led10, NA, NA, wcss0_dbg28,
-+		 wcss1_dbg28, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(50, rmii10, aud_pin, wifi0_rfsilient1, wifi1_rfsilient1,
-+		 led11, NA, NA, wcss0_dbg29, wcss1_dbg29, NA, NA, NA, NA, NA),
-+	PINGROUP(51, rmii11, aud_pin, wifi0_cal, wifi1_cal, NA, NA,
-+		 wcss0_dbg30, wcss1_dbg30, NA, boot7, NA, NA, NA, NA),
-+	PINGROUP(52, qpic_pad, mdc, pcie_clk, i2s_tx_mclk, NA, NA, wcss0_dbg31,
-+		 tm_clk0, wifi00, wifi10, NA, NA, NA, NA),
-+	PINGROUP(53, qpic_pad, mdio1, i2s_tx_bclk, prng_rosc, dbg_out, tm0,
-+		 wifi01, wifi11, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(54, qpic_pad, blsp_spi0, i2s_td1, atest_char3, pmu0, NA, NA,
-+		 boot8, tm1, NA, NA, NA, NA, NA),
-+	PINGROUP(55, qpic_pad, blsp_spi0, i2s_td2, atest_char2, pmu1, NA, NA,
-+		 boot9, tm2, NA, NA, NA, NA, NA),
-+	PINGROUP(56, qpic_pad, blsp_spi0, i2s_td3, atest_char1, NA, tm_ack,
-+		 wifi03, wifi13, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(57, qpic_pad4, blsp_spi0, i2s_tx_fsync, atest_char0, NA, tm3,
-+		 wifi02, wifi12, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(58, qpic_pad5, led2, blsp_i2c0, smart3, smart1, i2s_rx_mclk,
-+		 NA, wcss0_dbg14, tm4, wifi04, wifi14, NA, NA, NA),
-+	PINGROUP(59, qpic_pad6, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA,
-+		 NA, wcss0_dbg15, qdss_tracectl_a, boot18, tm5, NA, NA, NA),
-+	PINGROUP(60, qpic_pad7, blsp_uart0, smart1, smart3, led0, i2s_tx_bclk,
-+		 i2s_rx_bclk, atest_char, NA, wcss0_dbg4, qdss_traceclk_a,
-+		 boot19, tm6, NA),
-+	PINGROUP(61, qpic_pad, blsp_uart0, smart1, smart3, led1, i2s_tx_fsync,
-+		 i2s_rx_fsync, NA, NA, wcss0_dbg5, qdss_cti_trig_out_a0,
-+		 boot14, tm7, NA),
-+	PINGROUP(62, qpic_pad, chip_rst, wifi0_uart, wifi1_uart, i2s_spdif_out,
-+		 NA, NA, wcss0_dbg6, qdss_cti_trig_out_b0, boot11, tm8, NA, NA,
-+		 NA),
-+	PINGROUP(63, qpic_pad, wifi0_uart1, wifi1_uart1, wifi1_uart, i2s_td1,
-+		 i2s_rxd, i2s_spdif_out, i2s_spdif_in, NA, wcss0_dbg7,
-+		 wcss1_dbg7, boot20, tm9, NA),
-+	PINGROUP(64, qpic_pad1, audio_pwm0, NA, wcss0_dbg8, wcss1_dbg8, NA, NA,
-+		 NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(65, qpic_pad2, audio_pwm1, NA, wcss0_dbg9, wcss1_dbg9, NA, NA,
-+		 NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(66, qpic_pad3, audio_pwm2, NA, wcss0_dbg10, wcss1_dbg10, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(67, qpic_pad0, audio_pwm3, NA, wcss0_dbg11, wcss1_dbg11, NA,
-+		 NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(68, qpic_pad8, NA, wcss0_dbg12, wcss1_dbg12, NA, NA, NA, NA,
-+		 NA, NA, NA, NA, NA, NA),
-+	PINGROUP(69, qpic_pad, NA, wcss0_dbg, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA, NA),
- 	PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-@@ -433,7 +1526,8 @@ static const struct msm_pingroup ipq4019
- 	PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- 	PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
--	PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
-+	PINGROUP(98, wifi034, wifi134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
-+		 NA, NA),
- 	PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- };
- 
-@@ -460,6 +1554,7 @@ static const struct of_device_id ipq4019
- static struct platform_driver ipq4019_pinctrl_driver = {
- 	.driver = {
- 		.name = "ipq4019-pinctrl",
-+		.owner = THIS_MODULE,
- 		.of_match_table = ipq4019_pinctrl_of_match,
- 	},
- 	.probe = ipq4019_pinctrl_probe,
diff --git a/target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch b/target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch
deleted file mode 100644
index 07cf01b268..0000000000
--- a/target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch
+++ /dev/null
@@ -1,236 +0,0 @@
-From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Tue, 9 May 2017 11:45:00 +0530
-Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits
-
-GPIO_PULL bits configurations in TLMM_GPIO_CFG register
-differs for IPQ40xx from rest of the other qcom SoC's.
-This change add support to configure the msm_gpio_pull
-bits for ipq40xx, It is required to fix the proper
-configurations of gpio-pull bits for nand pins mux.
-
-IPQ40xx SoC:
-2'b10: Internal pull up enable.
-2'b11: Unsupport
-
-For other SoC's:
-2'b10: Keeper
-2'b11: Pull-Up
-
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- drivers/pinctrl/qcom/pinctrl-apq8064.c |  1 +
- drivers/pinctrl/qcom/pinctrl-apq8084.c |  1 +
- drivers/pinctrl/qcom/pinctrl-ipq4019.c |  8 ++++++++
- drivers/pinctrl/qcom/pinctrl-ipq8064.c |  1 +
- drivers/pinctrl/qcom/pinctrl-mdm9615.c |  1 +
- drivers/pinctrl/qcom/pinctrl-msm.c     | 21 ++++++++-------------
- drivers/pinctrl/qcom/pinctrl-msm.h     | 19 +++++++++++++++++++
- drivers/pinctrl/qcom/pinctrl-msm8660.c |  1 +
- drivers/pinctrl/qcom/pinctrl-msm8916.c |  1 +
- drivers/pinctrl/qcom/pinctrl-msm8960.c |  1 +
- drivers/pinctrl/qcom/pinctrl-msm8x74.c |  1 +
- 11 files changed, 43 insertions(+), 13 deletions(-)
-
---- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
-+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
-@@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = apq8064_groups,
- 	.ngroups = ARRAY_SIZE(apq8064_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int apq8064_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
-+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
-@@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = apq8084_groups,
- 	.ngroups = ARRAY_SIZE(apq8084_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int apq8084_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
-+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
-@@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019
- 	PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- };
- 
-+static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = {
-+	.no_pull = 0,
-+	.pull_down = 1,
-+	.keeper = 0,
-+	.pull_up = 2,
-+};
-+
- static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
- 	.pins = ipq4019_pins,
- 	.npins = ARRAY_SIZE(ipq4019_pins),
-@@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = ipq4019_groups,
- 	.ngroups = ARRAY_SIZE(ipq4019_groups),
- 	.ngpios = 100,
-+	.gpio_pull = &ipq4019_gpio_pull,
- };
- 
- static int ipq4019_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
-+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
-@@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = ipq8064_groups,
- 	.ngroups = ARRAY_SIZE(ipq8064_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int ipq8064_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
-+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
-@@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = mdm9615_groups,
- 	.ngroups = ARRAY_SIZE(mdm9615_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int mdm9615_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-msm.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
-@@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pin
- 	return 0;
- }
- 
--#define MSM_NO_PULL	0
--#define MSM_PULL_DOWN	1
--#define MSM_KEEPER	2
--#define MSM_PULL_UP	3
--
- static unsigned msm_regval_to_drive(u32 val)
- {
- 	return (val + 1) * 2;
-@@ -238,16 +233,16 @@ static int msm_config_group_get(struct p
- 	/* Convert register value to pinconf value */
- 	switch (param) {
- 	case PIN_CONFIG_BIAS_DISABLE:
--		arg = arg == MSM_NO_PULL;
-+		arg = arg == pctrl->soc->gpio_pull->no_pull;
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_DOWN:
--		arg = arg == MSM_PULL_DOWN;
-+		arg = arg == pctrl->soc->gpio_pull->pull_down;
- 		break;
- 	case PIN_CONFIG_BIAS_BUS_HOLD:
--		arg = arg == MSM_KEEPER;
-+		arg = arg == pctrl->soc->gpio_pull->keeper;
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_UP:
--		arg = arg == MSM_PULL_UP;
-+		arg = arg == pctrl->soc->gpio_pull->pull_up;
- 		break;
- 	case PIN_CONFIG_DRIVE_STRENGTH:
- 		arg = msm_regval_to_drive(arg);
-@@ -304,16 +299,16 @@ static int msm_config_group_set(struct p
- 		/* Convert pinconf values to register values */
- 		switch (param) {
- 		case PIN_CONFIG_BIAS_DISABLE:
--			arg = MSM_NO_PULL;
-+			arg = pctrl->soc->gpio_pull->no_pull;
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_DOWN:
--			arg = MSM_PULL_DOWN;
-+			arg = pctrl->soc->gpio_pull->pull_down;
- 			break;
- 		case PIN_CONFIG_BIAS_BUS_HOLD:
--			arg = MSM_KEEPER;
-+			arg = pctrl->soc->gpio_pull->keeper;
- 			break;
- 		case PIN_CONFIG_BIAS_PULL_UP:
--			arg = MSM_PULL_UP;
-+			arg = pctrl->soc->gpio_pull->pull_up;
- 			break;
- 		case PIN_CONFIG_DRIVE_STRENGTH:
- 			/* Check for invalid values */
---- a/drivers/pinctrl/qcom/pinctrl-msm.h
-+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
-@@ -98,6 +98,16 @@ struct msm_pingroup {
- };
- 
- /**
-+ * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
-+ */
-+struct msm_pinctrl_gpio_pull {
-+	unsigned no_pull;
-+	unsigned pull_down;
-+	unsigned keeper;
-+	unsigned pull_up;
-+};
-+
-+/**
-  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
-  * @pins:       An array describing all pins the pin controller affects.
-  * @npins:      The number of entries in @pins.
-@@ -106,6 +116,7 @@ struct msm_pingroup {
-  * @groups:     An array describing all pin groups the pin SoC supports.
-  * @ngroups:    The numbmer of entries in @groups.
-  * @ngpio:      The number of pingroups the driver should expose as GPIOs.
-+ * @gpio_pull_val: The pull value bit field descriptor.
-  */
- struct msm_pinctrl_soc_data {
- 	const struct pinctrl_pin_desc *pins;
-@@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data {
- 	const struct msm_pingroup *groups;
- 	unsigned ngroups;
- 	unsigned ngpios;
-+	const struct msm_pinctrl_gpio_pull *gpio_pull;
-+};
-+
-+static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
-+	.no_pull = 0,
-+	.pull_down = 1,
-+	.keeper = 2,
-+	.pull_up = 3,
- };
- 
- int msm_pinctrl_probe(struct platform_device *pdev,
---- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
-@@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = msm8660_groups,
- 	.ngroups = ARRAY_SIZE(msm8660_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int msm8660_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
-@@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = msm8916_groups,
- 	.ngroups = ARRAY_SIZE(msm8916_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int msm8916_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
-@@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = msm8960_groups,
- 	.ngroups = ARRAY_SIZE(msm8960_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int msm8960_pinctrl_probe(struct platform_device *pdev)
---- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
-+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
-@@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data
- 	.groups = msm8x74_groups,
- 	.ngroups = ARRAY_SIZE(msm8x74_groups),
- 	.ngpios = NUM_GPIO_PINGROUPS,
-+	.gpio_pull = &msm_gpio_pull,
- };
- 
- static int msm8x74_pinctrl_probe(struct platform_device *pdev)
diff --git a/target/linux/ipq806x/patches-4.9/860-qcom-mtd-nand-Add-bam_dma-support-in-qcom_nand-drive.patch b/target/linux/ipq806x/patches-4.9/860-qcom-mtd-nand-Add-bam_dma-support-in-qcom_nand-drive.patch
deleted file mode 100644
index 5a3c02c700..0000000000
--- a/target/linux/ipq806x/patches-4.9/860-qcom-mtd-nand-Add-bam_dma-support-in-qcom_nand-drive.patch
+++ /dev/null
@@ -1,370 +0,0 @@
-From 074036f9de6b8c5fc642e8e2540950f6a35aa804 Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Thu, 20 Apr 2017 10:31:10 +0530
-Subject: [PATCH] qcom: mtd: nand: Add bam_dma support in qcom_nand driver
-
-The current driver only support ADM DMA so this patch adds the
-BAM DMA support in current NAND driver with compatible string
-qcom,ebi2-nandc-bam.
-Added bam channels and data buffers, NAND BAM uses 3 channels:
-command, data tx and data rx, while ADM uses only single channel.
-So this patch adds the BAM channel in device tree and using the
-same in NAND driver allocation function.
-
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- .../devicetree/bindings/mtd/qcom_nandc.txt         |  69 +++++++--
- drivers/mtd/nand/qcom_nandc.c                      | 160 +++++++++++++++++----
- 2 files changed, 190 insertions(+), 39 deletions(-)
-
---- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
-+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
-@@ -1,21 +1,26 @@
- * Qualcomm NAND controller
- 
- Required properties:
--- compatible:		should be "qcom,ipq806x-nand"
-+- compatible:		"qcom,ipq806x-nand" for IPQ8064 which uses
-+			ADM DMA.
-+			"qcom,ebi2-nand-bam" - nand drivers using BAM DMA
-+			like IPQ4019.
- - reg:			MMIO address range
- - clocks:		must contain core clock and always on clock
- - clock-names:		must contain "core" for the core clock and "aon" for the
- 			always on clock
- - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
--			controller node and the channel number to be used for
--			NAND. Refer to dma.txt and qcom_adm.txt for more details
--- dma-names:		must be "rxtx"
--- qcom,cmd-crci:	must contain the ADM command type CRCI block instance
--			number specified for the NAND controller on the given
--			platform
--- qcom,data-crci:	must contain the ADM data type CRCI block instance
--			number specified for the NAND controller on the given
--			platform
-+			or BAM DMA controller node and the channel number to
-+			be used for NAND. Refer to dma.txt, qcom_adm.txt(ADM)
-+			and qcom_bam_dma.txt(BAM) for more details
-+- dma-names:		"rxtx" - ADM
-+			"tx", "rx", "cmd" - BAM
-+- qcom,cmd-crci:	Only required for ADM DMA. must contain the ADM command
-+			type CRCI block instance number specified for the NAND
-+			controller on the given platform.
-+- qcom,data-crci:	Only required for ADM DMA. must contain the ADM data
-+			type CRCI block instance number specified for the NAND
-+			controller on the given platform.
- - #address-cells:	<1> - subnodes give the chip-select number
- - #size-cells:		<0>
- 
-@@ -44,7 +49,7 @@ partition.txt for more detail.
- Example:
- 
- nand@1ac00000 {
--	compatible = "qcom,ebi2-nandc";
-+	compatible = "qcom,ipq806x-nand","qcom.qcom_nand";
- 	reg = <0x1ac00000 0x800>;
- 
- 	clocks = <&gcc EBI2_CLK>,
-@@ -58,6 +63,48 @@ nand@1ac00000 {
- 
- 	#address-cells = <1>;
- 	#size-cells = <0>;
-+
-+	nandcs@0 {
-+		compatible = "qcom,nandcs";
-+		reg = <0>;
-+
-+		nand-ecc-strength = <4>;
-+		nand-ecc-step-size = <512>;
-+		nand-bus-width = <8>;
-+
-+		partitions {
-+			compatible = "fixed-partitions";
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			partition@0 {
-+				label = "boot-nand";
-+				reg = <0 0x58a0000>;
-+			};
-+
-+			partition@58a0000 {
-+				label = "fs-nand";
-+				reg = <0x58a0000 0x4000000>;
-+			};
-+		};
-+	};
-+};
-+
-+nand@79B0000 {
-+	compatible = "qcom,ebi2-nandc-bam";
-+	reg = <0x79B0000 0x1000>;
-+
-+	clocks = <&gcc EBI2_CLK>,
-+		 <&gcc EBI2_AON_CLK>;
-+	clock-names = "core", "aon";
-+
-+	dmas = <&qpicbam 0>,
-+		<&qpicbam 1>,
-+		<&qpicbam 2>;
-+	dma-names = "tx", "rx", "cmd";
-+
-+	#address-cells = <1>;
-+	#size-cells = <0>;
- 
- 	nandcs@0 {
- 		compatible = "qcom,nandcs";
---- a/drivers/mtd/nand/qcom_nandc.c
-+++ b/drivers/mtd/nand/qcom_nandc.c
-@@ -234,6 +234,7 @@ struct nandc_regs {
-  *				by upper layers directly
-  * @buf_size/count/start:	markers for chip->read_buf/write_buf functions
-  * @reg_read_buf:		local buffer for reading back registers via DMA
-+ * @reg_read_buf_phys:         contains dma address for register read buffer
-  * @reg_read_pos:		marker for data read in reg_read_buf
-  *
-  * @regs:			a contiguous chunk of memory for DMA register
-@@ -242,7 +243,10 @@ struct nandc_regs {
-  * @cmd1/vld:			some fixed controller register values
-  * @ecc_modes:			supported ECC modes by the current controller,
-  *				initialized via DT match data
-- */
-+ * @bch_enabled:		flag to tell whether BCH or RS ECC mode is used
-+ * @dma_bam_enabled:		flag to tell whether nand controller is using
-+ *				bam dma
-+*/
- struct qcom_nand_controller {
- 	struct nand_hw_control controller;
- 	struct list_head host_list;
-@@ -255,17 +259,28 @@ struct qcom_nand_controller {
- 	struct clk *core_clk;
- 	struct clk *aon_clk;
- 
--	struct dma_chan *chan;
--	unsigned int cmd_crci;
--	unsigned int data_crci;
- 	struct list_head desc_list;
-+	union {
-+		struct {
-+			struct dma_chan *tx_chan;
-+			struct dma_chan *rx_chan;
-+			struct dma_chan *cmd_chan;
-+		};
-+		struct {
-+			struct dma_chan *chan;
-+			unsigned int cmd_crci;
-+			unsigned int data_crci;
-+		};
-+	};
- 
- 	u8		*data_buffer;
-+	bool            dma_bam_enabled;
- 	int		buf_size;
- 	int		buf_count;
- 	int		buf_start;
- 
- 	__le32 *reg_read_buf;
-+	dma_addr_t reg_read_buf_phys;
- 	int reg_read_pos;
- 
- 	struct nandc_regs *regs;
-@@ -324,6 +339,17 @@ struct qcom_nand_host {
- 	u32 clrreadstatus;
- };
- 
-+/*
-+ * This data type corresponds to the nand driver data which will be used at
-+ * driver probe time
-+ * @ecc_modes - ecc mode for nand
-+ * @dma_bam_enabled - whether this driver is using bam
-+ */
-+struct qcom_nand_driver_data {
-+	u32 ecc_modes;
-+	bool dma_bam_enabled;
-+};
-+
- static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
- {
- 	return container_of(chip, struct qcom_nand_host, chip);
-@@ -1949,16 +1975,46 @@ static int qcom_nandc_alloc(struct qcom_
- 	if (!nandc->regs)
- 		return -ENOMEM;
- 
--	nandc->reg_read_buf = devm_kzalloc(nandc->dev,
--				MAX_REG_RD * sizeof(*nandc->reg_read_buf),
--				GFP_KERNEL);
--	if (!nandc->reg_read_buf)
--		return -ENOMEM;
-+	if (!nandc->dma_bam_enabled) {
-+		nandc->reg_read_buf = devm_kzalloc(nandc->dev,
-+					MAX_REG_RD *
-+					sizeof(*nandc->reg_read_buf),
-+					GFP_KERNEL);
- 
--	nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
--	if (!nandc->chan) {
--		dev_err(nandc->dev, "failed to request slave channel\n");
--		return -ENODEV;
-+		if (!nandc->reg_read_buf)
-+			return -ENOMEM;
-+
-+		nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx");
-+		if (!nandc->chan) {
-+			dev_err(nandc->dev, "failed to request slave channel\n");
-+			return -ENODEV;
-+		}
-+	} else {
-+		nandc->reg_read_buf = dmam_alloc_coherent(nandc->dev,
-+					MAX_REG_RD *
-+					sizeof(*nandc->reg_read_buf),
-+					&nandc->reg_read_buf_phys, GFP_KERNEL);
-+
-+		if (!nandc->reg_read_buf)
-+			return -ENOMEM;
-+
-+		nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx");
-+		if (!nandc->tx_chan) {
-+			dev_err(nandc->dev, "failed to request tx channel\n");
-+			return -ENODEV;
-+		}
-+
-+		nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx");
-+		if (!nandc->rx_chan) {
-+			dev_err(nandc->dev, "failed to request rx channel\n");
-+			return -ENODEV;
-+		}
-+
-+		nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd");
-+		if (!nandc->cmd_chan) {
-+			dev_err(nandc->dev, "failed to request cmd channel\n");
-+			return -ENODEV;
-+		}
- 	}
- 
- 	INIT_LIST_HEAD(&nandc->desc_list);
-@@ -1971,8 +2027,35 @@ static int qcom_nandc_alloc(struct qcom_
- 
- static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
- {
--	dma_release_channel(nandc->chan);
--}
-+	if (nandc->dma_bam_enabled) {
-+		if (nandc->tx_chan)
-+			dma_release_channel(nandc->tx_chan);
-+
-+		if (nandc->rx_chan)
-+			dma_release_channel(nandc->rx_chan);
-+
-+		if (nandc->cmd_chan)
-+			dma_release_channel(nandc->tx_chan);
-+
-+		if (nandc->reg_read_buf)
-+			dmam_free_coherent(nandc->dev, MAX_REG_RD *
-+				sizeof(*nandc->reg_read_buf),
-+				nandc->reg_read_buf,
-+				nandc->reg_read_buf_phys);
-+	} else {
-+		if (nandc->chan)
-+			dma_release_channel(nandc->chan);
-+
-+		if (nandc->reg_read_buf)
-+			devm_kfree(nandc->dev, nandc->reg_read_buf);
-+	}
-+
-+	if (nandc->regs)
-+		devm_kfree(nandc->dev, nandc->regs);
-+
-+	if (nandc->data_buffer)
-+		devm_kfree(nandc->dev, nandc->data_buffer);
-+ }
- 
- /* one time setup of a few nand controller registers */
- static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
-@@ -2010,6 +2093,8 @@ static int qcom_nand_host_init(struct qc
- 	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
- 	mtd->owner = THIS_MODULE;
- 	mtd->dev.parent = dev;
-+	mtd->priv = chip;
-+	chip->priv = nandc;
- 
- 	chip->cmdfunc		= qcom_nandc_command;
- 	chip->select_chip	= qcom_nandc_select_chip;
-@@ -2057,16 +2142,20 @@ static int qcom_nandc_parse_dt(struct pl
- 	struct device_node *np = nandc->dev->of_node;
- 	int ret;
- 
--	ret = of_property_read_u32(np, "qcom,cmd-crci", &nandc->cmd_crci);
--	if (ret) {
--		dev_err(nandc->dev, "command CRCI unspecified\n");
--		return ret;
--	}
-+	if (!nandc->dma_bam_enabled) {
-+		ret = of_property_read_u32(np, "qcom,cmd-crci",
-+				&nandc->cmd_crci);
-+		if (ret) {
-+			dev_err(nandc->dev, "command CRCI unspecified\n");
-+			return ret;
-+		}
- 
--	ret = of_property_read_u32(np, "qcom,data-crci", &nandc->data_crci);
--	if (ret) {
--		dev_err(nandc->dev, "data CRCI unspecified\n");
--		return ret;
-+		ret = of_property_read_u32(np, "qcom,data-crci",
-+				&nandc->data_crci);
-+		if (ret) {
-+			dev_err(nandc->dev, "data CRCI unspecified\n");
-+			return ret;
-+		}
- 	}
- 
- 	return 0;
-@@ -2081,6 +2170,7 @@ static int qcom_nandc_probe(struct platf
- 	struct device_node *dn = dev->of_node, *child;
- 	struct resource *res;
- 	int ret;
-+	struct qcom_nand_driver_data *driver_data;
- 
- 	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
- 	if (!nandc)
-@@ -2095,7 +2185,10 @@ static int qcom_nandc_probe(struct platf
- 		return -ENODEV;
- 	}
- 
--	nandc->ecc_modes = (unsigned long)dev_data;
-+	driver_data = (struct qcom_nand_driver_data *)dev_data;
-+
-+	nandc->ecc_modes = driver_data->ecc_modes;
-+	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	nandc->base = devm_ioremap_resource(dev, res);
-@@ -2187,7 +2280,15 @@ static int qcom_nandc_remove(struct plat
- 	return 0;
- }
- 
--#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
-+struct qcom_nand_driver_data ebi2_nandc_bam_data = {
-+	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
-+	.dma_bam_enabled = true,
-+};
-+
-+struct qcom_nand_driver_data ebi2_nandc_data = {
-+	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
-+	.dma_bam_enabled = false,
-+};
- 
- /*
-  * data will hold a struct pointer containing more differences once we support
-@@ -2195,7 +2296,10 @@ static int qcom_nandc_remove(struct plat
-  */
- static const struct of_device_id qcom_nandc_of_match[] = {
- 	{	.compatible = "qcom,ipq806x-nand",
--		.data = (void *)EBI2_NANDC_ECC_MODES,
-+		.data = (void *) &ebi2_nandc_data,
-+	},
-+	{	.compatible = "qcom,ebi2-nandc-bam",
-+		.data = (void *) &ebi2_nandc_bam_data,
- 	},
- 	{}
- };
diff --git a/target/linux/ipq806x/patches-4.9/861-qcom-mtd-nand-Added-bam-transaction-and-support-addi.patch b/target/linux/ipq806x/patches-4.9/861-qcom-mtd-nand-Added-bam-transaction-and-support-addi.patch
deleted file mode 100644
index 4b9f672205..0000000000
--- a/target/linux/ipq806x/patches-4.9/861-qcom-mtd-nand-Added-bam-transaction-and-support-addi.patch
+++ /dev/null
@@ -1,1267 +0,0 @@
-From 645c7805f2602569263d7ac78050b2c9e91e3377 Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Thu, 20 Apr 2017 10:23:00 +0530
-Subject: [PATCH] qcom: mtd: nand: Added bam transaction and support
- additional CSRs
-
-This patch adds the following for NAND BAM DMA support
- - Bam transaction which will be used for any NAND request.
-    It contains the array of command elements, command and
-    data sgl. This transaction will be resetted before every
-    request.
- - Allocation function for NAND BAM transaction which will be
-    called only once at probe time.
- - Reset function for NAND BAM transaction which will be called
-    before any new NAND request.
- - Add support for additional CSRs.
-    NAND_READ_LOCATION - page offset for reading in BAM DMA mode
-    NAND_ERASED_CW_DETECT_CFG - status for erased code words
-    NAND_BUFFER_STATUS - status for ECC
-
-Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- drivers/mtd/nand/qcom_nandc.c    | 631 +++++++++++++++++++++++++++++++++++----
- include/linux/dma/qcom_bam_dma.h | 149 +++++++++
- 2 files changed, 721 insertions(+), 59 deletions(-)
- create mode 100644 include/linux/dma/qcom_bam_dma.h
-
---- a/drivers/mtd/nand/qcom_nandc.c
-+++ b/drivers/mtd/nand/qcom_nandc.c
-@@ -22,6 +22,7 @@
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/delay.h>
-+#include <linux/dma/qcom_bam_dma.h>
- 
- /* NANDc reg offsets */
- #define	NAND_FLASH_CMD			0x00
-@@ -53,6 +54,8 @@
- #define	NAND_VERSION			0xf08
- #define	NAND_READ_LOCATION_0		0xf20
- #define	NAND_READ_LOCATION_1		0xf24
-+#define	NAND_READ_LOCATION_2		0xf28
-+#define	NAND_READ_LOCATION_3		0xf2c
- 
- /* dummy register offsets, used by write_reg_dma */
- #define	NAND_DEV_CMD1_RESTORE		0xdead
-@@ -135,6 +138,11 @@
- #define	ERASED_PAGE			(PAGE_ALL_ERASED | PAGE_ERASED)
- #define	ERASED_CW			(CODEWORD_ALL_ERASED | CODEWORD_ERASED)
- 
-+/* NAND_READ_LOCATION_n bits */
-+#define READ_LOCATION_OFFSET           0
-+#define READ_LOCATION_SIZE             16
-+#define READ_LOCATION_LAST             31
-+
- /* Version Mask */
- #define	NAND_VERSION_MAJOR_MASK		0xf0000000
- #define	NAND_VERSION_MAJOR_SHIFT	28
-@@ -156,6 +164,9 @@
- #define NAND_DEV_CMD_VLD_VAL		(READ_START_VLD | WRITE_START_VLD | \
- 					 ERASE_START_VLD | SEQ_READ_START_VLD)
- 
-+/* NAND_CTRL bits */
-+#define        BAM_MODE_EN                     BIT(0)
-+
- /*
-  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
-  * the driver calls the chunks 'step' or 'codeword' interchangeably
-@@ -177,12 +188,77 @@
- #define	ECC_BCH_4BIT	BIT(2)
- #define	ECC_BCH_8BIT	BIT(3)
- 
-+/* Flags used for BAM DMA desc preparation*/
-+/* Don't set the EOT in current tx sgl */
-+#define DMA_DESC_FLAG_NO_EOT		(0x0001)
-+/* Set the NWD flag in current sgl */
-+#define DMA_DESC_FLAG_BAM_NWD		(0x0002)
-+/* Close current sgl and start writing in another sgl */
-+#define DMA_DESC_FLAG_BAM_NEXT_SGL	(0x0004)
-+/*
-+ * Erased codeword status is being used two times in single transfer so this
-+ * flag will determine the current value of erased codeword status register
-+ */
-+#define DMA_DESC_ERASED_CW_SET		(0x0008)
-+
-+/* Returns the dma address for reg read buffer */
-+#define REG_BUF_DMA_ADDR(chip, vaddr) \
-+	((chip)->reg_read_buf_phys + \
-+	((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
-+
-+/* Returns the nand register physical address */
-+#define NAND_REG_PHYS_ADDRESS(chip, addr) \
-+	((chip)->base_dma + (addr))
-+
-+/* command element array size in bam transaction */
-+#define BAM_CMD_ELEMENT_SIZE	(256)
-+/* command sgl size in bam transaction */
-+#define BAM_CMD_SGL_SIZE	(256)
-+/* data sgl size in bam transaction */
-+#define BAM_DATA_SGL_SIZE	(128)
-+
-+/*
-+ * This data type corresponds to the BAM transaction which will be used for any
-+ * nand request.
-+ * @bam_ce - the array of bam command elements
-+ * @cmd_sgl - sgl for nand bam command pipe
-+ * @tx_sgl - sgl for nand bam consumer pipe
-+ * @rx_sgl - sgl for nand bam producer pipe
-+ * @bam_ce_index - the index in bam_ce which is available for next sgl request
-+ * @pre_bam_ce_index - the index in bam_ce which marks the start position ce
-+ *                     for current sgl. It will be used for size calculation
-+ *                     for current sgl
-+ * @cmd_sgl_cnt - no of entries in command sgl.
-+ * @tx_sgl_cnt - no of entries in tx sgl.
-+ * @rx_sgl_cnt - no of entries in rx sgl.
-+ */
-+struct bam_transaction {
-+	struct bam_cmd_element bam_ce[BAM_CMD_ELEMENT_SIZE];
-+	struct qcom_bam_sgl cmd_sgl[BAM_CMD_SGL_SIZE];
-+	struct qcom_bam_sgl tx_sgl[BAM_DATA_SGL_SIZE];
-+	struct qcom_bam_sgl rx_sgl[BAM_DATA_SGL_SIZE];
-+	uint32_t bam_ce_index;
-+	uint32_t pre_bam_ce_index;
-+	uint32_t cmd_sgl_cnt;
-+	uint32_t tx_sgl_cnt;
-+	uint32_t rx_sgl_cnt;
-+};
-+
-+/**
-+ * This data type corresponds to the nand dma descriptor
-+ * @list - list for desc_info
-+ * @dir - DMA transfer direction
-+ * @sgl - sgl which will be used for single sgl dma descriptor
-+ * @dma_desc - low level dma engine descriptor
-+ * @bam_desc_data - used for bam desc mappings
-+ */
- struct desc_info {
- 	struct list_head node;
- 
- 	enum dma_data_direction dir;
- 	struct scatterlist sgl;
- 	struct dma_async_tx_descriptor *dma_desc;
-+	struct qcom_bam_custom_data bam_desc_data;
- };
- 
- /*
-@@ -210,6 +286,13 @@ struct nandc_regs {
- 	__le32 orig_vld;
- 
- 	__le32 ecc_buf_cfg;
-+	__le32 read_location0;
-+	__le32 read_location1;
-+	__le32 read_location2;
-+	__le32 read_location3;
-+
-+	__le32 erased_cw_detect_cfg_clr;
-+	__le32 erased_cw_detect_cfg_set;
- };
- 
- /*
-@@ -225,6 +308,7 @@ struct nandc_regs {
-  * @aon_clk:			another controller clock
-  *
-  * @chan:			dma channel
-+ * @bam_txn:                   contains the bam transaction address
-  * @cmd_crci:			ADM DMA CRCI for command flow control
-  * @data_crci:			ADM DMA CRCI for data flow control
-  * @desc_list:			DMA descriptor list (list of desc_infos)
-@@ -250,6 +334,7 @@ struct nandc_regs {
- struct qcom_nand_controller {
- 	struct nand_hw_control controller;
- 	struct list_head host_list;
-+	struct bam_transaction *bam_txn;
- 
- 	struct device *dev;
- 
-@@ -350,6 +435,45 @@ struct qcom_nand_driver_data {
- 	bool dma_bam_enabled;
- };
- 
-+/* Allocates and Initializes the BAM transaction */
-+struct bam_transaction *alloc_bam_transaction(
-+	struct qcom_nand_controller *nandc)
-+{
-+	struct bam_transaction *bam_txn;
-+
-+	bam_txn = kzalloc(sizeof(*bam_txn), GFP_KERNEL);
-+
-+	if (!bam_txn)
-+		return NULL;
-+
-+	bam_txn->bam_ce_index = 0;
-+	bam_txn->pre_bam_ce_index = 0;
-+	bam_txn->cmd_sgl_cnt = 0;
-+	bam_txn->tx_sgl_cnt = 0;
-+	bam_txn->rx_sgl_cnt = 0;
-+
-+	qcom_bam_sg_init_table(bam_txn->cmd_sgl, BAM_CMD_SGL_SIZE);
-+	qcom_bam_sg_init_table(bam_txn->tx_sgl, BAM_DATA_SGL_SIZE);
-+	qcom_bam_sg_init_table(bam_txn->rx_sgl, BAM_DATA_SGL_SIZE);
-+
-+	return bam_txn;
-+}
-+
-+/* Clears the BAM transaction index */
-+void clear_bam_transaction(struct qcom_nand_controller *nandc)
-+{
-+	struct bam_transaction *bam_txn = nandc->bam_txn;
-+
-+	if (!nandc->dma_bam_enabled)
-+		return;
-+
-+	bam_txn->bam_ce_index = 0;
-+	bam_txn->pre_bam_ce_index = 0;
-+	bam_txn->cmd_sgl_cnt = 0;
-+	bam_txn->tx_sgl_cnt = 0;
-+	bam_txn->rx_sgl_cnt = 0;
-+}
-+
- static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
- {
- 	return container_of(chip, struct qcom_nand_host, chip);
-@@ -406,6 +530,16 @@ static __le32 *offset_to_nandc_reg(struc
- 		return &regs->orig_vld;
- 	case NAND_EBI2_ECC_BUF_CFG:
- 		return &regs->ecc_buf_cfg;
-+	case NAND_BUFFER_STATUS:
-+		return &regs->clrreadstatus;
-+	case NAND_READ_LOCATION_0:
-+		return &regs->read_location0;
-+	case NAND_READ_LOCATION_1:
-+		return &regs->read_location1;
-+	case NAND_READ_LOCATION_2:
-+		return &regs->read_location2;
-+	case NAND_READ_LOCATION_3:
-+		return &regs->read_location3;
- 	default:
- 		return NULL;
- 	}
-@@ -447,7 +581,7 @@ static void update_rw_regs(struct qcom_n
- {
- 	struct nand_chip *chip = &host->chip;
- 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
--	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
-+	u32 cmd, cfg0, cfg1, ecc_bch_cfg, read_location0;
- 
- 	if (read) {
- 		if (host->use_ecc)
-@@ -464,12 +598,20 @@ static void update_rw_regs(struct qcom_n
- 
- 		cfg1 = host->cfg1;
- 		ecc_bch_cfg = host->ecc_bch_cfg;
-+		if (read)
-+			read_location0 = (0 << READ_LOCATION_OFFSET) |
-+				(host->cw_data << READ_LOCATION_SIZE) |
-+				(1 << READ_LOCATION_LAST);
- 	} else {
- 		cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) |
- 				(num_cw - 1) << CW_PER_PAGE;
- 
- 		cfg1 = host->cfg1_raw;
- 		ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
-+		if (read)
-+			read_location0 = (0 << READ_LOCATION_OFFSET) |
-+				(host->cw_size << READ_LOCATION_SIZE) |
-+				(1 << READ_LOCATION_LAST);
- 	}
- 
- 	nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
-@@ -480,8 +622,104 @@ static void update_rw_regs(struct qcom_n
- 	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
- 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
- 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
-+
-+	if (read)
-+		nandc_set_reg(nandc, NAND_READ_LOCATION_0, read_location0);
-+}
-+
-+/*
-+ * Prepares the command descriptor for BAM DMA which will be used for NAND
-+ * register read and write. The command descriptor requires the command
-+ * to be formed in command element type so this function uses the command
-+ * element from bam transaction ce array and fills the same with required
-+ * data. A single SGL can contain multiple command elements so
-+ * DMA_DESC_FLAG_BAM_NEXT_SGL will be used for starting the separate SGL
-+ * after the current command element.
-+ */
-+static int prep_dma_desc_command(struct qcom_nand_controller *nandc, bool read,
-+					int reg_off, const void *vaddr,
-+					int size, unsigned int flags)
-+{
-+	int bam_ce_size;
-+	int i;
-+	struct bam_cmd_element *bam_ce_buffer;
-+	struct bam_transaction *bam_txn = nandc->bam_txn;
-+
-+	bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_index];
-+
-+	/* fill the command desc */
-+	for (i = 0; i < size; i++) {
-+		if (read) {
-+			qcom_prep_bam_ce(&bam_ce_buffer[i],
-+				NAND_REG_PHYS_ADDRESS(nandc, reg_off + 4 * i),
-+				BAM_READ_COMMAND,
-+				REG_BUF_DMA_ADDR(nandc,
-+					(unsigned int *)vaddr + i));
-+		} else {
-+			qcom_prep_bam_ce(&bam_ce_buffer[i],
-+				NAND_REG_PHYS_ADDRESS(nandc, reg_off + 4 * i),
-+				BAM_WRITE_COMMAND,
-+				*((unsigned int *)vaddr + i));
-+		}
-+	}
-+
-+	/* use the separate sgl after this command */
-+	if (flags & DMA_DESC_FLAG_BAM_NEXT_SGL) {
-+		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->pre_bam_ce_index];
-+		bam_txn->bam_ce_index += size;
-+		bam_ce_size = (bam_txn->bam_ce_index -
-+				bam_txn->pre_bam_ce_index) *
-+				sizeof(struct bam_cmd_element);
-+		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_cnt].sgl,
-+				bam_ce_buffer,
-+				bam_ce_size);
-+		if (flags & DMA_DESC_FLAG_BAM_NWD)
-+			bam_txn->cmd_sgl[bam_txn->cmd_sgl_cnt].dma_flags =
-+				DESC_FLAG_NWD | DESC_FLAG_CMD;
-+		else
-+			bam_txn->cmd_sgl[bam_txn->cmd_sgl_cnt].dma_flags =
-+				DESC_FLAG_CMD;
-+
-+		bam_txn->cmd_sgl_cnt++;
-+		bam_txn->pre_bam_ce_index = bam_txn->bam_ce_index;
-+	} else {
-+		bam_txn->bam_ce_index += size;
-+	}
-+
-+	return 0;
- }
- 
-+/*
-+ * Prepares the data descriptor for BAM DMA which will be used for NAND
-+ * data read and write.
-+ */
-+static int prep_dma_desc_data_bam(struct qcom_nand_controller *nandc, bool read,
-+					int reg_off, const void *vaddr,
-+					int size, unsigned int flags)
-+{
-+	struct bam_transaction *bam_txn = nandc->bam_txn;
-+
-+	if (read) {
-+		sg_set_buf(&bam_txn->rx_sgl[bam_txn->rx_sgl_cnt].sgl,
-+				vaddr, size);
-+		bam_txn->rx_sgl[bam_txn->rx_sgl_cnt].dma_flags = 0;
-+		bam_txn->rx_sgl_cnt++;
-+	} else {
-+		sg_set_buf(&bam_txn->tx_sgl[bam_txn->tx_sgl_cnt].sgl,
-+				vaddr, size);
-+		if (flags & DMA_DESC_FLAG_NO_EOT)
-+			bam_txn->tx_sgl[bam_txn->tx_sgl_cnt].dma_flags = 0;
-+		else
-+			bam_txn->tx_sgl[bam_txn->tx_sgl_cnt].dma_flags =
-+				DESC_FLAG_EOT;
-+
-+		bam_txn->tx_sgl_cnt++;
-+	}
-+
-+	return 0;
-+}
-+
-+/* Prepares the dma desciptor for adm dma engine */
- static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
- 			 int reg_off, const void *vaddr, int size,
- 			 bool flow_control)
-@@ -560,7 +798,7 @@ err:
-  * @num_regs:		number of registers to read
-  */
- static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
--			int num_regs)
-+			int num_regs, unsigned int flags)
- {
- 	bool flow_control = false;
- 	void *vaddr;
-@@ -569,10 +807,18 @@ static int read_reg_dma(struct qcom_nand
- 	if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
- 		flow_control = true;
- 
--	size = num_regs * sizeof(u32);
- 	vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
- 	nandc->reg_read_pos += num_regs;
- 
-+	if (nandc->dma_bam_enabled) {
-+		size = num_regs;
-+
-+		return prep_dma_desc_command(nandc, true, first, vaddr, size,
-+						flags);
-+	}
-+
-+	size = num_regs * sizeof(u32);
-+
- 	return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
- }
- 
-@@ -584,7 +830,7 @@ static int read_reg_dma(struct qcom_nand
-  * @num_regs:		number of registers to write
-  */
- static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
--			 int num_regs)
-+			 int num_regs, unsigned int flags)
- {
- 	bool flow_control = false;
- 	struct nandc_regs *regs = nandc->regs;
-@@ -596,12 +842,29 @@ static int write_reg_dma(struct qcom_nan
- 	if (first == NAND_FLASH_CMD)
- 		flow_control = true;
- 
-+	if (first == NAND_ERASED_CW_DETECT_CFG) {
-+		if (flags & DMA_DESC_ERASED_CW_SET)
-+			vaddr = &regs->erased_cw_detect_cfg_set;
-+		else
-+			vaddr = &regs->erased_cw_detect_cfg_clr;
-+	}
-+
-+	if (first == NAND_EXEC_CMD)
-+		flags |= DMA_DESC_FLAG_BAM_NWD;
-+
- 	if (first == NAND_DEV_CMD1_RESTORE)
- 		first = NAND_DEV_CMD1;
- 
- 	if (first == NAND_DEV_CMD_VLD_RESTORE)
- 		first = NAND_DEV_CMD_VLD;
- 
-+	if (nandc->dma_bam_enabled) {
-+		size = num_regs;
-+
-+		return prep_dma_desc_command(nandc, false, first, vaddr, size,
-+						flags);
-+	}
-+
- 	size = num_regs * sizeof(u32);
- 
- 	return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
-@@ -616,8 +879,12 @@ static int write_reg_dma(struct qcom_nan
-  * @size:		DMA transaction size in bytes
-  */
- static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
--			 const u8 *vaddr, int size)
-+			 const u8 *vaddr, int size, unsigned int flags)
- {
-+	if (nandc->dma_bam_enabled)
-+		return prep_dma_desc_data_bam(nandc, true, reg_off, vaddr, size,
-+						flags);
-+
- 	return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
- }
- 
-@@ -630,8 +897,12 @@ static int read_data_dma(struct qcom_nan
-  * @size:		DMA transaction size in bytes
-  */
- static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
--			  const u8 *vaddr, int size)
-+			  const u8 *vaddr, int size, unsigned int flags)
- {
-+	if (nandc->dma_bam_enabled)
-+		return prep_dma_desc_data_bam(nandc, false, reg_off, vaddr,
-+							size, flags);
-+
- 	return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
- }
- 
-@@ -641,14 +912,57 @@ static int write_data_dma(struct qcom_na
-  */
- static void config_cw_read(struct qcom_nand_controller *nandc)
- {
--	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
--	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
--	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
- 
--	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
-+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
-+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
-+
-+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
-+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
-+				DMA_DESC_ERASED_CW_SET);
-+	if (nandc->dma_bam_enabled)
-+		write_reg_dma(nandc, NAND_READ_LOCATION_0, 1,
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
--	read_reg_dma(nandc, NAND_FLASH_STATUS, 2);
--	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1);
-+
-+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NWD |
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
-+
-+	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
-+	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
-+}
-+
-+/*
-+ * Helpers to prepare DMA descriptors for configuring registers
-+ * before reading a NAND page with BAM.
-+ */
-+static void config_bam_page_read(struct qcom_nand_controller *nandc)
-+{
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
-+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
-+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
-+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
-+	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
-+				DMA_DESC_ERASED_CW_SET |
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
-+}
-+
-+/*
-+ * Helpers to prepare DMA descriptors for configuring registers
-+ * before reading each codeword in NAND page with BAM.
-+ */
-+static void config_bam_cw_read(struct qcom_nand_controller *nandc)
-+{
-+	if (nandc->dma_bam_enabled)
-+		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, 0);
-+
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+
-+	read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
-+	read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1,
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
- }
- 
- /*
-@@ -657,19 +971,20 @@ static void config_cw_read(struct qcom_n
-  */
- static void config_cw_write_pre(struct qcom_nand_controller *nandc)
- {
--	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
--	write_reg_dma(nandc, NAND_DEV0_CFG0, 3);
--	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1);
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, 0);
-+	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
-+	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
- }
- 
- static void config_cw_write_post(struct qcom_nand_controller *nandc)
- {
--	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
-+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
--	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
-+	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
--	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
--	write_reg_dma(nandc, NAND_READ_STATUS, 1);
-+	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
-+	write_reg_dma(nandc, NAND_READ_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- }
- 
- /*
-@@ -683,6 +998,8 @@ static int nandc_param(struct qcom_nand_
- 	struct nand_chip *chip = &host->chip;
- 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- 
-+	clear_bam_transaction(nandc);
-+
- 	/*
- 	 * NAND_CMD_PARAM is called before we know much about the FLASH chip
- 	 * in use. we configure the controller to perform a raw read of 512
-@@ -715,9 +1032,13 @@ static int nandc_param(struct qcom_nand_
- 
- 	nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
- 	nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
-+	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
-+				(0 << READ_LOCATION_OFFSET) |
-+				(512 << READ_LOCATION_SIZE) |
-+				(1 << READ_LOCATION_LAST));
- 
--	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1);
--	write_reg_dma(nandc, NAND_DEV_CMD1, 1);
-+	write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
-+	write_reg_dma(nandc, NAND_DEV_CMD1, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
- 	nandc->buf_count = 512;
- 	memset(nandc->data_buffer, 0xff, nandc->buf_count);
-@@ -725,11 +1046,12 @@ static int nandc_param(struct qcom_nand_
- 	config_cw_read(nandc);
- 
- 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
--		      nandc->buf_count);
-+		      nandc->buf_count, 0);
- 
- 	/* restore CMD1 and VLD regs */
--	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1);
--	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1);
-+	write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0);
-+	write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1,
-+				DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
- 	return 0;
- }
-@@ -740,6 +1062,8 @@ static int erase_block(struct qcom_nand_
- 	struct nand_chip *chip = &host->chip;
- 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- 
-+	clear_bam_transaction(nandc);
-+
- 	nandc_set_reg(nandc, NAND_FLASH_CMD,
- 		      BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
- 	nandc_set_reg(nandc, NAND_ADDR0, page_addr);
-@@ -751,14 +1075,15 @@ static int erase_block(struct qcom_nand_
- 	nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
- 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
- 
--	write_reg_dma(nandc, NAND_FLASH_CMD, 3);
--	write_reg_dma(nandc, NAND_DEV0_CFG0, 2);
--	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
- 
--	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 3, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+	write_reg_dma(nandc, NAND_DEV0_CFG0, 2, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+
-+	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
--	write_reg_dma(nandc, NAND_FLASH_STATUS, 1);
--	write_reg_dma(nandc, NAND_READ_STATUS, 1);
-+	write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0);
-+	write_reg_dma(nandc, NAND_READ_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
- 	return 0;
- }
-@@ -772,16 +1097,19 @@ static int read_id(struct qcom_nand_host
- 	if (column == -1)
- 		return 0;
- 
-+	clear_bam_transaction(nandc);
-+
- 	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
- 	nandc_set_reg(nandc, NAND_ADDR0, column);
- 	nandc_set_reg(nandc, NAND_ADDR1, 0);
--	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
-+	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
-+			nandc->dma_bam_enabled ? 0 : DM_EN);
- 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
- 
--	write_reg_dma(nandc, NAND_FLASH_CMD, 4);
--	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 4, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
--	read_reg_dma(nandc, NAND_READ_ID, 1);
-+	read_reg_dma(nandc, NAND_READ_ID, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
- 	return 0;
- }
-@@ -792,28 +1120,108 @@ static int reset(struct qcom_nand_host *
- 	struct nand_chip *chip = &host->chip;
- 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- 
-+	clear_bam_transaction(nandc);
-+
- 	nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
- 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
- 
--	write_reg_dma(nandc, NAND_FLASH_CMD, 1);
--	write_reg_dma(nandc, NAND_EXEC_CMD, 1);
-+	write_reg_dma(nandc, NAND_FLASH_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
-+	write_reg_dma(nandc, NAND_EXEC_CMD, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
--	read_reg_dma(nandc, NAND_FLASH_STATUS, 1);
-+	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, DMA_DESC_FLAG_BAM_NEXT_SGL);
- 
- 	return 0;
- }
- 
-+static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
-+				struct dma_chan *chan,
-+				struct qcom_bam_sgl *bam_sgl,
-+				int sgl_cnt,
-+				enum dma_transfer_direction direction)
-+{
-+	struct desc_info *desc;
-+	struct dma_async_tx_descriptor *dma_desc;
-+
-+	if (!qcom_bam_map_sg(nandc->dev, bam_sgl, sgl_cnt, direction)) {
-+		dev_err(nandc->dev, "failure in mapping sgl\n");
-+		return -ENOMEM;
-+	}
-+
-+	desc = kzalloc(sizeof(*desc), GFP_KERNEL);
-+	if (!desc) {
-+		qcom_bam_unmap_sg(nandc->dev, bam_sgl, sgl_cnt, direction);
-+		return -ENOMEM;
-+	}
-+
-+
-+	desc->bam_desc_data.dir = direction;
-+	desc->bam_desc_data.sgl_cnt = sgl_cnt;
-+	desc->bam_desc_data.bam_sgl = bam_sgl;
-+
-+	dma_desc = dmaengine_prep_dma_custom_mapping(chan,
-+			&desc->bam_desc_data,
-+			0);
-+
-+	if (!dma_desc) {
-+		dev_err(nandc->dev, "failure in cmd prep desc\n");
-+		qcom_bam_unmap_sg(nandc->dev, bam_sgl, sgl_cnt, direction);
-+		kfree(desc);
-+		return -EINVAL;
-+	}
-+
-+	desc->dma_desc = dma_desc;
-+
-+	list_add_tail(&desc->node, &nandc->desc_list);
-+
-+	return 0;
-+
-+}
-+
- /* helpers to submit/free our list of dma descriptors */
- static int submit_descs(struct qcom_nand_controller *nandc)
- {
- 	struct desc_info *desc;
- 	dma_cookie_t cookie = 0;
-+	struct bam_transaction *bam_txn = nandc->bam_txn;
-+	int r;
-+
-+	if (nandc->dma_bam_enabled) {
-+		if (bam_txn->rx_sgl_cnt) {
-+			r = prepare_bam_async_desc(nandc, nandc->rx_chan,
-+				bam_txn->rx_sgl, bam_txn->rx_sgl_cnt,
-+				DMA_DEV_TO_MEM);
-+			if (r)
-+				return r;
-+		}
-+
-+		if (bam_txn->tx_sgl_cnt) {
-+			r = prepare_bam_async_desc(nandc, nandc->tx_chan,
-+				bam_txn->tx_sgl, bam_txn->tx_sgl_cnt,
-+				DMA_MEM_TO_DEV);
-+			if (r)
-+				return r;
-+		}
-+
-+		r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
-+			bam_txn->cmd_sgl, bam_txn->cmd_sgl_cnt,
-+			DMA_MEM_TO_DEV);
-+		if (r)
-+			return r;
-+	}
- 
- 	list_for_each_entry(desc, &nandc->desc_list, node)
- 		cookie = dmaengine_submit(desc->dma_desc);
- 
--	if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
--		return -ETIMEDOUT;
-+	if (nandc->dma_bam_enabled) {
-+		dma_async_issue_pending(nandc->tx_chan);
-+		dma_async_issue_pending(nandc->rx_chan);
-+
-+		if (dma_sync_wait(nandc->cmd_chan, cookie) != DMA_COMPLETE)
-+			return -ETIMEDOUT;
-+	} else {
-+		if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
-+			return -ETIMEDOUT;
-+	}
- 
- 	return 0;
- }
-@@ -824,7 +1232,16 @@ static void free_descs(struct qcom_nand_
- 
- 	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
- 		list_del(&desc->node);
--		dma_unmap_sg(nandc->dev, &desc->sgl, 1, desc->dir);
-+
-+		if (nandc->dma_bam_enabled)
-+			qcom_bam_unmap_sg(nandc->dev,
-+				desc->bam_desc_data.bam_sgl,
-+				desc->bam_desc_data.sgl_cnt,
-+				desc->bam_desc_data.dir);
-+		else
-+			dma_unmap_sg(nandc->dev, &desc->sgl, 1,
-+				desc->dir);
-+
- 		kfree(desc);
- 	}
- }
-@@ -1135,6 +1552,9 @@ static int read_page_ecc(struct qcom_nan
- 	struct nand_ecc_ctrl *ecc = &chip->ecc;
- 	int i, ret;
- 
-+	if (nandc->dma_bam_enabled)
-+		config_bam_page_read(nandc);
-+
- 	/* queue cmd descs for each codeword */
- 	for (i = 0; i < ecc->steps; i++) {
- 		int data_size, oob_size;
-@@ -1148,11 +1568,36 @@ static int read_page_ecc(struct qcom_nan
- 			oob_size = host->ecc_bytes_hw + host->spare_bytes;
- 		}
- 
--		config_cw_read(nandc);
-+		if (nandc->dma_bam_enabled) {
-+			if (data_buf && oob_buf) {
-+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
-+					(0 << READ_LOCATION_OFFSET) |
-+					(data_size << READ_LOCATION_SIZE) |
-+					(0 << READ_LOCATION_LAST));
-+				nandc_set_reg(nandc, NAND_READ_LOCATION_1,
-+					(data_size << READ_LOCATION_OFFSET) |
-+					(oob_size << READ_LOCATION_SIZE) |
-+					(1 << READ_LOCATION_LAST));
-+			} else if (data_buf) {
-+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
-+					(0 << READ_LOCATION_OFFSET) |
-+					(data_size << READ_LOCATION_SIZE) |
-+					(1 << READ_LOCATION_LAST));
-+			} else {
-+				nandc_set_reg(nandc, NAND_READ_LOCATION_0,
-+					(data_size << READ_LOCATION_OFFSET) |
-+					(oob_size << READ_LOCATION_SIZE) |
-+					(1 << READ_LOCATION_LAST));
-+			}
-+
-+			config_bam_cw_read(nandc);
-+		} else {
-+			config_cw_read(nandc);
-+		}
- 
- 		if (data_buf)
- 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
--				      data_size);
-+				      data_size, 0);
- 
- 		/*
- 		 * when ecc is enabled, the controller doesn't read the real
-@@ -1168,7 +1613,7 @@ static int read_page_ecc(struct qcom_nan
- 				*oob_buf++ = 0xff;
- 
- 			read_data_dma(nandc, FLASH_BUF_ACC + data_size,
--				      oob_buf, oob_size);
-+				      oob_buf, oob_size, 0);
- 		}
- 
- 		if (data_buf)
-@@ -1207,10 +1652,14 @@ static int copy_last_cw(struct qcom_nand
- 
- 	set_address(host, host->cw_size * (ecc->steps - 1), page);
- 	update_rw_regs(host, 1, true);
-+	nandc_set_reg(nandc, NAND_READ_LOCATION_0,
-+			(0 << READ_LOCATION_OFFSET) |
-+			(size << READ_LOCATION_SIZE) |
-+			(1 << READ_LOCATION_LAST));
- 
- 	config_cw_read(nandc);
- 
--	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size);
-+	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
- 
- 	ret = submit_descs(nandc);
- 	if (ret)
-@@ -1233,6 +1682,7 @@ static int qcom_nandc_read_page(struct m
- 	data_buf = buf;
- 	oob_buf = oob_required ? chip->oob_poi : NULL;
- 
-+	clear_bam_transaction(nandc);
- 	ret = read_page_ecc(host, data_buf, oob_buf);
- 	if (ret) {
- 		dev_err(nandc->dev, "failure to read page\n");
-@@ -1252,13 +1702,19 @@ static int qcom_nandc_read_page_raw(stru
- 	u8 *data_buf, *oob_buf;
- 	struct nand_ecc_ctrl *ecc = &chip->ecc;
- 	int i, ret;
-+	int read_location;
- 
- 	data_buf = buf;
- 	oob_buf = chip->oob_poi;
- 
- 	host->use_ecc = false;
-+
-+	clear_bam_transaction(nandc);
- 	update_rw_regs(host, ecc->steps, true);
- 
-+	if (nandc->dma_bam_enabled)
-+		config_bam_page_read(nandc);
-+
- 	for (i = 0; i < ecc->steps; i++) {
- 		int data_size1, data_size2, oob_size1, oob_size2;
- 		int reg_off = FLASH_BUF_ACC;
-@@ -1276,21 +1732,49 @@ static int qcom_nandc_read_page_raw(stru
- 			oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
- 		}
- 
--		config_cw_read(nandc);
-+		if (nandc->dma_bam_enabled) {
-+			read_location = 0;
-+			nandc_set_reg(nandc, NAND_READ_LOCATION_0,
-+				(read_location << READ_LOCATION_OFFSET) |
-+				(data_size1 << READ_LOCATION_SIZE) |
-+				(0 << READ_LOCATION_LAST));
-+			read_location += data_size1;
-+
-+			nandc_set_reg(nandc, NAND_READ_LOCATION_1,
-+				(read_location << READ_LOCATION_OFFSET) |
-+				(oob_size1 << READ_LOCATION_SIZE) |
-+				(0 << READ_LOCATION_LAST));
-+			read_location += oob_size1;
-+
-+			nandc_set_reg(nandc, NAND_READ_LOCATION_2,
-+				(read_location << READ_LOCATION_OFFSET) |
-+				(data_size2 << READ_LOCATION_SIZE) |
-+				(0 << READ_LOCATION_LAST));
-+			read_location += data_size2;
-+
-+			nandc_set_reg(nandc, NAND_READ_LOCATION_3,
-+				(read_location << READ_LOCATION_OFFSET) |
-+				(oob_size2 << READ_LOCATION_SIZE) |
-+				(1 << READ_LOCATION_LAST));
-+
-+			config_bam_cw_read(nandc);
-+		} else {
-+			config_cw_read(nandc);
-+		}
- 
--		read_data_dma(nandc, reg_off, data_buf, data_size1);
-+		read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
- 		reg_off += data_size1;
- 		data_buf += data_size1;
- 
--		read_data_dma(nandc, reg_off, oob_buf, oob_size1);
-+		read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0);
- 		reg_off += oob_size1;
- 		oob_buf += oob_size1;
- 
--		read_data_dma(nandc, reg_off, data_buf, data_size2);
-+		read_data_dma(nandc, reg_off, data_buf, data_size2, 0);
- 		reg_off += data_size2;
- 		data_buf += data_size2;
- 
--		read_data_dma(nandc, reg_off, oob_buf, oob_size2);
-+		read_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
- 		oob_buf += oob_size2;
- 	}
- 
-@@ -1313,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mt
- 	int ret;
- 
- 	clear_read_regs(nandc);
-+	clear_bam_transaction(nandc);
- 
- 	host->use_ecc = true;
- 	set_address(host, 0, page);
-@@ -1336,6 +1821,7 @@ static int qcom_nandc_write_page(struct
- 	int i, ret;
- 
- 	clear_read_regs(nandc);
-+	clear_bam_transaction(nandc);
- 
- 	data_buf = (u8 *)buf;
- 	oob_buf = chip->oob_poi;
-@@ -1357,7 +1843,8 @@ static int qcom_nandc_write_page(struct
- 
- 		config_cw_write_pre(nandc);
- 
--		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size);
-+		write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size,
-+				i == (ecc->steps - 1) ? DMA_DESC_FLAG_NO_EOT : 0);
- 
- 		/*
- 		 * when ECC is enabled, we don't really need to write anything
-@@ -1370,7 +1857,7 @@ static int qcom_nandc_write_page(struct
- 			oob_buf += host->bbm_size;
- 
- 			write_data_dma(nandc, FLASH_BUF_ACC + data_size,
--				       oob_buf, oob_size);
-+				       oob_buf, oob_size, 0);
- 		}
- 
- 		config_cw_write_post(nandc);
-@@ -1400,6 +1887,7 @@ static int qcom_nandc_write_page_raw(str
- 	int i, ret;
- 
- 	clear_read_regs(nandc);
-+	clear_bam_transaction(nandc);
- 
- 	data_buf = (u8 *)buf;
- 	oob_buf = chip->oob_poi;
-@@ -1426,19 +1914,22 @@ static int qcom_nandc_write_page_raw(str
- 
- 		config_cw_write_pre(nandc);
- 
--		write_data_dma(nandc, reg_off, data_buf, data_size1);
-+		write_data_dma(nandc, reg_off, data_buf, data_size1,
-+					DMA_DESC_FLAG_NO_EOT);
- 		reg_off += data_size1;
- 		data_buf += data_size1;
- 
--		write_data_dma(nandc, reg_off, oob_buf, oob_size1);
-+		write_data_dma(nandc, reg_off, oob_buf, oob_size1,
-+					DMA_DESC_FLAG_NO_EOT);
- 		reg_off += oob_size1;
- 		oob_buf += oob_size1;
- 
--		write_data_dma(nandc, reg_off, data_buf, data_size2);
-+		write_data_dma(nandc, reg_off, data_buf, data_size2,
-+					DMA_DESC_FLAG_NO_EOT);
- 		reg_off += data_size2;
- 		data_buf += data_size2;
- 
--		write_data_dma(nandc, reg_off, oob_buf, oob_size2);
-+		write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0);
- 		oob_buf += oob_size2;
- 
- 		config_cw_write_post(nandc);
-@@ -1474,6 +1965,7 @@ static int qcom_nandc_write_oob(struct m
- 
- 	host->use_ecc = true;
- 
-+	clear_bam_transaction(nandc);
- 	ret = copy_last_cw(host, page);
- 	if (ret)
- 		return ret;
-@@ -1493,7 +1985,7 @@ static int qcom_nandc_write_oob(struct m
- 
- 	config_cw_write_pre(nandc);
- 	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
--		       data_size + oob_size);
-+		       data_size + oob_size, 0);
- 	config_cw_write_post(nandc);
- 
- 	ret = submit_descs(nandc);
-@@ -1531,6 +2023,7 @@ static int qcom_nandc_block_bad(struct m
- 	 */
- 	host->use_ecc = false;
- 
-+	clear_bam_transaction(nandc);
- 	ret = copy_last_cw(host, page);
- 	if (ret)
- 		goto err;
-@@ -1561,6 +2054,7 @@ static int qcom_nandc_block_markbad(stru
- 	int page, ret, status = 0;
- 
- 	clear_read_regs(nandc);
-+	clear_bam_transaction(nandc);
- 
- 	/*
- 	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
-@@ -1577,7 +2071,8 @@ static int qcom_nandc_block_markbad(stru
- 	update_rw_regs(host, 1, false);
- 
- 	config_cw_write_pre(nandc);
--	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, host->cw_size);
-+	write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
-+				host->cw_size, 0);
- 	config_cw_write_post(nandc);
- 
- 	ret = submit_descs(nandc);
-@@ -1937,6 +2432,8 @@ static int qcom_nand_host_setup(struct q
- 
- 	host->clrflashstatus = FS_READY_BSY_N;
- 	host->clrreadstatus = 0xc0;
-+	nandc->regs->erased_cw_detect_cfg_clr = CLR_ERASED_PAGE_DET;
-+	nandc->regs->erased_cw_detect_cfg_set = SET_ERASED_PAGE_DET;
- 
- 	dev_dbg(nandc->dev,
- 		"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
-@@ -2015,6 +2512,12 @@ static int qcom_nandc_alloc(struct qcom_
- 			dev_err(nandc->dev, "failed to request cmd channel\n");
- 			return -ENODEV;
- 		}
-+
-+		nandc->bam_txn = alloc_bam_transaction(nandc);
-+		if (!nandc->bam_txn) {
-+			dev_err(nandc->dev, "failed to allocate bam transaction\n");
-+			return -ENOMEM;
-+		}
- 	}
- 
- 	INIT_LIST_HEAD(&nandc->desc_list);
-@@ -2050,6 +2553,9 @@ static void qcom_nandc_unalloc(struct qc
- 			devm_kfree(nandc->dev, nandc->reg_read_buf);
- 	}
- 
-+	if (nandc->bam_txn)
-+		devm_kfree(nandc->dev, nandc->bam_txn);
-+
- 	if (nandc->regs)
- 		devm_kfree(nandc->dev, nandc->regs);
- 
-@@ -2060,12 +2566,19 @@ static void qcom_nandc_unalloc(struct qc
- /* one time setup of a few nand controller registers */
- static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
- {
-+	u32 nand_ctrl;
-+
- 	/* kill onenand */
- 	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
- 	nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
- 
--	/* enable ADM DMA */
--	nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
-+	/* enable ADM or BAM DMA */
-+	if (!nandc->dma_bam_enabled) {
-+		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
-+	} else {
-+		nand_ctrl = nandc_read(nandc, NAND_CTRL);
-+		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
-+	}
- 
- 	/* save the original values of these registers */
- 	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
---- /dev/null
-+++ b/include/linux/dma/qcom_bam_dma.h
-@@ -0,0 +1,149 @@
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#ifndef _QCOM_BAM_DMA_H
-+#define _QCOM_BAM_DMA_H
-+
-+#include <linux/dma-mapping.h>
-+
-+#define DESC_FLAG_INT BIT(15)
-+#define DESC_FLAG_EOT BIT(14)
-+#define DESC_FLAG_EOB BIT(13)
-+#define DESC_FLAG_NWD BIT(12)
-+#define DESC_FLAG_CMD BIT(11)
-+
-+/*
-+ * QCOM BAM DMA SGL struct
-+ *
-+ * @sgl: DMA SGL
-+ * @dma_flags: BAM DMA flags
-+ */
-+struct qcom_bam_sgl {
-+	struct scatterlist sgl;
-+	unsigned int dma_flags;
-+};
-+
-+/*
-+ * This data type corresponds to the native Command Element
-+ * supported by BAM DMA Engine.
-+ *
-+ * @addr - register address.
-+ * @command - command type.
-+ * @data - for write command: content to be written into peripheral register.
-+ *	 for read command: dest addr to write peripheral register value to.
-+ * @mask - register mask.
-+ * @reserved - for future usage.
-+ *
-+ */
-+struct bam_cmd_element {
-+	__le32 addr:24;
-+	__le32 command:8;
-+	__le32 data;
-+	__le32 mask;
-+	__le32 reserved;
-+};
-+
-+/*
-+ * This enum indicates the command type in a command element
-+ */
-+enum bam_command_type {
-+	BAM_WRITE_COMMAND = 0,
-+	BAM_READ_COMMAND,
-+};
-+
-+/*
-+ * qcom_bam_sg_init_table - Init QCOM BAM SGL
-+ * @bam_sgl: bam sgl
-+ * @nents: number of entries in bam sgl
-+ *
-+ * This function performs the initialization for each SGL in BAM SGL
-+ * with generic SGL API.
-+ */
-+static inline void qcom_bam_sg_init_table(struct qcom_bam_sgl *bam_sgl,
-+		unsigned int nents)
-+{
-+	int i;
-+
-+	for (i = 0; i < nents; i++)
-+		sg_init_table(&bam_sgl[i].sgl, 1);
-+}
-+
-+/*
-+ * qcom_bam_unmap_sg - Unmap QCOM BAM SGL
-+ * @dev: device for which unmapping needs to be done
-+ * @bam_sgl: bam sgl
-+ * @nents: number of entries in bam sgl
-+ * @dir: dma transfer direction
-+ *
-+ * This function performs the DMA unmapping for each SGL in BAM SGL
-+ * with generic SGL API.
-+ */
-+static inline void qcom_bam_unmap_sg(struct device *dev,
-+	struct qcom_bam_sgl *bam_sgl, int nents, enum dma_data_direction dir)
-+{
-+	int i;
-+
-+	for (i = 0; i < nents; i++)
-+		dma_unmap_sg(dev, &bam_sgl[i].sgl, 1, dir);
-+}
-+
-+/*
-+ * qcom_bam_map_sg - Map QCOM BAM SGL
-+ * @dev: device for which mapping needs to be done
-+ * @bam_sgl: bam sgl
-+ * @nents: number of entries in bam sgl
-+ * @dir: dma transfer direction
-+ *
-+ * This function performs the DMA mapping for each SGL in BAM SGL
-+ * with generic SGL API.
-+ *
-+ * returns 0 on error and > 0 on success
-+ */
-+static inline int qcom_bam_map_sg(struct device *dev,
-+	struct qcom_bam_sgl *bam_sgl, int nents, enum dma_data_direction dir)
-+{
-+	int i, ret = 0;
-+
-+	for (i = 0; i < nents; i++) {
-+		ret = dma_map_sg(dev, &bam_sgl[i].sgl, 1, dir);
-+		if (!ret)
-+			break;
-+	}
-+
-+	/* unmap the mapped sgl from previous loop in case of error */
-+	if (!ret)
-+		qcom_bam_unmap_sg(dev, bam_sgl, i, dir);
-+
-+	return ret;
-+}
-+
-+/*
-+ * qcom_prep_bam_ce - Wrapper function to prepare a single BAM command element
-+ *	with the data that is passed to this function.
-+ * @bam_ce: bam command element
-+ * @addr: target address
-+ * @command: command in bam_command_type
-+ * @data: actual data for write and dest addr for read
-+ */
-+static inline void qcom_prep_bam_ce(struct bam_cmd_element *bam_ce,
-+				uint32_t addr, uint32_t command, uint32_t data)
-+{
-+	bam_ce->addr = cpu_to_le32(addr);
-+	bam_ce->command = cpu_to_le32(command);
-+	bam_ce->data = cpu_to_le32(data);
-+	bam_ce->mask = 0xFFFFFFFF;
-+}
-+#endif
diff --git a/target/linux/ipq806x/patches-4.9/862-dmaengine-qcom-bam_dma-Add-custom-data-mapping.patch b/target/linux/ipq806x/patches-4.9/862-dmaengine-qcom-bam_dma-Add-custom-data-mapping.patch
deleted file mode 100644
index 796938f2d0..0000000000
--- a/target/linux/ipq806x/patches-4.9/862-dmaengine-qcom-bam_dma-Add-custom-data-mapping.patch
+++ /dev/null
@@ -1,209 +0,0 @@
-From 5a7ccdf845d64b385affdcffaf2defbe9848be15 Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Thu, 20 Apr 2017 10:39:00 +0530
-Subject: [PATCH] dmaengine: qcom: bam_dma: Add custom data mapping
-
-Add a new function to support for preparing DMA descriptor
-for custom data.
-
-Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- drivers/dma/qcom/bam_dma.c       | 97 +++++++++++++++++++++++++++++++++++++---
- include/linux/dma/qcom_bam_dma.h | 14 ++++++
- include/linux/dmaengine.h        | 14 ++++++
- 3 files changed, 119 insertions(+), 6 deletions(-)
-
---- a/drivers/dma/qcom/bam_dma.c
-+++ b/drivers/dma/qcom/bam_dma.c
-@@ -49,6 +49,7 @@
- #include <linux/clk.h>
- #include <linux/dmaengine.h>
- #include <linux/pm_runtime.h>
-+#include <linux/dma/qcom_bam_dma.h>
- 
- #include "../dmaengine.h"
- #include "../virt-dma.h"
-@@ -61,11 +62,6 @@ struct bam_desc_hw {
- 
- #define BAM_DMA_AUTOSUSPEND_DELAY 100
- 
--#define DESC_FLAG_INT BIT(15)
--#define DESC_FLAG_EOT BIT(14)
--#define DESC_FLAG_EOB BIT(13)
--#define DESC_FLAG_NWD BIT(12)
--
- struct bam_async_desc {
- 	struct virt_dma_desc vd;
- 
-@@ -670,6 +666,93 @@ err_out:
- }
- 
- /**
-+ * bam_prep_dma_custom_mapping - Prep DMA descriptor from custom data
-+ *
-+ * @chan: dma channel
-+ * @data: custom data
-+ * @flags: DMA flags
-+ */
-+static struct dma_async_tx_descriptor *bam_prep_dma_custom_mapping(
-+		struct dma_chan *chan,
-+		void *data, unsigned long flags)
-+{
-+	struct bam_chan *bchan = to_bam_chan(chan);
-+	struct bam_device *bdev = bchan->bdev;
-+	struct bam_async_desc *async_desc;
-+	struct qcom_bam_custom_data *desc_data = data;
-+	u32 i;
-+	struct bam_desc_hw *desc;
-+	unsigned int num_alloc = 0;
-+
-+
-+	if (!is_slave_direction(desc_data->dir)) {
-+		dev_err(bdev->dev, "invalid dma direction\n");
-+		return NULL;
-+	}
-+
-+	/* calculate number of required entries */
-+	for (i = 0; i < desc_data->sgl_cnt; i++)
-+		num_alloc += DIV_ROUND_UP(
-+			sg_dma_len(&desc_data->bam_sgl[i].sgl), BAM_FIFO_SIZE);
-+
-+	/* allocate enough room to accommodate the number of entries */
-+	async_desc = kzalloc(sizeof(*async_desc) +
-+			(num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
-+
-+	if (!async_desc)
-+		goto err_out;
-+
-+	if (flags & DMA_PREP_FENCE)
-+		async_desc->flags |= DESC_FLAG_NWD;
-+
-+	if (flags & DMA_PREP_INTERRUPT)
-+		async_desc->flags |= DESC_FLAG_EOT;
-+	else
-+		async_desc->flags |= DESC_FLAG_INT;
-+
-+	async_desc->num_desc = num_alloc;
-+	async_desc->curr_desc = async_desc->desc;
-+	async_desc->dir = desc_data->dir;
-+
-+	/* fill in temporary descriptors */
-+	desc = async_desc->desc;
-+	for (i = 0; i < desc_data->sgl_cnt; i++) {
-+		unsigned int remainder;
-+		unsigned int curr_offset = 0;
-+
-+		remainder = sg_dma_len(&desc_data->bam_sgl[i].sgl);
-+
-+		do {
-+			desc->addr = cpu_to_le32(
-+				sg_dma_address(&desc_data->bam_sgl[i].sgl) +
-+						 curr_offset);
-+
-+			if (desc_data->bam_sgl[i].dma_flags)
-+				desc->flags |= cpu_to_le16(
-+					desc_data->bam_sgl[i].dma_flags);
-+
-+			if (remainder > BAM_FIFO_SIZE) {
-+				desc->size = cpu_to_le16(BAM_FIFO_SIZE);
-+				remainder -= BAM_FIFO_SIZE;
-+				curr_offset += BAM_FIFO_SIZE;
-+			} else {
-+				desc->size = cpu_to_le16(remainder);
-+				remainder = 0;
-+			}
-+
-+			async_desc->length += desc->size;
-+			desc++;
-+		} while (remainder > 0);
-+	}
-+
-+	return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
-+
-+err_out:
-+	kfree(async_desc);
-+	return NULL;
-+}
-+
-+/**
-  * bam_dma_terminate_all - terminate all transactions on a channel
-  * @bchan: bam dma channel
-  *
-@@ -960,7 +1043,7 @@ static void bam_start_dma(struct bam_cha
- 
- 	/* set any special flags on the last descriptor */
- 	if (async_desc->num_desc == async_desc->xfer_len)
--		desc[async_desc->xfer_len - 1].flags =
-+		desc[async_desc->xfer_len - 1].flags |=
- 					cpu_to_le16(async_desc->flags);
- 	else
- 		desc[async_desc->xfer_len - 1].flags |=
-@@ -1237,6 +1320,8 @@ static int bam_dma_probe(struct platform
- 	bdev->common.device_alloc_chan_resources = bam_alloc_chan;
- 	bdev->common.device_free_chan_resources = bam_free_chan;
- 	bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
-+	bdev->common.device_prep_dma_custom_mapping =
-+		bam_prep_dma_custom_mapping;
- 	bdev->common.device_config = bam_slave_config;
- 	bdev->common.device_pause = bam_pause;
- 	bdev->common.device_resume = bam_resume;
---- a/include/linux/dma/qcom_bam_dma.h
-+++ b/include/linux/dma/qcom_bam_dma.h
-@@ -65,6 +65,19 @@ enum bam_command_type {
- };
- 
- /*
-+ * QCOM BAM DMA custom data
-+ *
-+ * @sgl_cnt: number of sgl in bam_sgl
-+ * @dir: DMA data transfer direction
-+ * @bam_sgl: BAM SGL pointer
-+ */
-+struct qcom_bam_custom_data {
-+	u32 sgl_cnt;
-+	enum dma_transfer_direction dir;
-+	struct qcom_bam_sgl *bam_sgl;
-+};
-+
-+/*
-  * qcom_bam_sg_init_table - Init QCOM BAM SGL
-  * @bam_sgl: bam sgl
-  * @nents: number of entries in bam sgl
---- a/include/linux/dmaengine.h
-+++ b/include/linux/dmaengine.h
-@@ -692,6 +692,8 @@ struct dma_filter {
-  *	be called after period_len bytes have been transferred.
-  * @device_prep_interleaved_dma: Transfer expression in a generic way.
-  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
-+ * @device_prep_dma_custom_mapping: prepares a dma operation from dma driver
-+ * 	specific custom data
-  * @device_config: Pushes a new configuration to a channel, return 0 or an error
-  *	code
-  * @device_pause: Pauses any transfer happening on a channel. Returns
-@@ -783,6 +785,9 @@ struct dma_device {
- 	struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
- 		struct dma_chan *chan, dma_addr_t dst, u64 data,
- 		unsigned long flags);
-+	struct dma_async_tx_descriptor *(*device_prep_dma_custom_mapping)(
-+		struct dma_chan *chan, void *data,
-+		unsigned long flags);
- 
- 	int (*device_config)(struct dma_chan *chan,
- 			     struct dma_slave_config *config);
-@@ -899,6 +904,15 @@ static inline struct dma_async_tx_descri
- 			src_sg, src_nents, flags);
- }
- 
-+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_custom_mapping(
-+		struct dma_chan *chan,
-+		void *data,
-+		unsigned long flags)
-+{
-+	return chan->device->device_prep_dma_custom_mapping(chan, data,
-+			flags);
-+}
-+
- /**
-  * dmaengine_terminate_all() - Terminate all active DMA transfers
-  * @chan: The channel for which to terminate the transfers
diff --git a/target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch b/target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch
deleted file mode 100644
index f054927e03..0000000000
--- a/target/linux/ipq806x/patches-4.9/863-dts-ipq4019-add-nand-and-qpic-bam-dma-node.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From 02bbf3c46e1e38e9ca699143566903683e3a015d Mon Sep 17 00:00:00 2001
-From: Ram Chandra Jangir <rjangir@codeaurora.org>
-Date: Thu, 20 Apr 2017 10:45:00 +0530
-Subject: [PATCH] dts: ipq4019: add nand and qpic bam dma node
-
-This change adds QPIC BAM dma and NAND driver node's in
-IPQ4019 device tree, also enable this for AP-DK04.1 based
-boards.
-
-Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 75 +++++++++++++++++++++++++++
- arch/arm/boot/dts/qcom-ipq4019.dtsi           | 38 ++++++++++++++
- 2 files changed, 113 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-@@ -88,6 +88,86 @@
- 					bias-disable;
- 				};
- 			};
-+
-+			nand_pins: nand_pins {
-+
-+				 mux_1 {
-+					 pins = "gpio52", "gpio53", "gpio54",
-+						"gpio55", "gpio56", "gpio61",
-+						"gpio62", "gpio63", "gpio69";
-+					 function = "qpic_pad";
-+					 bias-disable;
-+				 };
-+
-+				mux_2 {
-+					pins = "gpio67";
-+					function = "qpic_pad0";
-+					bias-disable;
-+				};
-+
-+				mux_3 {
-+					pins = "gpio64";
-+					function = "qpic_pad1";
-+					bias-disable;
-+				};
-+
-+				mux_4 {
-+					pins = "gpio65";
-+					function = "qpic_pad2";
-+					bias-disable;
-+				};
-+
-+				mux_5 {
-+					pins = "gpio66";
-+					function = "qpic_pad3";
-+					bias-disable;
-+				};
-+
-+				mux_6 {
-+					pins = "gpio57";
-+					function = "qpic_pad4";
-+					bias-disable;
-+				};
-+
-+				mux_7 {
-+					pins = "gpio58";
-+					function = "qpic_pad5";
-+					bias-disable;
-+				};
-+
-+				mux_8 {
-+					pins = "gpio59";
-+					function = "qpic_pad6";
-+					bias-disable;
-+				};
-+
-+				mux_9 {
-+					pins = "gpio60";
-+					function = "qpic_pad7";
-+					bias-disable;
-+				};
-+
-+				mux_10 {
-+					pins = "gpio68";
-+					function = "qpic_pad8";
-+					bias-disable;
-+				};
-+
-+				pullups {
-+					pins = "gpio52", "gpio53", "gpio58",
-+						"gpio59";
-+					bias-pull-up;
-+				};
-+
-+				pulldowns {
-+					pins = "gpio54", "gpio55", "gpio56",
-+						"gpio57", "gpio60", "gpio61",
-+						"gpio62", "gpio63", "gpio64",
-+						"gpio65", "gpio66", "gpio67",
-+						"gpio68", "gpio69";
-+					bias-pull-down;
-+				};
-+			};
- 		};
- 
- 		blsp_dma: dma@7884000 {
-@@ -159,5 +239,15 @@
- 		watchdog@b017000 {
- 			status = "ok";
- 		};
-+
-+		qpic_bam: dma@7984000 {
-+			status = "ok";
-+		};
-+
-+		nand: qpic-nand@79b0000 {
-+			pinctrl-0 = <&nand_pins>;
-+			pinctrl-names = "default";
-+			status = "ok";
-+		};
- 	};
- };
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -580,5 +580,43 @@
- 					  "legacy";
- 			status = "disabled";
- 		};
-+
-+		qpic_bam: dma@7984000 {
-+			compatible = "qcom,bam-v1.7.0";
-+			reg = <0x7984000 0x1a000>;
-+			interrupts = <0 101 0>;
-+			clocks = <&gcc GCC_QPIC_AHB_CLK>;
-+			clock-names = "bam_clk";
-+			#dma-cells = <1>;
-+			qcom,ee = <0>;
-+			status = "disabled";
-+		};
-+
-+		nand: qpic-nand@79b0000 {
-+			compatible = "qcom,ebi2-nandc-bam", "qcom,msm-nand";
-+			reg = <0x79b0000 0x1000>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			clocks = <&gcc GCC_QPIC_CLK>,
-+				<&gcc GCC_QPIC_AHB_CLK>;
-+			clock-names = "core", "aon";
-+
-+			dmas = <&qpic_bam 0>,
-+				<&qpic_bam 1>,
-+				<&qpic_bam 2>;
-+			dma-names = "tx", "rx", "cmd";
-+			status = "disabled";
-+
-+			nandcs@0 {
-+				compatible = "qcom,nandcs";
-+				reg = <0>;
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+
-+				nand-ecc-strength = <4>;
-+				nand-ecc-step-size = <512>;
-+				nand-bus-width = <8>;
-+			};
-+		};
- 	};
- };
diff --git a/target/linux/ipq806x/patches-4.9/864-00-v3-1-2-dts-ipq4019-Fix-pinctrl-node-name.patch b/target/linux/ipq806x/patches-4.9/864-00-v3-1-2-dts-ipq4019-Fix-pinctrl-node-name.patch
deleted file mode 100644
index dbd5537f88..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-00-v3-1-2-dts-ipq4019-Fix-pinctrl-node-name.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From patchwork Mon Jul  3 07:47:12 2017
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [v3,1/2] dts: ipq4019: Fix pinctrl node name
-From: Varadarajan Narayanan <varada@codeaurora.org>
-X-Patchwork-Id: 9822099
-Message-Id: <1499068033-24000-2-git-send-email-varada@codeaurora.org>
-To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
- mark.rutland@arm.com, linux@armlinux.org.uk,
- linux-arm-msm@vger.kernel.org, 
- linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
-Cc: Varadarajan Narayanan <varada@codeaurora.org>
-Date: Mon,  3 Jul 2017 13:17:12 +0530
-
-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
- arch/arm/boot/dts/qcom-ipq4019.dtsi           | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -40,7 +40,7 @@
- 			clock-frequency = <48000000>;
- 		};
- 
--		pinctrl@0x01000000 {
-+		pinctrl@1000000 {
- 			serial_pins: serial_pinmux {
- 				mux {
- 					pins = "gpio60", "gpio61";
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -149,7 +149,7 @@
- 			reg = <0x1800000 0x60000>;
- 		};
- 
--		tlmm: pinctrl@0x01000000 {
-+		tlmm: pinctrl@1000000 {
- 			compatible = "qcom,ipq4019-pinctrl";
- 			reg = <0x01000000 0x300000>;
- 			gpio-controller;
diff --git a/target/linux/ipq806x/patches-4.9/864-00-v3-2-2-dts-ipq4019-Move-xo-and-timer-nodes-to-SoC-dtsi.patch b/target/linux/ipq806x/patches-4.9/864-00-v3-2-2-dts-ipq4019-Move-xo-and-timer-nodes-to-SoC-dtsi.patch
deleted file mode 100644
index 3e2c396111..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-00-v3-2-2-dts-ipq4019-Move-xo-and-timer-nodes-to-SoC-dtsi.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From patchwork Mon Jul  3 07:47:13 2017
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-Subject: [v3,2/2] dts: ipq4019: Move xo and timer nodes to SoC dtsi
-From: Varadarajan Narayanan <varada@codeaurora.org>
-X-Patchwork-Id: 9822107
-Message-Id: <1499068033-24000-3-git-send-email-varada@codeaurora.org>
-To: andy.gross@linaro.org, david.brown@linaro.org, robh+dt@kernel.org,
- mark.rutland@arm.com, linux@armlinux.org.uk,
- linux-arm-msm@vger.kernel.org, 
- linux-soc@vger.kernel.org, devicetree@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
-Cc: Varadarajan Narayanan <varada@codeaurora.org>
-Date: Mon,  3 Jul 2017 13:17:13 +0530
-
-The node for xo and timer belong to the SoC DTS file.
-Else, new board DT files may not inherit these nodes.
-
-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
----
- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 19 -------------------
- arch/arm/boot/dts/qcom-ipq4019.dtsi           | 15 +++++++++++++++
- 2 files changed, 15 insertions(+), 19 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -20,26 +20,7 @@
- 	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
- 	compatible = "qcom,ipq4019";
- 
--	clocks {
--                xo: xo {
--                        compatible = "fixed-clock";
--                        clock-frequency = <48000000>;
--                        #clock-cells = <0>;
--                };
--	};
--
- 	soc {
--
--
--		timer {
--			compatible = "arm,armv7-timer";
--			interrupts = <1 2 0xf08>,
--				     <1 3 0xf08>,
--				     <1 4 0xf08>,
--				     <1 1 0xf08>;
--			clock-frequency = <48000000>;
--		};
--
- 		pinctrl@1000000 {
- 			serial_pins: serial_pinmux {
- 				mux {
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -126,6 +126,21 @@
- 			clock-frequency = <32768>;
- 			#clock-cells = <0>;
- 		};
-+
-+		xo: xo {
-+			compatible = "fixed-clock";
-+			clock-frequency = <48000000>;
-+			#clock-cells = <0>;
-+		};
-+	};
-+
-+	timer {
-+		compatible = "arm,armv7-timer";
-+		interrupts = <1 2 0xf08>,
-+			     <1 3 0xf08>,
-+			     <1 4 0xf08>,
-+			     <1 1 0xf08>;
-+		clock-frequency = <48000000>;
- 	};
- 
- 	soc {
diff --git a/target/linux/ipq806x/patches-4.9/864-01-dts-ipq4019-ap-dk04-fix-pinctrl-node-name.patch b/target/linux/ipq806x/patches-4.9/864-01-dts-ipq4019-ap-dk04-fix-pinctrl-node-name.patch
deleted file mode 100644
index f2de6d618a..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-01-dts-ipq4019-ap-dk04-fix-pinctrl-node-name.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-@@ -38,7 +38,7 @@
- 			clock-frequency = <48000000>;
- 		};
- 
--		pinctrl@0x01000000 {
-+		pinctrl@1000000 {
- 			serial_0_pins: serial_pinmux {
- 				mux {
- 					pins = "gpio16", "gpio17";
diff --git a/target/linux/ipq806x/patches-4.9/864-02-dts-ipq4019-ap-dk04-remove-xo-and-timer-nodes.patch b/target/linux/ipq806x/patches-4.9/864-02-dts-ipq4019-ap-dk04-remove-xo-and-timer-nodes.patch
deleted file mode 100644
index dcbdb8d777..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-02-dts-ipq4019-ap-dk04-remove-xo-and-timer-nodes.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
-@@ -20,24 +20,7 @@
- 	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
- 	compatible = "qcom,ipq4019";
- 
--	clocks {
--                xo: xo {
--                        compatible = "fixed-clock";
--                        clock-frequency = <48000000>;
--                        #clock-cells = <0>;
--                };
--	};
--
- 	soc {
--		timer {
--			compatible = "arm,armv7-timer";
--			interrupts = <1 2 0xf08>,
--				     <1 3 0xf08>,
--				     <1 4 0xf08>,
--				     <1 1 0xf08>;
--			clock-frequency = <48000000>;
--		};
--
- 		pinctrl@1000000 {
- 			serial_0_pins: serial_pinmux {
- 				mux {
diff --git a/target/linux/ipq806x/patches-4.9/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch b/target/linux/ipq806x/patches-4.9/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch
deleted file mode 100644
index 9d11dc022e..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-03-dts-ipq4019-ap-dk01-add-tcsr-config-to-dtsi.patch
+++ /dev/null
@@ -1,42 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -15,12 +15,39 @@
-  */
- 
- #include "qcom-ipq4019.dtsi"
-+#include <dt-bindings/soc/qcom,tcsr.h>
- 
- / {
- 	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
- 	compatible = "qcom,ipq4019";
- 
- 	soc {
-+		tcsr@194b000 {
-+			/* select hostmode */
-+			compatible = "qcom,tcsr";
-+			reg = <0x194b000 0x100>;
-+			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
-+			status = "ok";
-+		};
-+
-+		ess_tcsr@1953000 {
-+			compatible = "qcom,tcsr";
-+			reg = <0x1953000 0x1000>;
-+			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
-+		};
-+
-+		tcsr@1949000 {
-+			compatible = "qcom,tcsr";
-+			reg = <0x1949000 0x100>;
-+			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
-+		};
-+
-+		tcsr@1957000 {
-+			compatible = "qcom,tcsr";
-+			reg = <0x1957000 0x100>;
-+			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
-+		};
-+
- 		pinctrl@1000000 {
- 			serial_pins: serial_pinmux {
- 				mux {
diff --git a/target/linux/ipq806x/patches-4.9/864-04-dts-ipq4019-ap-dk01-add-network-nodes-to-dtsi.patch b/target/linux/ipq806x/patches-4.9/864-04-dts-ipq4019-ap-dk01-add-network-nodes-to-dtsi.patch
deleted file mode 100644
index 02a102e37f..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-04-dts-ipq4019-ap-dk01-add-network-nodes-to-dtsi.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -136,5 +136,29 @@
- 		usb2: usb2@60f8800 {
- 			status = "ok";
- 		};
-+
-+		mdio@90000 {
-+			status = "okay";
-+		};
-+
-+		ess-switch@c000000 {
-+			status = "okay";
-+		};
-+
-+		ess-psgmii@98000 {
-+			status = "okay";
-+		};
-+
-+		edma@c080000 {
-+			status = "okay";
-+		};
-+
-+		wifi@a000000 {
-+			status = "okay";
-+		};
-+
-+		wifi@a800000 {
-+			status = "okay";
-+		};
- 	};
- };
diff --git a/target/linux/ipq806x/patches-4.9/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch b/target/linux/ipq806x/patches-4.9/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch
deleted file mode 100644
index 0d4b80b302..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-05-dts-ipq4019-ap-dk01-remove-spi-chip-node-from-dtsi.patch
+++ /dev/null
@@ -1,17 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
-@@ -89,14 +89,6 @@
- 			pinctrl-names = "default";
- 			status = "ok";
- 			cs-gpios = <&tlmm 54 0>;
--
--			mx25l25635e@0 {
--				#address-cells = <1>;
--				#size-cells = <1>;
--				reg = <0>;
--				compatible = "mx25l25635e";
--				spi-max-frequency = <24000000>;
--			};
- 		};
- 
- 		serial@78af000 {
diff --git a/target/linux/ipq806x/patches-4.9/864-06-dts-ipq4019-fix-max-cpu-speed.patch b/target/linux/ipq806x/patches-4.9/864-06-dts-ipq4019-fix-max-cpu-speed.patch
deleted file mode 100644
index 33f7f04f3c..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-06-dts-ipq4019-fix-max-cpu-speed.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -108,8 +108,8 @@
- 			opp-hz = /bits/ 64 <500000000>;
- 			clock-latency-ns = <256000>;
- 		};
--		opp@666000000 {
--			opp-hz = /bits/ 64 <666000000>;
-+		opp@716800000 {
-+			opp-hz = /bits/ 64 <716800000>;
- 			clock-latency-ns = <256000>;
- 		};
- 	};
diff --git a/target/linux/ipq806x/patches-4.9/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch b/target/linux/ipq806x/patches-4.9/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch
deleted file mode 100644
index e9d262069f..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-07-dts-ipq4019-ap-dk01.1-c1-add-spi-and-ram-nodes.patch
+++ /dev/null
@@ -1,115 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-@@ -19,4 +19,112 @@
- / {
- 	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
- 
-+	memory {
-+		device_type = "memory";
-+		reg = <0x80000000 0x10000000>;
-+	};
-+
-+	reserved-memory {
-+		#address-cells = <0x1>;
-+		#size-cells = <0x1>;
-+		ranges;
-+
-+		apps_bl@87000000 {
-+			reg = <0x87000000 0x400000>;
-+			no-map;
-+		};
-+
-+		sbl@87400000 {
-+			reg = <0x87400000 0x100000>;
-+			no-map;
-+		};
-+
-+		cnss_debug@87500000 {
-+			reg = <0x87500000 0x600000>;
-+			no-map;
-+		};
-+
-+		cpu_context_dump@87b00000 {
-+			reg = <0x87b00000 0x080000>;
-+			no-map;
-+		};
-+
-+		tz_apps@87b80000 {
-+			reg = <0x87b80000 0x280000>;
-+			no-map;
-+		};
-+
-+		smem@87e00000 {
-+			reg = <0x87e00000 0x080000>;
-+			no-map;
-+		};
-+
-+		tz@87e80000 {
-+			reg = <0x87e80000 0x180000>;
-+			no-map;
-+		};
-+	};
-+};
-+
-+&spi_0 {
-+	mx25l25635f@0 {
-+		compatible = "mx25l25635f", "jedec,spi-nor";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		reg = <0>;
-+		spi-max-frequency = <24000000>;
-+
-+		SBL1@0 {
-+			label = "SBL1";
-+			reg = <0x0 0x40000>;
-+			read-only;
-+		};
-+		MIBIB@40000 {
-+			label = "MIBIB";
-+			reg = <0x40000 0x20000>;
-+			read-only;
-+		};
-+		QSEE@60000 {
-+			label = "QSEE";
-+			reg = <0x60000 0x60000>;
-+			read-only;
-+		};
-+		CDT@c0000 {
-+			label = "CDT";
-+			reg = <0xc0000 0x10000>;
-+			read-only;
-+		};
-+		DDRPARAMS@d0000 {
-+			label = "DDRPARAMS";
-+			reg = <0xd0000 0x10000>;
-+			read-only;
-+		};
-+		APPSBLENV@e0000 {
-+			label = "APPSBLENV";
-+			reg = <0xe0000 0x10000>;
-+			read-only;
-+		};
-+		APPSBL@f0000 {
-+			label = "APPSBL";
-+			reg = <0xf0000 0x80000>;
-+			read-only;
-+		};
-+		ART@170000 {
-+			label = "ART";
-+			reg = <0x170000 0x10000>;
-+			read-only;
-+		};
-+		kernel@180000 {
-+			label = "kernel";
-+			reg = <0x180000 0x400000>;
-+		};
-+		rootfs@580000 {
-+			label = "rootfs";
-+			reg = <0x580000 0x1600000>;
-+		};
-+		firmware@180000 {
-+			label = "firmware";
-+			reg = <0x180000 0x1a00000>;
-+		};
-+	};
- };
diff --git a/target/linux/ipq806x/patches-4.9/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch b/target/linux/ipq806x/patches-4.9/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch
deleted file mode 100644
index 2d4ff31046..0000000000
--- a/target/linux/ipq806x/patches-4.9/864-08-dts-ipq4019-ap-dk01.1-c1-add-compatible-string.patch
+++ /dev/null
@@ -1,10 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
-@@ -18,6 +18,7 @@
- 
- / {
- 	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
-+	compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019";
- 
- 	memory {
- 		device_type = "memory";