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authorEtienne Champetier <champetier.etienne@gmail.com>2019-07-13 19:43:28 -0700
committerDavid Bauer <mail@david-bauer.net>2019-07-21 13:09:31 +0200
commit76a4c93f9dcafc0efd6f825fbd40eb4a2e53d456 (patch)
tree9406c1f012263ab06a29840b877b02f123f11fb3
parent4022035aafd3f68b9fa56069b5260f55cbf30e5e (diff)
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ar71xx: enable SGMII fixup on Mikrotik wAP AC
fixes intermittent loss of connectivity on 1Gbit port, with log message: > 803x_aneg_done: SGMII link is not ok Thanks to David Bauer for pointing me in the right direction. I just had to figure out the right bus_id, which you find in this log: > ag71xx ag71xx.1: connected to PHY at gpio-1:00 [uid=004dd074, driver=Atheros 8031 ethernet] Fixes FS#2236 Signed-off-by: Etienne Champetier <champetier.etienne@gmail.com> [Wrapped commit message - Fixed whitespace erors] Signed-off-by: David Bauer <mail@david-bauer.net> (cherry picked from commit 2a7519e29d6cbbe1eb73623ef35add0ef596fb5f)
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
index 96511a4080..6bb42c78e3 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
@@ -512,6 +512,18 @@ static struct platform_device rbwapgsc_phy_device = {
},
};
+static struct at803x_platform_data rbwapgsc_at803x_data = {
+ .override_sgmii_aneg = 1,
+};
+
+static struct mdio_board_info rbwapgsc_mdio_info[] = {
+ {
+ .bus_id = "gpio-1",
+ .mdio_addr = RBWAPGSC_MDIO_PHYADDR,
+ .platform_data = &rbwapgsc_at803x_data,
+ },
+};
+
/* RB911L GPIOs */
#define RB911L_GPIO_BTN_RESET 15
#define RB911L_GPIO_LED_1 13
@@ -1106,10 +1118,14 @@ static void __init rbwapgsc_setup(void)
platform_device_register(&rbwapgsc_phy_device);
+ mdiobus_register_board_info(rbwapgsc_mdio_info,
+ ARRAY_SIZE(rbwapgsc_mdio_info));
+
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
+ ath79_eth1_data.enable_sgmii_fixup = 1;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;