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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-12-14 20:54:07 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-12-14 20:54:07 +0000 |
| commit | 66c8cc0f6db70625de5da0f5d62b9771af014deb (patch) | |
| tree | e45260ad4f973191b9330092baf0e1027b8c8d37 | |
| parent | 0c38d36488943095722376ad16a63b4ded86f5de (diff) | |
| download | upstream-66c8cc0f6db70625de5da0f5d62b9771af014deb.tar.gz upstream-66c8cc0f6db70625de5da0f5d62b9771af014deb.tar.bz2 upstream-66c8cc0f6db70625de5da0f5d62b9771af014deb.zip | |
ar71xx: add GPIO function bit defines for AR933X
SVN-Revision: 29534
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 6ff886134c..47c2842baf 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -482,6 +482,26 @@ static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) #define AR91XX_GPIO_COUNT 22 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + #define AR933X_GPIO_COUNT 30 #define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) @@ -637,6 +657,7 @@ void ar71xx_ddr_flush(u32 reg); #define AR933X_RESET_REG_RESET_MODULE 0x1c #define AR933X_RESET_REG_BOOTSTRAP 0xac +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |