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| author | John Crispin <john@openwrt.org> | 2015-01-28 19:19:47 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-01-28 19:19:47 +0000 |
| commit | 259244624bae08f6ca396dca7f1ffde6d4110649 (patch) | |
| tree | 3b7384257f3cb378e2d7488523244bc220a05709 | |
| parent | 623716dd4318cd05022d5d1bb0875906ddfc12c2 (diff) | |
| download | upstream-259244624bae08f6ca396dca7f1ffde6d4110649.tar.gz upstream-259244624bae08f6ca396dca7f1ffde6d4110649.tar.bz2 upstream-259244624bae08f6ca396dca7f1ffde6d4110649.zip | |
ar71xx: fix D-Link DIR-615 rev. C1 WLAN MAC address
Fix the WLAN MAC address to match the one printed on the label by using the
correct address from the ART instead of the address of the LAN interface.
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
SVN-Revision: 44183
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c index 425be301e0..e55a43f9c7 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c @@ -38,6 +38,8 @@ #define DIR_615C1_CONFIG_ADDR 0x1f020000 #define DIR_615C1_CONFIG_SIZE 0x10000 +#define DIR_615C1_WLAN_MAC_ADDR 0x1f3fffb4 + static struct gpio_led dir_615c1_leds_gpio[] __initdata = { { .name = "d-link:orange:status", @@ -96,16 +98,16 @@ static void __init dir_615c1_setup(void) { const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); - u8 mac[6]; - u8 *wlan_mac = NULL; + u8 mac[ETH_ALEN], wlan_mac[ETH_ALEN]; if (ath79_nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, "lan_mac=", mac) == 0) { ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); - wlan_mac = mac; } + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615C1_WLAN_MAC_ADDR), wlan_mac); + ath79_register_mdio(0, DIR_615C1_MDIO_MASK); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |