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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-03-11 16:49:35 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-03-11 16:49:35 +0000 |
| commit | 77d0a8ca85876f55814bd4ae3f2b0debeef9a11f (patch) | |
| tree | 2ede72fd054cc07464f43876ab6540dfa92090cb | |
| parent | dad19ac8b2034e31b1926f1a25a680f6ff8ba52d (diff) | |
| download | upstream-77d0a8ca85876f55814bd4ae3f2b0debeef9a11f.tar.gz upstream-77d0a8ca85876f55814bd4ae3f2b0debeef9a11f.tar.bz2 upstream-77d0a8ca85876f55814bd4ae3f2b0debeef9a11f.zip | |
generic: ar8216: add a helper function for writing PHY debug registers
SVN-Revision: 30884
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c index c199ac178c..7dd3282306 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.c +++ b/target/linux/generic/files/drivers/net/phy/ar8216.c @@ -118,6 +118,18 @@ ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val) mutex_unlock(&bus->mdio_lock); } +static void +ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr, + u16 dbg_addr, u16 dbg_data) +{ + struct mii_bus *bus = priv->phy->bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); + mutex_unlock(&bus->mdio_lock); +} + static u32 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val) { @@ -719,14 +731,11 @@ ar8316_hw_init(struct ar8216_priv *priv) if ((i == 4) && priv->port4_phy && priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { /* work around for phy4 rgmii mode */ - mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x12); - mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x480c); + ar8216_phy_dbg_write(priv, i, 0x12, 0x480c); /* rx delay */ - mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x0); - mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x824e); + ar8216_phy_dbg_write(priv, i, 0x0, 0x824e); /* tx delay */ - mdiobus_write(bus, i, MII_ATH_DBG_ADDR, 0x5); - mdiobus_write(bus, i, MII_ATH_DBG_DATA, 0x3d47); + ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47); msleep(1000); } |