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| author | John Crispin <john@openwrt.org> | 2016-04-26 11:44:00 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2016-04-26 11:44:00 +0000 |
| commit | 687ab51fb239c83f992e851ab16afe442bbd01ef (patch) | |
| tree | d8ab7cc09df5238074fcc502b8d6d7d32b74f733 | |
| parent | 6a111b41bcb2802f42f9e92d152d1cef2c19b69b (diff) | |
| download | upstream-687ab51fb239c83f992e851ab16afe442bbd01ef.tar.gz upstream-687ab51fb239c83f992e851ab16afe442bbd01ef.tar.bz2 upstream-687ab51fb239c83f992e851ab16afe442bbd01ef.zip | |
cns3xxx: set both MPS 'and' MRSS to 128
Fixes some DMA issues with this platform. Because this isn't currently accepted,
and can potentially disrupt other platforms (as read in commit log), I will
leave this cns3xxx specific.
Original Patch: https://patchwork.ozlabs.org/patch/600024/
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
SVN-Revision: 49249
| -rw-r--r-- | target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch b/target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch new file mode 100644 index 0000000000..208c80a791 --- /dev/null +++ b/target/linux/cns3xxx/patches-4.4/130-Extend-PCIE_BUS_PEER2PEER-to-set-MRSS-128-to-fix-CNS3xxx-BM-DMA..patch @@ -0,0 +1,23 @@ +--- a/drivers/pci/probe.c ++++ b/drivers/pci/probe.c +@@ -1924,7 +1924,8 @@ static void pcie_write_mrrs(struct pci_d + /* In the "safe" case, do not configure the MRRS. There appear to be + * issues with setting MRRS to 0 on a number of devices. + */ +- if (pcie_bus_config != PCIE_BUS_PERFORMANCE) ++ if (pcie_bus_config != PCIE_BUS_PERFORMANCE && ++ pcie_bus_config != PCIE_BUS_PEER2PEER) + return; + + /* For Max performance, the MRRS must be set to the largest supported +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -756,7 +756,7 @@ enum pcie_bus_config_types { + PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ + PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ + PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ +- PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ ++ PCIE_BUS_PEER2PEER, /* set MPS and MRSS to 128 for all devices */ + }; + + extern enum pcie_bus_config_types pcie_bus_config; |