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| author | Hamish Guthrie <hcg@openwrt.org> | 2007-05-09 08:52:32 +0000 |
|---|---|---|
| committer | Hamish Guthrie <hcg@openwrt.org> | 2007-05-09 08:52:32 +0000 |
| commit | 9b27055a6cb9ff18de3e9402b81ab674f491ba89 (patch) | |
| tree | d4fb8ebaf25d891961aa0306076e0ea32fe309e9 | |
| parent | 91cdb3476d4327e4758d7885e9571bd31c22412f (diff) | |
| download | upstream-9b27055a6cb9ff18de3e9402b81ab674f491ba89.tar.gz upstream-9b27055a6cb9ff18de3e9402b81ab674f491ba89.tar.bz2 upstream-9b27055a6cb9ff18de3e9402b81ab674f491ba89.zip | |
Corrected inverted DCD/DTR logic
SVN-Revision: 7145
| -rw-r--r-- | target/linux/at91-2.6/patches/008-fdl-serial.patch | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/linux/at91-2.6/patches/008-fdl-serial.patch b/target/linux/at91-2.6/patches/008-fdl-serial.patch index 2260ffb6fe..3796915972 100644 --- a/target/linux/at91-2.6/patches/008-fdl-serial.patch +++ b/target/linux/at91-2.6/patches/008-fdl-serial.patch @@ -10,9 +10,9 @@ + * USART 0 - Drive DTR and RI pins manually + */ + if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PA19, 0); ++ at91_set_gpio_value(AT91_PIN_PB6, 0); + else -+ at91_set_gpio_value(AT91_PIN_PA19, 1); ++ at91_set_gpio_value(AT91_PIN_PB6, 1); + if (mctrl & TIOCM_RI) + at91_set_gpio_value(AT91_PIN_PB7, 0); + else @@ -25,9 +25,9 @@ + */ + if (port->mapbase == AT91RM9200_BASE_US3) { + if (mctrl & TIOCM_DTR) -+ at91_set_gpio_value(AT91_PIN_PA24, 0); ++ at91_set_gpio_value(AT91_PIN_PB29, 0); + else -+ at91_set_gpio_value(AT91_PIN_PA24, 1); ++ at91_set_gpio_value(AT91_PIN_PB29, 1); + if (mctrl & TIOCM_RI) + at91_set_gpio_value(AT91_PIN_PB2, 0); + else @@ -60,10 +60,10 @@ + * Read the GPIO's for the FDL VersaLink special case + */ + if (port->mapbase == AT91RM9200_BASE_US0) -+ if (!(at91_get_gpio_value(AT91_PIN_PB6))) ++ if (!(at91_get_gpio_value(AT91_PIN_PA19))) + ret |= TIOCM_CD; + if (port->mapbase == AT91RM9200_BASE_US3) -+ if (!(at91_get_gpio_value(AT91_PIN_PB29))) ++ if (!(at91_get_gpio_value(AT91_PIN_PA24))) + ret |= TIOCM_CD; + return ret; |