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authorJohn Crispin <john@openwrt.org>2016-03-16 09:27:04 +0000
committerJohn Crispin <john@openwrt.org>2016-03-16 09:27:04 +0000
commitbe68f34708db920a46d0dd6013b8bdae51685238 (patch)
treead681aaa3d80aacce40e749ecdf7b25516b44808
parenteff9a4b176c49f79d8ede2edf353606ca62916b2 (diff)
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ar71xx: Clear bits in ath79_setup_qca955x_eth_cfg
Some u-boot versions for QCA955x set currently not cleared bits depending on the used link speed. This breaks the rx/tx under OpenWrt. The mach-*.c file is responsible to select the correct configuration bits and thus the ath79_setup_qca955x_eth_cfg has to clear the unset. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49028
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index b43c80a376..2f2825f945 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -833,14 +833,24 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
void __init ath79_setup_qca955x_eth_cfg(u32 mask)
{
void __iomem *base;
- u32 t;
+ u32 t, m;
+
+ m = QCA955X_ETH_CFG_RGMII_EN |
+ QCA955X_ETH_CFG_MII_GE0 |
+ QCA955X_ETH_CFG_GMII_GE0 |
+ QCA955X_ETH_CFG_MII_GE0_MASTER |
+ QCA955X_ETH_CFG_MII_GE0_SLAVE |
+ QCA955X_ETH_CFG_GE0_ERR_EN |
+ QCA955X_ETH_CFG_GE0_SGMII |
+ QCA955X_ETH_CFG_RMII_GE0 |
+ QCA955X_ETH_CFG_MII_CNTL_SPEED |
+ QCA955X_ETH_CFG_RMII_GE0_MASTER;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
- t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
-
+ t &= ~m;
t |= mask;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);