aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorFelix Fietkau <nbd@openwrt.org>2013-07-31 08:54:56 +0000
committerFelix Fietkau <nbd@openwrt.org>2013-07-31 08:54:56 +0000
commit5f2e61addfa73ae73c0fa5d32a1f793422124246 (patch)
tree2d55c811e6b59d5a3f3079e9c99f1a0b51fa4e88
parent2771edf6477617dfff7c8f89bd1662bc96ae496c (diff)
downloadupstream-5f2e61addfa73ae73c0fa5d32a1f793422124246.tar.gz
upstream-5f2e61addfa73ae73c0fa5d32a1f793422124246.tar.bz2
upstream-5f2e61addfa73ae73c0fa5d32a1f793422124246.zip
gcc: merge a bugfix for a MIPS specific internal compiler error
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 37621
-rw-r--r--toolchain/gcc/patches/4.6-linaro/040-gcc_bug_49696.patch65
-rw-r--r--toolchain/gcc/patches/4.6.3/040-gcc_bug_49696.patch65
2 files changed, 130 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/4.6-linaro/040-gcc_bug_49696.patch b/toolchain/gcc/patches/4.6-linaro/040-gcc_bug_49696.patch
new file mode 100644
index 0000000000..74b9a86a8e
--- /dev/null
+++ b/toolchain/gcc/patches/4.6-linaro/040-gcc_bug_49696.patch
@@ -0,0 +1,65 @@
+--- a/gcc/config/mips/sync.md
++++ b/gcc/config/mips/sync.md
+@@ -136,7 +136,7 @@
+ [(match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")
+ (atomic_hiqi_op:SI (match_dup 0)
+- (match_operand:SI 3 "register_operand" "dJ"))]
++ (match_operand:SI 3 "reg_or_0_operand" "dJ"))]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 4 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -177,7 +177,7 @@
+ [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+ (atomic_hiqi_op:SI (match_dup 0)
+- (match_operand:SI 4 "register_operand" "dJ"))]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 5 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -218,7 +218,7 @@
+ (match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+ (atomic_hiqi_op:SI (match_dup 0)
+- (match_operand:SI 4 "register_operand" "dJ"))]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
+ UNSPEC_SYNC_NEW_OP_12))
+ (set (match_dup 1)
+ (unspec_volatile:SI
+@@ -259,7 +259,7 @@
+ [(match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")
+ (match_dup 0)
+- (match_operand:SI 3 "register_operand" "dJ")]
++ (match_operand:SI 3 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 4 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -298,7 +298,7 @@
+ (unspec_volatile:SI
+ [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+- (match_operand:SI 4 "register_operand" "dJ")]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 5 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -337,7 +337,7 @@
+ [(match_operand:SI 1 "memory_operand" "+R")
+ (match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+- (match_operand:SI 4 "register_operand" "dJ")]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_NEW_OP_12))
+ (set (match_dup 1)
+ (unspec_volatile:SI
+@@ -546,7 +546,7 @@
+ (set (match_dup 1)
+ (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+- (match_operand:SI 4 "arith_operand" "dJ")]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_EXCHANGE_12))]
+ "GENERATE_LL_SC"
+ { return mips_output_sync_loop (insn, operands); }
diff --git a/toolchain/gcc/patches/4.6.3/040-gcc_bug_49696.patch b/toolchain/gcc/patches/4.6.3/040-gcc_bug_49696.patch
new file mode 100644
index 0000000000..74b9a86a8e
--- /dev/null
+++ b/toolchain/gcc/patches/4.6.3/040-gcc_bug_49696.patch
@@ -0,0 +1,65 @@
+--- a/gcc/config/mips/sync.md
++++ b/gcc/config/mips/sync.md
+@@ -136,7 +136,7 @@
+ [(match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")
+ (atomic_hiqi_op:SI (match_dup 0)
+- (match_operand:SI 3 "register_operand" "dJ"))]
++ (match_operand:SI 3 "reg_or_0_operand" "dJ"))]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 4 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -177,7 +177,7 @@
+ [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+ (atomic_hiqi_op:SI (match_dup 0)
+- (match_operand:SI 4 "register_operand" "dJ"))]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 5 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -218,7 +218,7 @@
+ (match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+ (atomic_hiqi_op:SI (match_dup 0)
+- (match_operand:SI 4 "register_operand" "dJ"))]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
+ UNSPEC_SYNC_NEW_OP_12))
+ (set (match_dup 1)
+ (unspec_volatile:SI
+@@ -259,7 +259,7 @@
+ [(match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")
+ (match_dup 0)
+- (match_operand:SI 3 "register_operand" "dJ")]
++ (match_operand:SI 3 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 4 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -298,7 +298,7 @@
+ (unspec_volatile:SI
+ [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+- (match_operand:SI 4 "register_operand" "dJ")]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_OLD_OP_12))
+ (clobber (match_scratch:SI 5 "=&d"))]
+ "GENERATE_LL_SC"
+@@ -337,7 +337,7 @@
+ [(match_operand:SI 1 "memory_operand" "+R")
+ (match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+- (match_operand:SI 4 "register_operand" "dJ")]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_NEW_OP_12))
+ (set (match_dup 1)
+ (unspec_volatile:SI
+@@ -546,7 +546,7 @@
+ (set (match_dup 1)
+ (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
+ (match_operand:SI 3 "register_operand" "d")
+- (match_operand:SI 4 "arith_operand" "dJ")]
++ (match_operand:SI 4 "reg_or_0_operand" "dJ")]
+ UNSPEC_SYNC_EXCHANGE_12))]
+ "GENERATE_LL_SC"
+ { return mips_output_sync_loop (insn, operands); }