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| author | John Crispin <blogic@openwrt.org> | 2011-07-17 19:27:24 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2011-07-17 19:27:24 +0000 |
| commit | 0ecc62ed54414257cf5b456f11ddc860480b6bb6 (patch) | |
| tree | 06fece66a7b74a956574a99ffb3f3142f98e8414 | |
| parent | 2c0f2f82ef2ff3e69479323c23026e3220d1fcd7 (diff) | |
| download | upstream-0ecc62ed54414257cf5b456f11ddc860480b6bb6.tar.gz upstream-0ecc62ed54414257cf5b456f11ddc860480b6bb6.tar.bz2 upstream-0ecc62ed54414257cf5b456f11ddc860480b6bb6.zip | |
revert parts of r27488 to uboot-lantiq
Signed-off-by: Luka Perkov <openwrt@lukaperkov.net>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27663 3c298f89-4303-0410-b956-a3cf2f4a3e73
| -rw-r--r-- | package/uboot-lantiq/files/board/infineon/easy50712/danube.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c b/package/uboot-lantiq/files/board/infineon/easy50712/danube.c index 51b7577edb..e3845cb38f 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c +++ b/package/uboot-lantiq/files/board/infineon/easy50712/danube.c @@ -259,12 +259,12 @@ static int external_switch_init(void) /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */ udelay(100000); - printf("\nsearching for Samurai switch ... "); + debug("\nsearching for Samurai switch ... "); if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) && (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) { if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) && ((chipid1 & 0x000F) == ID_SAMURAI_1)) { - printf("found"); + debug("found"); /* enable "Crossover Auto Detect" + defaults */ /* P0 */ @@ -288,11 +288,10 @@ static int external_switch_init(void) } } - printf("%04X %04x\n", chipid0, chipid1); - printf("\nsearching for TANTOS switch ... "); + debug("\nsearching for TANTOS switch ... "); if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) { if (chipid0 == ID_TANTOS) { - printf("found"); + debug("found"); /* P5 Basic Control: Force Link Up */ miiphy_write(name, PHYADDR(0xA1), 0x0004); |