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authorPavel Kubelun <be.dissent@gmail.com>2016-11-08 15:52:46 +0300
committerJohn Crispin <john@phrozen.org>2016-11-16 10:59:30 +0100
commitbb8f5162fd76bba8a5bf661f674f4904259249f6 (patch)
tree1a2d64cc4a7fe78ed4fe22db5e13079907172cb3
parent84781cb6dc2004912cde1e2b37c91148c19a9ac4 (diff)
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ipq806x: fix pci pins
Fix pci pins drive-strength according to oem sources. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
-rw-r--r--target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi7
-rw-r--r--target/linux/ipq806x/patches-4.4/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch9
2 files changed, 9 insertions, 7 deletions
diff --git a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
index 0d5430370f..bff9979adf 100644
--- a/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
+++ b/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -305,7 +305,7 @@
mux {
pins = "gpio3";
function = "pcie1_rst";
- drive-strength = <12>;
+ drive-strength = <2>;
bias-disable;
};
};
@@ -314,7 +314,7 @@
mux {
pins = "gpio48";
function = "pcie2_rst";
- drive-strength = <12>;
+ drive-strength = <2>;
bias-disable;
};
};
@@ -323,8 +323,9 @@
mux {
pins = "gpio63";
function = "pcie3_rst";
- drive-strength = <12>;
+ drive-strength = <2>;
bias-disable;
+ output-low;
};
};
};
diff --git a/target/linux/ipq806x/patches-4.4/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.4/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index 2394926f8f..31a384f499 100644
--- a/target/linux/ipq806x/patches-4.4/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.4/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -63,7 +63,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
/ {
model = "Qualcomm IPQ8064";
-@@ -99,6 +102,33 @@
+@@ -99,6 +102,34 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;
@@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ mux {
+ pins = "gpio3";
+ function = "pcie1_rst";
-+ drive-strength = <12>;
++ drive-strength = <2>;
+ bias-disable;
+ };
+ };
@@ -81,7 +81,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ mux {
+ pins = "gpio48";
+ function = "pcie2_rst";
-+ drive-strength = <12>;
++ drive-strength = <2>;
+ bias-disable;
+ };
+ };
@@ -90,8 +90,9 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ mux {
+ pins = "gpio63";
+ function = "pcie3_rst";
-+ drive-strength = <12>;
++ drive-strength = <2>;
+ bias-disable;
++ output-low;
+ };
+ };
};