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authorGabor Juhos <juhosg@openwrt.org>2009-02-18 19:58:43 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-02-18 19:58:43 +0000
commit357ed07a8402bd0146feb09bbf3ca2cfab4c922d (patch)
tree1156302cd114f78c1e2d7491df1984ba6eec822a
parentd37ac90b828ccb1e18a47999a2127ed2de6f7f03 (diff)
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add a workaround for fixing the bad performance of the Ubiquiti RouterStation/LS-SR71 boards, until they fix their bootloader.
SVN-Revision: 14556
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h
new file mode 100644
index 0000000000..948d28034c
--- /dev/null
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h
@@ -0,0 +1,32 @@
+/*
+ * Atheros AR71xx specific kernel entry setup
+ *
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H
+#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H
+
+ /*
+ * Some bootloaders set the 'Kseg0 coherency algorithm' to
+ * 'Cacheable, noncoherent, write-through, no write allocate'
+ * and this cause performance issues. Let's go and change it to
+ * 'Cacheable, noncoherent, write-back, write allocate'
+ */
+ .macro kernel_entry_setup
+ mfc0 t0, CP0_CONFIG
+ li t1, ~CONF_CM_CMASK
+ and t0, t1
+ ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG
+ nop
+ .endm
+
+ .macro smp_slave_setup
+ .endm
+
+#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */