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| author | Gabor Juhos <juhosg@openwrt.org> | 2012-09-09 14:05:20 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2012-09-09 14:05:20 +0000 |
| commit | 94bac7366c2ad13a479c5476659658aeece43ca5 (patch) | |
| tree | 124e976c2bef866eedff2c6a00fa9ec973aeca28 | |
| parent | 759205777494fbf0b20eb9e133f4debb9e0d06ff (diff) | |
| download | upstream-94bac7366c2ad13a479c5476659658aeece43ca5.tar.gz upstream-94bac7366c2ad13a479c5476659658aeece43ca5.tar.bz2 upstream-94bac7366c2ad13a479c5476659658aeece43ca5.zip | |
ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x
SVN-Revision: 33343
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 33 | ||||
| -rw-r--r-- | target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch | 18 |
2 files changed, 47 insertions, 4 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index e6a5076019..d2d0ee87f0 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -19,6 +19,7 @@ #include <linux/etherdevice.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> +#include <linux/clk.h> #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> @@ -146,6 +147,31 @@ static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed) iounmap(base); } +static unsigned long ar934x_get_mdio_ref_clock(void) +{ + void __iomem *base; + unsigned long ret; + u32 t; + + base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + ret = 0; + t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) { + ret = 100 * 1000 * 1000; + } else { + struct clk *clk; + + clk = clk_get(NULL, "ref"); + if (!IS_ERR(clk)) + ret = clk_get_rate(clk); + } + + iounmap(base); + + return ret; +} + void __init ath79_register_mdio(unsigned int id, u32 phy_mask) { struct platform_device *mdio_dev; @@ -217,6 +243,13 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + if (id == 1) { + mdio_data->builtin_switch = 1; + mdio_data->ref_clock = ar934x_get_mdio_ref_clock(); + mdio_data->mdio_clock = 6250000; + } + mdio_data->is_ar934x = 1; + break; case ATH79_SOC_QCA9558: if (id == 1) mdio_data->builtin_switch = 1; diff --git a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch index ce1b9c50af..84d7166ca1 100644 --- a/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch @@ -74,15 +74,25 @@ #define AR933X_PLL_CPU_CONFIG_REG 0x00 #define AR933X_PLL_CLOCK_CTRL_REG 0x08 -@@ -212,6 +232,7 @@ +@@ -212,6 +232,8 @@ #define AR934X_PLL_CPU_CONFIG_REG 0x00 #define AR934X_PLL_DDR_CONFIG_REG 0x04 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -370,16 +391,50 @@ +@@ -244,6 +266,8 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 +@@ -370,16 +394,50 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) @@ -133,7 +143,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -520,6 +575,14 @@ +@@ -520,6 +578,14 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -148,7 +158,7 @@ #define AR71XX_GPIO_COUNT 16 #define AR724X_GPIO_COUNT 18 #define AR913X_GPIO_COUNT 22 -@@ -548,4 +611,133 @@ +@@ -548,4 +614,133 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 |