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authorJonas Gorski <jogo@openwrt.org>2015-06-10 09:21:31 +0000
committerJonas Gorski <jogo@openwrt.org>2015-06-10 09:21:31 +0000
commitd24d5412fff17cc0ddafecc47ca9564795e1df3a (patch)
tree0f83b10a347326147c5406bc5cd094e3c5ecb0ff
parente23052ab749ae9e9aa272caee7c065f7a98c82c1 (diff)
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b53: widen stp state mask to 3 bits (instead of 2)
At least on my b53 chip, the mask is 3 bits wide, and because of this some STP states are not set properly and discarded when read. Maybe for some other chips it makes sense to have just 2 bits width, but I don't have other versions around to test/validate. If that's the case then maybe we could add another STP state mask. Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com> Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 45937
-rw-r--r--target/linux/generic/files/drivers/net/phy/b53/b53_regs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index eef5c81779..144e1c8703 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -65,7 +65,7 @@
#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
#define PORT_CTRL_STP_STATE_S 5
-#define PORT_CTRL_STP_STATE_MASK (0x3 << PORT_CTRL_STP_STATE_S)
+#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S)
/* SMP Control Register (8 bit) */
#define B53_SMP_CTRL 0x0a