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authorGabor Juhos <juhosg@openwrt.org>2013-02-14 14:55:40 +0000
committerGabor Juhos <juhosg@openwrt.org>2013-02-14 14:55:40 +0000
commitf35c369710959b964e0d16d5c45dd497093df61e (patch)
tree7d6e3d7db3e109fb14da17317ac76335b6eae374
parentd64888ffc09247d51786931ca0b1bddeffd8efbf (diff)
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generic: ar8216: move PHY4 RGMII workaround code out of the loop
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 35603
-rw-r--r--target/linux/generic/files/drivers/net/phy/ar8216.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c
index 97a2cca6c0..b34c2a8637 100644
--- a/target/linux/generic/files/drivers/net/phy/ar8216.c
+++ b/target/linux/generic/files/drivers/net/phy/ar8216.c
@@ -820,20 +820,20 @@ ar8316_hw_init(struct ar8216_priv *priv)
priv->write(priv, AR8316_REG_POSTRIP, newval);
+ if (priv->port4_phy &&
+ priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
+ /* work around for phy4 rgmii mode */
+ ar8216_phy_dbg_write(priv, 4, 0x12, 0x480c);
+ /* rx delay */
+ ar8216_phy_dbg_write(priv, 4, 0x0, 0x824e);
+ /* tx delay */
+ ar8216_phy_dbg_write(priv, 4, 0x5, 0x3d47);
+ msleep(1000);
+ }
+
/* Initialize the ports */
bus = priv->mii_bus;
for (i = 0; i < 5; i++) {
- if ((i == 4) && priv->port4_phy &&
- priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
- /* work around for phy4 rgmii mode */
- ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
- /* rx delay */
- ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
- /* tx delay */
- ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
- msleep(1000);
- }
-
/* initialize the port itself */
mdiobus_write(bus, i, MII_ADVERTISE,
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);