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authorFelix Fietkau <nbd@openwrt.org>2013-08-12 17:26:03 +0000
committerFelix Fietkau <nbd@openwrt.org>2013-08-12 17:26:03 +0000
commit58e049ea8087c7c6fee3c0039de175ff8b356215 (patch)
tree02c28e96a810934f6b73e9a2a38df641cbec3e1d
parentf43b4ea962c7cccd74b04a60041f0a087cbe444d (diff)
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ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint
256 entries is a bit excessive, even for gigabit speeds Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 37762
-rw-r--r--target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
index 6d51e722b0..83607b38bf 100644
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
@@ -58,8 +58,8 @@
#define AG71XX_TX_RING_SIZE_DEFAULT 64
#define AG71XX_RX_RING_SIZE_DEFAULT 128
-#define AG71XX_TX_RING_SIZE_MAX 256
-#define AG71XX_RX_RING_SIZE_MAX 256
+#define AG71XX_TX_RING_SIZE_MAX 128
+#define AG71XX_RX_RING_SIZE_MAX 128
#ifdef CONFIG_AG71XX_DEBUG
#define DBG(fmt, args...) pr_debug(fmt, ## args)