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| author | John Crispin <john@phrozen.org> | 2016-09-29 14:23:08 +0200 |
|---|---|---|
| committer | Zoltan HERPAI <wigyori@uid0.hu> | 2016-09-29 14:23:08 +0200 |
| commit | 84ea6e0315f93c3c24ba408b4a7015bd30394348 (patch) | |
| tree | 80ae5f49e6bdd4c015ac90bef1c37165947380d7 | |
| parent | b5e7d8a212a4b2428ec681964fa7249a984caff1 (diff) | |
| download | upstream-84ea6e0315f93c3c24ba408b4a7015bd30394348.tar.gz upstream-84ea6e0315f93c3c24ba408b4a7015bd30394348.tar.bz2 upstream-84ea6e0315f93c3c24ba408b4a7015bd30394348.zip | |
ramips: fix usb phy initialisation
this broke usb20 device detection.
Signed-off-by: John Crispin <john@phrozen.org>
| -rw-r--r-- | target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch b/target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch index 4dc5a7528b..d4afb42eff 100644 --- a/target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch +++ b/target/linux/ramips/patches-3.18/0037-USB-phy-add-ralink-SoC-driver.patch @@ -58,19 +58,19 @@ +#define RT_SYSC_REG_CLKCFG1 0x030 +#define RT_SYSC_REG_USB_PHY_CFG 0x05c + -+#define OFS_U2_PHY_AC0 0x00 -+#define OFS_U2_PHY_AC1 0x04 -+#define OFS_U2_PHY_AC2 0x08 -+#define OFS_U2_PHY_ACR0 0x10 -+#define OFS_U2_PHY_ACR1 0x14 -+#define OFS_U2_PHY_ACR2 0x18 -+#define OFS_U2_PHY_ACR3 0x1C -+#define OFS_U2_PHY_ACR4 0x20 -+#define OFS_U2_PHY_AMON0 0x24 -+#define OFS_U2_PHY_DCR0 0x60 -+#define OFS_U2_PHY_DCR1 0x64 -+#define OFS_U2_PHY_DTM0 0x68 -+#define OFS_U2_PHY_DTM1 0x6C ++#define OFS_U2_PHY_AC0 0x800 ++#define OFS_U2_PHY_AC1 0x804 ++#define OFS_U2_PHY_AC2 0x808 ++#define OFS_U2_PHY_ACR0 0x810 ++#define OFS_U2_PHY_ACR1 0x814 ++#define OFS_U2_PHY_ACR2 0x818 ++#define OFS_U2_PHY_ACR3 0x81C ++#define OFS_U2_PHY_ACR4 0x820 ++#define OFS_U2_PHY_AMON0 0x824 ++#define OFS_U2_PHY_DCR0 0x860 ++#define OFS_U2_PHY_DCR1 0x864 ++#define OFS_U2_PHY_DTM0 0x868 ++#define OFS_U2_PHY_DTM1 0x86C + +#define RT_RSTCTRL_UDEV BIT(25) +#define RT_RSTCTRL_UHST BIT(22) |