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authorGabor Juhos <juhosg@openwrt.org>2009-07-01 19:41:00 +0000
committerGabor Juhos <juhosg@openwrt.org>2009-07-01 19:41:00 +0000
commita43abba1c3c9455d9babf6cabe26d23d8c6357cf (patch)
treefa695dc9ef36029bc694dab36397077b933ddef5
parent60d9465d365eecb20348fafc8bee58cf74a706f8 (diff)
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[ar71xx] fix ar71xx_device_{start,stop} functions on the AR7240 SoC
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16648 3c298f89-4303-0410-b956-a3cf2f4a3e73
-rw-r--r--target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c14
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h2
2 files changed, 16 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c b/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
index a13c928125..30d08c051a 100644
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
@@ -48,6 +48,13 @@ void ar71xx_device_stop(u32 mask)
local_irq_restore(flags);
break;
+ case AR71XX_SOC_AR7240:
+ local_irq_save(flags);
+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t | mask);
+ local_irq_restore(flags);
+ break;
+
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
local_irq_save(flags);
@@ -77,6 +84,13 @@ void ar71xx_device_start(u32 mask)
local_irq_restore(flags);
break;
+ case AR71XX_SOC_AR7240:
+ local_irq_save(flags);
+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t & ~mask);
+ local_irq_restore(flags);
+ break;
+
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
local_irq_save(flags);
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 14e5fe3dda..0fc0d20664 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -362,6 +362,8 @@ void ar71xx_ddr_flush(u32 reg);
#define AR91XX_RESET_REG_PERFC0 0x24
#define AR91XX_RESET_REG_PERFC1 0x28
+#define AR724X_RESET_REG_RESET_MODULE 0x1c
+
#define WDOG_CTRL_LAST_RESET BIT(31)
#define WDOG_CTRL_ACTION_MASK 3
#define WDOG_CTRL_ACTION_NONE 0 /* no action */