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| author | Gabor Juhos <juhosg@openwrt.org> | 2014-01-28 17:20:04 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2014-01-28 17:20:04 +0000 |
| commit | f555ce40f44dde9563eb2911b9cefa9453d25aa8 (patch) | |
| tree | 54310cf53ef462eb04589ccc44e5d6d01d102fdc | |
| parent | 05fe58447b71fa18a4665b02a01f23d53a98ed30 (diff) | |
| download | upstream-f555ce40f44dde9563eb2911b9cefa9453d25aa8.tar.gz upstream-f555ce40f44dde9563eb2911b9cefa9453d25aa8.tar.bz2 upstream-f555ce40f44dde9563eb2911b9cefa9453d25aa8.zip | |
AA: ath9k: add workaround for AR9331 USB host controller hang with USB1.1 devices
Backport of r39212
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/branches/attitude_adjustment@39407 3c298f89-4303-0410-b956-a3cf2f4a3e73
| -rw-r--r-- | package/mac80211/patches/561-ath9k-ar933x-usb-hang-workaround.patch | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/package/mac80211/patches/561-ath9k-ar933x-usb-hang-workaround.patch b/package/mac80211/patches/561-ath9k-ar933x-usb-hang-workaround.patch new file mode 100644 index 0000000000..40b6fef794 --- /dev/null +++ b/package/mac80211/patches/561-ath9k-ar933x-usb-hang-workaround.patch @@ -0,0 +1,77 @@ +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -313,6 +313,19 @@ void ath9k_hw_get_channel_centers(struct + centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); + } + ++static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah) ++{ ++ /* On AR9330 and AR9340 devices, some PHY registers must be ++ * tuned to gain better stability/performance. These registers ++ * might be changed while doing wlan reset so the registers must ++ * be reprogrammed after each reset. ++ */ ++ REG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20)); ++ REG_RMW(ah, AR_PHY_USB_CTRL2, ++ (1 << 21) | (0xf << 22), ++ (1 << 21) | (0x3 << 22)); ++} ++ + /******************/ + /* Chip Revisions */ + /******************/ +@@ -1397,6 +1410,9 @@ static bool ath9k_hw_set_reset(struct at + if (AR_SREV_9100(ah)) + udelay(50); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return true; + } + +@@ -1498,6 +1514,9 @@ static bool ath9k_hw_chip_reset(struct a + ath9k_hw_init_pll(ah, chan); + ath9k_hw_set_rfmode(ah, chan); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return true; + } + +@@ -1848,8 +1867,14 @@ static int ath9k_hw_do_fastcc(struct ath + if (AR_SREV_9271(ah)) + ar9002_hw_load_ani_reg(ah, chan); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return 0; + fail: ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return -EINVAL; + } + +@@ -2074,6 +2099,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st + if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv) + REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); + ++ if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) ++ ath9k_hw_disable_pll_lock_detect(ah); ++ + return 0; + } + EXPORT_SYMBOL(ath9k_hw_reset); +--- a/drivers/net/wireless/ath/ath9k/phy.h ++++ b/drivers/net/wireless/ath/ath9k/phy.h +@@ -48,4 +48,7 @@ + #define AR_PHY_PLL_CONTROL 0x16180 + #define AR_PHY_PLL_MODE 0x16184 + ++#define AR_PHY_USB_CTRL1 0x16c84 ++#define AR_PHY_USB_CTRL2 0x16c88 ++ + #endif |