From 716ca530e1c4515d8683c9d5be3d56b301758b66 Mon Sep 17 00:00:00 2001
From: James <>
Date: Wed, 4 Nov 2015 11:49:21 +0000
Subject: trunk-47381

---
 ...-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch | 98 ++++++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch

(limited to 'target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch')

diff --git a/target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch b/target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch
new file mode 100644
index 0000000..cfa7298
--- /dev/null
+++ b/target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch
@@ -0,0 +1,98 @@
+From 0f84c305351c993e4307e1e8c128d44760314e31 Mon Sep 17 00:00:00 2001
+From: Andrew Bresticker <abrestic@chromium.org>
+Date: Thu, 18 Sep 2014 14:47:07 -0700
+Subject: [PATCH 1/3] MIPS: Always use IRQ domains for CPU IRQs
+
+Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases.
+
+Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
+Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
+Tested-by: Qais Yousef <qais.yousef@imgtec.com>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Cc: Jason Cooper <jason@lakedaemon.net>
+Cc: Andrew Bresticker <abrestic@chromium.org>
+Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
+Cc: Markos Chandras <markos.chandras@imgtec.com>
+Cc: Paul Burton <paul.burton@imgtec.com>
+Cc: Qais Yousef <qais.yousef@imgtec.com>
+Cc: Jonas Gorski <jogo@openwrt.org>
+Cc: John Crispin <blogic@openwrt.org>
+Cc: David Daney <ddaney.cavm@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/7799/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/Kconfig          |    1 +
+ arch/mips/kernel/irq_cpu.c |   36 +++++++++++-------------------------
+ 2 files changed, 12 insertions(+), 25 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1056,6 +1056,7 @@ config MIPS_HUGE_TLB_SUPPORT
+ 
+ config IRQ_CPU
+ 	bool
++	select IRQ_DOMAIN
+ 
+ config IRQ_CPU_RM7K
+ 	bool
+--- a/arch/mips/kernel/irq_cpu.c
++++ b/arch/mips/kernel/irq_cpu.c
+@@ -98,28 +98,6 @@ static struct irq_chip mips_mt_cpu_irq_c
+ 	.irq_enable	= unmask_mips_irq,
+ };
+ 
+-void __init mips_cpu_irq_init(void)
+-{
+-	int irq_base = MIPS_CPU_IRQ_BASE;
+-	int i;
+-
+-	/* Mask interrupts. */
+-	clear_c0_status(ST0_IM);
+-	clear_c0_cause(CAUSEF_IP);
+-
+-	/* Software interrupts are used for MT/CMT IPI */
+-	for (i = irq_base; i < irq_base + 2; i++)
+-		irq_set_chip_and_handler(i, cpu_has_mipsmt ?
+-					 &mips_mt_cpu_irq_controller :
+-					 &mips_cpu_irq_controller,
+-					 handle_percpu_irq);
+-
+-	for (i = irq_base + 2; i < irq_base + 8; i++)
+-		irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
+-					 handle_percpu_irq);
+-}
+-
+-#ifdef CONFIG_IRQ_DOMAIN
+ static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
+ 			     irq_hw_number_t hw)
+ {
+@@ -142,8 +120,7 @@ static const struct irq_domain_ops mips_
+ 	.xlate = irq_domain_xlate_onecell,
+ };
+ 
+-int __init mips_cpu_intc_init(struct device_node *of_node,
+-			      struct device_node *parent)
++static void __init __mips_cpu_irq_init(struct device_node *of_node)
+ {
+ 	struct irq_domain *domain;
+ 
+@@ -155,7 +132,16 @@ int __init mips_cpu_intc_init(struct dev
+ 				       &mips_cpu_intc_irq_domain_ops, NULL);
+ 	if (!domain)
+ 		panic("Failed to add irqdomain for MIPS CPU");
++}
+ 
++void __init mips_cpu_irq_init(void)
++{
++	__mips_cpu_irq_init(NULL);
++}
++
++int __init mips_cpu_intc_init(struct device_node *of_node,
++			      struct device_node *parent)
++{
++	__mips_cpu_irq_init(of_node);
+ 	return 0;
+ }
+-#endif /* CONFIG_IRQ_DOMAIN */
-- 
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