From 716ca530e1c4515d8683c9d5be3d56b301758b66 Mon Sep 17 00:00:00 2001 From: James <> Date: Wed, 4 Nov 2015 11:49:21 +0000 Subject: trunk-47381 --- ...047-clk-iproc-Add-PLL-base-write-function.patch | 223 +++++++++++++++++++++ 1 file changed, 223 insertions(+) create mode 100644 target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch (limited to 'target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch') diff --git a/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch new file mode 100644 index 0000000..2f07cc6 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch @@ -0,0 +1,223 @@ +From acbb7a3de7e4d83b23c0bbb3eaf77d15a041d865 Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:28 -0400 +Subject: [PATCH 47/50] clk: iproc: Add PLL base write function + +All writes to the PLL base address must be flushed if the +IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the +necessary write and reads, we can make sure that any future code which +makes PLL base writes will do the correct thing. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/clk-iproc-pll.c | 80 +++++++++++++++++------------------------ + 1 file changed, 33 insertions(+), 47 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct ipro + return -EIO; + } + ++static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, ++ const u32 offset, u32 val) ++{ ++ const struct iproc_pll_ctrl *ctrl = pll->ctrl; ++ ++ writel(val, base + offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && ++ base == pll->pll_base)) ++ val = readl(base + offset); ++} ++ + static void __pll_disable(struct iproc_pll *pll) + { + const struct iproc_pll_ctrl *ctrl = pll->ctrl; +@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_p + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { + val = readl(pll->asiu_base + ctrl->asiu.offset); + val &= ~(1 << ctrl->asiu.en_shift); +- writel(val, pll->asiu_base + ctrl->asiu.offset); ++ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); + } + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pll_base + ctrl->aon.offset); +- +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { + /* latch input value so core power can be shut down */ + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= (1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + + /* power down the core */ + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + } + } + +@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pll_base + ctrl->aon.offset); +- +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; + val &= ~(1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + } + + /* certain PLLs also need to be ungated from the ASIU top level */ + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { + val = readl(pll->asiu_base + ctrl->asiu.offset); + val |= (1 << ctrl->asiu.en_shift); +- writel(val, pll->asiu_base + ctrl->asiu.offset); ++ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); + } + + return 0; +@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct ip + + val = readl(pll->pll_base + reset->offset); + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); +- writel(val, pll->pll_base + reset->offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + reset->offset); ++ iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } + + static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, +@@ -228,9 +232,7 @@ static void __pll_bring_out_reset(struct + val |= ki << reset->ki_shift | kp << reset->kp_shift | + ka << reset->ka_shift; + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; +- writel(val, pll->pll_base + reset->offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + reset->offset); ++ iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } + + static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, +@@ -285,9 +287,8 @@ static int pll_set_rate(struct iproc_clk + /* put PLL in reset */ + __pll_put_in_reset(pll); + +- writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->vco_ctrl.u_offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); ++ + val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); + + if (rate >= VCO_LOW && rate < VCO_MID) +@@ -298,17 +299,13 @@ static int pll_set_rate(struct iproc_clk + else + val |= (1 << PLL_VCO_HIGH_SHIFT); + +- writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->vco_ctrl.l_offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); + + /* program integer part of NDIV */ + val = readl(pll->pll_base + ctrl->ndiv_int.offset); + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); + val |= vco->ndiv_int << ctrl->ndiv_int.shift; +- writel(val, pll->pll_base + ctrl->ndiv_int.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->ndiv_int.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); + + /* program fractional part of NDIV */ + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +@@ -316,18 +313,15 @@ static int pll_set_rate(struct iproc_clk + val &= ~(bit_mask(ctrl->ndiv_frac.width) << + ctrl->ndiv_frac.shift); + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; +- writel(val, pll->pll_base + ctrl->ndiv_frac.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, ++ val); + } + + /* program PDIV */ + val = readl(pll->pll_base + ctrl->pdiv.offset); + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); + val |= vco->pdiv << ctrl->pdiv.shift; +- writel(val, pll->pll_base + ctrl->pdiv.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->pdiv.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); + + __pll_bring_out_reset(pll, kp, ka, ki); + +@@ -464,14 +458,12 @@ static int iproc_clk_enable(struct clk_h + /* channel enable is active low */ + val = readl(pll->pll_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.enable_shift); +- writel(val, pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + + /* also make sure channel is not held */ + val = readl(pll->pll_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.hold_shift); +- writel(val, pll->pll_base + ctrl->enable.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + + return 0; + } +@@ -488,9 +480,7 @@ static void iproc_clk_disable(struct clk + + val = readl(pll->pll_base + ctrl->enable.offset); + val |= 1 << ctrl->enable.enable_shift; +- writel(val, pll->pll_base + ctrl->enable.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + } + + static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, +@@ -559,9 +549,7 @@ static int iproc_clk_set_rate(struct clk + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + val |= div << ctrl->mdiv.shift; + } +- writel(val, pll->pll_base + ctrl->mdiv.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->mdiv.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); + clk->rate = parent_rate / div; + + return 0; +@@ -588,9 +576,7 @@ static void iproc_pll_sw_cfg(struct ipro + + val = readl(pll->pll_base + ctrl->sw_ctrl.offset); + val |= BIT(ctrl->sw_ctrl.shift); +- writel(val, pll->pll_base + ctrl->sw_ctrl.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->sw_ctrl.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); + } + } + -- cgit v1.2.3