From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 15 Dec 2013 20:46:26 +0100
Subject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs

Newer SoCs have 128 bit wide irq registers, thus 128 available internal
interupts.
---
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++-
 arch/mips/include/asm/mach-bcm63xx/irq.h         | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -1,10 +1,12 @@
 #ifndef BCM63XX_IRQ_H_
 #define BCM63XX_IRQ_H_
 
+#include <irq.h>
 #include <bcm63xx_cpu.h>
 
 #define IRQ_INTERNAL_BASE		8
-#define IRQ_EXTERNAL_BASE		100
+#define NR_INTERNAL_IRQS		128
+#define IRQ_EXTERNAL_BASE		(IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS)
 #define IRQ_EXT_0			(IRQ_EXTERNAL_BASE + 0)
 #define IRQ_EXT_1			(IRQ_EXTERNAL_BASE + 1)
 #define IRQ_EXT_2			(IRQ_EXTERNAL_BASE + 2)
--- a/arch/mips/include/asm/mach-bcm63xx/irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_MACH_BCM63XX_IRQ_H
 #define __ASM_MACH_BCM63XX_IRQ_H
 
-#define NR_IRQS 128
+#define NR_IRQS 256
 #define MIPS_CPU_IRQ_BASE 0
 
 #endif