From 716ca530e1c4515d8683c9d5be3d56b301758b66 Mon Sep 17 00:00:00 2001 From: James <> Date: Wed, 4 Nov 2015 11:49:21 +0000 Subject: trunk-47381 --- .../0066-arm-mediatek-add-m7623-devicetree.patch | 551 +++++++++++++++++++++ 1 file changed, 551 insertions(+) create mode 100644 target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch (limited to 'target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch') diff --git a/target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch b/target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch new file mode 100644 index 0000000..4516561 --- /dev/null +++ b/target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch @@ -0,0 +1,551 @@ +From a6bf117b5fe3acd76bbc45cc87fd80f589136e59 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:14:42 +0200 +Subject: [PATCH 66/76] arm: mediatek: add m7623 devicetree + +Signed-off-by: John Crispin +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/mt7623-evb.dts | 162 ++++++++++++++++++ + arch/arm/boot/dts/mt7623.dtsi | 348 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 511 insertions(+) + create mode 100644 arch/arm/boot/dts/mt7623-evb.dts + create mode 100644 arch/arm/boot/dts/mt7623.dtsi + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 992736b..525392e 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -658,6 +658,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ + dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6589-aquaris5.dtb \ + mt6592-evb.dtb \ ++ mt7623-evb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb + endif +diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts +new file mode 100644 +index 0000000..759142f +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623-evb.dts +@@ -0,0 +1,162 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Joe.C ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include ++#include "mt7623.dtsi" ++ ++/ { ++ model = "MediaTek MT7623 Evaluation Board"; ++ compatible = "mediatek,mt7623-evb", "mediatek,mt7623"; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ memory { ++ reg = <0 0x80000000 0 0x10000000>; ++ }; ++ ++ usb_p1_vbus: fixedregulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&pio 130 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++ ++&pio { ++ pinctrl_uart2_default: uart2@0 { ++ pins { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ pinctrl_i2c0_default: i2c@0 { ++ pins { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ pinctrl_pcie_default: pcie@0 { ++ pins { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ }; ++ }; ++ ++ pinctrl_spi_default: spi@0 { ++ pins { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++}; ++ ++&thermal { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_default>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c0_default>; ++}; ++ ++&spi { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_spi_default>; ++ ++ m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "mx25l12805d"; ++ reg = <0 0 0 0>; ++ linux,modalias = "m25p80", "w25q128"; ++ spi-max-frequency = <10000000>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0 0x30000>; ++ read-only; ++ }; ++ ++ partition@30000 { ++ label = "u-boot-env"; ++ reg = <0x30000 0x10000>; ++ read-only; ++ }; ++ ++ factory: partition@40000 { ++ label = "factory"; ++ reg = <0x40000 0x10000>; ++ read-only; ++ }; ++ ++ partition@50000 { ++ label = "firmware"; ++ reg = <0x50000 0xfb0000>; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ status = "okay"; ++ ++// pinctrl-names = "default", "state_uhs"; ++// pinctrl-0 = <&mmc0_pins_default>; ++// pinctrl-1 = <&mmc0_pins_uhs>; ++ bus-width = <8>; ++ max-frequency = <50000000>; ++ cap-mmc-highspeed; ++// vmmc-supply = <&mt6397_vemc_3v3_reg>; ++// vqmmc-supply = <&mt6397_vio18_reg>; ++ non-removable; ++}; ++ ++&u3phy { ++ reg-p1-vbus-supply = <&usb_p1_vbus>; ++}; ++ ++&pcie { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie_default>; ++}; +diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi +new file mode 100644 +index 0000000..ba74ed9 +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -0,0 +1,348 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Joe.C ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "skeleton64.dtsi" ++ ++/ { ++ compatible = "mediatek,mt7623"; ++ interrupt-parent = <&sysirq>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ enable-method = "mediatek,mt65xx-smp"; ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ }; ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x1>; ++ }; ++ cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x2>; ++ }; ++ cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x3>; ++ }; ++ ++ }; ++ ++ clk26m: oscillator@0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <26000000>; ++ clock-output-names = "clk26m"; ++ }; ++ ++ clk32k: oscillator@1 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32000>; ++ clock-output-names = "clk32k"; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <13000000>; ++ arm,cpu-registers-not-fw-configured; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu_thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ ++ thermal-sensors = <&thermal 1>; ++ }; ++ }; ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "simple-bus"; ++ ranges; ++ ++ topckgen: topckgen@10000000 { ++ compatible = "mediatek,mt7623-topckgen"; ++ reg = <0 0x10000000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ infracfg: infracfg@10001000 { ++ compatible = "mediatek,mt7623-infracfg", "syscon"; ++ reg = <0 0x10001000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pericfg: pericfg@10003000 { ++ compatible = "mediatek,mt7623-pericfg", "syscon"; ++ reg = <0 0x10003000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ /* ++ * Pinctrl access register at 0x10005000 through regmap. ++ * Register 0x1000b000 is used by EINT. ++ */ ++ pio: pinctrl@10005000 { ++ compatible = "mediatek,mt7623-pinctrl"; ++ reg = <0 0x1000b000 0 0x1000>; ++ mediatek,pctl-regmap = <&syscfg_pctl_a>; ++ pins-are-numbered; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = ; ++ }; ++ ++ syscfg_pctl_a: syscfg_pctl_a@10005000 { ++ compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; ++ reg = <0 0x10005000 0 0x1000>; ++ }; ++ ++ wdt: watchdog@10007000 { ++ compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt"; ++ reg = <0 0x10007000 0 0x18>; ++ }; ++ ++ timer: timer@10008000 { ++ compatible = "mediatek,mt7623-timer", ++ "mediatek,mt6577-timer"; ++ reg = <0 0x10008000 0 0x80>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_AXI_SEL>, ++ <&topckgen CLK_TOP_RTC_SEL>; ++ clock-names = "system-clk", "rtc-clk"; ++ }; ++ ++ sysirq: interrupt-controller@10200100 { ++ compatible = "mediatek,mt7623-sysirq", ++ "mediatek,mt6577-sysirq"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10200100 0 0x1c>; ++ }; ++ ++ apmixedsys: apmixedsys@10209000 { ++ compatible = "mediatek,mt7623-apmixedsys"; ++ reg = <0 0x10209000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ gic: interrupt-controller@10211000 { ++ compatible = "arm,cortex-a7-gic"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10211000 0 0x1000>, ++ <0 0x10212000 0 0x1000>, ++ <0 0x10214000 0 0x2000>, ++ <0 0x10216000 0 0x2000>; ++ }; ++ ++ auxadc: auxadc@11001000 { ++ compatible = "mediatek,mt7623-auxadc", "mediatek,mt8173-auxadc"; ++ reg = <0 0x11001000 0 0x1000>; ++ }; ++ ++ uart0: serial@11006000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11002000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ uart1: serial@11007000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11003000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ uart2: serial@11008000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11004000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ uart3: serial@11009000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11005000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ spi: spi@1100a000 { ++ compatible = "medi/THEatek,mt7623-spi", "mediatek,mt6589-spi"; ++ reg = <0 0x1100a000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_SPI0>; ++ clock-names = "main"; ++ ++ status = "disabled"; ++ }; ++ ++ thermal: thermal@1100b000 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt7623-thermal", "mediatek,mt8173-thermal"; ++ reg = <0 0x1100b000 0 0x1000>; ++ interrupts = <0 38 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; ++ clock-names = "therm", "auxadc"; ++ resets = <&pericfg MT7623_PERI_THERM_SW_RST>; ++ reset-names = "therm"; ++ auxadc = <&auxadc>; ++ apmixedsys = <&apmixedsys>; ++ ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@11007000 { ++ compatible = "mediatek,mt7623-i2c", "mediatek,mt6577-i2c"; ++ reg = <0 0x11007000 0 0x70>, ++ <0 0x11000300 0 0x80>; ++ interrupts = <0 44 IRQ_TYPE_LEVEL_LOW>; ++ clock-frequency = <400000>; ++ clock-div = <16>; ++ clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; ++ clock-names = "main", "dma"; ++ ++ status = "disabled"; ++ }; ++ ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7623-mmc", ++ "mediatek,mt8135-mmc"; ++ reg = <0 0x11230000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_MSDC20_1>, ++ <&topckgen CLK_TOP_MSDC30_0_SEL>; ++ clock-names = "source", "hclk"; ++ status = "disabled"; ++ }; ++ ++ usb: usb30@11270000 { ++ compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci", "generic-xhci"; ++ reg = <0 0x11270000 0 0x1000>; ++ interrupts = ; ++ usb-phy = <&u3phy>; ++ usb3-lpm-capable; ++ }; ++ ++ u3phy: usb-phy@11271000 { ++ compatible = "mediatek,mt7623-u3phy", "mediatek,mt8173-u3phy"; ++ reg = <0 0x11271000 0 0x3000>, ++ <0 0x11280000 0 0x20000>; ++// power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; ++// reg-vusb33-supply = <&mt6397_vusb_reg>; ++ clocks = <&pericfg CLK_PERI_USB0>, ++ <&pericfg CLK_PERI_USB1>, ++ <&topckgen CLK_TOP_USB20_SEL>; ++// <&apmixedsys CLK_APMIXED_REF2USB_TX>; ++ clock-names = "wakeup_deb_p0", ++ "wakeup_deb_p1", ++ "sys_mac"; ++// "u3phya_ref"; ++ disable-usb2-p1; ++ }; ++ }; ++ ++ ethernet@1B100000 { ++ compatible = "mediatek,mt7623-net"; ++ interrupts = <0 200 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ ++ pcie: pcie@1a140000 { ++ compatible = "mediatek,mt7623-pcie"; ++ reg = <0 0x1a140000 0 0x10000>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ ++ bus-range = <0 255>; ++ ranges = < ++ 0x02000000 0 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ ++ 0x01000000 0 0 0x00000000 0x1A160000 0 0x00010000 /* io space */ ++ >; ++ ++ pcie0 { ++ reg = <0x0000 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ }; ++ ++ pcie1 { ++ reg = <0x0800 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ }; ++ ++ pcie2 { ++ reg = <0x1000 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ }; ++ ++ status = "disabled"; ++ }; ++}; +-- +1.7.10.4 + -- cgit v1.2.3