From 716ca530e1c4515d8683c9d5be3d56b301758b66 Mon Sep 17 00:00:00 2001 From: James <> Date: Wed, 4 Nov 2015 11:49:21 +0000 Subject: trunk-47381 --- .../adm8668/files-3.18/arch/mips/adm8668/clock.c | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c (limited to 'target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c') diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c new file mode 100644 index 0000000..1e010fc --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c @@ -0,0 +1,76 @@ +/* + * ADM8668 minimal clock support + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under the terms of the GPLv2 + */ + +#include +#include +#include +#include +#include + +#include + +struct clk { + unsigned long rate; +}; + +static struct clk uart_clk = { + .rate = 62500000, +}; + +static struct clk sys_clk; + +struct clk *clk_get(struct device *dev, const char *id) +{ + const char *lookup = id; + + if (dev) + lookup = dev_name(dev); + + if (!strcmp(lookup, "apb:uart0")) + return &uart_clk; + if (!strcmp(lookup, "sys")) + return &sys_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +void __init adm8668_init_clocks(void) +{ + u32 adj; + + /* adjustable clock selection + * CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc... + */ + adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf; + sys_clk.rate = 175000000 + (adj * 5000000); + + pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000); +} -- cgit v1.2.3