From 716ca530e1c4515d8683c9d5be3d56b301758b66 Mon Sep 17 00:00:00 2001
From: James <>
Date: Wed, 4 Nov 2015 11:49:21 +0000
Subject: trunk-47381

---
 .../patches/040-no_extern_inline.patch             | 112 +++++++++++++++++++++
 1 file changed, 112 insertions(+)
 create mode 100644 package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch

(limited to 'package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch')

diff --git a/package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch b/package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch
new file mode 100644
index 0000000..5c01691
--- /dev/null
+++ b/package/boot/uboot-ar71xx/patches/040-no_extern_inline.patch
@@ -0,0 +1,112 @@
+--- a/include/asm-mips/io.h
++++ b/include/asm-mips/io.h
+@@ -118,12 +118,12 @@ static inline void set_io_port_base(unsi
+  * Change virtual addresses to physical addresses and vv.
+  * These are trivial on the 1:1 Linux/MIPS mapping
+  */
+-extern inline phys_addr_t virt_to_phys(volatile void * address)
++static inline phys_addr_t virt_to_phys(volatile void * address)
+ {
+ 	return CPHYSADDR(address);
+ }
+ 
+-extern inline void * phys_to_virt(unsigned long address)
++static inline void * phys_to_virt(unsigned long address)
+ {
+ 	return (void *)KSEG0ADDR(address);
+ }
+@@ -131,12 +131,12 @@ extern inline void * phys_to_virt(unsign
+ /*
+  * IO bus memory addresses are also 1:1 with the physical address
+  */
+-extern inline unsigned long virt_to_bus(volatile void * address)
++static inline unsigned long virt_to_bus(volatile void * address)
+ {
+ 	return CPHYSADDR(address);
+ }
+ 
+-extern inline void * bus_to_virt(unsigned long address)
++static inline void * bus_to_virt(unsigned long address)
+ {
+ 	return (void *)KSEG0ADDR(address);
+ }
+@@ -150,12 +150,12 @@ extern unsigned long isa_slot_offset;
+ extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+ 
+ #if 0
+-extern inline void *ioremap(unsigned long offset, unsigned long size)
++static inline void *ioremap(unsigned long offset, unsigned long size)
+ {
+ 	return __ioremap(offset, size, _CACHE_UNCACHED);
+ }
+ 
+-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
++static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+ {
+ 	return __ioremap(offset, size, _CACHE_UNCACHED);
+ }
+@@ -238,7 +238,7 @@ out:
+  */
+ 
+ #define __OUT1(s) \
+-extern inline void __out##s(unsigned int value, unsigned int port) {
++static inline void __out##s(unsigned int value, unsigned int port) {
+ 
+ #define __OUT2(m) \
+ __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
+@@ -252,7 +252,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__iosw
+ 	SLOW_DOWN_IO; }
+ 
+ #define __IN1(t,s) \
+-extern __inline__ t __in##s(unsigned int port) { t _v;
++static inline t __in##s(unsigned int port) { t _v;
+ 
+ /*
+  * Required nops will be inserted by the assembler
+@@ -267,7 +267,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i
+ __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
+ 
+ #define __INS1(s) \
+-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
++static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+ 
+ #define __INS2(m) \
+ if (count) \
+@@ -295,7 +295,7 @@ __INS1(s##c) __INS2(m) \
+ 	: "$1");}
+ 
+ #define __OUTS1(s) \
+-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
++static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+ 
+ #define __OUTS2(m) \
+ if (count) \
+--- a/include/asm-mips/system.h
++++ b/include/asm-mips/system.h
+@@ -23,7 +23,7 @@
+ #include <linux/kernel.h>
+ #endif
+ 
+-extern __inline__ void
++static inline void
+ __sti(void)
+ {
+ 	__asm__ __volatile__(
+@@ -47,7 +47,7 @@ __sti(void)
+  * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+  * no nops at all.
+  */
+-extern __inline__ void
++static inline void
+ __cli(void)
+ {
+ 	__asm__ __volatile__(
+@@ -208,7 +208,7 @@ do { \
+  * For 32 and 64 bit operands we can take advantage of ll and sc.
+  * FIXME: This doesn't work for R3000 machines.
+  */
+-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
++static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
+ {
+ #ifdef CONFIG_CPU_HAS_LLSC
+ 	unsigned long dummy;
-- 
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