/* Copyright 2000-2010 Broadcom Corporation Unless you and Broadcom execute a separate written software license agreement governing use of this software, this software is licensed to you under the terms of the GNU General Public License version 2 (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, with the following added to such license: As a special exception, the copyright holders of this software give you permission to link this software with independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from this software. The special exception does not apply to any modifications of the software. Notwithstanding the above, under no circumstances may you combine this software in any way with any other Broadcom software provided under a license other than the GPL, without Broadcom's express prior written consent. */ /***********************************************************************/ /* */ /* MODULE: bcm_hwdefs.h */ /* PURPOSE: Define all base device addresses and HW specific macros. */ /* */ /***********************************************************************/ #ifndef _BCM_HWDEFS_H #define _BCM_HWDEFS_H #ifdef __cplusplus extern "C" { #endif #define DYING_GASP_API /*****************************************************************************/ /* Physical Memory Map */ /*****************************************************************************/ #define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */ #if defined(CONFIG_BRCM_IKOS) #define PHYS_FLASH_BASE 0x18000000 /* Flash Memory */ #else #define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */ #endif /*****************************************************************************/ /* Note that the addresses above are physical addresses and that programs */ /* have to use converted addresses defined below: */ /*****************************************************************************/ #define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */ #define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */ /* Binary images are always built for a standard MIPS boot address */ #define IMAGE_BASE (0xA0000000 | PHYS_FLASH_BASE) /* Some chips don't support alternative boot vector */ #if defined(CONFIG_BRCM_IKOS) #define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */ #define BOOT_OFFSET 0 #else #if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362) #define FLASH_BASE 0xB8000000 #else #define FLASH_BASE (0xA0000000 | (MPI->cs[0].base & 0xFFFFFF00)) #endif #define BOOT_OFFSET (FLASH_BASE - IMAGE_BASE) #endif /*****************************************************************************/ /* Select the PLL value to get the desired CPU clock frequency. */ /*****************************************************************************/ #define FPERIPH 50000000 /*****************************************************************************/ /* Board memory type offset */ /*****************************************************************************/ #define ONEK 1024 #define FLASH_LENGTH_BOOT_ROM (64*ONEK) #define PROJECT_ID_LEN 7 /* Foxconn added by zacker, 02/29/2008, strlen("U12H094") */ #ifdef _CFE_ #define FLASH_SIZE 32 * 1024 * 1024 #endif #define BOARD_DATA_ADDR (FLASH_BASE + FLASH_SIZE - 0x20000) #define BOARD_FOXNVRAM_ADDR (FLASH_BASE + FLASH_SIZE - 0x10000) #define FOX_BOARD_ID_MAX_LEN 64 #define BOARD_ID "U12L161" /*****************************************************************************/ /* NVRAM Offset and definition */ /*****************************************************************************/ #define NVRAM_SECTOR 0 #define NVRAM_DATA_OFFSET 0x0580 #define NVRAM_DATA_ID 0x0f1e2d3c // This is only for backwards compatability #define NVRAM_LENGTH ONEK // 1k nvram #define NVRAM_VERSION_NUMBER 6 #define NVRAM_FULL_LEN_VERSION_NUMBER 5 /* version in which the checksum was placed at the end of the NVRAM structure */ #define NVRAM_BOOTLINE_LEN 256 #define NVRAM_BOARD_ID_STRING_LEN 16 #define NVRAM_MAC_ADDRESS_LEN 6 #define NVRAM_GPON_SERIAL_NUMBER_LEN 13 #define NVRAM_GPON_PASSWORD_LEN 11 #define NVRAM_WLAN_PARAMS_LEN 256 #define NVRAM_WPS_DEVICE_PIN_LEN 8 #define THREAD_NUM_ADDRESS_OFFSET (NVRAM_DATA_OFFSET + 4 + NVRAM_BOOTLINE_LEN + NVRAM_BOARD_ID_STRING_LEN) #define THREAD_NUM_ADDRESS (0x80000000 + THREAD_NUM_ADDRESS_OFFSET) #define DEFAULT_BOOTLINE "e=192.168.1.1:ffffff00 h=192.168.1.100 g= r=f f=vmlinux i=bcm963xx_fs_kernel d=1 p=0 " #define DEFAULT_BOARD_IP "192.168.1.1" #define DEFAULT_MAC_NUM 10 #define DEFAULT_BOARD_MAC "00:10:18:00:00:00" #define DEFAULT_TP_NUM 0 #define DEFAULT_PSI_SIZE 24 #define DEFAULT_GPON_SN "BRCM12345678" #define DEFAULT_GPON_PW " " #define DEFAULT_WPS_DEVICE_PIN "12345670" #define DEFAULT_VOICE_BOARD_ID "NONE" #define NVRAM_MAC_COUNT_MAX 32 #define NVRAM_MAX_PSI_SIZE 64 #define NVRAM_MAX_SYSLOG_SIZE 256 #define NP_BOOT 0 #define NP_ROOTFS_1 1 #define NP_ROOTFS_2 2 #define NP_DATA 3 #define NP_BBT 4 #define NP_TOTAL 5 #define NAND_DATA_SIZE_KB 1024 #define NAND_BBT_THRESHOLD_KB (512 * 1024) #define NAND_BBT_SMALL_SIZE_KB 1024 #define NAND_BBT_BIG_SIZE_KB 4096 #define NAND_CFE_RAM_NAME "cferam.000" #ifndef _LANGUAGE_ASSEMBLY typedef struct { unsigned long ulVersion; char szBootline[NVRAM_BOOTLINE_LEN]; char szBoardId[NVRAM_BOARD_ID_STRING_LEN]; unsigned long ulMainTpNum; unsigned long ulPsiSize; unsigned long ulNumMacAddrs; unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN]; char pad; char backupPsi; /**< if 0x01, allocate space for a backup PSI */ unsigned long ulCheckSumV4; char gponSerialNumber[NVRAM_GPON_SERIAL_NUMBER_LEN]; char gponPassword[NVRAM_GPON_PASSWORD_LEN]; char wpsDevicePin[NVRAM_WPS_DEVICE_PIN_LEN]; char wlanParams[NVRAM_WLAN_PARAMS_LEN]; unsigned long ulSyslogSize; /**< number of KB to allocate for persistent syslog */ unsigned long ulNandPartOfsKb[NP_TOTAL]; unsigned long ulNandPartSizeKb[NP_TOTAL]; char szVoiceBoardId[NVRAM_BOARD_ID_STRING_LEN]; unsigned long afeId[2]; char szFirmwareUpgradeBoardId[32]; /* foxconn added Bob, 07/12/2010, for TFTP firmware upgrade */ char chUnused[332]; /* reduce array size from 364 to 332, total size of NVRAM_DATA is unchanged, Bob, 07/12/2010 */ unsigned long ulCheckSum; } NVRAM_DATA, *PNVRAM_DATA; #endif #define BOOT_LATEST_IMAGE '0' #define BOOT_PREVIOUS_IMAGE '1' /*****************************************************************************/ /* Misc Offsets */ /*****************************************************************************/ #define CFE_VERSION_OFFSET 0x0570 #define CFE_VERSION_MARK_SIZE 5 #define CFE_VERSION_SIZE 5 #ifdef __cplusplus } #endif #endif /* _BCM_HWDEFS_H */