/* <:copyright-broadcom Copyright (c) 2007 Broadcom Corporation All Rights Reserved No portions of this material may be reproduced in any form without the written permission of: Broadcom Corporation 16215 Alton Parkway Irvine, California 92619 All information contained in this document is Broadcom Corporation company private, proprietary, and trade secret. :> */ /***********************************************************************/ /* */ /* MODULE: 6362_map.h */ /* DATE: 05/30/08 */ /* PURPOSE: Define addresses of major hardware components of */ /* BCM6362 */ /* */ /***********************************************************************/ #ifndef __BCM6362_MAP_H #define __BCM6362_MAP_H #ifdef __cplusplus extern "C" { #endif #include "bcmtypes.h" #include "6362_common.h" #include "6362_intr.h" /* macro to convert logical data addresses to physical */ /* DMA hardware must see physical address */ #define LtoP( x ) ( (uint32)x & 0x1fffffff ) #define PtoL( x ) ( LtoP(x) | 0xa0000000 ) typedef struct DDRPhyControl { uint32 REVISION; /* 0x00 */ uint32 CLK_PM_CTRL; /* 0x04 */ uint32 unused0[2]; /* 0x08-0x10 */ uint32 PLL_STATUS; /* 0x10 */ uint32 PLL_CONFIG; /* 0x14 */ uint32 PLL_PRE_DIVIDER; /* 0x18 */ uint32 PLL_DIVIDER; /* 0x1c */ uint32 PLL_CONTROL1; /* 0x20 */ uint32 PLL_CONTROL2; /* 0x24 */ uint32 PLL_SS_EN; /* 0x28 */ uint32 PLL_SS_CFG; /* 0x2c */ uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ uint32 IDLE_PAD_CONTROL; /* 0x38 */ uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ uint32 DRIVE_PAD_CTL; /* 0x40 */ uint32 CLOCK_REG_CONTROL; /* 0x44 */ uint32 unused1[46]; } DDRPhyControl; typedef struct DDRPhyByteLaneControl { uint32 REVISION; /* 0x00 */ uint32 VDL_CALIBRATE; /* 0x04 */ uint32 VDL_STATUS; /* 0x08 */ uint32 unused; /* 0x0c */ uint32 VDL_OVERRIDE_0; /* 0x10 */ uint32 VDL_OVERRIDE_1; /* 0x14 */ uint32 VDL_OVERRIDE_2; /* 0x18 */ uint32 VDL_OVERRIDE_3; /* 0x1c */ uint32 VDL_OVERRIDE_4; /* 0x20 */ uint32 VDL_OVERRIDE_5; /* 0x24 */ uint32 VDL_OVERRIDE_6; /* 0x28 */ uint32 VDL_OVERRIDE_7; /* 0x2c */ uint32 READ_CONTROL; /* 0x30 */ uint32 READ_FIFO_STATUS; /* 0x34 */ uint32 READ_FIFO_CLEAR; /* 0x38 */ uint32 IDLE_PAD_CONTROL; /* 0x3c */ uint32 DRIVE_PAD_CTL; /* 0x40 */ uint32 CLOCK_PAD_DISABLE; /* 0x44 */ uint32 WR_PREAMBLE_MODE; /* 0x48 */ uint32 CLOCK_REG_CONTROL; /* 0x4C */ uint32 unused0[44]; } DDRPhyByteLaneControl; typedef struct DDRControl { uint32 CNFG; /* 0x000 */ uint32 CSST; /* 0x004 */ uint32 CSEND; /* 0x008 */ uint32 unused; /* 0x00c */ uint32 ROW00_0; /* 0x010 */ uint32 ROW00_1; /* 0x014 */ uint32 ROW01_0; /* 0x018 */ uint32 ROW01_1; /* 0x01c */ uint32 unused0[4]; uint32 ROW20_0; /* 0x030 */ uint32 ROW20_1; /* 0x034 */ uint32 ROW21_0; /* 0x038 */ uint32 ROW21_1; /* 0x03c */ uint32 unused1[4]; uint32 COL00_0; /* 0x050 */ uint32 COL00_1; /* 0x054 */ uint32 COL01_0; /* 0x058 */ uint32 COL01_1; /* 0x05c */ uint32 unused2[4]; uint32 COL20_0; /* 0x070 */ uint32 COL20_1; /* 0x074 */ uint32 COL21_0; /* 0x078 */ uint32 COL21_1; /* 0x07c */ uint32 unused3[4]; uint32 BNK10; /* 0x090 */ uint32 BNK32; /* 0x094 */ uint32 unused4[26]; uint32 DCMD; /* 0x100 */ #define DCMD_CS1 (1 << 5) #define DCMD_CS0 (1 << 4) #define DCMD_SET_SREF 4 uint32 DMODE_0; /* 0x104 */ uint32 DMODE_1; /* 0x108 */ #define DMODE_1_DRAMSLEEP (1 << 11) uint32 CLKS; /* 0x10c */ uint32 ODT; /* 0x110 */ uint32 TIM1_0; /* 0x114 */ uint32 TIM1_1; /* 0x118 */ uint32 TIM2; /* 0x11c */ uint32 CTL_CRC; /* 0x120 */ uint32 DOUT_CRC; /* 0x124 */ uint32 DIN_CRC; /* 0x128 */ uint32 unused5[53]; DDRPhyControl PhyControl; /* 0x200 */ DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ uint32 unused6[64]; uint32 GCFG; /* 0x800 */ uint32 LBIST_CFG; /* 0x804 */ uint32 LBIST_SEED; /* 0x808 */ uint32 ARB; /* 0x80c */ uint32 PI_GCF; /* 0x810 */ uint32 PI_UBUS_CTL; /* 0x814 */ uint32 PI_MIPS_CTL; /* 0x818 */ uint32 PI_DSL_MIPS_CTL; /* 0x81c */ uint32 PI_DSL_PHY_CTL; /* 0x820 */ uint32 PI_UBUS_ST; /* 0x824 */ uint32 PI_MIPS_ST; /* 0x828 */ uint32 PI_DSL_MIPS_ST; /* 0x82c */ uint32 PI_DSL_PHY_ST; /* 0x830 */ uint32 PI_UBUS_SMPL; /* 0x834 */ uint32 TESTMODE; /* 0x838 */ uint32 TEST_CFG1; /* 0x83c */ uint32 TEST_PAT; /* 0x840 */ uint32 TEST_COUNT; /* 0x844 */ uint32 TEST_CURR_COUNT; /* 0x848 */ uint32 TEST_ADDR_UPDT; /* 0x84c */ uint32 TEST_ADDR; /* 0x850 */ uint32 TEST_DATA0; /* 0x854 */ uint32 TEST_DATA1; /* 0x858 */ uint32 TEST_DATA2; /* 0x85c */ uint32 TEST_DATA3; /* 0x860 */ } DDRControl; #define DDR ((volatile DDRControl * const) DDR_BASE) /* ** Peripheral Controller */ #define IRQ_BITS 64 typedef struct { uint64 IrqMask; uint64 IrqStatus; } IrqControl_t; typedef struct PerfControl { uint32 RevID; /* (00) word 0 */ uint32 blkEnables; /* (04) word 1 */ #define NAND_CLK_EN (1 << 20) #define PHYMIPS_CLK_EN (1 << 19) #define FAP_CLK_EN (1 << 18) #define PCIE_CLK_EN (1 << 17) #define HS_SPI_CLK_EN (1 << 16) #define SPI_CLK_EN (1 << 15) #define IPSEC_CLK_EN (1 << 14) #define USBH_CLK_EN (1 << 13) #define USBD_CLK_EN (1 << 12) #define PCM_CLK_EN (1 << 11) #define ROBOSW_CLK_EN (1 << 10) #define SAR_CLK_EN (1 << 9) #define SWPKT_SAR_CLK_EN (1 << 8) #define SWPKT_USB_CLK_EN (1 << 7) #define WLAN_OCP_CLK_EN (1 << 5) #define MIPS_CLK_EN (1 << 4) #define ADSL_CLK_EN (1 << 3) #define ADSL_AFE_EN (1 << 2) #define ADSL_QPROC_EN (1 << 1) #define DISABLE_GLESS (1 << 0) uint32 pll_control; /* (08) word 2 */ #define SOFT_RESET 0x00000001 // 0 uint32 deviceTimeoutEn; /* (0c) word 3 */ uint32 softResetB; /* (10) word 4 */ #define SOFT_RST_WLAN_SHIM_UBUS (1 << 14) #define SOFT_RST_FAP (1 << 13) #define SOFT_RST_DDR_PHY (1 << 12) #define SOFT_RST_WLAN_SHIM (1 << 11) #define SOFT_RST_PCIE_EXT (1 << 10) #define SOFT_RST_PCIE (1 << 9) #define SOFT_RST_PCIE_CORE (1 << 8) #define SOFT_RST_PCM (1 << 7) #define SOFT_RST_USBH (1 << 6) #define SOFT_RST_USBD (1 << 5) #define SOFT_RST_SWITCH (1 << 4) #define SOFT_RST_SAR (1 << 3) #define SOFT_RST_EPHY (1 << 2) #define SOFT_RST_IPSEC (1 << 1) #define SOFT_RST_SPI (1 << 0) uint32 diagControl; /* (14) word 5 */ uint32 ExtIrqCfg; /* (18) word 6*/ uint32 unused1; /* (1c) word 7 */ #define EI_SENSE_SHFT 0 #define EI_STATUS_SHFT 4 #define EI_CLEAR_SHFT 8 #define EI_MASK_SHFT 12 #define EI_INSENS_SHFT 16 #define EI_LEVEL_SHFT 20 IrqControl_t IrqControl[2]; } PerfControl; #define PERF ((volatile PerfControl * const) PERF_BASE) /* ** Timer */ typedef struct Timer { uint16 unused0; byte TimerMask; #define TIMER0EN 0x01 #define TIMER1EN 0x02 #define TIMER2EN 0x04 byte TimerInts; #define TIMER0 0x01 #define TIMER1 0x02 #define TIMER2 0x04 #define WATCHDOG 0x08 uint32 TimerCtl0; uint32 TimerCtl1; uint32 TimerCtl2; #define TIMERENABLE 0x80000000 #define RSTCNTCLR 0x40000000 uint32 TimerCnt0; uint32 TimerCnt1; uint32 TimerCnt2; uint32 WatchDogDefCount; /* Write 0xff00 0x00ff to Start timer * Write 0xee00 0x00ee to Stop and re-load default count * Read from this register returns current watch dog count */ uint32 WatchDogCtl; /* Number of 50-MHz ticks for WD Reset pulse to last */ uint32 WDResetCount; } Timer; #define TIMER ((volatile Timer * const) TIMR_BASE) /* ** UART */ typedef struct UartChannel { byte unused0; byte control; #define BRGEN 0x80 /* Control register bit defs */ #define TXEN 0x40 #define RXEN 0x20 #define LOOPBK 0x10 #define TXPARITYEN 0x08 #define TXPARITYEVEN 0x04 #define RXPARITYEN 0x02 #define RXPARITYEVEN 0x01 byte config; #define XMITBREAK 0x40 #define BITS5SYM 0x00 #define BITS6SYM 0x10 #define BITS7SYM 0x20 #define BITS8SYM 0x30 #define ONESTOP 0x07 #define TWOSTOP 0x0f /* 4-LSBS represent STOP bits/char * in 1/8 bit-time intervals. Zero * represents 1/8 stop bit interval. * Fifteen represents 2 stop bits. */ byte fifoctl; #define RSTTXFIFOS 0x80 #define RSTRXFIFOS 0x40 /* 5-bit TimeoutCnt is in low bits of this register. * This count represents the number of characters * idle times before setting receive Irq when below threshold */ uint32 baudword; /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate */ byte txf_levl; /* Read-only fifo depth */ byte rxf_levl; /* Read-only fifo depth */ byte fifocfg; /* Upper 4-bits are TxThresh, Lower are * RxThreshold. Irq can be asserted * when rx fifo> thresh, txfifoUserBits[((sizeof(OTP->UserBits)/4) - (x)/32 - 1)] >> ((x) % 32)) & 1) /* ** Spi Controller */ typedef struct SpiControl { uint16 spiMsgCtl; /* (0x0) control byte */ #define FULL_DUPLEX_RW 0 #define HALF_DUPLEX_W 1 #define HALF_DUPLEX_R 2 #define SPI_MSG_TYPE_SHIFT 14 #define SPI_BYTE_CNT_SHIFT 0 byte spiMsgData[0x21e]; /* (0x02 - 0x21f) msg data */ byte unused0[0x1e0]; byte spiRxDataFifo[0x220]; /* (0x400 - 0x61f) rx data */ byte unused1[0xe0]; uint16 spiCmd; /* (0x700): SPI command */ #define SPI_CMD_NOOP 0 #define SPI_CMD_SOFT_RESET 1 #define SPI_CMD_HARD_RESET 2 #define SPI_CMD_START_IMMEDIATE 3 #define SPI_CMD_COMMAND_SHIFT 0 #define SPI_CMD_COMMAND_MASK 0x000f #define SPI_CMD_DEVICE_ID_SHIFT 4 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 #define SPI_CMD_ONE_BYTE_SHIFT 11 #define SPI_CMD_ONE_WIRE_SHIFT 12 #define SPI_DEV_ID_0 0 #define SPI_DEV_ID_1 1 #define SPI_DEV_ID_2 2 #define SPI_DEV_ID_3 3 byte spiIntStatus; /* (0x702): SPI interrupt status */ byte spiMaskIntStatus; /* (0x703): SPI masked interrupt status */ byte spiIntMask; /* (0x704): SPI interrupt mask */ #define SPI_INTR_CMD_DONE 0x01 #define SPI_INTR_RX_OVERFLOW 0x02 #define SPI_INTR_INTR_TX_UNDERFLOW 0x04 #define SPI_INTR_TX_OVERFLOW 0x08 #define SPI_INTR_RX_UNDERFLOW 0x10 #define SPI_INTR_CLEAR_ALL 0x1f byte spiStatus; /* (0x705): SPI status */ #define SPI_RX_EMPTY 0x02 #define SPI_CMD_BUSY 0x04 #define SPI_SERIAL_BUSY 0x08 byte spiClkCfg; /* (0x706): SPI clock configuration */ #define SPI_CLK_0_391MHZ 1 #define SPI_CLK_0_781MHZ 2 /* default */ #define SPI_CLK_1_563MHZ 3 #define SPI_CLK_3_125MHZ 4 #define SPI_CLK_6_250MHZ 5 #define SPI_CLK_12_50MHZ 6 #define SPI_CLK_MASK 0x07 #define SPI_SSOFFTIME_MASK 0x38 #define SPI_SSOFFTIME_SHIFT 3 #define SPI_BYTE_SWAP 0x80 byte spiFillByte; /* (0x707): SPI fill byte */ byte unused2; byte spiMsgTail; /* (0x709): msgtail */ byte unused3; byte spiRxTail; /* (0x70B): rxtail */ } SpiControl; #define SPI ((volatile SpiControl * const) SPI_BASE) /* ** High-Speed SPI Controller */ #define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) typedef struct HsSpiControl { uint32 hs_spiGlobalCtrl; // 0x0000 #define HS_SPI_MOSI_IDLE (1 << 18) #define HS_SPI_CLK_POLARITY (1 << 17) #define HS_SPI_CLK_GATE_SSOFF (1 << 16) #define HS_SPI_PLL_CLK_CTRL (8) #define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) #define HS_SPI_SS_POLARITY (0) #define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) uint32 hs_spiExtTrigCtrl; // 0x0004 #define HS_SPI_TRIG_RAW_STATE (24) #define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) #define HS_SPI_TRIG_LATCHED (16) #define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) #define HS_SPI_TRIG_SENSE (8) #define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) #define HS_SPI_TRIG_TYPE (0) #define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) #define HS_SPI_TRIG_TYPE_EDGE (0) #define HS_SPI_TRIG_TYPE_LEVEL (1) uint32 hs_spiIntStatus; // 0x0008 #define HS_SPI_IRQ_PING1_USER (28) #define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) #define HS_SPI_IRQ_PING0_USER (24) #define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) #define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) #define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) #define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) uint32 hs_spiIntStatusMasked; // 0x000C #define HS_SPI_IRQSM__PING1_USER (28) #define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) #define HS_SPI_IRQSM__PING0_USER (24) #define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) #define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) #define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) #define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) uint32 hs_spiIntMask; // 0x0010 #define HS_SPI_IRQM_PING1_USER (28) #define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) #define HS_SPI_IRQM_PING0_USER (24) #define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) #define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) #define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) #define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) #define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) uint32 hs_spiFlashCtrl; // 0x0014 #define HS_SPI_FCTRL_MB_ENABLE (1 << 23) #define HS_SPI_FCTRL_SS_NUM (20) #define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) #define HS_SPI_FCTRL_PROFILE_NUM (16) #define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) #define HS_SPI_FCTRL_DUMMY_BYTES (10) #define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) #define HS_SPI_FCTRL_ADDR_BYTES (8) #define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) #define HS_SPI_FCTRL_ADDR_BYTES_2 (0) #define HS_SPI_FCTRL_ADDR_BYTES_3 (1) #define HS_SPI_FCTRL_ADDR_BYTES_4 (2) #define HS_SPI_FCTRL_READ_OPCODE (0) #define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) uint32 hs_spiFlashAddrBase; // 0x0018 char fill0[0x80 - 0x18]; uint32 hs_spiPP_0_Cmd; // 0x0080 #define HS_SPI_PP_SS_NUM (12) #define HS_SPI_PP_SS_NUM_MASK __mask(14, HS_SPI_PP_SS_NUM) #define HS_SPI_PP_PROFILE_NUM (8) #define HS_SPI_PP_PROFILE_NUM_MASK __mask(10, HS_SPI_PP_PROFILE_NUM) } HsSpiControl; typedef struct HsSpiPingPong { uint32 command; #define HS_SPI_SS_NUM (12) #define HS_SPI_PROFILE_NUM (8) #define HS_SPI_TRIGGER_NUM (4) #define HS_SPI_COMMAND_VALUE (0) #define HS_SPI_COMMAND_NOOP (0) #define HS_SPI_COMMAND_START_NOW (1) #define HS_SPI_COMMAND_START_TRIGGER (2) #define HS_SPI_COMMAND_HALT (3) #define HS_SPI_COMMAND_FLUSH (4) uint32 status; #define HS_SPI_ERROR_BYTE_OFFSET (16) #define HS_SPI_WAIT_FOR_TRIGGER (2) #define HS_SPI_SOURCE_BUSY (1) #define HS_SPI_SOURCE_GNT (0) uint32 fifo_status; uint32 control; } HsSpiPingPong; typedef struct HsSpiProfile { uint32 clk_ctrl; #define HS_SPI_ACCUM_RST_ON_LOOP (15) #define HS_SPI_SPI_CLK_2X_SEL (14) #define HS_SPI_FREQ_CTRL_WORD (0) uint32 signal_ctrl; #define HS_SPI_ASYNC_INPUT_PATH (1 << 16) #define HS_SPI_LAUNCH_RISING (1 << 13) #define HS_SPI_LATCH_RISING (1 << 12) uint32 mode_ctrl; #define HS_SPI_PREPENDBYTE_CNT (24) #define HS_SPI_MODE_ONE_WIRE (20) #define HS_SPI_MULTIDATA_WR_SIZE (18) #define HS_SPI_MULTIDATA_RD_SIZE (16) #define HS_SPI_MULTIDATA_WR_STRT (12) #define HS_SPI_MULTIDATA_RD_STRT (8) #define HS_SPI_FILLBYTE (0) uint32 polling_config; uint32 polling_and_mask; uint32 polling_compare; uint32 polling_timeout; uint32 reserved; } HsSpiProfile; #define HS_SPI_OP_CODE 13 #define HS_SPI_OP_SLEEP (0) #define HS_SPI_OP_READ_WRITE (1) #define HS_SPI_OP_WRITE (2) #define HS_SPI_OP_READ (3) #define HS_SPI_OP_SETIRQ (4) #define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) #define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) #define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) #define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) #define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) #define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) /* ** Misc Register Set Definitions. */ typedef struct Misc { uint32 unused1; /* 0x00 */ uint32 miscSerdesCtrl; /* 0x04 */ #define SERDES_PCIE_ENABLE 0x00000001 #define SERDES_PCIE_EXD_ENABLE (1<<15) uint32 miscSerdesSts; /* 0x08 */ uint32 miscIrqOutMask; /* 0x0C */ #define MISC_PCIE_EP_IRQ_MASK0 (1<<0) #define MISC_PCIE_EP_IRQ_MASK1 (1<<1) uint32 miscMemcControl; /* 0x10 */ #define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE (1<<3) #define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE (1<<2) #define MISC_MEMC_CONTROL_DDR_TEST_DONE (1<<1) #define MISC_MEMC_CONTROL_DDR_TEST_DISABLE (1<<0) uint32 miscStrapBus; /* 0x14 */ #define MISC_STRAP_BUS_RESET_CFG_DELAY (1<<18) #define MISC_STRAP_BUS_RESET_OUT_SHIFT 16 #define MISC_STRAP_BUS_RESET_OUT_MASK (3<>8)&0xf) #define UDC20_INTF(x) ((x>>4)&0xf) #define UDC20_CFG(x) ((x>>0)&0xf) uint32 usbd_status; #define USBD_LINK (0x1<<10) #define USBD_SET_CSRS 0x40 #define USBD_SUSPEND 0x20 #define USBD_EARLY_SUSPEND 0x10 #define USBD_SOF 0x08 #define USBD_ENUMON 0x04 #define USBD_SETUP 0x02 #define USBD_USBRESET 0x01 uint32 usbd_events; uint32 usbd_events_irq; #define UPPER(x) (16+x) #define ENABLE(x) (1<