--- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -13,14 +13,6 @@ #ifndef _MT7620_REGS_H_ #define _MT7620_REGS_H_ -enum mt762x_soc_type { - MT762X_SOC_UNKNOWN = 0, - MT762X_SOC_MT7620A, - MT762X_SOC_MT7620N, - MT762X_SOC_MT7628AN, -}; -extern enum mt762x_soc_type mt762x_soc; - #define MT7620_SYSC_BASE 0x10000000 #define SYSC_REG_CHIP_NAME0 0x00 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h @@ -13,6 +13,20 @@ #ifndef _RALINK_REGS_H_ #define _RALINK_REGS_H_ +enum ralink_soc_type { + RALINK_UNKNOWN = 0, + RT305X_SOC_RT3050, + RT305X_SOC_RT3052, + RT305X_SOC_RT3350, + RT305X_SOC_RT3352, + RT305X_SOC_RT5350, + MT762X_SOC_MT7620A, + MT762X_SOC_MT7620N, + MT762X_SOC_MT7621AT, + MT762X_SOC_MT7628AN, +}; +extern enum ralink_soc_type ralink_soc; + extern __iomem void *rt_sysc_membase; extern __iomem void *rt_memc_membase; --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -13,25 +13,16 @@ #ifndef _RT305X_REGS_H_ #define _RT305X_REGS_H_ -enum rt305x_soc_type { - RT305X_SOC_UNKNOWN = 0, - RT305X_SOC_RT3050, - RT305X_SOC_RT3052, - RT305X_SOC_RT3350, - RT305X_SOC_RT3352, - RT305X_SOC_RT5350, -}; - -extern enum rt305x_soc_type rt305x_soc; +extern enum ralink_soc_type ralink_soc; static inline int soc_is_rt3050(void) { - return rt305x_soc == RT305X_SOC_RT3050; + return ralink_soc == RT305X_SOC_RT3050; } static inline int soc_is_rt3052(void) { - return rt305x_soc == RT305X_SOC_RT3052; + return ralink_soc == RT305X_SOC_RT3052; } static inline int soc_is_rt305x(void) @@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void) static inline int soc_is_rt3350(void) { - return rt305x_soc == RT305X_SOC_RT3350; + return ralink_soc == RT305X_SOC_RT3350; } static inline int soc_is_rt3352(void) { - return rt305x_soc == RT305X_SOC_RT3352; + return ralink_soc == RT305X_SOC_RT3352; } static inline int soc_is_rt5350(void) { - return rt305x_soc == RT305X_SOC_RT5350; + return ralink_soc == RT305X_SOC_RT5350; } #define RT305X_SYSC_BASE 0x10000000 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -43,8 +43,6 @@ #define CLKCFG_FFRAC_MASK 0x001f #define CLKCFG_FFRAC_USB_VAL 0x0003 -enum mt762x_soc_type mt762x_soc; - /* does the board have sdram or ddram */ static int dram_type; @@ -375,7 +373,7 @@ void __init ralink_clk_init(void) #define RINT(x) ((x) / 1000000) #define RFRAC(x) (((x) / 1000) % 1000) - if (mt762x_soc == MT762X_SOC_MT7628AN) { + if (ralink_soc == MT762X_SOC_MT7628AN) { if (xtal_rate == MHZ(40)) cpu_rate = MHZ(580); else @@ -420,7 +418,7 @@ void __init ralink_clk_init(void) ralink_clk_add("10000e00.uart2", periph_rate); ralink_clk_add("10180000.wmac", xtal_rate); - if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) { + if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) { /* * When the CPU goes into sleep mode, the BUS clock will be too low for * USB to function properly @@ -508,11 +506,11 @@ void prom_soc_init(struct ralink_soc_inf if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { if (bga) { - mt762x_soc = MT762X_SOC_MT7620A; + ralink_soc = MT762X_SOC_MT7620A; name = "MT7620A"; soc_info->compatible = "ralink,mt7620a-soc"; } else { - mt762x_soc = MT762X_SOC_MT7620N; + ralink_soc = MT762X_SOC_MT7620N; name = "MT7620N"; soc_info->compatible = "ralink,mt7620n-soc"; #ifdef CONFIG_PCI @@ -520,7 +518,7 @@ void prom_soc_init(struct ralink_soc_inf #endif } } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { - mt762x_soc = MT762X_SOC_MT7628AN; + ralink_soc = MT762X_SOC_MT7628AN; name = "MT7628AN"; soc_info->compatible = "ralink,mt7628an-soc"; } else { @@ -537,7 +535,7 @@ void prom_soc_init(struct ralink_soc_inf dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; soc_info->mem_base = MT7620_DRAM_BASE; - if (mt762x_soc == MT762X_SOC_MT7628AN) + if (ralink_soc == MT762X_SOC_MT7628AN) mt7628_dram_init(soc_info); else mt7620_dram_init(soc_info); @@ -550,7 +548,7 @@ void prom_soc_init(struct ralink_soc_inf pr_info("Digital PMU set to %s control\n", (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - if (mt762x_soc == MT762X_SOC_MT7628AN) + if (ralink_soc == MT762X_SOC_MT7628AN) rt2880_pinmux_data = mt7628an_pinmux_data; else rt2880_pinmux_data = mt7620a_pinmux_data; --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -21,8 +21,6 @@ #include "common.h" -enum rt305x_soc_type rt305x_soc; - static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; static struct rt2880_pmx_func uartf_func[] = { @@ -234,24 +232,24 @@ void prom_soc_init(struct ralink_soc_inf icache_sets = (read_c0_config1() >> 22) & 7; if (icache_sets == 1) { - rt305x_soc = RT305X_SOC_RT3050; + ralink_soc = RT305X_SOC_RT3050; name = "RT3050"; soc_info->compatible = "ralink,rt3050-soc"; } else { - rt305x_soc = RT305X_SOC_RT3052; + ralink_soc = RT305X_SOC_RT3052; name = "RT3052"; soc_info->compatible = "ralink,rt3052-soc"; } } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT3350; + ralink_soc = RT305X_SOC_RT3350; name = "RT3350"; soc_info->compatible = "ralink,rt3350-soc"; } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT3352; + ralink_soc = RT305X_SOC_RT3352; name = "RT3352"; soc_info->compatible = "ralink,rt3352-soc"; } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT5350; + ralink_soc = RT305X_SOC_RT5350; name = "RT5350"; soc_info->compatible = "ralink,rt5350-soc"; } else { --- a/arch/mips/ralink/prom.c +++ b/arch/mips/ralink/prom.c @@ -15,9 +15,13 @@ #include #include +#include + #include "common.h" struct ralink_soc_info soc_info; +enum ralink_soc_type ralink_soc; +EXPORT_SYMBOL_GPL(ralink_soc); const char *get_system_type(void) { --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -193,6 +193,7 @@ void prom_soc_init(struct ralink_soc_inf soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; soc_info->mem_base = MT7621_DRAM_BASE; + ralink_soc = MT762X_SOC_MT7621AT; rt2880_pinmux_data = mt7621_pinmux_data;