From 626d9efa74685720020e816f3a917b7591d3cf7a Mon Sep 17 00:00:00 2001 From: James <> Date: Sat, 26 Sep 2015 12:29:31 +0100 Subject: trunk-47048 --- target/linux/mvebu/Makefile | 25 + target/linux/mvebu/base-files.mk | 3 + target/linux/mvebu/base-files/etc/crontabs/root | 1 + target/linux/mvebu/base-files/etc/diag.sh | 32 ++ .../mvebu/base-files/etc/init.d/linksys_recovery | 20 + .../mvebu/base-files/etc/uci-defaults/01_leds | 32 ++ .../mvebu/base-files/etc/uci-defaults/02_network | 43 ++ .../mvebu/base-files/etc/uci-defaults/03_wireless | 39 ++ target/linux/mvebu/base-files/lib/mvebu.sh | 70 +++ .../mvebu/base-files/lib/preinit/06_set_iface_mac | 26 + .../mvebu/base-files/lib/preinit/81_linksys_syscfg | 36 ++ .../linux/mvebu/base-files/lib/upgrade/linksys.sh | 86 ++++ .../linux/mvebu/base-files/lib/upgrade/platform.sh | 50 ++ target/linux/mvebu/base-files/sbin/fan_ctrl.sh | 28 ++ target/linux/mvebu/config-3.18 | 355 ++++++++++++++ target/linux/mvebu/config-4.0 | 362 ++++++++++++++ .../arm/boot/dts/armada-385-linksys-caiman.dts | 320 ++++++++++++ .../arch/arm/boot/dts/armada-385-linksys-cobra.dts | 320 ++++++++++++ .../arch/arm/boot/dts/armada-385-linksys.dtsi | 301 ++++++++++++ target/linux/mvebu/image/Makefile | 214 ++++++++ .../mvebu/patches-3.18/001-add_mamba_support.patch | 388 +++++++++++++++ .../patches-3.18/002-add_mamba_powertables.patch | 103 ++++ .../mvebu/patches-3.18/003-add_mamba_switch.patch | 19 + .../mvebu/patches-3.18/004-mamba_disable_rtc.patch | 14 + .../007-fix_the_aurora_l2_cache_node.patch | 40 ++ .../008-armada-xp_consolidate_pinctrl_node.patch | 81 ++++ ...ode_alias_to_pinctrl_and_add_base_address.patch | 103 ++++ .../patches-3.18/011-use_pinctrl_node_alias.patch | 258 ++++++++++ .../012-move_ge_pinctrl_settings_for_rgmii.patch | 81 ++++ .../013-add_ge0_pinctrl_settings_for_gmii.patch | 31 ++ .../mvebu/patches-3.18/014-add_uartx_labels.patch | 58 +++ ...ove_armada_370_xp_pinctrl_node_definition.patch | 538 +++++++++++++++++++++ .../016-common_armada_xp_uart2_3_pinctrl.patch | 52 ++ ..._use_common_armada_xp_spi_pinctrl_setting.patch | 69 +++ ...normalize_pinctrl_entries_for_armada_socs.patch | 98 ++++ ...M-mvebu-Add-a-number-of-pinctrl-functions.patch | 65 +++ ...dd-Armada-385-Access-Point-Development-Bo.patch | 212 ++++++++ ...-mvebu-A385-AP-Enable-the-NAND-controller.patch | 34 ++ ...nctrl-mvebu-a38x-Add-UART1-muxing-options.patch | 37 ++ .../024-ARM-mvebu-a38x-Fix-node-names.patch | 85 ++++ .../025-ARM-mvebu-Use-arm_coherent_dma_ops.patch | 111 +++++ .../050-leds_tlc59116_document_binding.patch | 51 ++ .../051-leds_tlc59116_add_driver.patch | 297 ++++++++++++ ...bu-Update-cpuidle-thresholds-for-Armada-X.patch | 66 +++ .../patches-3.18/099-build_linksys_a385_dts.patch | 11 + .../mvebu/patches-3.18/100-find_active_root.patch | 61 +++ .../mvebu/patches-3.18/102-revert_i2c_delay.patch | 15 + .../mvebu/patches-3.18/140-alias_mdio_node.patch | 11 + ...q-dt_platform_data_for_independent_clocks.patch | 44 ++ .../patches-3.18/198-gpio_mvebu_suspend.patch | 137 ++++++ .../patches-3.18/199-gpio_mvebu_drop_owner.patch | 15 + .../200-gpio_mvebu_checkpatch_fixes.patch | 223 +++++++++ ...201-gpio_mvebu_fix_probe_cleanup_on_error.patch | 63 +++ .../202-gpio_mvebu_add_limited_pwm_support.patch | 433 +++++++++++++++++ ..._extend_mvebu_gpio_documentation_with_pwm.patch | 52 ++ ...mvebu_xp_add_pwm_properties_to_dtsi_files.patch | 149 ++++++ .../205-arm_mvebu_enable_pwm_in_defconfig.patch | 18 + ...rt1900ac_use_pwm-fan_rather_than_gpio-fan.patch | 28 ++ .../207-armada-385-rd-mtd-partitions.patch | 19 + .../208-ARM-mvebu-385-ap-Add-partitions.patch | 34 ++ .../patches-3.18/300-add_missing_labels.patch | 29 ++ .../mvebu/patches-3.18/600-armada_38x_rtc.patch | 403 +++++++++++++++ .../700-usb_xhci_plat_phy_support.patch | 47 ++ .../mvebu/patches-4.0/001-add_mamba_support.patch | 388 +++++++++++++++ .../patches-4.0/002-add_mamba_powertables.patch | 103 ++++ .../mvebu/patches-4.0/003-add_mamba_switch.patch | 19 + .../patches-4.0/005-build_linksys_a385_dts.patch | 11 + ...-mvebu-A385-AP-Enable-the-NAND-controller.patch | 34 ++ .../050-leds_tlc59116_document_binding.patch | 51 ++ .../patches-4.0/051-leds_tlc59116_add_driver.patch | 297 ++++++++++++ .../mvebu/patches-4.0/100-find_active_root.patch | 61 +++ .../mvebu/patches-4.0/102-revert_i2c_delay.patch | 15 + .../202-gpio_mvebu_add_limited_pwm_support.patch | 433 +++++++++++++++++ ..._extend_mvebu_gpio_documentation_with_pwm.patch | 52 ++ ...mvebu_xp_add_pwm_properties_to_dtsi_files.patch | 149 ++++++ .../205-arm_mvebu_enable_pwm_in_defconfig.patch | 18 + ...rt1900ac_use_pwm-fan_rather_than_gpio-fan.patch | 28 ++ .../207-armada-385-rd-mtd-partitions.patch | 19 + .../208-ARM-mvebu-385-ap-Add-partitions.patch | 34 ++ .../mvebu/patches-4.0/300-add_missing_labels.patch | 11 + .../700-usb_xhci_plat_phy_support.patch | 47 ++ target/linux/mvebu/profiles/000-Default.mk | 26 + target/linux/mvebu/profiles/globalscale.mk | 21 + target/linux/mvebu/profiles/linksys.mk | 65 +++ target/linux/mvebu/profiles/marvell.mk | 95 ++++ target/linux/mvebu/profiles/plathome.mk | 21 + 86 files changed, 9044 insertions(+) create mode 100644 target/linux/mvebu/Makefile create mode 100644 target/linux/mvebu/base-files.mk create mode 100644 target/linux/mvebu/base-files/etc/crontabs/root create mode 100644 target/linux/mvebu/base-files/etc/diag.sh create mode 100755 target/linux/mvebu/base-files/etc/init.d/linksys_recovery create mode 100644 target/linux/mvebu/base-files/etc/uci-defaults/01_leds create mode 100644 target/linux/mvebu/base-files/etc/uci-defaults/02_network create mode 100644 target/linux/mvebu/base-files/etc/uci-defaults/03_wireless create mode 100755 target/linux/mvebu/base-files/lib/mvebu.sh create mode 100644 target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac create mode 100644 target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg create mode 100644 target/linux/mvebu/base-files/lib/upgrade/linksys.sh create mode 100755 target/linux/mvebu/base-files/lib/upgrade/platform.sh create mode 100755 target/linux/mvebu/base-files/sbin/fan_ctrl.sh create mode 100644 target/linux/mvebu/config-3.18 create mode 100644 target/linux/mvebu/config-4.0 create mode 100644 target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts create mode 100644 target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts create mode 100644 target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi create mode 100644 target/linux/mvebu/image/Makefile create mode 100644 target/linux/mvebu/patches-3.18/001-add_mamba_support.patch create mode 100644 target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch create mode 100644 target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch create mode 100644 target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch create mode 100644 target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch create mode 100644 target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch create mode 100644 target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch create mode 100644 target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch create mode 100644 target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch create mode 100644 target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch create mode 100644 target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch create mode 100644 target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch create mode 100644 target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch create mode 100644 target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch create mode 100644 target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch create mode 100644 target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch create mode 100644 target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch create mode 100644 target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch create mode 100644 target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch create mode 100644 target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch create mode 100644 target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch create mode 100644 target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch create mode 100644 target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch create mode 100644 target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch create mode 100644 target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch create mode 100644 target/linux/mvebu/patches-3.18/100-find_active_root.patch create mode 100644 target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch create mode 100644 target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch create mode 100644 target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch create mode 100644 target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch create mode 100644 target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch create mode 100644 target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch create mode 100644 target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch create mode 100644 target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch create mode 100644 target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch create mode 100644 target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch create mode 100644 target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch create mode 100644 target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch create mode 100644 target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch create mode 100644 target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch create mode 100644 target/linux/mvebu/patches-3.18/300-add_missing_labels.patch create mode 100644 target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch create mode 100644 target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch create mode 100644 target/linux/mvebu/patches-4.0/001-add_mamba_support.patch create mode 100644 target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch create mode 100644 target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch create mode 100644 target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch create mode 100644 target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch create mode 100644 target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch create mode 100644 target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch create mode 100644 target/linux/mvebu/patches-4.0/100-find_active_root.patch create mode 100644 target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch create mode 100644 target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch create mode 100644 target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch create mode 100644 target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch create mode 100644 target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch create mode 100644 target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch create mode 100644 target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch create mode 100644 target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch create mode 100644 target/linux/mvebu/patches-4.0/300-add_missing_labels.patch create mode 100644 target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch create mode 100644 target/linux/mvebu/profiles/000-Default.mk create mode 100644 target/linux/mvebu/profiles/globalscale.mk create mode 100644 target/linux/mvebu/profiles/linksys.mk create mode 100644 target/linux/mvebu/profiles/marvell.mk create mode 100644 target/linux/mvebu/profiles/plathome.mk (limited to 'target/linux/mvebu') diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile new file mode 100644 index 0000000..5b09285 --- /dev/null +++ b/target/linux/mvebu/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=mvebu +BOARDNAME:=Marvell Armada 37x/38x/XP +FEATURES:=usb pci pcie gpio nand squashfs +CPU_TYPE:=cortex-a9 +CPU_SUBTYPE:=vfpv3 +MAINTAINER:=Imre Kaloz + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=zImage dtbs + +DEFAULT_PACKAGES += uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/mvebu/base-files.mk b/target/linux/mvebu/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/mvebu/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/mvebu/base-files/etc/crontabs/root b/target/linux/mvebu/base-files/etc/crontabs/root new file mode 100644 index 0000000..e692f57 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/crontabs/root @@ -0,0 +1 @@ +*/5 * * * * /sbin/fan_ctrl.sh diff --git a/target/linux/mvebu/base-files/etc/diag.sh b/target/linux/mvebu/base-files/etc/diag.sh new file mode 100644 index 0000000..6534ac3 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/diag.sh @@ -0,0 +1,32 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/mvebu.sh + +get_status_led() { + case $(mvebu_board_name) in + armada-xp-linksys-mamba) + status_led="mamba:white:power" + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/mvebu/base-files/etc/init.d/linksys_recovery b/target/linux/mvebu/base-files/etc/init.d/linksys_recovery new file mode 100755 index 0000000..60d7be0 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/init.d/linksys_recovery @@ -0,0 +1,20 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2015 OpenWrt.org + +START=97 +boot() { +. /lib/functions.sh +. /lib/mvebu.sh + +case $(mvebu_board_name) in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-xp-linksys-mamba) + # make sure auto_recovery in uboot is always on + AUTO_RECOVERY_ENA="`fw_printenv -n auto_recovery`" + if [ "$AUTO_RECOVERY_ENA" != "yes" ] ; then + fw_setenv auto_recovery yes + fi + # reset the boot counter + mtd resetbc s_env + ;; +esac +} diff --git a/target/linux/mvebu/base-files/etc/uci-defaults/01_leds b/target/linux/mvebu/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..50c2f8d --- /dev/null +++ b/target/linux/mvebu/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,32 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/mvebu.sh + +board=$(mvebu_board_name) + +case "$board" in +armada-385-linksys-caiman) + ucidef_set_led_netdev "wan" "WAN" "pca963x:caiman:white:wan" "eth0" + ucidef_set_led_usbdev "usb2" "USB2" "pca963x:caiman:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "pca963x:caiman:white:usb3_1" "2-1" + ;; +armada-385-linksys-cobra) + ucidef_set_led_netdev "wan" "WAN" "pca963x:cobra:white:wan" "eth0" + ucidef_set_led_usbdev "usb2" "USB2" "pca963x:cobra:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "pca963x:cobra:white:usb3_1" "2-1" + ;; +armada-xp-linksys-mamba) + ucidef_set_led_netdev "wan" "WAN" "mamba:white:wan" "eth1" + ucidef_set_led_usbdev "usb2" "USB2" "mamba:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "mamba:white:usb3_1" "2-2" + ;; + +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/mvebu/base-files/etc/uci-defaults/02_network b/target/linux/mvebu/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..d1ead03 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/uci-defaults/02_network @@ -0,0 +1,43 @@ +#!/bin/sh +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/mvebu.sh + +ucidef_set_interface_loopback + +board=$(mvebu_board_name) + +case "$board" in +armada-385-linksys-caiman) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +armada-385-linksys-cobra) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +armada-xp-linksys-mamba) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5" + ucidef_add_switch_vlan "switch0" "2" "4 6" + ;; +armada-385-db-ap) + ucidef_set_interfaces_lan_wan "eth0 eth1" "eth2" + ;; +armada-xp-gp) + ucidef_set_interface_lan "eth0 eth1 eth2 eth3" + ;; +*) + ucidef_set_interface_lan "eth0" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/mvebu/base-files/etc/uci-defaults/03_wireless b/target/linux/mvebu/base-files/etc/uci-defaults/03_wireless new file mode 100644 index 0000000..c5d670a --- /dev/null +++ b/target/linux/mvebu/base-files/etc/uci-defaults/03_wireless @@ -0,0 +1,39 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +[ ! -e /etc/config/wireless ] && exit 0 + +. /lib/mvebu.sh + +board=$(mvebu_board_name) + +case "$board" in +armada-385-linksys-caiman|armada-385-linksys-cobra|armada-xp-linksys-mamba) + SKU=$(strings /dev/mtd3|sed -ne 's/^cert_region=//p') + case "$SKU" in + AP) + REGD=CN + ;; + AU) + REGD=AU + ;; + CA) + REGD=CA + ;; + EU) + REGD=DE + ;; + US) + REGD=US + ;; + esac + uci get wireless.radio0.country || uci set wireless.radio0.country=$REGD + uci get wireless.radio1.country || uci set wireless.radio1.country=$REGD + ;; +esac + +uci commit wireless + +exit 0 diff --git a/target/linux/mvebu/base-files/lib/mvebu.sh b/target/linux/mvebu/base-files/lib/mvebu.sh new file mode 100755 index 0000000..3edfa6b --- /dev/null +++ b/target/linux/mvebu/base-files/lib/mvebu.sh @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (C) 2013-2015 OpenWrt.org +# + +MVEBU_BOARD_NAME= +MVEBU_MODEL= + +mvebu_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + *"Marvell Armada 370 Evaluation Board") + name="armada-370-db" + ;; + *"Globalscale Mirabox") + name="mirabox" + ;; + *"Marvell Armada 370 Reference Design") + name="armada-370-rd" + ;; + *"Marvell Armada XP Evaluation Board") + name="armada-xp-db" + ;; + *"PlatHome OpenBlocks AX3-4 board") + name="openblocks-ax3-4" + ;; + *"Marvell Armada XP GP Board") + name="armada-xp-gp" + ;; + *"Linksys WRT1200AC") + name="armada-385-linksys-caiman" + ;; + *"Linksys WRT1900AC") + name="armada-xp-linksys-mamba" + ;; + *"Linksys WRT1900ACv2") + name="armada-385-linksys-cobra" + ;; + *"Marvell Armada 385 Access Point Development Board") + name="armada-385-db-ap" + ;; + *"Marvell Armada XP Development Board DB-MV784MP-GP") + name="armada-xp-gp" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$MVEBU_BOARD_NAME" ] && MVEBU_BOARD_NAME="$name" + [ -z "$MVEBU_MODEL" ] && MVEBU_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$MVEBU_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$MVEBU_MODEL" > /tmp/sysinfo/model +} + +mvebu_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] || mvebu_board_detect + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac b/target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac new file mode 100644 index 0000000..9fc8d9a --- /dev/null +++ b/target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac @@ -0,0 +1,26 @@ +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +preinit_set_mac_address() { + local mac + + . /lib/functions.sh + . /lib/mvebu.sh + + case $(mvebu_board_name) in + armada-xp-linksys-mamba) + mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + ifconfig eth0 hw ether $mac 2>/dev/null + ifconfig eth1 hw ether $mac 2>/dev/null + ;; + armada-385-linksys-caiman|armada-385-linksys-cobra) + mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + mac_wan=$(macaddr_setbit_la "$mac") + ifconfig eth1 hw ether $mac 2>/dev/null + ifconfig eth0 hw ether $mac_wan 2>/dev/null + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address diff --git a/target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg b/target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg new file mode 100644 index 0000000..d665cb1 --- /dev/null +++ b/target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg @@ -0,0 +1,36 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +preinit_mount_syscfg() { + + . /lib/functions.sh + . /lib/mvebu.sh + + case $(mvebu_board_name) in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-xp-linksys-mamba) + needs_recovery=0 + ubiattach -m 8 || needs_recovery=1 + if [ $needs_recovery -eq 1 ] + then + echo "ubifs syscfg partition is damaged, reformatting" + ubidetach -m 8 + ubiformat -y -O 2048 -q /dev/mtd8 + ubiattach -m 8 + ubimkvol /dev/ubi1 -n 0 -N syscfg -t dynamic --maxavsize + fi + mkdir /tmp/syscfg + mount -t ubifs ubi1:syscfg /tmp/syscfg + [ -f /tmp/syscfg/sysupgrade.tgz ] && { + echo "- config restore -" + cd / + mv /tmp/syscfg/sysupgrade.tgz /tmp + tar xzf /tmp/sysupgrade.tgz + rm -f /tmp/sysupgrade.tgz + sync + } + ;; + esac +} + +boot_hook_add preinit_main preinit_mount_syscfg diff --git a/target/linux/mvebu/base-files/lib/upgrade/linksys.sh b/target/linux/mvebu/base-files/lib/upgrade/linksys.sh new file mode 100644 index 0000000..fc40333 --- /dev/null +++ b/target/linux/mvebu/base-files/lib/upgrade/linksys.sh @@ -0,0 +1,86 @@ +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +linksys_get_target_firmware() { + cur_boot_part=`/usr/sbin/fw_printenv -n boot_part` + target_firmware="" + if [ "$cur_boot_part" = "1" ] + then + # current primary boot - update alt boot + target_firmware="kernel2" + fw_setenv boot_part 2 + fw_setenv bootcmd "run altnandboot" + elif [ "$cur_boot_part" = "2" ] + then + # current alt boot - update primary boot + target_firmware="kernel1" + fw_setenv boot_part 1 + fw_setenv bootcmd "run nandboot" + fi + + # re-enable recovery so we get back if the new firmware is broken + fw_setenv auto_recovery yes + + echo "$target_firmware" +} + +linksys_get_root_magic() { + (get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null +} + +platform_do_upgrade_linksys() { + local magic_long="$(get_magic_long "$1")" + + mkdir -p /var/lock + local part_label="$(linksys_get_target_firmware)" + touch /var/lock/fw_printenv.lock + + if [ ! -n "$part_label" ] + then + echo "cannot find target partition" + exit 1 + fi + + local target_mtd=$(find_mtd_part $part_label) + + [ "$magic_long" = "73797375" ] && { + CI_KERNPART="$part_label" + if [ "$part_label" = "kernel1" ] + then + CI_UBIPART="rootfs1" + else + CI_UBIPART="rootfs2" + fi + + nand_upgrade_tar "$1" + } + [ "$magic_long" = "27051956" ] && { + # check firmwares' rootfs types + local target_mtd=$(find_mtd_part $part_label) + local oldroot="$(linksys_get_root_magic $target_mtd)" + local newroot="$(linksys_get_root_magic "$1")" + + if [ "$newroot" = "55424923" -a "$oldroot" = "55424923" ] + # we're upgrading from a firmware with UBI to one with UBI + then + # erase everything to be safe + mtd erase $part_label + get_image "$1" | mtd -n write - $part_label + else + get_image "$1" | mtd write - $part_label + fi + } +} + +linksys_preupgrade() { + export RAMFS_COPY_BIN="${RAMFS_COPY_BIN} /usr/sbin/fw_printenv /usr/sbin/fw_setenv" + export RAMFS_COPY_BIN="${RAMFS_COPY_BIN} /bin/mkdir /bin/touch" + export RAMFS_COPY_DATA="${RAMFS_COPY_DATA} /etc/fw_env.config /var/lock/fw_printenv.lock" + + [ -f /tmp/sysupgrade.tgz ] && { + cp /tmp/sysupgrade.tgz /tmp/syscfg/sysupgrade.tgz + } +} + +append sysupgrade_pre_upgrade linksys_preupgrade diff --git a/target/linux/mvebu/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..5e9c04b --- /dev/null +++ b/target/linux/mvebu/base-files/lib/upgrade/platform.sh @@ -0,0 +1,50 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +. /lib/mvebu.sh + +RAMFS_COPY_DATA=/lib/mvebu.sh + +platform_check_image() { + local board=$(mvebu_board_name) + local magic_long="$(get_magic_long "$1")" + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-xp-linksys-mamba) + [ "$magic_long" != "27051956" -a "$magic_long" != "73797375" ] && { + echo "Invalid image type." + return 1 + } + return 0; + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(mvebu_board_name) + + case "$board" in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-xp-linksys-mamba) + platform_do_upgrade_linksys "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/mvebu/base-files/sbin/fan_ctrl.sh b/target/linux/mvebu/base-files/sbin/fan_ctrl.sh new file mode 100755 index 0000000..06e4621 --- /dev/null +++ b/target/linux/mvebu/base-files/sbin/fan_ctrl.sh @@ -0,0 +1,28 @@ +#!/bin/sh + +CPU_TEMP=`cut -c1-2 /sys/class/hwmon/hwmon2/temp1_input` +DDR_TEMP=`cut -c1-2 /sys/class/hwmon/hwmon1/temp1_input` +WIFI_TEMP=`cut -c1-2 /sys/class/hwmon/hwmon1/temp2_input` + +CPU_LOW=85 +CPU_HIGH=95 +DDR_LOW=65 +DDR_HIGH=75 +WIFI_LOW=100 +WIFI_HIGH=115 + +if [ -d /sys/devices/pwm_fan ];then + FAN_CTRL=/sys/devices/pwm_fan/hwmon/hwmon0/pwm1 +elif [ -d /sys/devices/platform/pwm_fan ];then + FAN_CTRL=/sys/devices/platform/pwm_fan/hwmon/hwmon0/pwm1 +else + exit 0 +fi + +if [ "$CPU_TEMP" -ge "$CPU_HIGH" -o "$DDR_TEMP" -ge "$DDR_HIGH" -o "$WIFI_TEMP" -ge "$WIFI_HIGH" ];then + echo "255" > $FAN_CTRL +elif [ "$CPU_TEMP" -ge "$CPU_LOW" -o "$DDR_TEMP" -ge "$DDR_LOW" -o "$WIFI_TEMP" -ge "$WIFI_LOW" ];then + echo "100" > $FAN_CTRL +else + echo "0" > $FAN_CTRL +fi diff --git a/target/linux/mvebu/config-3.18 b/target/linux/mvebu/config-3.18 new file mode 100644 index 0000000..a5eac43 --- /dev/null +++ b/target/linux/mvebu/config-3.18 @@ -0,0 +1,355 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARMADA_370_CLK=y +CONFIG_ARMADA_370_XP_TIMER=y +CONFIG_ARMADA_38X_CLK=y +CONFIG_ARMADA_XP_CLK=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_FEROCEON_L2 is not set +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PJ4B=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART=y +# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xd0012000 +# CONFIG_DEBUG_UART_PL01X is not set +CONFIG_DEBUG_UART_VIRT=0xfec12000 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_MVEBU_PWM=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_ARMADA_370=y +# CONFIG_MACH_ARMADA_375 is not set +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_XP=y +# CONFIG_MACH_DOVE is not set +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MACH_MVEBU_V7=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANGLE_BOOTARGS=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_CLK_COREDIV=y +CONFIG_MVEBU_CLK_CPU=y +CONFIG_MVEBU_DEVBUS=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +CONFIG_MVNETA=y +CONFIG_MVSW61XX_PHY=y +CONFIG_MV_XOR=y +CONFIG_NEED_DMA_MAP_STATE=y +# CONFIG_NEON is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_370=y +CONFIG_PINCTRL_ARMADA_38X=y +CONFIG_PINCTRL_ARMADA_XP=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PLAT_ORION=y +CONFIG_PM_OPP=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PWM=y +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_SYSFS=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_ARMADA38X is not set +# CONFIG_RTC_DRV_MV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_DW=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_STOP_MACHINE=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mvebu/config-4.0 b/target/linux/mvebu/config-4.0 new file mode 100644 index 0000000..a682f1f --- /dev/null +++ b/target/linux/mvebu/config-4.0 @@ -0,0 +1,362 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARMADA_370_CLK=y +CONFIG_ARMADA_370_XP_TIMER=y +CONFIG_ARMADA_38X_CLK=y +CONFIG_ARMADA_XP_CLK=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_FEROCEON_L2 is not set +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PJ4B=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART0=y +# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set +# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xd0012000 +CONFIG_DEBUG_UART_VIRT=0xfec12000 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_MVEBU_PWM=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_ARMADA_370=y +# CONFIG_MACH_ARMADA_375 is not set +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_XP=y +# CONFIG_MACH_DOVE is not set +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MACH_MVEBU_V7=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANGLE_BOOTARGS=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_CLK_COREDIV=y +CONFIG_MVEBU_CLK_CPU=y +CONFIG_MVEBU_DEVBUS=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +CONFIG_MVNETA=y +CONFIG_MVSW61XX_PHY=y +CONFIG_MV_XOR=y +CONFIG_NEED_DMA_MAP_STATE=y +# CONFIG_NEON is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +# CONFIG_PCI_DOMAINS_GENERIC is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_370=y +CONFIG_PINCTRL_ARMADA_38X=y +CONFIG_PINCTRL_ARMADA_XP=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PLAT_ORION=y +CONFIG_PM_OPP=y +CONFIG_PWM=y +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_SYSFS=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_DW=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts new file mode 100644 index 0000000..2c3b77f --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts @@ -0,0 +1,320 @@ +/* + * Device Tree include for the Linksys WRT1200AC (Caiman) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1200AC"; + compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "caiman:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "caiman:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "caiman:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "caiman:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "caiman:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "caiman:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "caiman:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "caiman:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "caiman:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + + pcie-controller { + pcie@1,0 { + mwlwifi { + marvell,2ghz = <0>; + marvell,chainmask = <2 2>; + marvell,powertable { + AU = + <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>; 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+ ETSI = + <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>; + FCC = + <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; + }; + }; + }; + + pcie@2,0 { + mwlwifi { + marvell,5ghz = <0>; + marvell,chainmask = <2 2>; + marvell,powertable { + AU = + <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; + CA = + <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>, + <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>; + CN = + <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; + ETSI = + <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; + FCC = + <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "caiman:white:power"; + }; + + sata { + label = "caiman:white:sata"; + }; + }; +}; diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts new file mode 100644 index 0000000..890cfa8 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts @@ -0,0 +1,320 @@ +/* + * Device Tree file for the Linksys WRT1900ACv2 (Cobra) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1900ACv2"; + compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "cobra:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "cobra:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "cobra:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "cobra:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "cobra:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "cobra:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "cobra:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "cobra:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "cobra:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + + pcie-controller { + pcie@1,0 { + mwlwifi { + marvell,2ghz = <0>; + marvell,chainmask = <4 4>; + marvell,powertable { + AU = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; + CA = + <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; + CN = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; + ETSI = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; + FCC = + <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, + <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; + }; + }; + }; + + pcie@2,0 { + mwlwifi { + marvell,5ghz = <0>; + marvell,chainmask = <4 4>; + marvell,powertable { + AU = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + CA = + <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; + CN = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + ETSI = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + FCC = + <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "cobra:white:power"; + }; + + sata { + label = "cobra:white:sata"; + }; + }; +}; diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi new file mode 100644 index 0000000..c6caa86 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -0,0 +1,301 @@ +/* + * Device Tree include file for Armada 385 based Linksys boards + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "armada-385.dtsi" + +/ { + model = "Linksys boards based on Armada 385"; + compatible = "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + spi@10600 { + status = "disabled"; + }; + + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9635"; + reg = <0x68>; + }; + }; + + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@34000 { + status = "okay"; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio { + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MB */ + }; + }; + + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { + label = "WPS"; + linux,code = ; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin &sata_led_pin>; + pinctrl-names = "default"; + + power { + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + sata { + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mvsw61xx { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,88e6176"; + status = "okay"; + reg = <0x10>; + + mii-bus = <&mdio>; + cpu-port-0 = <5>; + cpu-port-1 = <6>; + }; +}; + +&pinctrl { + keys_pin: keys-pin { + marvell,pins = "mpp24", "mpp29"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp55"; + marvell,function = "gpio"; + }; + + sata_led_pin: sata-led-pin { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; + + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; +}; diff --git a/target/linux/mvebu/image/Makefile b/target/linux/mvebu/image/Makefile new file mode 100644 index 0000000..7f270dd --- /dev/null +++ b/target/linux/mvebu/image/Makefile @@ -0,0 +1,214 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +JFFS2_BLOCKSIZE = 128k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +LOADADDR:=0x00008000 + +define Image/Build/DTB + cp $(KDIR)/zImage$(2) $(KDIR)/zImage$(2)-$(1); + cat $(DTS_DIR)/$(1).dtb >> $(KDIR)/zImage$(2)-$(1); + $(call Image/BuildKernel/MkuImage, \ + none, $(LOADADDR), $(LOADADDR), \ + $(KDIR)/zImage$(2)-$(1), $(KDIR)/uImage$(2)-$(1)) +endef + +# $(1): Profile Name +# $(2): DTB Name +# $(3): Erase Block Size +# $(4): Page Size +# $(5): Sub-Page Size (optional) +# $(6): VID offset (optional) +define NANDProfile + define Image/BuildKernel/Profile/$(1) + $(call Image/Build/DTB,$(2)) + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile,$(1)/Initramfs) + endif + endef + + define Image/Build/Profile/$(1)/BuildSysupgrade + $(call Image/Build/SysupgradeNAND,$(2),$$(1),$(KDIR)/uImage-$(2)) + endef + + define Image/Build/Profile/$(1)/Initramfs + $(call Image/Build/DTB,$(2),-initramfs) + cp $(KDIR)/uImage-initramfs-$(2) $(BIN_DIR)/$(IMG_PREFIX)-$(2)-initramfs + endef + + define Image/Build/Profile/$(1)/squashfs + $(call Image/Build/UbinizeImage,$(2),,squashfs, -p $(3) -m $(4) $(if $(5),-s $(5)) $(if $(6),-O $(6))) + endef + + PROFILES_LIST += $(1) +endef + +# $(1): Profile Name +# $(2): DTB Name +# $(3): Erase Block Size +define UBINORProfile + define Image/BuildKernel/Profile/$(1) + $(call Image/Build/DTB,$(2)) + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile,$(1)/Initramfs) + endif + endef + + define Image/Build/Profile/$(1)/Initramfs + $(call Image/Build/DTB,$(2),-initramfs) + endef + + define Image/Build/Profile/$(1)/squashfs + $(call Image/Build/UbinizeImage,$(2),,squashfs, -p $(3) -m 1) + endef + + PROFILES_LIST += $(1) +endef + +# $(1): Profile Name +# $(2): DTB Name +# $(3): Erase Block Size +define NORProfile + define Image/BuildKernel/Profile/$(1) + $(call Image/Build/DTB,$(2)) + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile,$(1)/Initramfs) + endif + endef + + define Image/Build/Profile/$(1)/Initramfs + $(call Image/Build/DTB,$(2),-initramfs) + endef + + define Image/Build/Profile/$(1)/squashfs + ( \ + dd if=$(KDIR)/uImage-$(2) bs=$(3) conv=sync; \ + dd if=$(KDIR)/root.squashfs bs=$(3) conv=sync; \ + ) > $$(BIN_DIR)/$$(IMG_PREFIX)-$(2)-squashfs-firmware.bin + endef + + PROFILES_LIST += $(1) +endef + +# $(1): Profile Name +# $(2): Sub Profiles list +define MultiProfile + define Image/BuildKernel/Profile/$(1) + $(foreach profile, $(2), + $(call Image/BuildKernel/Profile/$(profile))) + endef + + define Image/Build/Profile/$(1)/BuildSysupgrade + $(foreach profile, $(2), + $(call Image/Build/Profile/$(profile)/BuildSysupgrade,$$(1))) + endef + + define Image/Build/Profile/$(1)/Initramfs + $(foreach profile, $(2), + $(call Image/Build/Profile/$(profile)/Initramfs)) + endef + + define Image/Build/Profile/$(1)/squashfs + $(foreach profile, $(2), + $(call Image/Build/Profile/$(profile)/squashfs)) + endef +endef + +# Boards with NAND, without subpages +$(eval $(call NANDProfile,370-DB,armada-370-db,512KiB,4096)) +$(eval $(call NANDProfile,370-RD,armada-370-rd,512KiB,4096)) +$(eval $(call NANDProfile,385-DB-AP,armada-385-db-ap,256KiB,4096)) +$(eval $(call NANDProfile,Mirabox,armada-370-mirabox,512KiB,4096)) +$(eval $(call NANDProfile,XP-DB,armada-xp-db,512KiB,4096)) +$(eval $(call NANDProfile,XP-GP,armada-xp-gp,512KiB,4096)) + +# Boards with NAND, with subpages +$(eval $(call NANDProfile,Mamba,armada-xp-linksys-mamba,128KiB,2048,512,2048)) +$(eval $(call NANDProfile,Caiman,armada-385-linksys-caiman,128KiB,2048,512,2048)) +$(eval $(call NANDProfile,Cobra,armada-385-linksys-cobra,128KiB,2048,512,2048)) + +# Boards with large NOR, where we want to use UBI +$(eval $(call UBINORProfile,OpenBlocks-AX-3-4,armada-xp-openblocks-ax3-4,128KiB)) + +# Boards with small NOR, where UBI doesn't make sense +$(eval $(call NORProfile,385-RD,armada-385-rd,256KiB)) + +### +### Linksys +### + +# Caiman: Linksys WRT1200AC +define Image/Build/Profile/Caiman/squashfs + $(call Image/Build/UbinizeImage,armada-385-linksys-caiman,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-385-linksys-caiman bs=6M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-linksys-caiman-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-linksys-caiman-squashfs-factory.img +endef + +# Cobra: Linksys WRT1900ACv2 +define Image/Build/Profile/Cobra/squashfs + $(call Image/Build/UbinizeImage,armada-385-linksys-cobra,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-385-linksys-cobra bs=6M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-linksys-cobra-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-linksys-cobra-squashfs-factory.img +endef + +# Mamba: Linksys WRT1900AC +define Image/Build/Profile/Mamba/squashfs + $(call Image/Build/UbinizeImage,armada-xp-linksys-mamba,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-xp-linksys-mamba bs=3072k conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-xp-linksys-mamba-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-xp-linksys-mamba-squashfs-factory.img +endef + +### +### Marvell +### + +# Marvell Armada 385 Access Point Development board (DB-88F6820-AP) +define Image/Build/Profile/385-DB-AP/squashfs + $(call Image/Build/UbinizeImage,armada-385-db-ap,,squashfs, -p 256KiB -m 4096) + ( \ + dd if=$(KDIR)/uImage-armada-385-db-ap bs=8M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-db-ap-squashfs-ubinized.bin \ + bs=4096 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-db-ap-squashfs-factory.img +endef + + +# The Default profile should build everything +$(eval $(call MultiProfile,Default,$(PROFILES_LIST))) + +define Image/BuildKernel + $(call Image/BuildKernel/Profile/$(PROFILE)) +endef + +define Image/Build/squashfs + # Align the squashfs image size before calling the profiles, + # otherwise the size would keep growing + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + $(call Image/Build/Profile/$(PROFILE)/squashfs) +endef + +define Image/Build + $(call Image/Build/$(1)) + $(call Image/Build/Profile/$(PROFILE)/BuildSysupgrade,$(1)) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile/$(PROFILE)/Initramfs) +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/mvebu/patches-3.18/001-add_mamba_support.patch b/target/linux/mvebu/patches-3.18/001-add_mamba_support.patch new file mode 100644 index 0000000..44a1adc --- /dev/null +++ b/target/linux/mvebu/patches-3.18/001-add_mamba_support.patch @@ -0,0 +1,388 @@ +From 4824140f4bd1caaf900215aabe27e4bdd1677704 Mon Sep 17 00:00:00 2001 +From: Imre Kaloz +Date: Mon, 16 Feb 2015 13:31:04 +0100 +Subject: [PATCH] ARM: mvebu: add Linksys WRT1900AC (Mamba) support + +The Linksys WRT1900AC (Mamba) is a router that has + +- 2 mini-PCIe slots with Marvell 88W8864 radios +- 1 USB 3.0 port +- 1 USB 2.0/eSATAp port +- 2 Ethernet interfaces connected to a 88E6172 switch (1x WAN + 4x LAN) +- 128MB NAND flash +- 256MB RAM + +gregory.clement@free-electrons.com: - add ARM to the title + - fix the reference to CONFIG_DEBUG_MVEBU_UART0_ALTERNATE + - fix the unbalanced comment for the syscfg partition + +Signed-off-by: Imre Kaloz +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 348 ++++++++++++++++++++++++++ + 2 files changed, 349 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-xp-linksys-mamba.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -506,6 +506,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-db.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ ++ armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -0,0 +1,348 @@ ++/* ++ * Device Tree file for the Linksys WRT1900AC (Mamba). ++ * ++ * Note: this board is shipped with a new generation boot loader that ++ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk ++ * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be ++ * used. ++ * ++ * Copyright (C) 2014 Imre Kaloz ++ * ++ * Based on armada-xp-axpwifiap.dts: ++ * ++ * Copyright (C) 2013 Marvell ++ * ++ * Thomas Petazzoni ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "armada-xp-mv78230.dtsi" ++ ++/ { ++ model = "Linksys WRT1900AC"; ++ compatible = "linksys,mamba", "marvell,armadaxp-mv78230", ++ "marvell,armadaxp", "marvell,armada-370-xp"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ ++ }; ++ ++ soc { ++ ranges = ; ++ ++ pcie-controller { ++ status = "okay"; ++ ++ /* Etron EJ168 USB 3.0 controller */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ /* First mini-PCIe port */ ++ pcie@2,0 { ++ /* Port 0, Lane 1 */ ++ status = "okay"; ++ }; ++ ++ /* Second mini-PCIe port */ ++ pcie@3,0 { ++ /* Port 0, Lane 3 */ ++ status = "okay"; ++ }; ++ }; ++ ++ internal-regs { ++ ++ /* J10: VCC, NC, RX, NC, TX, GND */ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ sata@a0000 { ++ nr-ports = <1>; ++ status = "okay"; ++ }; ++ ++ ethernet@70000 { ++ pinctrl-0 = <&ge0_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ ethernet@74000 { ++ pinctrl-0 = <&ge1_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ /* USB part of the eSATA/USB 2.0 port */ ++ usb@50000 { ++ status = "okay"; ++ }; ++ ++ i2c@11000 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ ++ tmp421@4c { ++ compatible = "ti,tmp421"; ++ reg = <0x4c>; ++ }; ++ ++ tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #gpio-cells = <2>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan_amber@0 { ++ label = "mamba:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ wan_white@1 { ++ label = "mamba:white:wan"; ++ reg = <0x1>; ++ }; ++ ++ wlan_2g@2 { ++ label = "mamba:white:wlan_2g"; ++ reg = <0x2>; ++ }; ++ ++ wlan_5g@3 { ++ label = "mamba:white:wlan_5g"; ++ reg = <0x3>; ++ }; ++ ++ esata@4 { ++ label = "mamba:white:esata"; ++ reg = <0x4>; ++ }; ++ ++ usb2@5 { ++ label = "mamba:white:usb2"; ++ reg = <0x5>; ++ }; ++ ++ usb3_1@6 { ++ label = "mamba:white:usb3_1"; ++ reg = <0x6>; ++ }; ++ ++ usb3_2@7 { ++ label = "mamba:white:usb3_2"; ++ reg = <0x7>; ++ }; ++ ++ wps_white@8 { ++ label = "mamba:white:wps"; ++ reg = <0x8>; ++ }; ++ ++ wps_amber@9 { ++ label = "mamba:amber:wps"; ++ reg = <0x9>; ++ }; ++ }; ++ }; ++ ++ nand@d0000 { ++ status = "okay"; ++ num-cs = <1>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u_env"; ++ reg = <0x100000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@140000 { ++ label = "s_env"; ++ reg = <0x140000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@900000 { ++ label = "devinfo"; ++ reg = <0x900000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ /* kernel1 overlaps with rootfs1 by design */ ++ partition@a00000 { ++ label = "kernel1"; ++ reg = <0xa00000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@d00000 { ++ label = "rootfs1"; ++ reg = <0xd00000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* kernel2 overlaps with rootfs2 by design */ ++ partition@3200000 { ++ label = "kernel2"; ++ reg = <0x3200000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@3500000 { ++ label = "rootfs2"; ++ reg = <0x3500000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* ++ * 38MB, last MB is for the BBT, not writable ++ */ ++ partition@5a00000 { ++ label = "syscfg"; ++ reg = <0x5a00000 0x2600000>; ++ }; ++ ++ /* ++ * Unused area between "s_env" and "devinfo". ++ * Moved here because otherwise the renumbered ++ * partitions would break the bootloader ++ * supplied bootargs ++ */ ++ partition@180000 { ++ label = "unused_area"; ++ reg = <0x180000 0x780000>; /* 7.5MB */ ++ }; ++ }; ++ ++ spi0: spi@10600 { ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "everspin,mr25h256"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <40000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&keys_pin>; ++ pinctrl-names = "default"; ++ ++ button@1 { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button@2 { ++ label = "Factory Reset Button"; ++ linux,code = ; ++ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&power_led_pin>; ++ pinctrl-names = "default"; ++ ++ power { ++ label = "mamba:white:power"; ++ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ gpio_fan { ++ /* SUNON HA4010V4-0000-C99 */ ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 24 0>; ++ ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ }; ++}; ++ ++&pinctrl { ++ ++ keys_pin: keys-pin { ++ marvell,pins = "mpp32", "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp40"; ++ marvell,function = "gpio"; ++ }; ++ ++ gpio_fan_pin: gpio-fan-pin { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch b/target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch new file mode 100644 index 0000000..6b51e48 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch @@ -0,0 +1,103 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -84,12 +84,100 @@ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,5ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; ++ ++ ETSI = ++ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; ++ }; ++ }; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,2ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; ++ ++ ETSI = ++ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch b/target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch new file mode 100644 index 0000000..e43d164 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -415,6 +415,16 @@ + gpio-fan,speed-map = <0 0 + 4500 1>; + }; ++ ++ mvsw61xx { ++ compatible = "marvell,88e6172"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ }; + }; + + &pinctrl { diff --git a/target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch b/target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch new file mode 100644 index 0000000..925bab0 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch @@ -0,0 +1,14 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -183,6 +183,11 @@ + + internal-regs { + ++ rtc@10300 { ++ /* No crystal connected to the internal RTC */ ++ status = "disabled"; ++ }; ++ + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; diff --git a/target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch b/target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch new file mode 100644 index 0000000..20f0f71 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch @@ -0,0 +1,40 @@ +From a9ce1afb35317d2a0646c7530f0ae9822c93cd69 Mon Sep 17 00:00:00 2001 +From: Gregory CLEMENT +Date: Mon, 6 Oct 2014 11:37:56 +0200 +Subject: ARM: mvebu: Fix the Aurora L2 cache node with the required + cache-unified property + +The L2 cache controller on the Armada 370 and Armada XP SoCs is a +unified cache. Moreover, the Aurora cache controller is compatible +with the L2x0 cache controller: the "cache-unified" property is +required by its binding. + +This patch fixes the Aurora L2 cache node for the Armada 370 and +Armada XP SoCs by adding this property. + +Reported-by: Sebastian Hesselbarth +Signed-off-by: Gregory CLEMENT +Acked-by: Sebastian Hesselbarth +Link: https://lkml.kernel.org/r/1412588276-4514-1-git-send-email-gregory.clement@free-electrons.com +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -95,6 +95,7 @@ + compatible = "marvell,aurora-outer-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; ++ cache-unified; + wt-override; + }; + +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -39,6 +39,7 @@ + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; ++ cache-unified; + wt-override; + }; + diff --git a/target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch b/target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch new file mode 100644 index 0000000..2e1010c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch @@ -0,0 +1,81 @@ +From b324fa60ac94b9c00c59f621743715c036d134fa Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:07:09 +0200 +Subject: ARM: mvebu: armada-xp: Consolidate pinctrl node + +All current Armada XP SoCs have their pin controller at 0x18000/0x38. +Move the common properties of pinctrl nodes to armada-xp.dtsi to allow +to share pinctrl settings later. + +Signed-off-by: Sebastian Hesselbarth +Acked-by: Thomas Petazzoni +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -169,13 +169,6 @@ + internal-regs { + pinctrl { + compatible = "marvell,mv78230-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; + }; + + gpio0: gpio@18100 { +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -253,13 +253,6 @@ + internal-regs { + pinctrl { + compatible = "marvell,mv78260-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; + }; + + gpio0: gpio@18100 { +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -291,13 +291,6 @@ + internal-regs { + pinctrl { + compatible = "marvell,mv78460-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; + }; + + gpio0: gpio@18100 { +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -72,6 +72,16 @@ + status = "disabled"; + }; + ++ pinctrl { ++ reg = <0x18000 0x38>; ++ ++ sdio_pins: sdio-pins { ++ marvell,pins = "mpp30", "mpp31", "mpp32", ++ "mpp33", "mpp34", "mpp35"; ++ marvell,function = "sd0"; ++ }; ++ }; ++ + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; diff --git a/target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch b/target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch new file mode 100644 index 0000000..7224361 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch @@ -0,0 +1,103 @@ +From 264a05e19bf50f93f1a377e16497a626ae9f931e Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:12:00 +0200 +Subject: ARM: mvebu: armada-xp: Add node alias to pinctrl and add base address + +In other MVEBU SoCs, the pin controller node is called pin-ctrl with +its base address added. Also, we have a node alias to access the pinctrl +node easily. Fix this for Armada XP pinctrl nodes to be consistent with +other SoCs. + +Signed-off-by: Sebastian Hesselbarth +Acked-by: Thomas Petazzoni +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -60,7 +60,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + +--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts ++++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +@@ -51,7 +51,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + poweroff_pin: poweroff-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -167,7 +167,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + compatible = "marvell,mv78230-pinctrl"; + }; + +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -251,7 +251,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + compatible = "marvell,mv78260-pinctrl"; + }; + +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -289,7 +289,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + compatible = "marvell,mv78460-pinctrl"; + }; + +--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts ++++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +@@ -55,7 +55,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts ++++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +@@ -81,7 +81,7 @@ + serial@12100 { + status = "okay"; + }; +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -72,7 +72,7 @@ + status = "disabled"; + }; + +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + + sdio_pins: sdio-pins { diff --git a/target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch b/target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch new file mode 100644 index 0000000..d10e092 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch @@ -0,0 +1,258 @@ +From 01c434225ee67388711e78166cfe9b159e34fc9d Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:20:09 +0200 +Subject: ARM: mvebu: armada-xp: Use pinctrl node alias + +Armada XP pinctrl node gained an alias, make use of it. + +Signed-off-by: Sebastian Hesselbarth +Acked-by: Thomas Petazzoni +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -60,40 +60,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- pinctrl-0 = <&pmx_phy_int>; +- pinctrl-names = "default"; +- +- pmx_ge0: pmx-ge0 { +- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge1: pmx-ge1 { +- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- +- pmx_keys: pmx-keys { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +- +- pmx_spi: pmx-spi { +- marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; +- marvell,function = "spi"; +- }; +- +- pmx_phy_int: pmx-phy-int { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- }; +- + serial@12000 { + status = "okay"; + }; +@@ -162,3 +128,37 @@ + }; + }; + }; ++ ++&pinctrl { ++ pinctrl-0 = <&pmx_phy_int>; ++ pinctrl-names = "default"; ++ ++ pmx_ge0: pmx-ge0 { ++ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge1: pmx-ge1 { ++ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge1"; ++ }; ++ ++ pmx_keys: pmx-keys { ++ marvell,pins = "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ ++ pmx_spi: pmx-spi { ++ marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; ++ marvell,function = "spi"; ++ }; ++ ++ pmx_phy_int: pmx-phy-int { ++ marvell,pins = "mpp32"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts ++++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +@@ -51,37 +51,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- poweroff_pin: poweroff-pin { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- select_button_pin: select-button-pin { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- scroll_button_pin: scroll-button-pin { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- hdd_led_pin: hdd-led-pin { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +- }; +- + serial@12000 { + status = "okay"; + }; +@@ -282,3 +251,34 @@ + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + }; ++ ++&pinctrl { ++ poweroff_pin: poweroff-pin { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_button_pin: power-button-pin { ++ marvell,pins = "mpp44"; ++ marvell,function = "gpio"; ++ }; ++ ++ reset_button_pin: reset-button-pin { ++ marvell,pins = "mpp45"; ++ marvell,function = "gpio"; ++ }; ++ select_button_pin: select-button-pin { ++ marvell,pins = "mpp41"; ++ marvell,function = "gpio"; ++ }; ++ ++ scroll_button_pin: scroll-button-pin { ++ marvell,pins = "mpp42"; ++ marvell,function = "gpio"; ++ }; ++ ++ hdd_led_pin: hdd-led-pin { ++ marvell,pins = "mpp26"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -167,10 +167,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- compatible = "marvell,mv78230-pinctrl"; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -195,3 +191,7 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv78230-pinctrl"; ++}; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -251,10 +251,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- compatible = "marvell,mv78260-pinctrl"; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -298,3 +294,7 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv78260-pinctrl"; ++}; +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -289,10 +289,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- compatible = "marvell,mv78460-pinctrl"; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -336,3 +332,7 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv78460-pinctrl"; ++}; +--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts ++++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +@@ -81,12 +81,7 @@ + serial@12100 { + status = "okay"; + }; +- pinctrl: pin-ctrl@18000 { +- led_pins: led-pins-0 { +- marvell,pins = "mpp49", "mpp51", "mpp53"; +- marvell,function = "gpio"; +- }; +- }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -191,3 +186,10 @@ + }; + }; + }; ++ ++&pinctrl { ++ led_pins: led-pins-0 { ++ marvell,pins = "mpp49", "mpp51", "mpp53"; ++ marvell,function = "gpio"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch b/target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch new file mode 100644 index 0000000..0aadd89 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch @@ -0,0 +1,81 @@ +From e59451432d7e0f7953e29c15e70111dfdbecc145 Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:24:34 +0200 +Subject: ARM: mvebu: armada-xp: Move GE0/1 pinctrl settings for RGMII + +Pinctrl settings for GE0 and GE1 are not only usable on RD-AXPWiFiAP. +Moreover, naming the RGMII settings pmx-ge{0,1} is not precise enough +as there is also a GMII setting for GE0. + +Move the pinctrl sub-nodes to the common pinctrl node and rename them +to pmx-ge{0,1}-rgmii. + +Signed-off-by: Sebastian Hesselbarth +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -84,14 +84,14 @@ + }; + + ethernet@70000 { +- pinctrl-0 = <&pmx_ge0>; ++ pinctrl-0 = <&pmx_ge0_rgmii>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { +- pinctrl-0 = <&pmx_ge1>; ++ pinctrl-0 = <&pmx_ge1_rgmii>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; +@@ -133,20 +133,6 @@ + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + +- pmx_ge0: pmx-ge0 { +- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge1: pmx-ge1 { +- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- + pmx_keys: pmx-keys { + marvell,pins = "mpp33"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -75,6 +75,22 @@ + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + ++ pmx_ge0_rgmii: pmx-ge0-rgmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge1_rgmii: pmx-ge1-rgmii { ++ marvell,pins = ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge1"; ++ }; ++ + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; diff --git a/target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch b/target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch new file mode 100644 index 0000000..37bdae6 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch @@ -0,0 +1,31 @@ +From 7254f6c52b5da38c0a79ab953d34e556fe16942f Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:27:55 +0200 +Subject: ARM: mvebu: armada-xp: Add GE0 pinctrl settings for GMII + +There is a GMII setting for GE0, add it to the common pinctrl node. + +Signed-off-by: Sebastian Hesselbarth +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -75,6 +75,17 @@ + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + ++ pmx_ge0_gmii: pmx-ge0-gmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11", ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge0"; ++ }; ++ + pmx_ge0_rgmii: pmx-ge0-rgmii { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", diff --git a/target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch b/target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch new file mode 100644 index 0000000..acd6ecc --- /dev/null +++ b/target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch @@ -0,0 +1,58 @@ +From 181d9b28cbc9ae10e1467e2d013033b672d91d4b Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:45:35 +0100 +Subject: arm: mvebu: add uartX labels for Armada SoC serial nodes + +This patch adds uartX labels for Armada SoC serial nodes. This is +a preliminary work to be able to easily reference the serial lines +in Device Tree files. One expected use is when providing stdout-path +property for barebox. + +Reviewed-by: Thomas Petazzoni +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/0683d1a823fe9b75849f3dafcf1cf6ee291cdca6.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -151,7 +151,7 @@ + status = "disabled"; + }; + +- serial@12000 { ++ uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; +@@ -160,7 +160,8 @@ + clocks = <&coreclk 0>; + status = "disabled"; + }; +- serial@12100 { ++ ++ uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -53,7 +53,7 @@ + reg = <0x11100 0x100>; + }; + +- serial@12200 { ++ uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; +@@ -62,7 +62,8 @@ + clocks = <&coreclk 0>; + status = "disabled"; + }; +- serial@12300 { ++ ++ uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; diff --git a/target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch b/target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch new file mode 100644 index 0000000..ed36d68 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch @@ -0,0 +1,538 @@ +From 4904a82a9399d037588162e6fb4b293fa6a37f7c Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:45:56 +0100 +Subject: arm: mvebu: move Armada 370/XP pinctrl node definition + armada-370-xp.dtsi + +What was done by Sebastian in 264a05e19bf5 ("ARM: mvebu: armada-xp: +Add node alias to pinctrl and add base address") and 01c434225ee6 +("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for +Armada 370, i.e. + + - Rename Armada 370 pinctrl node to pin-ctrl with its address encoded + - Add a node alias to access the pinctrl node easily. + - use the newly available alias in existing Armada 370 .dts files + +We can even go a bit further by putting the pinctrl node definition in +armada-370-xp.dtsi, with only its reg property defined. This allows us +to then also use the newly defined node alias in armada-xp.dtsi, +armada-370.dtsi. + +Suggested-by: Sebastian Hesselbarth +Suggested-by: Andrew Lunn +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/b54eb45e5242728aace3ce8aef2eae4251f8dea3.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-370-db.dts ++++ b/arch/arm/boot/dts/armada-370-db.dts +@@ -157,3 +157,27 @@ + compatible = "linux,spdif-dir"; + }; + }; ++ ++&pinctrl { ++ /* ++ * These pins might be muxed as I2S by ++ * the bootloader, but it conflicts ++ * with the real I2S pins that are ++ * muxed using i2s_pins. We must mux ++ * those pins to a function other than ++ * I2S. ++ */ ++ pinctrl-0 = <&hog_pins1 &hog_pins2>; ++ pinctrl-names = "default"; ++ ++ hog_pins1: hog-pins1 { ++ marvell,pins = "mpp6", "mpp8", "mpp10", ++ "mpp12", "mpp13"; ++ marvell,function = "gpio"; ++ }; ++ ++ hog_pins2: hog-pins2 { ++ marvell,pins = "mpp5", "mpp7", "mpp9"; ++ marvell,function = "gpo"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-mirabox.dts ++++ b/arch/arm/boot/dts/armada-370-mirabox.dts +@@ -54,18 +54,6 @@ + status = "okay"; + }; + +- pinctrl { +- pwr_led_pin: pwr-led-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpo"; +- }; +- +- stat_led_pins: stat-led-pins { +- marvell,pins = "mpp64", "mpp65"; +- marvell,function = "gpio"; +- }; +- }; +- + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -169,3 +157,16 @@ + }; + }; + }; ++ ++&pinctrl { ++ pwr_led_pin: pwr-led-pin { ++ marvell,pins = "mpp63"; ++ marvell,function = "gpo"; ++ }; ++ ++ stat_led_pins: stat-led-pins { ++ marvell,pins = "mpp64", "mpp65"; ++ marvell,function = "gpio"; ++ }; ++}; ++ +--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts ++++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts +@@ -58,48 +58,6 @@ + status = "okay"; + }; + +- pinctrl { +- power_led_pin: power-led-pin { +- marvell,pins = "mpp57"; +- marvell,function = "gpio"; +- }; +- +- sata1_led_pin: sata1-led-pin { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- sata2_led_pin: sata2-led-pin { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp56"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp58"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp6"; +- marvell,function = "gpio"; +- }; +- +- poweroff: poweroff { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- }; +- + mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +@@ -256,3 +214,45 @@ + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + }; ++ ++&pinctrl { ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp57"; ++ marvell,function = "gpio"; ++ }; ++ ++ sata1_led_pin: sata1-led-pin { ++ marvell,pins = "mpp15"; ++ marvell,function = "gpio"; ++ }; ++ ++ sata2_led_pin: sata2-led-pin { ++ marvell,pins = "mpp14"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_led_pin: backup-led-pin { ++ marvell,pins = "mpp56"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_button_pin: backup-button-pin { ++ marvell,pins = "mpp58"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_button_pin: power-button-pin { ++ marvell,pins = "mpp62"; ++ marvell,function = "gpio"; ++ }; ++ ++ reset_button_pin: reset-button-pin { ++ marvell,pins = "mpp6"; ++ marvell,function = "gpio"; ++ }; ++ ++ poweroff: poweroff { ++ marvell,pins = "mpp8"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts ++++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts +@@ -53,38 +53,6 @@ + status = "okay"; + }; + +- pinctrl { +- poweroff: poweroff { +- marvell,pins = "mpp60"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp52"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpo"; +- }; +- +- power_led_pin: power-led-pin { +- marvell,pins = "mpp64"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp65"; +- marvell,function = "gpio"; +- }; +- }; +- + mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +@@ -269,3 +237,35 @@ + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; ++ ++&pinctrl { ++ poweroff: poweroff { ++ marvell,pins = "mpp60"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_button_pin: backup-button-pin { ++ marvell,pins = "mpp52"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_button_pin: power-button-pin { ++ marvell,pins = "mpp62"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_led_pin: backup-led-pin { ++ marvell,pins = "mpp63"; ++ marvell,function = "gpo"; ++ }; ++ ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp64"; ++ marvell,function = "gpio"; ++ }; ++ ++ reset_button_pin: reset-button-pin { ++ marvell,pins = "mpp65"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-rd.dts ++++ b/arch/arm/boot/dts/armada-370-rd.dts +@@ -59,18 +59,6 @@ + }; + + internal-regs { +- pinctrl { +- fan_pins: fan-pins { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- +- led_pins: led-pins { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- }; +- + serial@12000 { + status = "okay"; + }; +@@ -174,3 +162,15 @@ + }; + }; + }; ++ ++&pinctrl { ++ fan_pins: fan-pins { ++ marvell,pins = "mpp8"; ++ marvell,function = "gpio"; ++ }; ++ ++ led_pins: led-pins { ++ marvell,pins = "mpp32"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -171,6 +171,10 @@ + status = "disabled"; + }; + ++ pinctrl: pin-ctrl@18000 { ++ reg = <0x18000 0x38>; ++ }; ++ + coredivclk: corediv-clock@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -107,67 +107,6 @@ + reg = <0x11100 0x20>; + }; + +- pinctrl { +- compatible = "marvell,mv88f6710-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins1: sdio-pins1 { +- marvell,pins = "mpp9", "mpp11", "mpp12", +- "mpp13", "mpp14", "mpp15"; +- marvell,function = "sd0"; +- }; +- +- sdio_pins2: sdio-pins2 { +- marvell,pins = "mpp47", "mpp48", "mpp49", +- "mpp50", "mpp51", "mpp52"; +- marvell,function = "sd0"; +- }; +- +- sdio_pins3: sdio-pins3 { +- marvell,pins = "mpp48", "mpp49", "mpp50", +- "mpp51", "mpp52", "mpp53"; +- marvell,function = "sd0"; +- }; +- +- i2c0_pins: i2c0-pins { +- marvell,pins = "mpp2", "mpp3"; +- marvell,function = "i2c0"; +- }; +- +- i2s_pins1: i2s-pins1 { +- marvell,pins = "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", +- "mpp12", "mpp13"; +- marvell,function = "audio"; +- }; +- +- i2s_pins2: i2s-pins2 { +- marvell,pins = "mpp49", "mpp47", "mpp50", +- "mpp59", "mpp57", "mpp61", +- "mpp62", "mpp60", "mpp58"; +- marvell,function = "audio"; +- }; +- +- mdio_pins: mdio-pins { +- marvell,pins = "mpp17", "mpp18"; +- marvell,function = "ge"; +- }; +- +- ge0_rgmii_pins: ge0-rgmii-pins { +- marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", +- "mpp9", "mpp10", "mpp11", "mpp12", +- "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "ge0"; +- }; +- +- ge1_rgmii_pins: ge1-rgmii-pins { +- marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", "mpp26", +- "mpp27", "mpp28", "mpp29", "mpp30"; +- marvell,function = "ge1"; +- }; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -314,3 +253,63 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv88f6710-pinctrl"; ++ ++ sdio_pins1: sdio-pins1 { ++ marvell,pins = "mpp9", "mpp11", "mpp12", ++ "mpp13", "mpp14", "mpp15"; ++ marvell,function = "sd0"; ++ }; ++ ++ sdio_pins2: sdio-pins2 { ++ marvell,pins = "mpp47", "mpp48", "mpp49", ++ "mpp50", "mpp51", "mpp52"; ++ marvell,function = "sd0"; ++ }; ++ ++ sdio_pins3: sdio-pins3 { ++ marvell,pins = "mpp48", "mpp49", "mpp50", ++ "mpp51", "mpp52", "mpp53"; ++ marvell,function = "sd0"; ++ }; ++ ++ i2c0_pins: i2c0-pins { ++ marvell,pins = "mpp2", "mpp3"; ++ marvell,function = "i2c0"; ++ }; ++ ++ i2s_pins1: i2s-pins1 { ++ marvell,pins = "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", ++ "mpp12", "mpp13"; ++ marvell,function = "audio"; ++ }; ++ ++ i2s_pins2: i2s-pins2 { ++ marvell,pins = "mpp49", "mpp47", "mpp50", ++ "mpp59", "mpp57", "mpp61", ++ "mpp62", "mpp60", "mpp58"; ++ marvell,function = "audio"; ++ }; ++ ++ mdio_pins: mdio-pins { ++ marvell,pins = "mpp17", "mpp18"; ++ marvell,function = "ge"; ++ }; ++ ++ ge0_rgmii_pins: ge0-rgmii-pins { ++ marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", ++ "mpp9", "mpp10", "mpp11", "mpp12", ++ "mpp13", "mpp14", "mpp15", "mpp16"; ++ marvell,function = "ge0"; ++ }; ++ ++ ge1_rgmii_pins: ge1-rgmii-pins { ++ marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", ++ "mpp23", "mpp24", "mpp25", "mpp26", ++ "mpp27", "mpp28", "mpp29", "mpp30"; ++ marvell,function = "ge1"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -73,43 +73,6 @@ + status = "disabled"; + }; + +- pinctrl: pin-ctrl@18000 { +- reg = <0x18000 0x38>; +- +- pmx_ge0_gmii: pmx-ge0-gmii { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11", +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge0_rgmii: pmx-ge0-rgmii { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge1_rgmii: pmx-ge1-rgmii { +- marvell,pins = +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; +- }; +- + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; +@@ -246,3 +209,38 @@ + }; + }; + }; ++ ++&pinctrl { ++ pmx_ge0_gmii: pmx-ge0-gmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11", ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge0_rgmii: pmx-ge0-rgmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge1_rgmii: pmx-ge1-rgmii { ++ marvell,pins = ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge1"; ++ }; ++ ++ sdio_pins: sdio-pins { ++ marvell,pins = "mpp30", "mpp31", "mpp32", ++ "mpp33", "mpp34", "mpp35"; ++ marvell,function = "sd0"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch b/target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch new file mode 100644 index 0000000..4cccdb3 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch @@ -0,0 +1,52 @@ +From d352f41e87e7226692d1346bb97c603615eeb817 Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:46:28 +0100 +Subject: arm: mvebu: define and use common Armada XP UART2/3 pinctrl settings + +This patch defines common Armada XP pinctrl settings for uart2 and +uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP): + + uart2: MPP42-43 as default + uart3: MPP44-45 as default + +Suggested-by: Andrew Lunn +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -55,6 +55,8 @@ + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <43>; +@@ -65,6 +67,8 @@ + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; ++ pinctrl-0 = <&uart3_pins>; ++ pinctrl-names = "default"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <44>; +@@ -243,4 +247,14 @@ + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; ++ ++ uart2_pins: uart2-pins { ++ marvell,pins = "mpp42", "mpp43"; ++ marvell,function = "uart2"; ++ }; ++ ++ uart3_pins: uart3-pins { ++ marvell,pins = "mpp44", "mpp45"; ++ marvell,function = "uart3"; ++ }; + }; diff --git a/target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch b/target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch new file mode 100644 index 0000000..9085db0 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch @@ -0,0 +1,69 @@ +From 547c653b64022618250ca9c7c30151927509ae98 Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:46:39 +0100 +Subject: arm: mvebu: define and use common Armada XP SPI pinctrl setting + +This patch defines common Armada XP pinctrl settings in armada-xp.dtsi +for the supported SPI interface (MPP36-39) and use it as default +for Armada XP spi interface. That being done, it removes the now +redundant definitions in armada-xp-axpwifiap.dts. + +Note: this patch has the potential to break out-of-tree users w/o +specific pinctrl settings for their spi interfaces if the default +above does not match their config (i.e. if they do not use CS0). + +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/d404b7abd80ee5a0fd8e8d3586d33cd37740d589.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -100,8 +100,6 @@ + + spi0: spi@10600 { + status = "okay"; +- pinctrl-0 = <&pmx_spi>; +- pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; +@@ -138,11 +136,6 @@ + marvell,function = "gpio"; + }; + +- pmx_spi: pmx-spi { +- marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; +- marvell,function = "spi"; +- }; +- + pmx_phy_int: pmx-phy-int { + marvell,pins = "mpp32"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -43,6 +43,11 @@ + wt-override; + }; + ++ spi0: spi@10600 { ++ pinctrl-0 = <&spi0_pins>; ++ pinctrl-names = "default"; ++ }; ++ + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +@@ -248,6 +253,12 @@ + marvell,function = "sd0"; + }; + ++ spi0_pins: spi0-pins { ++ marvell,pins = "mpp36", "mpp37", ++ "mpp38", "mpp39"; ++ marvell,function = "spi"; ++ }; ++ + uart2_pins: uart2-pins { + marvell,pins = "mpp42", "mpp43"; + marvell,function = "uart2"; diff --git a/target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch b/target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch new file mode 100644 index 0000000..ca7b13b --- /dev/null +++ b/target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch @@ -0,0 +1,98 @@ +From 70ee4e9d9f054e258480fd51c90cfc2b72be8b78 Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 17:23:30 +0100 +Subject: arm: mvebu: normalize pinctrl entries for Armada SoCs + +There are currently 2 differents naming conventions used between the +existing Armada SoC DT files for pinctrl entries (*_pin(s): *-pin(s) +and pmx_*: pmx-*) with a vast majority of files using the former: + +$ grep _pin arch/arm/boot/dts/armada-*.dts* | wc -l +155 +$ grep pmx arch/arm/boot/dts/armada-*.dts* | wc -l +13 + +In fact, only some Armada XP files are using the second variant. +This patch normalizes those files (mainly ge0/1 entries) to use +the first variant. + +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/00114c3169e1d93259ff4150ed46ee36eae16b1e.1416670812.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -84,14 +84,14 @@ + }; + + ethernet@70000 { +- pinctrl-0 = <&pmx_ge0_rgmii>; ++ pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { +- pinctrl-0 = <&pmx_ge1_rgmii>; ++ pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; +@@ -116,7 +116,7 @@ + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; +- pinctrl-0 = <&pmx_keys>; ++ pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { +@@ -128,15 +128,15 @@ + }; + + &pinctrl { +- pinctrl-0 = <&pmx_phy_int>; ++ pinctrl-0 = <&phy_int_pin>; + pinctrl-names = "default"; + +- pmx_keys: pmx-keys { ++ keys_pin: keys-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + +- pmx_phy_int: pmx-phy-int { ++ phy_int_pin: phy-int-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -220,7 +220,7 @@ + }; + + &pinctrl { +- pmx_ge0_gmii: pmx-ge0-gmii { ++ ge0_gmii_pins: ge0-gmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", +@@ -231,7 +231,7 @@ + marvell,function = "ge0"; + }; + +- pmx_ge0_rgmii: pmx-ge0-rgmii { ++ ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", +@@ -239,7 +239,7 @@ + marvell,function = "ge0"; + }; + +- pmx_ge1_rgmii: pmx-ge1-rgmii { ++ ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", diff --git a/target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch b/target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch new file mode 100644 index 0000000..551d5bf --- /dev/null +++ b/target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch @@ -0,0 +1,65 @@ +From 91b4c91f919abffa72cbf7545a944252f8e4f775 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 8 Jan 2015 18:38:08 +0100 +Subject: [PATCH 3/4] ARM: mvebu: Add a number of pinctrl functions + +Some pinctrl functions can be shared with all DTS out there, since they are +generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid +duplication. + +Signed-off-by: Maxime Ripard +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -196,6 +196,45 @@ + pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; ++ ++ ge0_rgmii_pins: ge-rgmii-pins-0 { ++ marvell,pins = "mpp6", "mpp7", "mpp8", ++ "mpp9", "mpp10", "mpp11", ++ "mpp12", "mpp13", "mpp14", ++ "mpp15", "mpp16", "mpp17"; ++ marvell,function = "ge0"; ++ }; ++ ++ i2c0_pins: i2c-pins-0 { ++ marvell,pins = "mpp2", "mpp3"; ++ marvell,function = "i2c0"; ++ }; ++ ++ mdio_pins: mdio-pins { ++ marvell,pins = "mpp4", "mpp5"; ++ marvell,function = "ge"; ++ }; ++ ++ ref_clk0_pins: ref-clk-pins-0 { ++ marvell,pins = "mpp45"; ++ marvell,function = "ref"; ++ }; ++ ++ spi1_pins: spi-pins-1 { ++ marvell,pins = "mpp56", "mpp57", "mpp58", ++ "mpp59"; ++ marvell,function = "spi1"; ++ }; ++ ++ uart0_pins: uart-pins-0 { ++ marvell,pins = "mpp0", "mpp1"; ++ marvell,function = "ua0"; ++ }; ++ ++ uart1_pins: uart-pins-1 { ++ marvell,pins = "mpp19", "mpp20"; ++ marvell,function = "ua1"; ++ }; + }; + + gpio0: gpio@18100 { diff --git a/target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch b/target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch new file mode 100644 index 0000000..cc9311b --- /dev/null +++ b/target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch @@ -0,0 +1,212 @@ +From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 8 Jan 2015 18:38:09 +0100 +Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board + support + +The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB +SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage. + +[gregory.clement@free-electrons.com: switch the license to the dual +X11/GPL with the agreement of the author] + +Signed-off-by: Maxime Ripard +Signed-off-by: Gregory CLEMENT +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++ + 2 files changed, 179 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -500,6 +500,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb \ ++ armada-385-db-ap.dtb \ + armada-385-rd.dtb + dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -0,0 +1,178 @@ ++/* ++ * Device Tree file for Marvell Armada 385 Access Point Development board ++ * (DB-88F6820-AP) ++ * ++ * Copyright (C) 2014 Marvell ++ * ++ * Nadav Haklai ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "armada-385.dtsi" ++ ++#include ++ ++/ { ++ model = "Marvell Armada 385 Access Point Development Board"; ++ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ stdout-path = &uart1; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x80000000>; /* 2GB */ ++ }; ++ ++ soc { ++ ranges = ; ++ ++ internal-regs { ++ spi1: spi@10680 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p128"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <54000000>; ++ }; ++ }; ++ ++ i2c0: i2c@11000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ ++ /* ++ * This bus is wired to two EEPROM ++ * sockets, one of which holding the ++ * board ID used by the bootloader. ++ * Erasing this EEPROM's content will ++ * brick the board. ++ * Use this bus with caution. ++ */ ++ }; ++ ++ mdio@72004 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mdio_pins>; ++ ++ phy0: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ ++ phy1: ethernet-phy@4 { ++ reg = <4>; ++ }; ++ ++ phy2: ethernet-phy@6 { ++ reg = <6>; ++ }; ++ }; ++ ++ /* UART0 is exposed through the JP8 connector */ ++ uart0: serial@12000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++ }; ++ ++ /* ++ * UART1 is exposed through a FTDI chip ++ * wired to the mini-USB connector ++ */ ++ uart1: serial@12100 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ ++ ethernet@30000 { ++ status = "okay"; ++ phy = <&phy2>; ++ phy-mode = "sgmii"; ++ }; ++ ++ ethernet@34000 { ++ status = "okay"; ++ phy = <&phy1>; ++ phy-mode = "sgmii"; ++ }; ++ ++ ethernet@70000 { ++ pinctrl-names = "default"; ++ ++ /* ++ * The Reference Clock 0 is used to ++ * provide a clock to the PHY ++ */ ++ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; ++ status = "okay"; ++ phy = <&phy0>; ++ phy-mode = "rgmii-id"; ++ }; ++ }; ++ ++ pcie-controller { ++ status = "okay"; ++ ++ /* ++ * The three PCIe units are accessible through ++ * standard mini-PCIe slots on the board. ++ */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ pcie@2,0 { ++ /* Port 1, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ pcie@3,0 { ++ /* Port 2, Lane 0 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch b/target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch new file mode 100644 index 0000000..3c4a111 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch @@ -0,0 +1,34 @@ +From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 11 Dec 2014 14:14:58 +0100 +Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller + +The A385 AP has a 1GB NAND chip. Enable it. + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -150,6 +150,19 @@ + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; ++ ++ nfc: flash@d0000 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ num-cs = <1>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ }; + }; + + pcie-controller { diff --git a/target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch b/target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch new file mode 100644 index 0000000..07f8e29 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch @@ -0,0 +1,37 @@ +From a95308d88c07e0093aedae7e64f92cb1e165f592 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 5 Dec 2014 15:44:57 +0100 +Subject: [PATCH] pinctrl: mvebu: a38x: Add UART1 muxing options + +The MPP19 and MMP20 pins also have the ability to be muxed to the uart1 +function. + +Add this case to the pinctrl driver. + +Signed-off-by: Maxime Ripard +Acked-by: Jason Cooper +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +@@ -146,13 +146,15 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS), diff --git a/target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch b/target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch new file mode 100644 index 0000000..37dd4c2 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch @@ -0,0 +1,85 @@ +From 4a25432b13090b57d257fa0ffb6712d8acf94523 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 8 Jan 2015 18:38:05 +0100 +Subject: [PATCH 1/4] ARM: mvebu: a38x: Fix node names + +Some nodes in the DTs have a reg property but no unit name in their node name. + +This contradicts the way the ePAPR defines the node names. Fix this. + +Signed-off-by: Maxime Ripard +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-380.dtsi | 2 +- + arch/arm/boot/dts/armada-385-db.dts | 2 +- + arch/arm/boot/dts/armada-385-rd.dts | 2 +- + arch/arm/boot/dts/armada-385.dtsi | 2 +- + arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- + 5 files changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -32,7 +32,7 @@ + + soc { + internal-regs { +- pinctrl { ++ pinctrl@18000 { + compatible = "marvell,mv88f6810-pinctrl"; + reg = <0x18000 0x20>; + }; +--- a/arch/arm/boot/dts/armada-385-db.dts ++++ b/arch/arm/boot/dts/armada-385-db.dts +@@ -74,7 +74,7 @@ + phy-mode = "rgmii-id"; + }; + +- mdio { ++ mdio@72004 { + phy0: ethernet-phy@0 { + reg = <0>; + }; +--- a/arch/arm/boot/dts/armada-385-rd.dts ++++ b/arch/arm/boot/dts/armada-385-rd.dts +@@ -67,7 +67,7 @@ + }; + + +- mdio { ++ mdio@72004 { + phy0: ethernet-phy@0 { + reg = <0>; + }; +--- a/arch/arm/boot/dts/armada-385.dtsi ++++ b/arch/arm/boot/dts/armada-385.dtsi +@@ -37,7 +37,7 @@ + + soc { + internal-regs { +- pinctrl { ++ pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + }; +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -193,7 +193,7 @@ + status = "disabled"; + }; + +- pinctrl { ++ pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + +@@ -412,7 +412,7 @@ + status = "disabled"; + }; + +- mdio { ++ mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch b/target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch new file mode 100644 index 0000000..e3d1415 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch @@ -0,0 +1,111 @@ +From 1bd4d8a6de5cda605e8b99fbf081be2ea2959380 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 16 Jan 2015 17:11:29 +0100 +Subject: ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O + coherency + +Now that we have enabled automatic I/O synchronization barriers, we no +longer need any explicit barriers. We can therefore simplify +arch/arm/mach-mvebu/coherency.c by using the existing +arm_coherent_dma_ops instead of our custom mvebu_hwcc_dma_ops, and +re-enable hardware I/O coherency support. + +Signed-off-by: Thomas Petazzoni +[Andrew Lunn : Remove forgotten comment] +Signed-off-by: Andrew Lunn + +--- a/arch/arm/mach-mvebu/coherency.c ++++ b/arch/arm/mach-mvebu/coherency.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #include "armada-370-xp.h" + #include "coherency.h" + #include "mvebu-soc-id.h" +@@ -223,59 +224,6 @@ static void __init armada_375_coherency_ + coherency_wa_enabled = true; + } + +-static inline void mvebu_hwcc_sync_io_barrier(void) +-{ +- if (coherency_wa_enabled) { +- mvebu_hwcc_armada375_sync_io_barrier_wa(); +- return; +- } +- +- writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET); +- while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1); +-} +- +-static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, +- enum dma_data_direction dir, +- struct dma_attrs *attrs) +-{ +- if (dir != DMA_TO_DEVICE) +- mvebu_hwcc_sync_io_barrier(); +- return pfn_to_dma(dev, page_to_pfn(page)) + offset; +-} +- +- +-static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, +- size_t size, enum dma_data_direction dir, +- struct dma_attrs *attrs) +-{ +- if (dir != DMA_TO_DEVICE) +- mvebu_hwcc_sync_io_barrier(); +-} +- +-static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle, +- size_t size, enum dma_data_direction dir) +-{ +- if (dir != DMA_TO_DEVICE) +- mvebu_hwcc_sync_io_barrier(); +-} +- +-static struct dma_map_ops mvebu_hwcc_dma_ops = { +- .alloc = arm_dma_alloc, +- .free = arm_dma_free, +- .mmap = arm_dma_mmap, +- .map_page = mvebu_hwcc_dma_map_page, +- .unmap_page = mvebu_hwcc_dma_unmap_page, +- .get_sgtable = arm_dma_get_sgtable, +- .map_sg = arm_dma_map_sg, +- .unmap_sg = arm_dma_unmap_sg, +- .sync_single_for_cpu = mvebu_hwcc_dma_sync, +- .sync_single_for_device = mvebu_hwcc_dma_sync, +- .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, +- .sync_sg_for_device = arm_dma_sync_sg_for_device, +- .set_dma_mask = arm_dma_set_mask, +-}; +- + static int mvebu_hwcc_notifier(struct notifier_block *nb, + unsigned long event, void *__dev) + { +@@ -283,7 +231,7 @@ static int mvebu_hwcc_notifier(struct no + + if (event != BUS_NOTIFY_ADD_DEVICE) + return NOTIFY_DONE; +- set_dma_ops(dev, &mvebu_hwcc_dma_ops); ++ set_dma_ops(dev, &arm_coherent_dma_ops); + + return NOTIFY_OK; + } +@@ -405,14 +353,9 @@ static int coherency_type(void) + return type; + } + +-/* +- * As a precaution, we currently completely disable hardware I/O +- * coherency, until enough testing is done with automatic I/O +- * synchronization barriers to validate that it is a proper solution. +- */ + int coherency_available(void) + { +- return false; ++ return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; + } + + int __init coherency_init(void) diff --git a/target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch b/target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch new file mode 100644 index 0000000..e55eca3 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch @@ -0,0 +1,51 @@ +Document the binding for the TLC59116 LED driver. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/leds/leds-tlc59116.txt | 40 ++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc59116.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/leds/leds-tlc59116.txt +@@ -0,0 +1,40 @@ ++LEDs connected to tcl59116 ++ ++Required properties ++- compatible: should be "ti,tlc59116" ++- #address-cells: must be 1 ++- #size-cells: must be 0 ++- reg: typically 0x68 ++ ++Each led is represented as a sub-node of the ti,,tlc59116. ++See Documentation/devicetree/bindings/leds/common.txt ++ ++LED sub-node properties: ++- reg: number of LED line, 0 to 15 ++- label: (optional) name of LED ++- linux,default-trigger : (optional) ++ ++Examples: ++ ++tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan@0 { ++ label = "wrt1900ac:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ 2g@2 { ++ label = "wrt1900ac:white:2g"; ++ reg = <0x2>; ++ }; ++ ++ alive@9 { ++ label = "wrt1900ac:green:alive"; ++ reg = <0x9>; ++ linux,default_trigger = "heartbeat"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch b/target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch new file mode 100644 index 0000000..fd22aef --- /dev/null +++ b/target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch @@ -0,0 +1,297 @@ +The TLC59116 is an I2C bus controlled 16-channel LED driver. Each LED +output has its own 8-bit fixed-frequency PWM controller to control the +brightness of the LED. + +This is based on a driver from Belkin, but has been extensively +rewritten. + +Signed-off-by: Andrew Lunn +--- + drivers/leds/Kconfig | 8 ++ + drivers/leds/Makefile | 1 + + drivers/leds/leds-tlc59116.c | 252 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 261 insertions(+) + create mode 100644 drivers/leds/leds-tlc59116.c + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -446,6 +446,14 @@ config LEDS_TCA6507 + LED driver chips accessed via the I2C bus. + Driver support brightness control and hardware-assisted blinking. + ++config LEDS_TLC59116 ++ tristate "LED driver for TLC59116F controllers" ++ depends on LEDS_CLASS && I2C ++ select REGMAP_I2C ++ help ++ This option enables support for Texas Instruments TLC59116F ++ LED controller. ++ + config LEDS_MAX8997 + tristate "LED support for MAX8997 PMIC" + depends on LEDS_CLASS && MFD_MAX8997 +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_LP5562) += leds-lp556 + obj-$(CONFIG_LEDS_LP8501) += leds-lp8501.o + obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o + obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o ++obj-$(CONFIG_LEDS_TLC59116) += leds-tlc59116.o + obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o + obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o + obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o +--- /dev/null ++++ b/drivers/leds/leds-tlc59116.c +@@ -0,0 +1,252 @@ ++/* ++ * Copyright 2014 Belkin Inc. ++ * Copyright 2014 Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TLC59116_LEDS 16 ++ ++#define TLC59116_REG_MODE1 0x00 ++#define MODE1_RESPON_ADDR_MASK 0xF0 ++#define MODE1_NORMAL_MODE (0 << 4) ++#define MODE1_SPEED_MODE (1 << 4) ++ ++#define TLC59116_REG_MODE2 0x01 ++#define MODE2_DIM (0 << 5) ++#define MODE2_BLINK (1 << 5) ++#define MODE2_OCH_STOP (0 << 3) ++#define MODE2_OCH_ACK (1 << 3) ++ ++#define TLC59116_REG_PWM(x) (0x02 + (x)) ++ ++#define TLC59116_REG_GRPPWM 0x12 ++#define TLC59116_REG_GRPFREQ 0x13 ++ ++/* LED Driver Output State, determine the source that drives LED outputs */ ++#define TLC59116_REG_LEDOUT(x) (0x14 + ((x) >> 2)) ++#define TLC59116_LED_OFF 0x0 /* Output LOW */ ++#define TLC59116_LED_ON 0x1 /* Output HI-Z */ ++#define TLC59116_DIM 0x2 /* Dimming */ ++#define TLC59116_BLINK 0x3 /* Blinking */ ++#define LED_MASK 0x3 ++ ++#define ldev_to_led(c) container_of(c, struct tlc59116_led, ldev) ++#define work_to_led(work) container_of(work, struct tlc59116_led, work) ++ ++struct tlc59116_led { ++ bool active; ++ struct regmap *regmap; ++ unsigned int led_no; ++ struct led_classdev ldev; ++ struct work_struct work; ++}; ++ ++struct tlc59116_priv { ++ struct tlc59116_led leds[TLC59116_LEDS]; ++}; ++ ++static int ++tlc59116_set_mode(struct regmap *regmap, u8 mode) ++{ ++ int err; ++ u8 val; ++ ++ if ((mode != MODE2_DIM) && (mode != MODE2_BLINK)) ++ mode = MODE2_DIM; ++ ++ /* Configure MODE1 register */ ++ err = regmap_write(regmap, TLC59116_REG_MODE1, MODE1_NORMAL_MODE); ++ if (err) ++ return err; ++ ++ /* Configure MODE2 Reg */ ++ val = MODE2_OCH_STOP | mode; ++ ++ return regmap_write(regmap, TLC59116_REG_MODE2, val); ++} ++ ++static int ++tlc59116_set_led(struct tlc59116_led *led, u8 val) ++{ ++ struct regmap *regmap = led->regmap; ++ unsigned int i = (led->led_no % 4) * 2; ++ unsigned int addr = TLC59116_REG_LEDOUT(led->led_no); ++ unsigned int mask = LED_MASK << i; ++ ++ val = val << i; ++ ++ return regmap_update_bits(regmap, addr, mask, val); ++} ++ ++static void ++tlc59116_led_work(struct work_struct *work) ++{ ++ struct tlc59116_led *led = work_to_led(work); ++ struct regmap *regmap = led->regmap; ++ int err; ++ u8 pwm; ++ ++ pwm = TLC59116_REG_PWM(led->led_no); ++ err = regmap_write(regmap, pwm, led->ldev.brightness); ++ if (err) ++ dev_err(led->ldev.dev, "Failed setting brightness\n"); ++} ++ ++static void ++tlc59116_led_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ struct tlc59116_led *led = ldev_to_led(led_cdev); ++ ++ led->ldev.brightness = value; ++ schedule_work(&led->work); ++} ++ ++static void ++tlc59116_destroy_devices(struct tlc59116_priv *priv, unsigned int i) ++{ ++ while (--i >= 0) { ++ if (priv->leds[i].active) { ++ led_classdev_unregister(&priv->leds[i].ldev); ++ cancel_work_sync(&priv->leds[i].work); ++ } ++ } ++} ++ ++static int ++tlc59116_configure(struct device *dev, ++ struct tlc59116_priv *priv, ++ struct regmap *regmap) ++{ ++ unsigned int i; ++ int err = 0; ++ ++ tlc59116_set_mode(regmap, MODE2_DIM); ++ for (i = 0; i < TLC59116_LEDS; i++) { ++ struct tlc59116_led *led = &priv->leds[i]; ++ ++ if (!led->active) ++ continue; ++ ++ led->regmap = regmap; ++ led->led_no = i; ++ led->ldev.brightness_set = tlc59116_led_set; ++ led->ldev.max_brightness = LED_FULL; ++ INIT_WORK(&led->work, tlc59116_led_work); ++ err = led_classdev_register(dev, &led->ldev); ++ if (err < 0) { ++ dev_err(dev, "couldn't register LED %s\n", ++ led->ldev.name); ++ goto exit; ++ } ++ tlc59116_set_led(led, TLC59116_DIM); ++ } ++ ++ return 0; ++ ++exit: ++ tlc59116_destroy_devices(priv, i); ++ return err; ++} ++ ++static const struct regmap_config tlc59116_regmap = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = 0x1e, ++}; ++ ++static int ++tlc59116_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ struct device *dev = &client->dev; ++ struct device_node *np = client->dev.of_node, *child; ++ struct regmap *regmap; ++ int err, count, reg; ++ ++ count = of_get_child_count(np); ++ if (!count || count > TLC59116_LEDS) ++ return -EINVAL; ++ ++ if (!i2c_check_functionality(client->adapter, ++ I2C_FUNC_SMBUS_BYTE_DATA)) ++ return -EIO; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ regmap = devm_regmap_init_i2c(client, &tlc59116_regmap); ++ if (IS_ERR(regmap)) { ++ err = PTR_ERR(regmap); ++ dev_err(dev, "Failed to allocate register map: %d\n", err); ++ return err; ++ } ++ ++ i2c_set_clientdata(client, priv); ++ ++ for_each_child_of_node(np, child) { ++ err = of_property_read_u32(child, "reg", ®); ++ if (err) ++ return err; ++ if (reg < 0 || reg >= TLC59116_LEDS) ++ return -EINVAL; ++ if (priv->leds[reg].active) ++ return -EINVAL; ++ priv->leds[reg].active = true; ++ priv->leds[reg].ldev.name = ++ of_get_property(child, "label", NULL) ? : child->name; ++ priv->leds[reg].ldev.default_trigger = ++ of_get_property(child, "linux,default-trigger", NULL); ++ } ++ return tlc59116_configure(dev, priv, regmap); ++} ++ ++static int ++tlc59116_remove(struct i2c_client *client) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ ++ tlc59116_destroy_devices(priv, TLC59116_LEDS); ++ ++ return 0; ++} ++ ++static const struct of_device_id of_tlc59116_leds_match[] = { ++ { .compatible = "ti,tlc59116", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, of_tlc59116_leds_match); ++ ++static const struct i2c_device_id tlc59116_id[] = { ++ { "tlc59116" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(i2c, tlc59116_id); ++ ++static struct i2c_driver tlc59116_driver = { ++ .driver = { ++ .name = "tlc59116", ++ .of_match_table = of_match_ptr(of_tlc59116_leds_match), ++ }, ++ .probe = tlc59116_probe, ++ .remove = tlc59116_remove, ++ .id_table = tlc59116_id, ++}; ++ ++module_i2c_driver(tlc59116_driver); ++ ++MODULE_AUTHOR("Andrew Lunn "); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("TLC59116 LED driver"); diff --git a/target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch b/target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch new file mode 100644 index 0000000..bc0f1a6 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch @@ -0,0 +1,66 @@ +From ce6031c89a35cffd5a5992b08377b77f49a004b9 Mon Sep 17 00:00:00 2001 +From: Sebastien Rannou +Date: Fri, 13 Feb 2015 15:55:03 +0100 +Subject: [PATCH] cpuidle: mvebu: Update cpuidle thresholds for Armada XP SOCs + +Originally, the thresholds used in the cpuidle driver for Armada SOCs +were temporarily chosen, leaving room for improvements. + +This commit updates the thresholds for the Armada XP SOCs with values +that positively impact performances: + + without patch with patch vendor kernel + - iperf localhost (gbit/sec) ~3.7 ~6.4 ~5.4 + - ioping tmpfs (iops) ~163k ~206k ~179k + - ioping tmpfs (mib/s) ~636 ~805 ~699 + +The idle power consumption is negatively impacted (proportionally less +than the performance gain), and we are still performing better than +the vendor kernel here: + + without patch with patch vendor kernel + - power consumption idle (W) ~2.4 ~3.2 ~4.4 + - power consumption busy (W) ~8.6 ~8.3 ~8.6 + +There is still room for improvement regarding the value of these +thresholds, they were chosen to mimic the vendor kernel. + +This patch only impacts Armada XP SOCs and was tested on Online Labs +C1 boards. A similar approach can be taken to improve the performances +of the Armada 370 and Armada 38x SOCs. + +Thanks a lot to Thomas Petazzoni, Gregory Clement and Willy Tarreau +for the discussions and tips around this topic. + +Signed-off-by: Sebastien Rannou +Signed-off-by: Daniel Lezcano +Acked-by: Gregory CLEMENT +--- + drivers/cpuidle/cpuidle-mvebu-v7.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/cpuidle/cpuidle-mvebu-v7.c ++++ b/drivers/cpuidle/cpuidle-mvebu-v7.c +@@ -50,18 +50,18 @@ static struct cpuidle_driver armadaxp_id + .states[0] = ARM_CPUIDLE_WFI_STATE, + .states[1] = { + .enter = mvebu_v7_enter_idle, +- .exit_latency = 10, ++ .exit_latency = 100, + .power_usage = 50, +- .target_residency = 100, ++ .target_residency = 1000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "MV CPU IDLE", + .desc = "CPU power down", + }, + .states[2] = { + .enter = mvebu_v7_enter_idle, +- .exit_latency = 100, ++ .exit_latency = 1000, + .power_usage = 5, +- .target_residency = 1000, ++ .target_residency = 10000, + .flags = CPUIDLE_FLAG_TIME_VALID | + MVEBU_V7_FLAG_DEEP_IDLE, + .name = "MV CPU DEEP IDLE", diff --git a/target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch b/target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch new file mode 100644 index 0000000..b55bba1 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -501,6 +501,8 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb \ + armada-385-db-ap.dtb \ ++ armada-385-linksys-caiman.dtb \ ++ armada-385-linksys-cobra.dtb \ + armada-385-rd.dtb + dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ diff --git a/target/linux/mvebu/patches-3.18/100-find_active_root.patch b/target/linux/mvebu/patches-3.18/100-find_active_root.patch new file mode 100644 index 0000000..e32b608 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/100-find_active_root.patch @@ -0,0 +1,61 @@ +The WRT1900AC among other Linksys routers uses a dual-firmware layout. +Dynamically rename the active partition to "ubi". + +Signed-off-by: Imre Kaloz + +--- a/drivers/mtd/ofpart.c ++++ b/drivers/mtd/ofpart.c +@@ -25,12 +25,15 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static int mangled_rootblock; ++ + static int parse_ofpart_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { + struct device_node *node; + const char *partname; ++ const char *owrtpart = "ubi"; + struct device_node *pp; + int nr_parts, i; + +@@ -78,9 +81,15 @@ static int parse_ofpart_partitions(struc + (*pparts)[i].offset = of_read_number(reg, a_cells); + (*pparts)[i].size = of_read_number(reg + a_cells, s_cells); + +- partname = of_get_property(pp, "label", &len); +- if (!partname) +- partname = of_get_property(pp, "name", &len); ++ if (mangled_rootblock && (i == mangled_rootblock)) { ++ partname = owrtpart; ++ } else { ++ partname = of_get_property(pp, "label", &len); ++ ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ } ++ + (*pparts)[i].name = partname; + + if (of_get_property(pp, "read-only", &len)) +@@ -178,6 +187,18 @@ static int __init ofpart_parser_init(voi + return 0; + } + ++static int __init active_root(char *str) ++{ ++ get_option(&str, &mangled_rootblock); ++ ++ if (!mangled_rootblock) ++ return 1; ++ ++ return 1; ++} ++ ++__setup("mangled_rootblock=", active_root); ++ + static void __exit ofpart_parser_exit(void) + { + deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch new file mode 100644 index 0000000..9089534 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch @@ -0,0 +1,15 @@ +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -49,12 +49,10 @@ + }; + + i2c0: i2c@11000 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + }; + + i2c1: i2c@11100 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; + }; + diff --git a/target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch b/target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch new file mode 100644 index 0000000..818fae7 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -236,7 +236,7 @@ + status = "disabled"; + }; + +- mdio { ++ mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch b/target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch new file mode 100644 index 0000000..1fea44f --- /dev/null +++ b/target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch @@ -0,0 +1,44 @@ +From 842f7d2c4d392c0571cf72e3eaca26742bebbd1e Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 2 Dec 2014 17:48:02 +0100 +Subject: ARM: mvebu: use the cpufreq-dt platform_data for independent clocks + +This commit adjusts the registration of the cpufreq-dt driver in the +mvebu platform to indicate to the cpufreq driver that the platform has +independent clocks for each CPU. + +Signed-off-by: Thomas Petazzoni +Acked-by: Jason Cooper +Signed-off-by: Arnd Bergmann + +--- a/arch/arm/mach-mvebu/pmsu.c ++++ b/arch/arm/mach-mvebu/pmsu.c +@@ -20,6 +20,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -586,6 +587,10 @@ int mvebu_pmsu_dfs_request(int cpu) + return 0; + } + ++struct cpufreq_dt_platform_data cpufreq_dt_pd = { ++ .independent_clocks = true, ++}; ++ + static int __init armada_xp_pmsu_cpufreq_init(void) + { + struct device_node *np; +@@ -658,7 +663,8 @@ static int __init armada_xp_pmsu_cpufreq + } + } + +- platform_device_register_simple("cpufreq-dt", -1, NULL, 0); ++ platform_device_register_data(NULL, "cpufreq-dt", -1, ++ &cpufreq_dt_pd, sizeof(cpufreq_dt_pd)); + return 0; + } + diff --git a/target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch b/target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch new file mode 100644 index 0000000..9ef1815 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch @@ -0,0 +1,137 @@ +This commit adds the implementation of ->suspend() and ->resume() +platform_driver hooks in order to save and restore the state of the +GPIO configuration. In order to achieve that, additional fields are +added to the mvebu_gpio_chip structure. + +Signed-off-by: Thomas Petazzoni +Acked-by: Alexandre Courbot +Signed-off-by: Linus Walleij + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -83,6 +83,14 @@ struct mvebu_gpio_chip { + int irqbase; + struct irq_domain *domain; + int soc_variant; ++ ++ /* Used to preserve GPIO registers accross suspend/resume */ ++ u32 out_reg; ++ u32 io_conf_reg; ++ u32 blink_en_reg; ++ u32 in_pol_reg; ++ u32 edge_mask_regs[4]; ++ u32 level_mask_regs[4]; + }; + + /* +@@ -562,6 +570,93 @@ static const struct of_device_id mvebu_g + }; + MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); + ++static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); ++ int i; ++ ++ mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); ++ mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); ++ mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); ++ mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); ++ ++ switch (mvchip->soc_variant) { ++ case MVEBU_GPIO_SOC_VARIANT_ORION: ++ mvchip->edge_mask_regs[0] = ++ readl(mvchip->membase + GPIO_EDGE_MASK_OFF); ++ mvchip->level_mask_regs[0] = ++ readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_MV78200: ++ for (i = 0; i < 2; i++) { ++ mvchip->edge_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_EDGE_MASK_MV78200_OFF(i)); ++ mvchip->level_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_LEVEL_MASK_MV78200_OFF(i)); ++ } ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: ++ for (i = 0; i < 4; i++) { ++ mvchip->edge_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_EDGE_MASK_ARMADAXP_OFF(i)); ++ mvchip->level_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ return 0; ++} ++ ++static int mvebu_gpio_resume(struct platform_device *pdev) ++{ ++ struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); ++ int i; ++ ++ writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); ++ writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); ++ writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); ++ writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); ++ ++ switch (mvchip->soc_variant) { ++ case MVEBU_GPIO_SOC_VARIANT_ORION: ++ writel(mvchip->edge_mask_regs[0], ++ mvchip->membase + GPIO_EDGE_MASK_OFF); ++ writel(mvchip->level_mask_regs[0], ++ mvchip->membase + GPIO_LEVEL_MASK_OFF); ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_MV78200: ++ for (i = 0; i < 2; i++) { ++ writel(mvchip->edge_mask_regs[i], ++ mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); ++ writel(mvchip->level_mask_regs[i], ++ mvchip->membase + ++ GPIO_LEVEL_MASK_MV78200_OFF(i)); ++ } ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: ++ for (i = 0; i < 4; i++) { ++ writel(mvchip->edge_mask_regs[i], ++ mvchip->membase + ++ GPIO_EDGE_MASK_ARMADAXP_OFF(i)); ++ writel(mvchip->level_mask_regs[i], ++ mvchip->membase + ++ GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ return 0; ++} ++ + static int mvebu_gpio_probe(struct platform_device *pdev) + { + struct mvebu_gpio_chip *mvchip; +@@ -585,6 +680,8 @@ static int mvebu_gpio_probe(struct platf + if (!mvchip) + return -ENOMEM; + ++ platform_set_drvdata(pdev, mvchip); ++ + if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { + dev_err(&pdev->dev, "Missing ngpios OF property\n"); + return -ENODEV; +@@ -743,5 +840,7 @@ static struct platform_driver mvebu_gpio + .of_match_table = mvebu_gpio_of_match, + }, + .probe = mvebu_gpio_probe, ++ .suspend = mvebu_gpio_suspend, ++ .resume = mvebu_gpio_resume, + }; + module_platform_driver(mvebu_gpio_driver); diff --git a/target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch b/target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch new file mode 100644 index 0000000..fe74199 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch @@ -0,0 +1,15 @@ +A platform_driver does not need to set an owner, it will be populated by the +driver core. + +Signed-off-by: Wolfram Sang + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -836,7 +836,6 @@ static int mvebu_gpio_probe(struct platf + static struct platform_driver mvebu_gpio_driver = { + .driver = { + .name = "mvebu-gpio", +- .owner = THIS_MODULE, + .of_match_table = mvebu_gpio_of_match, + }, + .probe = mvebu_gpio_probe, diff --git a/target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch b/target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch new file mode 100644 index 0000000..48ab67d --- /dev/null +++ b/target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch @@ -0,0 +1,223 @@ +Wrap some long lines. +Prefer seq_puts() over seq_printf(). +space to tab conversions. +Spelling error fix. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/gpio-mvebu.c | 77 ++++++++++++++++++++++++++--------------------- + 1 file changed, 42 insertions(+), 35 deletions(-) + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -59,7 +59,7 @@ + #define GPIO_LEVEL_MASK_OFF 0x001c + + /* The MV78200 has per-CPU registers for edge mask and level mask */ +-#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) ++#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) + #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) + + /* The Armada XP has per-CPU registers for interrupt cause, interrupt +@@ -69,11 +69,11 @@ + #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) + #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) + +-#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 +-#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 ++#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 ++#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 + #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 + +-#define MVEBU_MAX_GPIO_PER_BANK 32 ++#define MVEBU_MAX_GPIO_PER_BANK 32 + + struct mvebu_gpio_chip { + struct gpio_chip chip; +@@ -82,9 +82,9 @@ struct mvebu_gpio_chip { + void __iomem *percpu_membase; + int irqbase; + struct irq_domain *domain; +- int soc_variant; ++ int soc_variant; + +- /* Used to preserve GPIO registers accross suspend/resume */ ++ /* Used to preserve GPIO registers across suspend/resume */ + u32 out_reg; + u32 io_conf_reg; + u32 blink_en_reg; +@@ -107,7 +107,8 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_BLINK_EN_OFF; + } + +-static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) + { + return mvchip->membase + GPIO_IO_CONF_OFF; + } +@@ -117,12 +118,14 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_IN_POL_OFF; + } + +-static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) + { + return mvchip->membase + GPIO_DATA_IN_OFF; + } + +-static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) + { + int cpu; + +@@ -132,13 +135,15 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_EDGE_CAUSE_OFF; + case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: + cpu = smp_processor_id(); +- return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); ++ return mvchip->percpu_membase + ++ GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); + default: + BUG(); + } + } + +-static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) + { + int cpu; + +@@ -150,7 +155,8 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); + case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: + cpu = smp_processor_id(); +- return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); ++ return mvchip->percpu_membase + ++ GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); + default: + BUG(); + } +@@ -168,7 +174,8 @@ static void __iomem *mvebu_gpioreg_level + return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); + case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: + cpu = smp_processor_id(); +- return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); ++ return mvchip->percpu_membase + ++ GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); + default: + BUG(); + } +@@ -372,22 +379,22 @@ static void mvebu_gpio_level_irq_unmask( + * value of the line or the opposite value. + * + * Level IRQ handlers: DATA_IN is used directly as cause register. +- * Interrupt are masked by LEVEL_MASK registers. ++ * Interrupt are masked by LEVEL_MASK registers. + * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. +- * Interrupt are masked by EDGE_MASK registers. ++ * Interrupt are masked by EDGE_MASK registers. + * Both-edge handlers: Similar to regular Edge handlers, but also swaps +- * the polarity to catch the next line transaction. +- * This is a race condition that might not perfectly +- * work on some use cases. ++ * the polarity to catch the next line transaction. ++ * This is a race condition that might not perfectly ++ * work on some use cases. + * + * Every eight GPIO lines are grouped (OR'ed) before going up to main + * cause register. + * +- * EDGE cause mask +- * data-in /--------| |-----| |----\ +- * -----| |----- ---- to main cause reg +- * X \----------------| |----/ +- * polarity LEVEL mask ++ * EDGE cause mask ++ * data-in /--------| |-----| |----\ ++ * -----| |----- ---- to main cause reg ++ * X \----------------| |----/ ++ * polarity LEVEL mask + * + ****************************************************************************/ + +@@ -402,9 +409,8 @@ static int mvebu_gpio_irq_set_type(struc + pin = d->hwirq; + + u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); +- if (!u) { ++ if (!u) + return -EINVAL; +- } + + type &= IRQ_TYPE_SENSE_MASK; + if (type == IRQ_TYPE_NONE) +@@ -537,13 +543,13 @@ static void mvebu_gpio_dbg_show(struct s + (data_in ^ in_pol) & msk ? "hi" : "lo", + in_pol & msk ? "lo" : "hi"); + if (!((edg_msk | lvl_msk) & msk)) { +- seq_printf(s, " disabled\n"); ++ seq_puts(s, " disabled\n"); + continue; + } + if (edg_msk & msk) +- seq_printf(s, " edge "); ++ seq_puts(s, " edge "); + if (lvl_msk & msk) +- seq_printf(s, " level"); ++ seq_puts(s, " level"); + seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); + } + } +@@ -554,15 +560,15 @@ static void mvebu_gpio_dbg_show(struct s + static const struct of_device_id mvebu_gpio_of_match[] = { + { + .compatible = "marvell,orion-gpio", +- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, + }, + { + .compatible = "marvell,mv78200-gpio", +- .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, + }, + { + .compatible = "marvell,armadaxp-gpio", +- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, + }, + { + /* sentinel */ +@@ -676,7 +682,8 @@ static int mvebu_gpio_probe(struct platf + else + soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; + +- mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); ++ mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), ++ GFP_KERNEL); + if (!mvchip) + return -ENOMEM; + +@@ -775,8 +782,8 @@ static int mvebu_gpio_probe(struct platf + * interrupt handlers, with each handler dealing with 8 GPIO + * pins. */ + for (i = 0; i < 4; i++) { +- int irq; +- irq = platform_get_irq(pdev, i); ++ int irq = platform_get_irq(pdev, i); ++ + if (irq < 0) + continue; + irq_set_handler_data(irq, mvchip); +@@ -835,7 +842,7 @@ static int mvebu_gpio_probe(struct platf + + static struct platform_driver mvebu_gpio_driver = { + .driver = { +- .name = "mvebu-gpio", ++ .name = "mvebu-gpio", + .of_match_table = mvebu_gpio_of_match, + }, + .probe = mvebu_gpio_probe, diff --git a/target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch b/target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch new file mode 100644 index 0000000..aeb884a --- /dev/null +++ b/target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch @@ -0,0 +1,63 @@ +Ensure that when there is an error during probe that the gpiochip is +removed and the generic irq chip is removed. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/gpio-mvebu.c | 23 +++++++++++++++++------ + 1 file changed, 17 insertions(+), 6 deletions(-) + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -675,6 +675,7 @@ static int mvebu_gpio_probe(struct platf + unsigned int ngpios; + int soc_variant; + int i, cpu, id; ++ int err; + + match = of_match_device(mvebu_gpio_of_match, &pdev->dev); + if (match) +@@ -793,14 +794,16 @@ static int mvebu_gpio_probe(struct platf + mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); + if (mvchip->irqbase < 0) { + dev_err(&pdev->dev, "no irqs\n"); +- return mvchip->irqbase; ++ err = mvchip->irqbase; ++ goto err_gpiochip_add; + } + + gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, + mvchip->membase, handle_level_irq); + if (!gc) { + dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); +- return -ENOMEM; ++ err = -ENOMEM; ++ goto err_gpiochip_add; + } + + gc->private = mvchip; +@@ -831,13 +834,21 @@ static int mvebu_gpio_probe(struct platf + if (!mvchip->domain) { + dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", + mvchip->chip.label); +- irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, +- IRQ_LEVEL | IRQ_NOPROBE); +- kfree(gc); +- return -ENODEV; ++ err = -ENODEV; ++ goto err_generic_chip; + } + + return 0; ++ ++err_generic_chip: ++ irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, ++ IRQ_LEVEL | IRQ_NOPROBE); ++ kfree(gc); ++ ++err_gpiochip_add: ++ gpiochip_remove(&mvchip->chip); ++ ++ return err; + } + + static struct platform_driver mvebu_gpio_driver = { diff --git a/target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch b/target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch new file mode 100644 index 0000000..49a8c0a --- /dev/null +++ b/target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch @@ -0,0 +1,433 @@ +Armada 370/XP devices can 'blink' gpio lines with a configurable on +and off period. This can be modelled as a PWM. + +However, there are only two sets of PWM configuration registers for +all the gpio lines. This driver simply allows a single gpio line per +gpio chip of 32 lines to be used as a PWM. Attempts to use more return +EBUSY. + +Due to the interleaving of registers it is not simple to separate the +PWM driver from the gpio driver. Thus the gpio driver has been +extended with a PWM driver. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/Kconfig | 5 ++ + drivers/gpio/Makefile | 1 + + drivers/gpio/gpio-mvebu-pwm.c | 202 ++++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpio-mvebu.c | 37 +++----- + drivers/gpio/gpio-mvebu.h | 79 +++++++++++++++++ + 5 files changed, 299 insertions(+), 25 deletions(-) + create mode 100644 drivers/gpio/gpio-mvebu-pwm.c + create mode 100644 drivers/gpio/gpio-mvebu.h + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -223,6 +223,11 @@ config GPIO_MVEBU + select GPIO_GENERIC + select GENERIC_IRQ_CHIP + ++config GPIO_MVEBU_PWM ++ def_bool y ++ depends on GPIO_MVEBU ++ depends on PWM ++ + config GPIO_MXC + def_bool y + depends on ARCH_MXC +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -58,6 +58,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o + obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o + obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o + obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o ++obj-$(CONFIG_GPIO_MVEBU_PWM) += gpio-mvebu-pwm.o + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o + obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu-pwm.c +@@ -0,0 +1,202 @@ ++#include "asm/io.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include "gpio-mvebu.h" ++#include "gpiolib.h" ++static void __iomem *mvebu_gpioreg_blink_select(struct mvebu_gpio_chip *mvchip) ++{ ++ return mvchip->membase + GPIO_BLINK_CNT_SELECT; ++} ++ ++static inline struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) ++{ ++ return container_of(chip, struct mvebu_pwm, chip); ++} ++ ++static inline struct mvebu_gpio_chip *to_mvchip(struct mvebu_pwm *pwm) ++{ ++ return container_of(pwm, struct mvebu_gpio_chip, pwm); ++} ++ ++static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ int ret = 0; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ if (pwm->used) { ++ ret = -EBUSY; ++ } else { ++ if (!desc) { ++ ret = -ENODEV; ++ goto out; ++ } ++ ret = gpiod_request(desc, "mvebu-pwm"); ++ if (ret) ++ goto out; ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiod_free(desc); ++ goto out; ++ } ++ ++ pwm->pin = pwmd->pwm - mvchip->chip.base; ++ pwm->used = true; ++ } ++ ++out: ++ spin_unlock_irqrestore(&pwm->lock, flags); ++ return ret; ++} ++ ++static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ gpiod_free(desc); ++ pwm->used = false; ++ spin_unlock_irqrestore(&pwm->lock, flags); ++} ++ ++static int mvebu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwmd, ++ int duty_ns, int period_ns) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ unsigned int on, off; ++ unsigned long long val; ++ u32 u; ++ ++ val = (unsigned long long) pwm->clk_rate * duty_ns; ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ on = val; ++ else ++ on = 1; ++ ++ val = (unsigned long long) pwm->clk_rate * (period_ns - duty_ns); ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ off = val; ++ else ++ off = 1; ++ ++ u = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ u &= ~(1 << pwm->pin); ++ u |= (pwm->id << pwm->pin); ++ writel_relaxed(u, mvebu_gpioreg_blink_select(mvchip)); ++ ++ writel_relaxed(on, pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(off, pwm->membase + BLINK_OFF_DURATION); ++ ++ return 0; ++} ++ ++static int mvebu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 1); ++ ++ return 0; ++} ++ ++static void mvebu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 0); ++} ++ ++static const struct pwm_ops mvebu_pwm_ops = { ++ .request = mvebu_pwm_request, ++ .free = mvebu_pwm_free, ++ .config = mvebu_pwm_config, ++ .enable = mvebu_pwm_enable, ++ .disable = mvebu_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ pwm->blink_select = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ pwm->blink_on_duration = ++ readl_relaxed(pwm->membase + BLINK_ON_DURATION); ++ pwm->blink_off_duration = ++ readl_relaxed(pwm->membase + BLINK_OFF_DURATION); ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ writel_relaxed(pwm->blink_select, mvebu_gpioreg_blink_select(mvchip)); ++ writel_relaxed(pwm->blink_on_duration, ++ pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(pwm->blink_off_duration, ++ pwm->membase + BLINK_OFF_DURATION); ++} ++ ++/* ++ * Armada 370/XP has simple PWM support for gpio lines. Other SoCs ++ * don't have this hardware. So if we don't have the necessary ++ * resource, it is not an error. ++ */ ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ struct device *dev = &pdev->dev; ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ struct resource *res; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); ++ if (!res) ++ return 0; ++ ++ mvchip->pwm.membase = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mvchip->pwm.membase)) ++ return PTR_ERR(mvchip->percpu_membase); ++ ++ if (id < 0 || id > 1) ++ return -EINVAL; ++ pwm->id = id; ++ ++ if (IS_ERR(mvchip->clk)) ++ return PTR_ERR(mvchip->clk); ++ ++ pwm->clk_rate = clk_get_rate(mvchip->clk); ++ if (!pwm->clk_rate) { ++ dev_err(dev, "failed to get clock rate\n"); ++ return -EINVAL; ++ } ++ ++ pwm->chip.dev = dev; ++ pwm->chip.ops = &mvebu_pwm_ops; ++ pwm->chip.base = mvchip->chip.base; ++ pwm->chip.npwm = mvchip->chip.ngpio; ++ pwm->chip.can_sleep = false; ++ ++ spin_lock_init(&pwm->lock); ++ ++ return pwmchip_add(&pwm->chip); ++} +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -42,10 +42,11 @@ + #include + #include + #include ++#include + #include + #include + #include +- ++#include "gpio-mvebu.h" + /* + * GPIO unit register offsets. + */ +@@ -75,24 +76,6 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + +-struct mvebu_gpio_chip { +- struct gpio_chip chip; +- spinlock_t lock; +- void __iomem *membase; +- void __iomem *percpu_membase; +- int irqbase; +- struct irq_domain *domain; +- int soc_variant; +- +- /* Used to preserve GPIO registers across suspend/resume */ +- u32 out_reg; +- u32 io_conf_reg; +- u32 blink_en_reg; +- u32 in_pol_reg; +- u32 edge_mask_regs[4]; +- u32 level_mask_regs[4]; +-}; +- + /* + * Functions returning addresses of individual registers for a given + * GPIO controller. +@@ -228,7 +211,7 @@ static int mvebu_gpio_get(struct gpio_ch + return (u >> pin) & 1; + } + +-static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) + { + struct mvebu_gpio_chip *mvchip = + container_of(chip, struct mvebu_gpio_chip, chip); +@@ -617,6 +600,8 @@ static int mvebu_gpio_suspend(struct pla + BUG(); + } + ++ mvebu_pwm_suspend(mvchip); ++ + return 0; + } + +@@ -660,6 +645,8 @@ static int mvebu_gpio_resume(struct plat + BUG(); + } + ++ mvebu_pwm_resume(mvchip); ++ + return 0; + } + +@@ -671,7 +658,6 @@ static int mvebu_gpio_probe(struct platf + struct resource *res; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; +- struct clk *clk; + unsigned int ngpios; + int soc_variant; + int i, cpu, id; +@@ -701,10 +687,10 @@ static int mvebu_gpio_probe(struct platf + return id; + } + +- clk = devm_clk_get(&pdev->dev, NULL); ++ mvchip->clk = devm_clk_get(&pdev->dev, NULL); + /* Not all SoCs require a clock.*/ +- if (!IS_ERR(clk)) +- clk_prepare_enable(clk); ++ if (!IS_ERR(mvchip->clk)) ++ clk_prepare_enable(mvchip->clk); + + mvchip->soc_variant = soc_variant; + mvchip->chip.label = dev_name(&pdev->dev); +@@ -838,7 +824,8 @@ static int mvebu_gpio_probe(struct platf + goto err_generic_chip; + } + +- return 0; ++ /* Armada 370/XP has simple PWM support for gpio lines */ ++ return mvebu_pwm_probe(pdev, mvchip, id); + + err_generic_chip: + irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu.h +@@ -0,0 +1,79 @@ ++/* ++ * Interface between MVEBU GPIO driver and PWM driver for GPIO pins ++ * ++ * Copyright (C) 2015, Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef MVEBU_GPIO_PWM_H ++#define MVEBU_GPIO_PWM_H ++ ++#define BLINK_ON_DURATION 0x0 ++#define BLINK_OFF_DURATION 0x4 ++#define GPIO_BLINK_CNT_SELECT 0x0020 ++ ++struct mvebu_pwm { ++ void __iomem *membase; ++ unsigned long clk_rate; ++ bool used; ++ unsigned pin; ++ struct pwm_chip chip; ++ int id; ++ spinlock_t lock; ++ ++ /* Used to preserve GPIO/PWM registers across suspend / ++ * resume */ ++ u32 blink_select; ++ u32 blink_on_duration; ++ u32 blink_off_duration; ++}; ++ ++struct mvebu_gpio_chip { ++ struct gpio_chip chip; ++ spinlock_t lock; ++ void __iomem *membase; ++ void __iomem *percpu_membase; ++ int irqbase; ++ struct irq_domain *domain; ++ int soc_variant; ++ struct clk *clk; ++#ifdef CONFIG_PWM ++ struct mvebu_pwm pwm; ++#endif ++ /* Used to preserve GPIO registers across suspend/resume */ ++ u32 out_reg; ++ u32 io_conf_reg; ++ u32 blink_en_reg; ++ u32 in_pol_reg; ++ u32 edge_mask_regs[4]; ++ u32 level_mask_regs[4]; ++}; ++ ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value); ++ ++#ifdef CONFIG_PWM ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id); ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip); ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip); ++#else ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ return 0; ++} ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++} ++#endif ++#endif diff --git a/target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch b/target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch new file mode 100644 index 0000000..48f9394 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch @@ -0,0 +1,52 @@ +Document the optional parameters needed for PWM operation of gpio +lines. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 ++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt ++++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +@@ -38,6 +38,23 @@ Required properties: + - #gpio-cells: Should be two. The first cell is the pin number. The + second cell is reserved for flags, unused at the moment. + ++Optional properties: ++ ++In order to use the gpio lines in PWM mode, some additional optional ++properties are required. Only Armada 370 and XP supports these ++properties. ++ ++- reg: an additional register set is needed, for the GPIO Blink ++ Counter on/off registers. ++ ++- reg-names: Must contain an entry "pwm" corresponding to the ++ additional register range needed for pwm operation. ++ ++- #pwm-cells: Should be two. The first cell is the pin number. The ++ second cell is reserved for flags, unused at the moment. ++ ++- clocks: Must be a phandle to the clock for the gpio controller. ++ + Example: + + gpio0: gpio@d0018100 { +@@ -51,3 +68,17 @@ Example: + #interrupt-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; ++ ++ gpio1: gpio@18140 { ++ compatible = "marvell,orion-gpio"; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; ++ ngpios = <17>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #pwm-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; ++ }; diff --git a/target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch b/target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch new file mode 100644 index 0000000..9272d99 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch @@ -0,0 +1,149 @@ +Add properties to the gpio nodes to allow them to be also used +as pwm lines. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-370.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 8 ++++++-- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 10 ++++++++-- + 4 files changed, 30 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -109,24 +109,30 @@ + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -169,24 +169,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -253,24 +253,28 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -291,24 +291,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { diff --git a/target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch b/target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch new file mode 100644 index 0000000..1ff724c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch @@ -0,0 +1,18 @@ +Now that the gpio driver also supports PWM operation, enable +the PWM framework in mvebu_v7_defconfig. + +Signed-off-by: Andrew Lunn +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -109,6 +109,7 @@ CONFIG_DMADEVICES=y + CONFIG_MV_XOR=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_MEMORY=y ++CONFIG_PWM=y + CONFIG_EXT4_FS=y + CONFIG_ISO9660_FS=y + CONFIG_JOLIET=y diff --git a/target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch b/target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch new file mode 100644 index 0000000..58d8280 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch @@ -0,0 +1,28 @@ +The mvebu gpio driver can also perform PWM on some pins. Us the +pwm-fan driver to control the fan of the WRT1900AC, giving us fine +grain control over its speed and hence noise. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-xp-wrt1900ac.dts | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -412,13 +412,11 @@ + }; + }; + +- gpio_fan { ++ pwm_fan { + /* SUNON HA4010V4-0000-C99 */ +- compatible = "gpio-fan"; +- gpios = <&gpio0 24 0>; + +- gpio-fan,speed-map = <0 0 +- 4500 1>; ++ compatible = "pwm-fan"; ++ pwms = <&gpio0 24 4000 0>; + }; + + mvsw61xx { diff --git a/target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch new file mode 100644 index 0000000..80cec30 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-385-rd.dts ++++ b/arch/arm/boot/dts/armada-385-rd.dts +@@ -42,6 +42,16 @@ + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; ++ ++ partition@0 { ++ label = "uboot"; ++ reg = <0 0x400000>; ++ }; ++ ++ partition@1 { ++ label = "firmware"; ++ reg = <0x400000 0xc00000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch new file mode 100644 index 0000000..2845181 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch @@ -0,0 +1,34 @@ +From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Tue, 13 Jan 2015 11:14:09 +0100 +Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -162,6 +162,21 @@ + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; ++ ++ mtd0@00000000 { ++ label = "u-boot"; ++ reg = <0x00000000 0x00800000>; ++ }; ++ ++ mtd1@00800000 { ++ label = "kernel"; ++ reg = <0x00800000 0x00800000>; ++ }; ++ ++ mtd2@01000000 { ++ label = "ubi"; ++ reg = <0x01000000 0x3f000000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-3.18/300-add_missing_labels.patch b/target/linux/mvebu/patches-3.18/300-add_missing_labels.patch new file mode 100644 index 0000000..b674b56 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/300-add_missing_labels.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -173,7 +173,7 @@ + status = "disabled"; + }; + +- serial@12000 { ++ uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; +@@ -193,7 +193,7 @@ + status = "disabled"; + }; + +- pinctrl@18000 { ++ pinctrl: pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + +@@ -412,7 +412,7 @@ + status = "disabled"; + }; + +- mdio@72004 { ++ mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch b/target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch new file mode 100644 index 0000000..399421d --- /dev/null +++ b/target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch @@ -0,0 +1,403 @@ +--- /dev/null ++++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt +@@ -0,0 +1,22 @@ ++* Real Time Clock of the Armada 38x SoCs ++ ++RTC controller for the Armada 38x SoCs ++ ++Required properties: ++- compatible : Should be "marvell,armada-380-rtc" ++- reg: a list of base address and size pairs, one for each entry in ++ reg-names ++- reg names: should contain: ++ * "rtc" for the RTC registers ++ * "rtc-soc" for the SoC related registers and among them the one ++ related to the interrupt. ++- interrupts: IRQ line for the RTC. ++ ++Example: ++ ++rtc@a3800 { ++ compatible = "marvell,armada-380-rtc"; ++ reg = <0xa3800 0x20>, <0x184a0 0x0c>; ++ reg-names = "rtc", "rtc-soc"; ++ interrupts = ; ++}; +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1262,6 +1262,16 @@ config RTC_DRV_MV + This driver can also be built as a module. If so, the module + will be called rtc-mv. + ++config RTC_DRV_ARMADA38X ++ tristate "Armada 38x Marvell SoC RTC" ++ depends on ARCH_MVEBU ++ help ++ If you say yes here you will get support for the in-chip RTC ++ that can be found in the Armada 38x Marvell's SoC device ++ ++ This driver can also be built as a module. If so, the module ++ will be called armada38x-rtc. ++ + config RTC_DRV_PS3 + tristate "PS3 RTC" + depends on PPC_PS3 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-8 + obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o + obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o + obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o ++obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o + obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o + obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o + obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o +--- /dev/null ++++ b/drivers/rtc/rtc-armada38x.c +@@ -0,0 +1,320 @@ ++/* ++ * RTC driver for the Armada 38x Marvell SoCs ++ * ++ * Copyright (C) 2015 Marvell ++ * ++ * Gregory Clement ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_STATUS 0x0 ++#define RTC_STATUS_ALARM1 BIT(0) ++#define RTC_STATUS_ALARM2 BIT(1) ++#define RTC_IRQ1_CONF 0x4 ++#define RTC_IRQ1_AL_EN BIT(0) ++#define RTC_IRQ1_FREQ_EN BIT(1) ++#define RTC_IRQ1_FREQ_1HZ BIT(2) ++#define RTC_TIME 0xC ++#define RTC_ALARM1 0x10 ++ ++#define SOC_RTC_INTERRUPT 0x8 ++#define SOC_RTC_ALARM1 BIT(0) ++#define SOC_RTC_ALARM2 BIT(1) ++#define SOC_RTC_ALARM1_MASK BIT(2) ++#define SOC_RTC_ALARM2_MASK BIT(3) ++ ++struct armada38x_rtc { ++ struct rtc_device *rtc_dev; ++ void __iomem *regs; ++ void __iomem *regs_soc; ++ spinlock_t lock; ++ int irq; ++}; ++ ++/* ++ * According to the datasheet, the OS should wait 5us after every ++ * register write to the RTC hard macro so that the required update ++ * can occur without holding off the system bus ++ */ ++static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) ++{ ++ writel(val, rtc->regs + offset); ++ udelay(5); ++} ++ ++static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long time, time_check, flags; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ time = readl(rtc->regs + RTC_TIME); ++ /* ++ * WA for failing time set attempts. As stated in HW ERRATA if ++ * more than one second between two time reads is detected ++ * then read once again. ++ */ ++ time_check = readl(rtc->regs + RTC_TIME); ++ if ((time_check - time) > 1) ++ time_check = readl(rtc->regs + RTC_TIME); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ rtc_time_to_tm(time_check, tm); ++ ++ return 0; ++} ++ ++static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ int ret = 0; ++ unsigned long time, flags; ++ ++ ret = rtc_tm_to_time(tm, &time); ++ ++ if (ret) ++ goto out; ++ /* ++ * Setting the RTC time not always succeeds. According to the ++ * errata we need to first write on the status register and ++ * then wait for 100ms before writing to the time register to be ++ * sure that the data will be taken into account. ++ */ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ rtc_delayed_write(0, rtc, RTC_STATUS); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ msleep(100); ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ rtc_delayed_write(time, rtc, RTC_TIME); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++out: ++ return ret; ++} ++ ++static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long time, flags; ++ u32 val; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ time = readl(rtc->regs + RTC_ALARM1); ++ val = readl(rtc->regs + RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN; ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ alrm->enabled = val ? 1 : 0; ++ rtc_time_to_tm(time, &alrm->time); ++ ++ return 0; ++} ++ ++static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long time, flags; ++ int ret = 0; ++ u32 val; ++ ++ ret = rtc_tm_to_time(&alrm->time, &time); ++ ++ if (ret) ++ goto out; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ rtc_delayed_write(time, rtc, RTC_ALARM1); ++ ++ if (alrm->enabled) { ++ rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF); ++ val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); ++ writel(val | SOC_RTC_ALARM1_MASK, ++ rtc->regs_soc + SOC_RTC_INTERRUPT); ++ } ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++out: ++ return ret; ++} ++ ++static int armada38x_rtc_alarm_irq_enable(struct device *dev, ++ unsigned int enabled) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ if (enabled) ++ rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF); ++ else ++ rtc_delayed_write(0, rtc, RTC_IRQ1_CONF); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ return 0; ++} ++ ++static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data) ++{ ++ struct armada38x_rtc *rtc = data; ++ u32 val; ++ int event = RTC_IRQF | RTC_AF; ++ ++ dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq); ++ ++ spin_lock(&rtc->lock); ++ ++ val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); ++ ++ writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT); ++ val = readl(rtc->regs + RTC_IRQ1_CONF); ++ /* disable all the interrupts for alarm 1 */ ++ rtc_delayed_write(0, rtc, RTC_IRQ1_CONF); ++ /* Ack the event */ ++ rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS); ++ ++ spin_unlock(&rtc->lock); ++ ++ if (val & RTC_IRQ1_FREQ_EN) { ++ if (val & RTC_IRQ1_FREQ_1HZ) ++ event |= RTC_UF; ++ else ++ event |= RTC_PF; ++ } ++ ++ rtc_update_irq(rtc->rtc_dev, 1, event); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct rtc_class_ops armada38x_rtc_ops = { ++ .read_time = armada38x_rtc_read_time, ++ .set_time = armada38x_rtc_set_time, ++ .read_alarm = armada38x_rtc_read_alarm, ++ .set_alarm = armada38x_rtc_set_alarm, ++ .alarm_irq_enable = armada38x_rtc_alarm_irq_enable, ++}; ++ ++static __init int armada38x_rtc_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct armada38x_rtc *rtc; ++ int ret; ++ ++ rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc), ++ GFP_KERNEL); ++ if (!rtc) ++ return -ENOMEM; ++ ++ spin_lock_init(&rtc->lock); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc"); ++ rtc->regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(rtc->regs)) ++ return PTR_ERR(rtc->regs); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc"); ++ rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(rtc->regs_soc)) ++ return PTR_ERR(rtc->regs_soc); ++ ++ rtc->irq = platform_get_irq(pdev, 0); ++ ++ if (rtc->irq < 0) { ++ dev_err(&pdev->dev, "no irq\n"); ++ return rtc->irq; ++ } ++ if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq, ++ 0, pdev->name, rtc) < 0) { ++ dev_warn(&pdev->dev, "Interrupt not available.\n"); ++ rtc->irq = -1; ++ /* ++ * If there is no interrupt available then we can't ++ * use the alarm ++ */ ++ armada38x_rtc_ops.set_alarm = NULL; ++ armada38x_rtc_ops.alarm_irq_enable = NULL; ++ } ++ platform_set_drvdata(pdev, rtc); ++ if (rtc->irq != -1) ++ device_init_wakeup(&pdev->dev, 1); ++ ++ rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, ++ &armada38x_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc->rtc_dev)) { ++ ret = PTR_ERR(rtc->rtc_dev); ++ dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int armada38x_rtc_suspend(struct device *dev) ++{ ++ if (device_may_wakeup(dev)) { ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ ++ return enable_irq_wake(rtc->irq); ++ } ++ ++ return 0; ++} ++ ++static int armada38x_rtc_resume(struct device *dev) ++{ ++ if (device_may_wakeup(dev)) { ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ ++ return disable_irq_wake(rtc->irq); ++ } ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops, ++ armada38x_rtc_suspend, armada38x_rtc_resume); ++ ++#ifdef CONFIG_OF ++static const struct of_device_id armada38x_rtc_of_match_table[] = { ++ { .compatible = "marvell,armada-380-rtc", }, ++ {} ++}; ++#endif ++ ++static struct platform_driver armada38x_rtc_driver = { ++ .driver = { ++ .name = "armada38x-rtc", ++ .pm = &armada38x_rtc_pm_ops, ++ .of_match_table = of_match_ptr(armada38x_rtc_of_match_table), ++ }, ++}; ++ ++module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe); ++ ++MODULE_DESCRIPTION("Marvell Armada 38x RTC driver"); ++MODULE_AUTHOR("Gregory CLEMENT "); ++MODULE_LICENSE("GPL"); +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1136,6 +1136,7 @@ M: Sebastian Hesselbarth +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -420,6 +420,13 @@ + clocks = <&gateclk 4>; + }; + ++ rtc@a3800 { ++ compatible = "marvell,armada-380-rtc"; ++ reg = <0xa3800 0x20>, <0x184a0 0x0c>; ++ reg-names = "rtc", "rtc-soc"; ++ interrupts = ; ++ }; ++ + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; diff --git a/target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch b/target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch new file mode 100644 index 0000000..3ee9f5c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch @@ -0,0 +1,47 @@ +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -158,12 +159,27 @@ static int xhci_plat_probe(struct platfo + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) + xhci->shared_hcd->can_do_streams = 1; + ++ hcd->usb_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0); ++ if (IS_ERR(hcd->usb_phy)) { ++ ret = PTR_ERR(hcd->usb_phy); ++ if (ret == -EPROBE_DEFER) ++ goto put_usb3_hcd; ++ hcd->usb_phy = NULL; ++ } else { ++ ret = usb_phy_init(hcd->usb_phy); ++ if (ret) ++ goto put_usb3_hcd; ++ } ++ + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); + if (ret) +- goto put_usb3_hcd; ++ goto disable_usb_phy; + + return 0; + ++disable_usb_phy: ++ usb_phy_shutdown(hcd->usb_phy); ++ + put_usb3_hcd: + usb_put_hcd(xhci->shared_hcd); + +@@ -187,6 +203,7 @@ static int xhci_plat_remove(struct platf + struct clk *clk = xhci->clk; + + usb_remove_hcd(xhci->shared_hcd); ++ usb_phy_shutdown(hcd->usb_phy); + usb_put_hcd(xhci->shared_hcd); + + usb_remove_hcd(hcd); diff --git a/target/linux/mvebu/patches-4.0/001-add_mamba_support.patch b/target/linux/mvebu/patches-4.0/001-add_mamba_support.patch new file mode 100644 index 0000000..0fc2638 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/001-add_mamba_support.patch @@ -0,0 +1,388 @@ +From 4824140f4bd1caaf900215aabe27e4bdd1677704 Mon Sep 17 00:00:00 2001 +From: Imre Kaloz +Date: Mon, 16 Feb 2015 13:31:04 +0100 +Subject: [PATCH] ARM: mvebu: add Linksys WRT1900AC (Mamba) support + +The Linksys WRT1900AC (Mamba) is a router that has + +- 2 mini-PCIe slots with Marvell 88W8864 radios +- 1 USB 3.0 port +- 1 USB 2.0/eSATAp port +- 2 Ethernet interfaces connected to a 88E6172 switch (1x WAN + 4x LAN) +- 128MB NAND flash +- 256MB RAM + +gregory.clement@free-electrons.com: - add ARM to the title + - fix the reference to CONFIG_DEBUG_MVEBU_UART0_ALTERNATE + - fix the unbalanced comment for the syscfg partition + +Signed-off-by: Imre Kaloz +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 348 ++++++++++++++++++++++++++ + 2 files changed, 349 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-xp-linksys-mamba.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -629,6 +629,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-db.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ ++ armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -0,0 +1,348 @@ ++/* ++ * Device Tree file for the Linksys WRT1900AC (Mamba). ++ * ++ * Note: this board is shipped with a new generation boot loader that ++ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk ++ * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be ++ * used. ++ * ++ * Copyright (C) 2014 Imre Kaloz ++ * ++ * Based on armada-xp-axpwifiap.dts: ++ * ++ * Copyright (C) 2013 Marvell ++ * ++ * Thomas Petazzoni ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "armada-xp-mv78230.dtsi" ++ ++/ { ++ model = "Linksys WRT1900AC"; ++ compatible = "linksys,mamba", "marvell,armadaxp-mv78230", ++ "marvell,armadaxp", "marvell,armada-370-xp"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ ++ }; ++ ++ soc { ++ ranges = ; ++ ++ pcie-controller { ++ status = "okay"; ++ ++ /* Etron EJ168 USB 3.0 controller */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ /* First mini-PCIe port */ ++ pcie@2,0 { ++ /* Port 0, Lane 1 */ ++ status = "okay"; ++ }; ++ ++ /* Second mini-PCIe port */ ++ pcie@3,0 { ++ /* Port 0, Lane 3 */ ++ status = "okay"; ++ }; ++ }; ++ ++ internal-regs { ++ ++ /* J10: VCC, NC, RX, NC, TX, GND */ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ sata@a0000 { ++ nr-ports = <1>; ++ status = "okay"; ++ }; ++ ++ ethernet@70000 { ++ pinctrl-0 = <&ge0_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ ethernet@74000 { ++ pinctrl-0 = <&ge1_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ /* USB part of the eSATA/USB 2.0 port */ ++ usb@50000 { ++ status = "okay"; ++ }; ++ ++ i2c@11000 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ ++ tmp421@4c { ++ compatible = "ti,tmp421"; ++ reg = <0x4c>; ++ }; ++ ++ tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #gpio-cells = <2>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan_amber@0 { ++ label = "mamba:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ wan_white@1 { ++ label = "mamba:white:wan"; ++ reg = <0x1>; ++ }; ++ ++ wlan_2g@2 { ++ label = "mamba:white:wlan_2g"; ++ reg = <0x2>; ++ }; ++ ++ wlan_5g@3 { ++ label = "mamba:white:wlan_5g"; ++ reg = <0x3>; ++ }; ++ ++ esata@4 { ++ label = "mamba:white:esata"; ++ reg = <0x4>; ++ }; ++ ++ usb2@5 { ++ label = "mamba:white:usb2"; ++ reg = <0x5>; ++ }; ++ ++ usb3_1@6 { ++ label = "mamba:white:usb3_1"; ++ reg = <0x6>; ++ }; ++ ++ usb3_2@7 { ++ label = "mamba:white:usb3_2"; ++ reg = <0x7>; ++ }; ++ ++ wps_white@8 { ++ label = "mamba:white:wps"; ++ reg = <0x8>; ++ }; ++ ++ wps_amber@9 { ++ label = "mamba:amber:wps"; ++ reg = <0x9>; ++ }; ++ }; ++ }; ++ ++ nand@d0000 { ++ status = "okay"; ++ num-cs = <1>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u_env"; ++ reg = <0x100000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@140000 { ++ label = "s_env"; ++ reg = <0x140000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@900000 { ++ label = "devinfo"; ++ reg = <0x900000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ /* kernel1 overlaps with rootfs1 by design */ ++ partition@a00000 { ++ label = "kernel1"; ++ reg = <0xa00000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@d00000 { ++ label = "rootfs1"; ++ reg = <0xd00000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* kernel2 overlaps with rootfs2 by design */ ++ partition@3200000 { ++ label = "kernel2"; ++ reg = <0x3200000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@3500000 { ++ label = "rootfs2"; ++ reg = <0x3500000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* ++ * 38MB, last MB is for the BBT, not writable ++ */ ++ partition@5a00000 { ++ label = "syscfg"; ++ reg = <0x5a00000 0x2600000>; ++ }; ++ ++ /* ++ * Unused area between "s_env" and "devinfo". ++ * Moved here because otherwise the renumbered ++ * partitions would break the bootloader ++ * supplied bootargs ++ */ ++ partition@180000 { ++ label = "unused_area"; ++ reg = <0x180000 0x780000>; /* 7.5MB */ ++ }; ++ }; ++ ++ spi0: spi@10600 { ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "everspin,mr25h256"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <40000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&keys_pin>; ++ pinctrl-names = "default"; ++ ++ button@1 { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button@2 { ++ label = "Factory Reset Button"; ++ linux,code = ; ++ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&power_led_pin>; ++ pinctrl-names = "default"; ++ ++ power { ++ label = "mamba:white:power"; ++ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ gpio_fan { ++ /* SUNON HA4010V4-0000-C99 */ ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 24 0>; ++ ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ }; ++}; ++ ++&pinctrl { ++ ++ keys_pin: keys-pin { ++ marvell,pins = "mpp32", "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp40"; ++ marvell,function = "gpio"; ++ }; ++ ++ gpio_fan_pin: gpio-fan-pin { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch b/target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch new file mode 100644 index 0000000..6b51e48 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch @@ -0,0 +1,103 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -84,12 +84,100 @@ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,5ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; ++ ++ ETSI = ++ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; ++ }; ++ }; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,2ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; ++ ++ ETSI = ++ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch b/target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch new file mode 100644 index 0000000..e43d164 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -415,6 +415,16 @@ + gpio-fan,speed-map = <0 0 + 4500 1>; + }; ++ ++ mvsw61xx { ++ compatible = "marvell,88e6172"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ }; + }; + + &pinctrl { diff --git a/target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch b/target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch new file mode 100644 index 0000000..960a9fa --- /dev/null +++ b/target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -621,6 +621,8 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db-ap.dtb \ ++ armada-385-linksys-caiman.dtb \ ++ armada-385-linksys-cobra.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-rd.dtb diff --git a/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch b/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch new file mode 100644 index 0000000..3c4a111 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch @@ -0,0 +1,34 @@ +From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 11 Dec 2014 14:14:58 +0100 +Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller + +The A385 AP has a 1GB NAND chip. Enable it. + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -150,6 +150,19 @@ + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; ++ ++ nfc: flash@d0000 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ num-cs = <1>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ }; + }; + + pcie-controller { diff --git a/target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch b/target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch new file mode 100644 index 0000000..e55eca3 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch @@ -0,0 +1,51 @@ +Document the binding for the TLC59116 LED driver. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/leds/leds-tlc59116.txt | 40 ++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc59116.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/leds/leds-tlc59116.txt +@@ -0,0 +1,40 @@ ++LEDs connected to tcl59116 ++ ++Required properties ++- compatible: should be "ti,tlc59116" ++- #address-cells: must be 1 ++- #size-cells: must be 0 ++- reg: typically 0x68 ++ ++Each led is represented as a sub-node of the ti,,tlc59116. ++See Documentation/devicetree/bindings/leds/common.txt ++ ++LED sub-node properties: ++- reg: number of LED line, 0 to 15 ++- label: (optional) name of LED ++- linux,default-trigger : (optional) ++ ++Examples: ++ ++tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan@0 { ++ label = "wrt1900ac:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ 2g@2 { ++ label = "wrt1900ac:white:2g"; ++ reg = <0x2>; ++ }; ++ ++ alive@9 { ++ label = "wrt1900ac:green:alive"; ++ reg = <0x9>; ++ linux,default_trigger = "heartbeat"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch b/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch new file mode 100644 index 0000000..31110ad --- /dev/null +++ b/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch @@ -0,0 +1,297 @@ +The TLC59116 is an I2C bus controlled 16-channel LED driver. Each LED +output has its own 8-bit fixed-frequency PWM controller to control the +brightness of the LED. + +This is based on a driver from Belkin, but has been extensively +rewritten. + +Signed-off-by: Andrew Lunn +--- + drivers/leds/Kconfig | 8 ++ + drivers/leds/Makefile | 1 + + drivers/leds/leds-tlc59116.c | 252 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 261 insertions(+) + create mode 100644 drivers/leds/leds-tlc59116.c + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -467,6 +467,14 @@ config LEDS_TCA6507 + LED driver chips accessed via the I2C bus. + Driver support brightness control and hardware-assisted blinking. + ++config LEDS_TLC59116 ++ tristate "LED driver for TLC59116F controllers" ++ depends on LEDS_CLASS && I2C ++ select REGMAP_I2C ++ help ++ This option enables support for Texas Instruments TLC59116F ++ LED controller. ++ + config LEDS_MAX8997 + tristate "LED support for MAX8997 PMIC" + depends on LEDS_CLASS && MFD_MAX8997 +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_LEDS_LP8501) += leds-lp850 + obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o + obj-$(CONFIG_LEDS_LP8860) += leds-lp8860.o + obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o ++obj-$(CONFIG_LEDS_TLC59116) += leds-tlc59116.o + obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o + obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o + obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o +--- /dev/null ++++ b/drivers/leds/leds-tlc59116.c +@@ -0,0 +1,252 @@ ++/* ++ * Copyright 2014 Belkin Inc. ++ * Copyright 2014 Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TLC59116_LEDS 16 ++ ++#define TLC59116_REG_MODE1 0x00 ++#define MODE1_RESPON_ADDR_MASK 0xF0 ++#define MODE1_NORMAL_MODE (0 << 4) ++#define MODE1_SPEED_MODE (1 << 4) ++ ++#define TLC59116_REG_MODE2 0x01 ++#define MODE2_DIM (0 << 5) ++#define MODE2_BLINK (1 << 5) ++#define MODE2_OCH_STOP (0 << 3) ++#define MODE2_OCH_ACK (1 << 3) ++ ++#define TLC59116_REG_PWM(x) (0x02 + (x)) ++ ++#define TLC59116_REG_GRPPWM 0x12 ++#define TLC59116_REG_GRPFREQ 0x13 ++ ++/* LED Driver Output State, determine the source that drives LED outputs */ ++#define TLC59116_REG_LEDOUT(x) (0x14 + ((x) >> 2)) ++#define TLC59116_LED_OFF 0x0 /* Output LOW */ ++#define TLC59116_LED_ON 0x1 /* Output HI-Z */ ++#define TLC59116_DIM 0x2 /* Dimming */ ++#define TLC59116_BLINK 0x3 /* Blinking */ ++#define LED_MASK 0x3 ++ ++#define ldev_to_led(c) container_of(c, struct tlc59116_led, ldev) ++#define work_to_led(work) container_of(work, struct tlc59116_led, work) ++ ++struct tlc59116_led { ++ bool active; ++ struct regmap *regmap; ++ unsigned int led_no; ++ struct led_classdev ldev; ++ struct work_struct work; ++}; ++ ++struct tlc59116_priv { ++ struct tlc59116_led leds[TLC59116_LEDS]; ++}; ++ ++static int ++tlc59116_set_mode(struct regmap *regmap, u8 mode) ++{ ++ int err; ++ u8 val; ++ ++ if ((mode != MODE2_DIM) && (mode != MODE2_BLINK)) ++ mode = MODE2_DIM; ++ ++ /* Configure MODE1 register */ ++ err = regmap_write(regmap, TLC59116_REG_MODE1, MODE1_NORMAL_MODE); ++ if (err) ++ return err; ++ ++ /* Configure MODE2 Reg */ ++ val = MODE2_OCH_STOP | mode; ++ ++ return regmap_write(regmap, TLC59116_REG_MODE2, val); ++} ++ ++static int ++tlc59116_set_led(struct tlc59116_led *led, u8 val) ++{ ++ struct regmap *regmap = led->regmap; ++ unsigned int i = (led->led_no % 4) * 2; ++ unsigned int addr = TLC59116_REG_LEDOUT(led->led_no); ++ unsigned int mask = LED_MASK << i; ++ ++ val = val << i; ++ ++ return regmap_update_bits(regmap, addr, mask, val); ++} ++ ++static void ++tlc59116_led_work(struct work_struct *work) ++{ ++ struct tlc59116_led *led = work_to_led(work); ++ struct regmap *regmap = led->regmap; ++ int err; ++ u8 pwm; ++ ++ pwm = TLC59116_REG_PWM(led->led_no); ++ err = regmap_write(regmap, pwm, led->ldev.brightness); ++ if (err) ++ dev_err(led->ldev.dev, "Failed setting brightness\n"); ++} ++ ++static void ++tlc59116_led_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ struct tlc59116_led *led = ldev_to_led(led_cdev); ++ ++ led->ldev.brightness = value; ++ schedule_work(&led->work); ++} ++ ++static void ++tlc59116_destroy_devices(struct tlc59116_priv *priv, unsigned int i) ++{ ++ while (--i >= 0) { ++ if (priv->leds[i].active) { ++ led_classdev_unregister(&priv->leds[i].ldev); ++ cancel_work_sync(&priv->leds[i].work); ++ } ++ } ++} ++ ++static int ++tlc59116_configure(struct device *dev, ++ struct tlc59116_priv *priv, ++ struct regmap *regmap) ++{ ++ unsigned int i; ++ int err = 0; ++ ++ tlc59116_set_mode(regmap, MODE2_DIM); ++ for (i = 0; i < TLC59116_LEDS; i++) { ++ struct tlc59116_led *led = &priv->leds[i]; ++ ++ if (!led->active) ++ continue; ++ ++ led->regmap = regmap; ++ led->led_no = i; ++ led->ldev.brightness_set = tlc59116_led_set; ++ led->ldev.max_brightness = LED_FULL; ++ INIT_WORK(&led->work, tlc59116_led_work); ++ err = led_classdev_register(dev, &led->ldev); ++ if (err < 0) { ++ dev_err(dev, "couldn't register LED %s\n", ++ led->ldev.name); ++ goto exit; ++ } ++ tlc59116_set_led(led, TLC59116_DIM); ++ } ++ ++ return 0; ++ ++exit: ++ tlc59116_destroy_devices(priv, i); ++ return err; ++} ++ ++static const struct regmap_config tlc59116_regmap = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = 0x1e, ++}; ++ ++static int ++tlc59116_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ struct device *dev = &client->dev; ++ struct device_node *np = client->dev.of_node, *child; ++ struct regmap *regmap; ++ int err, count, reg; ++ ++ count = of_get_child_count(np); ++ if (!count || count > TLC59116_LEDS) ++ return -EINVAL; ++ ++ if (!i2c_check_functionality(client->adapter, ++ I2C_FUNC_SMBUS_BYTE_DATA)) ++ return -EIO; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ regmap = devm_regmap_init_i2c(client, &tlc59116_regmap); ++ if (IS_ERR(regmap)) { ++ err = PTR_ERR(regmap); ++ dev_err(dev, "Failed to allocate register map: %d\n", err); ++ return err; ++ } ++ ++ i2c_set_clientdata(client, priv); ++ ++ for_each_child_of_node(np, child) { ++ err = of_property_read_u32(child, "reg", ®); ++ if (err) ++ return err; ++ if (reg < 0 || reg >= TLC59116_LEDS) ++ return -EINVAL; ++ if (priv->leds[reg].active) ++ return -EINVAL; ++ priv->leds[reg].active = true; ++ priv->leds[reg].ldev.name = ++ of_get_property(child, "label", NULL) ? : child->name; ++ priv->leds[reg].ldev.default_trigger = ++ of_get_property(child, "linux,default-trigger", NULL); ++ } ++ return tlc59116_configure(dev, priv, regmap); ++} ++ ++static int ++tlc59116_remove(struct i2c_client *client) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ ++ tlc59116_destroy_devices(priv, TLC59116_LEDS); ++ ++ return 0; ++} ++ ++static const struct of_device_id of_tlc59116_leds_match[] = { ++ { .compatible = "ti,tlc59116", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, of_tlc59116_leds_match); ++ ++static const struct i2c_device_id tlc59116_id[] = { ++ { "tlc59116" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(i2c, tlc59116_id); ++ ++static struct i2c_driver tlc59116_driver = { ++ .driver = { ++ .name = "tlc59116", ++ .of_match_table = of_match_ptr(of_tlc59116_leds_match), ++ }, ++ .probe = tlc59116_probe, ++ .remove = tlc59116_remove, ++ .id_table = tlc59116_id, ++}; ++ ++module_i2c_driver(tlc59116_driver); ++ ++MODULE_AUTHOR("Andrew Lunn "); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("TLC59116 LED driver"); diff --git a/target/linux/mvebu/patches-4.0/100-find_active_root.patch b/target/linux/mvebu/patches-4.0/100-find_active_root.patch new file mode 100644 index 0000000..e32b608 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/100-find_active_root.patch @@ -0,0 +1,61 @@ +The WRT1900AC among other Linksys routers uses a dual-firmware layout. +Dynamically rename the active partition to "ubi". + +Signed-off-by: Imre Kaloz + +--- a/drivers/mtd/ofpart.c ++++ b/drivers/mtd/ofpart.c +@@ -25,12 +25,15 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static int mangled_rootblock; ++ + static int parse_ofpart_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { + struct device_node *node; + const char *partname; ++ const char *owrtpart = "ubi"; + struct device_node *pp; + int nr_parts, i; + +@@ -78,9 +81,15 @@ static int parse_ofpart_partitions(struc + (*pparts)[i].offset = of_read_number(reg, a_cells); + (*pparts)[i].size = of_read_number(reg + a_cells, s_cells); + +- partname = of_get_property(pp, "label", &len); +- if (!partname) +- partname = of_get_property(pp, "name", &len); ++ if (mangled_rootblock && (i == mangled_rootblock)) { ++ partname = owrtpart; ++ } else { ++ partname = of_get_property(pp, "label", &len); ++ ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ } ++ + (*pparts)[i].name = partname; + + if (of_get_property(pp, "read-only", &len)) +@@ -178,6 +187,18 @@ static int __init ofpart_parser_init(voi + return 0; + } + ++static int __init active_root(char *str) ++{ ++ get_option(&str, &mangled_rootblock); ++ ++ if (!mangled_rootblock) ++ return 1; ++ ++ return 1; ++} ++ ++__setup("mangled_rootblock=", active_root); ++ + static void __exit ofpart_parser_exit(void) + { + deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch new file mode 100644 index 0000000..42ee3b4 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch @@ -0,0 +1,15 @@ +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -88,12 +88,10 @@ + }; + + i2c0: i2c@11000 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + }; + + i2c1: i2c@11100 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; + }; + diff --git a/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch b/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch new file mode 100644 index 0000000..f1b8688 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch @@ -0,0 +1,433 @@ +Armada 370/XP devices can 'blink' gpio lines with a configurable on +and off period. This can be modelled as a PWM. + +However, there are only two sets of PWM configuration registers for +all the gpio lines. This driver simply allows a single gpio line per +gpio chip of 32 lines to be used as a PWM. Attempts to use more return +EBUSY. + +Due to the interleaving of registers it is not simple to separate the +PWM driver from the gpio driver. Thus the gpio driver has been +extended with a PWM driver. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/Kconfig | 5 ++ + drivers/gpio/Makefile | 1 + + drivers/gpio/gpio-mvebu-pwm.c | 202 ++++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpio-mvebu.c | 37 +++----- + drivers/gpio/gpio-mvebu.h | 79 +++++++++++++++++ + 5 files changed, 299 insertions(+), 25 deletions(-) + create mode 100644 drivers/gpio/gpio-mvebu-pwm.c + create mode 100644 drivers/gpio/gpio-mvebu.h + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -246,6 +246,11 @@ config GPIO_MVEBU + select GPIO_GENERIC + select GENERIC_IRQ_CHIP + ++config GPIO_MVEBU_PWM ++ def_bool y ++ depends on GPIO_MVEBU ++ depends on PWM ++ + config GPIO_MXC + def_bool y + depends on ARCH_MXC +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o + obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o + obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o + obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o ++obj-$(CONFIG_GPIO_MVEBU_PWM) += gpio-mvebu-pwm.o + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o + obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu-pwm.c +@@ -0,0 +1,202 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "gpio-mvebu.h" ++#include "gpiolib.h" ++ ++static void __iomem *mvebu_gpioreg_blink_select(struct mvebu_gpio_chip *mvchip) ++{ ++ return mvchip->membase + GPIO_BLINK_CNT_SELECT; ++} ++ ++static inline struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) ++{ ++ return container_of(chip, struct mvebu_pwm, chip); ++} ++ ++static inline struct mvebu_gpio_chip *to_mvchip(struct mvebu_pwm *pwm) ++{ ++ return container_of(pwm, struct mvebu_gpio_chip, pwm); ++} ++ ++static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ int ret = 0; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ if (pwm->used) { ++ ret = -EBUSY; ++ } else { ++ if (!desc) { ++ ret = -ENODEV; ++ goto out; ++ } ++ ret = gpiod_request(desc, "mvebu-pwm"); ++ if (ret) ++ goto out; ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiod_free(desc); ++ goto out; ++ } ++ ++ pwm->pin = pwmd->pwm - mvchip->chip.base; ++ pwm->used = true; ++ } ++ ++out: ++ spin_unlock_irqrestore(&pwm->lock, flags); ++ return ret; ++} ++ ++static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ gpiod_free(desc); ++ pwm->used = false; ++ spin_unlock_irqrestore(&pwm->lock, flags); ++} ++ ++static int mvebu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwmd, ++ int duty_ns, int period_ns) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ unsigned int on, off; ++ unsigned long long val; ++ u32 u; ++ ++ val = (unsigned long long) pwm->clk_rate * duty_ns; ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ on = val; ++ else ++ on = 1; ++ ++ val = (unsigned long long) pwm->clk_rate * (period_ns - duty_ns); ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ off = val; ++ else ++ off = 1; ++ ++ u = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ u &= ~(1 << pwm->pin); ++ u |= (pwm->id << pwm->pin); ++ writel_relaxed(u, mvebu_gpioreg_blink_select(mvchip)); ++ ++ writel_relaxed(on, pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(off, pwm->membase + BLINK_OFF_DURATION); ++ ++ return 0; ++} ++ ++static int mvebu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 1); ++ ++ return 0; ++} ++ ++static void mvebu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 0); ++} ++ ++static const struct pwm_ops mvebu_pwm_ops = { ++ .request = mvebu_pwm_request, ++ .free = mvebu_pwm_free, ++ .config = mvebu_pwm_config, ++ .enable = mvebu_pwm_enable, ++ .disable = mvebu_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ pwm->blink_select = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ pwm->blink_on_duration = ++ readl_relaxed(pwm->membase + BLINK_ON_DURATION); ++ pwm->blink_off_duration = ++ readl_relaxed(pwm->membase + BLINK_OFF_DURATION); ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ writel_relaxed(pwm->blink_select, mvebu_gpioreg_blink_select(mvchip)); ++ writel_relaxed(pwm->blink_on_duration, ++ pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(pwm->blink_off_duration, ++ pwm->membase + BLINK_OFF_DURATION); ++} ++ ++/* ++ * Armada 370/XP has simple PWM support for gpio lines. Other SoCs ++ * don't have this hardware. So if we don't have the necessary ++ * resource, it is not an error. ++ */ ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ struct device *dev = &pdev->dev; ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ struct resource *res; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); ++ if (!res) ++ return 0; ++ ++ mvchip->pwm.membase = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mvchip->pwm.membase)) ++ return PTR_ERR(mvchip->percpu_membase); ++ ++ if (id < 0 || id > 1) ++ return -EINVAL; ++ pwm->id = id; ++ ++ if (IS_ERR(mvchip->clk)) ++ return PTR_ERR(mvchip->clk); ++ ++ pwm->clk_rate = clk_get_rate(mvchip->clk); ++ if (!pwm->clk_rate) { ++ dev_err(dev, "failed to get clock rate\n"); ++ return -EINVAL; ++ } ++ ++ pwm->chip.dev = dev; ++ pwm->chip.ops = &mvebu_pwm_ops; ++ pwm->chip.base = mvchip->chip.base; ++ pwm->chip.npwm = mvchip->chip.ngpio; ++ pwm->chip.can_sleep = false; ++ ++ spin_lock_init(&pwm->lock); ++ ++ return pwmchip_add(&pwm->chip); ++} +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -42,10 +42,11 @@ + #include + #include + #include ++#include + #include + #include + #include +- ++#include "gpio-mvebu.h" + /* + * GPIO unit register offsets. + */ +@@ -75,24 +76,6 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + +-struct mvebu_gpio_chip { +- struct gpio_chip chip; +- spinlock_t lock; +- void __iomem *membase; +- void __iomem *percpu_membase; +- int irqbase; +- struct irq_domain *domain; +- int soc_variant; +- +- /* Used to preserve GPIO registers across suspend/resume */ +- u32 out_reg; +- u32 io_conf_reg; +- u32 blink_en_reg; +- u32 in_pol_reg; +- u32 edge_mask_regs[4]; +- u32 level_mask_regs[4]; +-}; +- + /* + * Functions returning addresses of individual registers for a given + * GPIO controller. +@@ -228,7 +211,7 @@ static int mvebu_gpio_get(struct gpio_ch + return (u >> pin) & 1; + } + +-static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) + { + struct mvebu_gpio_chip *mvchip = + container_of(chip, struct mvebu_gpio_chip, chip); +@@ -617,6 +600,8 @@ static int mvebu_gpio_suspend(struct pla + BUG(); + } + ++ mvebu_pwm_suspend(mvchip); ++ + return 0; + } + +@@ -660,6 +645,8 @@ static int mvebu_gpio_resume(struct plat + BUG(); + } + ++ mvebu_pwm_resume(mvchip); ++ + return 0; + } + +@@ -671,7 +658,6 @@ static int mvebu_gpio_probe(struct platf + struct resource *res; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; +- struct clk *clk; + unsigned int ngpios; + int soc_variant; + int i, cpu, id; +@@ -701,10 +687,10 @@ static int mvebu_gpio_probe(struct platf + return id; + } + +- clk = devm_clk_get(&pdev->dev, NULL); ++ mvchip->clk = devm_clk_get(&pdev->dev, NULL); + /* Not all SoCs require a clock.*/ +- if (!IS_ERR(clk)) +- clk_prepare_enable(clk); ++ if (!IS_ERR(mvchip->clk)) ++ clk_prepare_enable(mvchip->clk); + + mvchip->soc_variant = soc_variant; + mvchip->chip.label = dev_name(&pdev->dev); +@@ -838,7 +824,8 @@ static int mvebu_gpio_probe(struct platf + goto err_generic_chip; + } + +- return 0; ++ /* Armada 370/XP has simple PWM support for gpio lines */ ++ return mvebu_pwm_probe(pdev, mvchip, id); + + err_generic_chip: + irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu.h +@@ -0,0 +1,79 @@ ++/* ++ * Interface between MVEBU GPIO driver and PWM driver for GPIO pins ++ * ++ * Copyright (C) 2015, Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef MVEBU_GPIO_PWM_H ++#define MVEBU_GPIO_PWM_H ++ ++#define BLINK_ON_DURATION 0x0 ++#define BLINK_OFF_DURATION 0x4 ++#define GPIO_BLINK_CNT_SELECT 0x0020 ++ ++struct mvebu_pwm { ++ void __iomem *membase; ++ unsigned long clk_rate; ++ bool used; ++ unsigned pin; ++ struct pwm_chip chip; ++ int id; ++ spinlock_t lock; ++ ++ /* Used to preserve GPIO/PWM registers across suspend / ++ * resume */ ++ u32 blink_select; ++ u32 blink_on_duration; ++ u32 blink_off_duration; ++}; ++ ++struct mvebu_gpio_chip { ++ struct gpio_chip chip; ++ spinlock_t lock; ++ void __iomem *membase; ++ void __iomem *percpu_membase; ++ int irqbase; ++ struct irq_domain *domain; ++ int soc_variant; ++ struct clk *clk; ++#ifdef CONFIG_PWM ++ struct mvebu_pwm pwm; ++#endif ++ /* Used to preserve GPIO registers across suspend/resume */ ++ u32 out_reg; ++ u32 io_conf_reg; ++ u32 blink_en_reg; ++ u32 in_pol_reg; ++ u32 edge_mask_regs[4]; ++ u32 level_mask_regs[4]; ++}; ++ ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value); ++ ++#ifdef CONFIG_PWM ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id); ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip); ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip); ++#else ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ return 0; ++} ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++} ++#endif ++#endif diff --git a/target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch b/target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch new file mode 100644 index 0000000..48f9394 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch @@ -0,0 +1,52 @@ +Document the optional parameters needed for PWM operation of gpio +lines. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 ++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt ++++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +@@ -38,6 +38,23 @@ Required properties: + - #gpio-cells: Should be two. The first cell is the pin number. The + second cell is reserved for flags, unused at the moment. + ++Optional properties: ++ ++In order to use the gpio lines in PWM mode, some additional optional ++properties are required. Only Armada 370 and XP supports these ++properties. ++ ++- reg: an additional register set is needed, for the GPIO Blink ++ Counter on/off registers. ++ ++- reg-names: Must contain an entry "pwm" corresponding to the ++ additional register range needed for pwm operation. ++ ++- #pwm-cells: Should be two. The first cell is the pin number. The ++ second cell is reserved for flags, unused at the moment. ++ ++- clocks: Must be a phandle to the clock for the gpio controller. ++ + Example: + + gpio0: gpio@d0018100 { +@@ -51,3 +68,17 @@ Example: + #interrupt-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; ++ ++ gpio1: gpio@18140 { ++ compatible = "marvell,orion-gpio"; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; ++ ngpios = <17>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #pwm-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; ++ }; diff --git a/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch b/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch new file mode 100644 index 0000000..dff29dc --- /dev/null +++ b/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch @@ -0,0 +1,149 @@ +Add properties to the gpio nodes to allow them to be also used +as pwm lines. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-370.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 8 ++++++-- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 10 ++++++++-- + 4 files changed, 30 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -157,24 +157,30 @@ + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -203,24 +203,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -287,24 +287,28 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -325,24 +325,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { diff --git a/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch b/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch new file mode 100644 index 0000000..4b52ac2 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch @@ -0,0 +1,18 @@ +Now that the gpio driver also supports PWM operation, enable +the PWM framework in mvebu_v7_defconfig. + +Signed-off-by: Andrew Lunn +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -118,6 +118,7 @@ CONFIG_DMADEVICES=y + CONFIG_MV_XOR=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_MEMORY=y ++CONFIG_PWM=y + CONFIG_EXT4_FS=y + CONFIG_ISO9660_FS=y + CONFIG_JOLIET=y diff --git a/target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch b/target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch new file mode 100644 index 0000000..dddd67a --- /dev/null +++ b/target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch @@ -0,0 +1,28 @@ +The mvebu gpio driver can also perform PWM on some pins. Us the +pwm-fan driver to control the fan of the WRT1900AC, giving us fine +grain control over its speed and hence noise. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-xp-wrt1900ac.dts | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -407,13 +407,11 @@ + }; + }; + +- gpio_fan { ++ pwm_fan { + /* SUNON HA4010V4-0000-C99 */ +- compatible = "gpio-fan"; +- gpios = <&gpio0 24 0>; + +- gpio-fan,speed-map = <0 0 +- 4500 1>; ++ compatible = "pwm-fan"; ++ pwms = <&gpio0 24 4000 0>; + }; + + mvsw61xx { diff --git a/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch new file mode 100644 index 0000000..51408dd --- /dev/null +++ b/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-388-rd.dts ++++ b/arch/arm/boot/dts/armada-388-rd.dts +@@ -77,6 +77,16 @@ + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; ++ ++ partition@0 { ++ label = "uboot"; ++ reg = <0 0x400000>; ++ }; ++ ++ partition@1 { ++ label = "firmware"; ++ reg = <0x400000 0xc00000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch new file mode 100644 index 0000000..2845181 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch @@ -0,0 +1,34 @@ +From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Tue, 13 Jan 2015 11:14:09 +0100 +Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -162,6 +162,21 @@ + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; ++ ++ mtd0@00000000 { ++ label = "u-boot"; ++ reg = <0x00000000 0x00800000>; ++ }; ++ ++ mtd1@00800000 { ++ label = "kernel"; ++ reg = <0x00800000 0x00800000>; ++ }; ++ ++ mtd2@01000000 { ++ label = "ubi"; ++ reg = <0x01000000 0x3f000000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-4.0/300-add_missing_labels.patch b/target/linux/mvebu/patches-4.0/300-add_missing_labels.patch new file mode 100644 index 0000000..a34f689 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/300-add_missing_labels.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -491,7 +491,7 @@ + status = "disabled"; + }; + +- mdio@72004 { ++ mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch b/target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch new file mode 100644 index 0000000..a315b87 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch @@ -0,0 +1,47 @@ +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -155,12 +156,27 @@ static int xhci_plat_probe(struct platfo + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) + xhci->shared_hcd->can_do_streams = 1; + ++ hcd->usb_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0); ++ if (IS_ERR(hcd->usb_phy)) { ++ ret = PTR_ERR(hcd->usb_phy); ++ if (ret == -EPROBE_DEFER) ++ goto put_usb3_hcd; ++ hcd->usb_phy = NULL; ++ } else { ++ ret = usb_phy_init(hcd->usb_phy); ++ if (ret) ++ goto put_usb3_hcd; ++ } ++ + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); + if (ret) +- goto put_usb3_hcd; ++ goto disable_usb_phy; + + return 0; + ++disable_usb_phy: ++ usb_phy_shutdown(hcd->usb_phy); ++ + put_usb3_hcd: + usb_put_hcd(xhci->shared_hcd); + +@@ -184,6 +200,7 @@ static int xhci_plat_remove(struct platf + struct clk *clk = xhci->clk; + + usb_remove_hcd(xhci->shared_hcd); ++ usb_phy_shutdown(hcd->usb_phy); + usb_put_hcd(xhci->shared_hcd); + + usb_remove_hcd(hcd); diff --git a/target/linux/mvebu/profiles/000-Default.mk b/target/linux/mvebu/profiles/000-Default.mk new file mode 100644 index 0000000..5660836 --- /dev/null +++ b/target/linux/mvebu/profiles/000-Default.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:= \ + kmod-mmc kmod-mvsdio swconfig \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-hwmon-pwmfan kmod-leds-tlc59116 \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + kmod-ata-mvebu-ahci +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef + +$(eval $(call Profile,Default)) diff --git a/target/linux/mvebu/profiles/globalscale.mk b/target/linux/mvebu/profiles/globalscale.mk new file mode 100644 index 0000000..7938c35 --- /dev/null +++ b/target/linux/mvebu/profiles/globalscale.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Mirabox + NAME:=Globalscale Mirabox + PACKAGES:= \ + kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-rtc-marvell kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-mmc kmod-mvsdio +endef + +define Profile/Mirabox/Description + Package set compatible with the Globalscale Mirabox. +endef + +$(eval $(call Profile,Mirabox)) diff --git a/target/linux/mvebu/profiles/linksys.mk b/target/linux/mvebu/profiles/linksys.mk new file mode 100644 index 0000000..ed20cb0 --- /dev/null +++ b/target/linux/mvebu/profiles/linksys.mk @@ -0,0 +1,65 @@ +# +# Copyright (C) 2013-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Caiman + NAME:=Linksys WRT1200AC (Caiman) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-mvebu-ahci \ + kmod-rtc-armada38x kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-leds-pca963x \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Caiman/Description + Package set compatible with the Linksys WRT1200AC (Caiman). +endef + +$(eval $(call Profile,Caiman)) + + +define Profile/Cobra + NAME:=Linksys WRT1900ACv2 (Cobra) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-mvebu-ahci \ + kmod-rtc-armada38x kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-leds-pca963x \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Cobra/Description + Package set compatible with the Linksys WRT1900AC (Cobra). +endef + +$(eval $(call Profile,Cobra)) + + +define Profile/Mamba + NAME:=Linksys WRT1900AC (Mamba) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-hwmon-pwmfan kmod-leds-tlc59116 \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Mamba/Description + Package set compatible with the Linksys WRT1900AC (Mamba). +endef + +$(eval $(call Profile,Mamba)) diff --git a/target/linux/mvebu/profiles/marvell.mk b/target/linux/mvebu/profiles/marvell.mk new file mode 100644 index 0000000..e8ca9bd --- /dev/null +++ b/target/linux/mvebu/profiles/marvell.mk @@ -0,0 +1,95 @@ +# +# Copyright (C) 2013-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/370-DB + NAME:=Marvell Armada 370 DB (DB-88F6710-BP-DDR3) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/370-DB/Description + Package set compatible with the Armada 370 evaluation board (DB-88F6710-BP-DDR3). +endef + +$(eval $(call Profile,370-DB)) + +define Profile/370-RD + NAME:=Marvell Armada 370 RD (RD-88F6710-A1) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/370-RD/Description + Package set compatible with the Armada 370 reference design board (RD-88F6710-A1). +endef + +$(eval $(call Profile,370-RD)) + +define Profile/385-RD + NAME:=Marvell Armada 385 RD (RD-88F6820-AP) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-thermal-armada +endef + +define Profile/385-RD/Description + Package set compatible with the Armada 385 reference design board (RD-88F6820-AP). +endef + +$(eval $(call Profile,385-RD)) + +define Profile/385-DB-AP + NAME:=Marvell Armada 385 DB AP (DB-88F6820-AP) + PACKAGES:= \ + kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-thermal-armada +endef + +define Profile/385-DB-AP/Description + Package set compatible with the Armada 385 access point development board (DB-88F6820-AP). +endef + +$(eval $(call Profile,385-DB-AP)) + +define Profile/XP-DB + NAME:=Marvell Armada XP DB (DB-78460-BP) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/XP-DB/Description + Package set compatible with the Marvell Armada XP evaluation board (DB-78460-BP). +endef + +$(eval $(call Profile,XP-DB)) + +define Profile/XP-GP + NAME:=Marvell Armada XP GP (DB-MV784MP-GP) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/XP-GP/Description + Package set compatible with the Armada XP development board (DB-MV784MP-GP). +endef + +$(eval $(call Profile,XP-GP)) diff --git a/target/linux/mvebu/profiles/plathome.mk b/target/linux/mvebu/profiles/plathome.mk new file mode 100644 index 0000000..63cdb71 --- /dev/null +++ b/target/linux/mvebu/profiles/plathome.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OpenBlocks-AX-3-4 + NAME:=Plat'Home OpenBlocks AX3 + PACKAGES:= \ + kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/OpenBlocks-AX-3-4/Description + Package set compatible with the Plat'Home OpenBlocks AX3. +endef + +$(eval $(call Profile,OpenBlocks-AX-3-4)) -- cgit v1.2.3