From 626d9efa74685720020e816f3a917b7591d3cf7a Mon Sep 17 00:00:00 2001 From: James <> Date: Sat, 26 Sep 2015 12:29:31 +0100 Subject: trunk-47048 --- target/linux/ar71xx/Makefile | 24 + target/linux/ar71xx/base-files.mk | 3 + target/linux/ar71xx/base-files/etc/diag.sh | 392 ++++ .../etc/hotplug.d/firmware/10-ath9k-eeprom | 65 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 98 + .../base-files/etc/hotplug.d/net/10-ar922x-led-fix | 51 + target/linux/ar71xx/base-files/etc/inittab | 3 + .../base-files/etc/uci-defaults/01_gpio-switches | 25 + .../ar71xx/base-files/etc/uci-defaults/01_leds | 635 ++++++ .../ar71xx/base-files/etc/uci-defaults/02_network | 528 +++++ .../etc/uci-defaults/03_network-switchX-migration | 110 + .../etc/uci-defaults/03_network-vlan-migration | 13 + .../base-files/etc/uci-defaults/04_led_migration | 90 + .../etc/uci-defaults/09_fix-seama-header | 21 + .../base-files/etc/uci-defaults/09_fix-trx-header | 19 + target/linux/ar71xx/base-files/lib/ar71xx.sh | 990 ++++++++ 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target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h create mode 100644 target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h create mode 100644 target/linux/ar71xx/files/drivers/gpio/gpio-latch.c create mode 100644 target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c create mode 100644 target/linux/ar71xx/files/drivers/leds/leds-rb750.c create mode 100644 target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c create mode 100644 target/linux/ar71xx/files/drivers/mtd/cybertan_part.c create mode 100644 target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c create mode 100644 target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c create mode 100644 target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c create mode 100644 target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c create mode 100644 target/linux/ar71xx/files/drivers/mtd/tplinkpart.c create mode 100644 target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c create mode 100644 target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c create mode 100644 target/linux/ar71xx/files/drivers/spi/spi-ap83.c create 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target/linux/ar71xx/generic/profiles/8devices.mk create mode 100644 target/linux/ar71xx/generic/profiles/alfa.mk create mode 100644 target/linux/ar71xx/generic/profiles/allnet.mk create mode 100644 target/linux/ar71xx/generic/profiles/antminer.mk create mode 100644 target/linux/ar71xx/generic/profiles/atheros.mk create mode 100644 target/linux/ar71xx/generic/profiles/atlantis.mk create mode 100644 target/linux/ar71xx/generic/profiles/belkin.mk create mode 100644 target/linux/ar71xx/generic/profiles/bhu.mk create mode 100644 target/linux/ar71xx/generic/profiles/buffalo.mk create mode 100644 target/linux/ar71xx/generic/profiles/comfast.mk create mode 100644 target/linux/ar71xx/generic/profiles/compex.mk create mode 100644 target/linux/ar71xx/generic/profiles/d-link.mk create mode 100644 target/linux/ar71xx/generic/profiles/devolo-dlan.mk create mode 100644 target/linux/ar71xx/generic/profiles/dragino.mk create mode 100644 target/linux/ar71xx/generic/profiles/easylink.mk create mode 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target/linux/ar71xx/generic/profiles/qihoo.mk create mode 100644 target/linux/ar71xx/generic/profiles/redwave.mk create mode 100644 target/linux/ar71xx/generic/profiles/rosewill.mk create mode 100644 target/linux/ar71xx/generic/profiles/senao.mk create mode 100644 target/linux/ar71xx/generic/profiles/sitecom.mk create mode 100644 target/linux/ar71xx/generic/profiles/smartelectronics.mk create mode 100644 target/linux/ar71xx/generic/profiles/tp-link.mk create mode 100644 target/linux/ar71xx/generic/profiles/trendnet.mk create mode 100644 target/linux/ar71xx/generic/profiles/ubnt.mk create mode 100644 target/linux/ar71xx/generic/profiles/wd.mk create mode 100644 target/linux/ar71xx/generic/profiles/weio.mk create mode 100644 target/linux/ar71xx/generic/profiles/zcomax.mk create mode 100644 target/linux/ar71xx/generic/profiles/zyxel.mk create mode 100644 target/linux/ar71xx/generic/target.mk create mode 100644 target/linux/ar71xx/image/Makefile create mode 100644 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target/linux/ar71xx/image/lzma-loader/src/loader.lds create mode 100644 target/linux/ar71xx/image/lzma-loader/src/loader2.lds create mode 100644 target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds create mode 100644 target/linux/ar71xx/image/lzma-loader/src/printf.c create mode 100644 target/linux/ar71xx/image/lzma-loader/src/printf.h create mode 100644 target/linux/ar71xx/image/ubinize-nbg6716.ini create mode 100644 target/linux/ar71xx/image/ubinize-wndr4300.ini create mode 100644 target/linux/ar71xx/mikrotik/config-default create mode 100644 target/linux/ar71xx/mikrotik/profiles/01-minimal.mk create mode 100644 target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk create mode 100644 target/linux/ar71xx/mikrotik/target.mk create mode 100644 target/linux/ar71xx/modules.mk create mode 100644 target/linux/ar71xx/nand/config-default create mode 100644 target/linux/ar71xx/nand/profiles/netgear.mk create mode 100644 target/linux/ar71xx/nand/profiles/zyxel.mk create mode 100644 target/linux/ar71xx/nand/target.mk create mode 100644 target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch create mode 100644 target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch create mode 100644 target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch create mode 100644 target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch create mode 100644 target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch create mode 100644 target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch create mode 100644 target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch create mode 100644 target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch create mode 100644 target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch create mode 100644 target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch create mode 100644 target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch create mode 100644 target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch create mode 100644 target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch create mode 100644 target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch create mode 100644 target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch create mode 100644 target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch create mode 100644 target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch create mode 100644 target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch 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target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch create mode 100644 target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch create mode 100644 target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch create mode 100644 target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch create mode 100644 target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch create mode 100644 target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch create mode 100644 target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch create mode 100644 target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch create mode 100644 target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch create mode 100644 target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch create mode 100644 target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch create mode 100644 target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch create mode 100644 target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch create mode 100644 target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch create mode 100644 target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch create mode 100644 target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch create mode 100644 target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch create mode 100644 target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch create mode 100644 target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch create mode 100644 target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch create mode 100644 target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch create mode 100644 target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch create mode 100644 target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch create mode 100644 target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch create mode 100644 target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch create mode 100644 target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch create mode 100644 target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch create mode 100644 target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch create mode 100644 target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch create mode 100644 target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch create mode 100644 target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch create mode 100644 target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch create mode 100644 target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch create mode 100644 target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch create mode 100644 target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch create mode 100644 target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch create mode 100644 target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch create mode 100644 target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch create mode 100644 target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch create mode 100644 target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch create mode 100644 target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch create mode 100644 target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch create mode 100644 target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch create mode 100644 target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch (limited to 'target/linux/ar71xx') diff --git a/target/linux/ar71xx/Makefile b/target/linux/ar71xx/Makefile new file mode 100644 index 0000000..24d7d5c --- /dev/null +++ b/target/linux/ar71xx/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (C) 2008-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +BOARD:=ar71xx +BOARDNAME:=Atheros AR7xxx/AR9xxx +FEATURES:=mips16 +CPU_TYPE=34kc +SUBTARGETS:=generic nand mikrotik + +KERNEL_PATCHVER:=4.1 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += \ + kmod-gpio-button-hotplug swconfig \ + kmod-ath9k wpad-mini uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/ar71xx/base-files.mk b/target/linux/ar71xx/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/ar71xx/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/ar71xx/base-files/etc/diag.sh b/target/linux/ar71xx/base-files/etc/diag.sh new file mode 100644 index 0000000..cfba6b4 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/diag.sh @@ -0,0 +1,392 @@ +#!/bin/sh +# Copyright (C) 2009-2013 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/ar71xx.sh + +get_status_led() { + case $(ar71xx_board_name) in + alfa-nx) + status_led="alfa:green:led_8" + ;; + all0305) + status_led="eap7660d:green:ds4" + ;; + antminer-s1|\ + antminer-s3) + status_led="bitmain:green:system" + ;; + ap132) + status_led="ap132:green:status" + ;; + ap136-010|\ + ap136-020) + status_led="ap136:green:status" + ;; + ap147-010) + status_led="ap147:green:status" + ;; + ap135-020) + status_led="ap135:green:status" + ;; + ap81) + status_led="ap81:green:status" + ;; + ap83) + status_led="ap83:green:power" + ;; + ap96) + status_led="ap96:green:led2" + ;; + aw-nr580) + status_led="aw-nr580:green:ready" + ;; + bsb) + status_led="bsb:red:sys" + ;; + bullet-m | rocket-m | rocket-m-xw | nano-m | nanostation-m | nanostation-m-xw | loco-m-xw) + status_led="ubnt:green:link4" + ;; + rocket-m-ti) + status_led="ubnt:green:link6" + ;; + bxu2000n-2-a1) + status_led="bhu:green:status" + ;; + cap4200ag) + status_led="senao:green:pwr" + ;; + cf-e316n-v2) + status_led="$(ar71xx_board_name):blue:wan" + ;; + cpe510) + status_led="tp-link:green:link4" + ;; + db120) + status_led="db120:green:status" + ;; + dgl-5500-a1 |\ + dhp-1565-a1|\ + dir-505-a1 |\ + dir-600-a1 |\ + dir-615-e1 |\ + dir-615-i1 |\ + dir-615-e4) + status_led="d-link:green:power" + ;; + dir-615-c1) + status_led="d-link:green:status" + ;; + dir-825-b1) + status_led="d-link:orange:power" + ;; + dir-825-c1 |\ + dir-835-a1) + status_led="d-link:amber:power" + ;; + dlan-pro-500-wp) + status_led="devolo:green:wlan-2g" + ;; + dlan-pro-1200-ac) + status_led="devolo:status:wlan" + ;; + dragino2) + status_led="dragino2:red:system" + ;; + eap300v2) + status_led="engenius:blue:power" + ;; + eap7660d) + status_led="eap7660d:green:ds4" + ;; + el-mini | \ + el-m150) + status_led="easylink:green:system" + ;; + ew-dorin | ew-dorin-router) + status_led="dorin:green:status" + ;; + f9k1115v2) + status_led="belkin:blue:status" + ;; + gl-inet) + status_led="gl-connect:green:lan" + ;; + epg5000) + status_led="epg5000:amber:power" + ;; + esr1750) + status_led="esr1750:amber:power" + ;; + esr900) + status_led="engenius:amber:power" + ;; + hiwifi-hc6361) + status_led="hiwifi:blue:system" + ;; + hornet-ub | \ + hornet-ub-x2) + status_led="alfa:blue:wps" + ;; + ja76pf | \ + ja76pf2) + status_led="jjplus:green:led1" + ;; + ls-sr71) + status_led="ubnt:green:d22" + ;; + mc-mac1200r) + status_led="mercury:green:system" + ;; + mr12) + status_led="mr12:green:power" + ;; + mr16) + status_led="mr16:green:power" + ;; + mr600) + status_led="mr600:orange:power" + ;; + mr600v2) + status_led="mr600:blue:power" + ;; + mr1750) + status_led="mr1750:blue:power" + ;; + mr900 | \ + mr900v2) + status_led="mr900:blue:power" + ;; + mynet-n600 | \ + mynet-n750) + status_led="wd:blue:power" + ;; + mynet-rext) + status_led="wd:blue:power" + ;; + mzk-w04nu | \ + mzk-w300nh) + status_led="planex:green:status" + ;; + nbg460n_550n_550nh) + status_led="nbg460n:green:power" + ;; + nbg6716) + status_led="zyxel:white:power" + ;; + om2p | \ + om2pv2 | \ + om2p-hs | \ + om2p-hsv2 | \ + om2p-lc) + status_led="om2p:blue:power" + ;; + om5p | \ + om5p-an) + status_led="om5p:blue:power" + ;; + onion-omega) + status_led="onion:amber:system" + ;; + pb44) + status_led="pb44:amber:jump1" + ;; + rb-2011l|\ + rb-2011uas|\ + rb-2011uas-2hnd) + status_led="rb:green:usr" + ;; + rb-411 | rb-411u | rb-433 | rb-433u | rb-450 | rb-450g | rb-493) + status_led="rb4xx:yellow:user" + ;; + rb-750) + status_led="rb750:green:act" + ;; + rb-911g-2hpnd|\ + rb-911g-5hpacd|\ + rb-911g-5hpnd|\ + rb-912uag-2hpnd|\ + rb-912uag-5hpnd) + status_led="rb:green:user" + ;; + rb-951ui-2hnd) + status_led="rb:green:act" + ;; + rb-sxt2n|\ + rb-sxt5n) + status_led="rb:green:power" + ;; + routerstation | routerstation-pro) + status_led="ubnt:green:rf" + ;; + rw2458n) + status_led="rw2458n:green:d3" + ;; + smart-300) + status_led="nc-link:green:system" + ;; + oolite) + status_led="oolite:red:system" + ;; + qihoo-c301) + status_led="qihoo:green:status" + ;; + tew-632brp) + status_led="tew-632brp:green:status" + ;; + tew-673gru) + status_led="trendnet:blue:wps" + ;; + tew-712br|\ + tew-732br) + status_led="trendnet:green:power" + ;; + tl-mr3020) + status_led="tp-link:green:wps" + ;; + tl-wa750re) + status_led="tp-link:orange:re" + ;; + tl-wa850re) + status_led="tp-link:blue:re" + ;; + tl-wa860re) + status_led="tp-link:green:power" + ;; + tl-mr3220 | \ + tl-mr3220-v2 | \ + tl-mr3420 | \ + tl-mr3420-v2 | \ + tl-wa701nd-v2 | \ + tl-wa801nd-v2 | \ + tl-wa901nd | \ + tl-wa901nd-v2 | \ + tl-wa901nd-v3 | \ + tl-wdr3320-v2 | \ + tl-wdr3500 | \ + tl-wr1041n-v2 | \ + tl-wr1043nd | \ + tl-wr1043nd-v2 | \ + tl-wr741nd | \ + tl-wr741nd-v4 | \ + tl-wr841n-v1 | \ + tl-wr841n-v7 | \ + tl-wr841n-v8 | \ + tl-wa830re-v2 | \ + tl-wr842n-v2 | \ + tl-wr941nd | \ + tl-wr941nd-v5) + status_led="tp-link:green:system" + ;; + archer-c5 | \ + archer-c7 | \ + tl-wdr4900-v2 | \ + tl-mr10u | \ + tl-mr12u | \ + tl-mr13u | \ + tl-wdr4300 | \ + tl-wr703n | \ + tl-wr710n | \ + tl-wr720n-v3) + status_led="tp-link:blue:system" + ;; + tl-wr841n-v9) + status_led="tp-link:green:qss" + ;; + tl-wr2543n) + status_led="tp-link:green:wps" + ;; + tl-wdr6500-v2) + status_led="tp-link:white:system" + ;; + tube2h) + status_led="alfa:green:signal4" + ;; + unifi) + status_led="ubnt:green:dome" + ;; + uap-pro) + status_led="ubnt:white:dome" + ;; + unifi-outdoor-plus) + status_led="ubnt:white:front" + ;; + airgateway | \ + airgatewaypro) + status_led="ubnt:white:status" + ;; + whr-g301n | \ + whr-hp-g300n | \ + whr-hp-gn | \ + wzr-hp-g300nh) + status_led="buffalo:green:router" + ;; + wlae-ag300n) + status_led="buffalo:green:status" + ;; + wzr-hp-ag300h | \ + wzr-hp-g300nh2) + status_led="buffalo:red:diag" + ;; + r6100 | \ + wndap360 | \ + wndr3700 | \ + wndr3700v4 | \ + wndr4300 | \ + wnr2000 | \ + wnr2200 |\ + wnr612-v2 |\ + wnr1000-v2) + status_led="netgear:green:power" + ;; + wp543) + status_led="wp543:green:diag" + ;; + wpj344) + status_led="wpj344:green:status" + ;; + wpj531) + status_led="wpj531:green:sig3" + ;; + wpj558) + status_led="wpj558:green:sig3" + ;; + wrt400n) + status_led="wrt400n:blue:wps" + ;; + wrt160nl) + status_led="wrt160nl:blue:wps" + ;; + zcn-1523h-2 | zcn-1523h-5) + status_led="zcn-1523h:amber:init" + ;; + wlr8100) + status_led="sitecom:amber:status" + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + case $(ar71xx_board_name) in + qihoo-c301) + local n=$(fw_printenv activeregion | cut -d = -f 2) + fw_setenv "image${n}trynum" 0 + ;; + esac + ;; + esac +} diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom new file mode 100644 index 0000000..b5f0588 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -0,0 +1,65 @@ +#!/bin/sh + +ath9k_eeprom_die() { + echo "ath9k eeprom: " "$*" + exit 1 +} + +ath9k_eeprom_extract() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + + mtd=$(find_mtd_chardev $part) + [ -n "$mtd" ] || \ + ath9k_eeprom_die "no mtd device found for partition $part" + + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ + ath9k_eeprom_die "failed to extract from $mtd" +} + +ath9k_patch_firmware_mac() { + local mac=$1 + + [ -z "$mac" ] && return + + macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=2 count=6 +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/ar71xx.sh +. /lib/functions.sh +. /lib/functions/system.sh + +board=$(ar71xx_board_name) + +case "$FIRMWARE" in +"soc_wmac.eeprom") + case $board in + r6100 | \ + wndr3700v4 | \ + wndr4300) + ath9k_eeprom_extract "caldata" 4096 2048 + ath9k_patch_firmware_mac $(mtd_get_mac_binary caldata 0) + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; + +"pci_wmac0.eeprom") + case $board in + wndr3700v4 | \ + wndr4300) + ath9k_eeprom_extract "caldata" 20480 2048 + ath9k_patch_firmware_mac $(mtd_get_mac_binary caldata 12) + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100644 index 0000000..f53c853 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,98 @@ +#!/bin/sh + +ath10kcal_die() { + echo "ath10cal: " "$*" + exit 1 +} + +ath10kcal_from_file() { + local source=$1 + local offset=$2 + local count=$3 + + dd if=$source of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ + ath10kcal_die "failed to extract calibration data from $source" +} + +ath10kcal_extract() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + + mtd=$(find_mtd_chardev $part) + [ -n "$mtd" ] || \ + ath10kcal_die "no mtd device found for partition $part" + + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ + ath10kcal_die "failed to extract calibration data from $mtd" +} + +ath10kcal_patch_mac() { + local mac=$1 + + [ -z "$mac" ] && return + + macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=6 count=6 +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/ar71xx.sh +. /lib/functions.sh +. /lib/functions/system.sh + +board=$(ar71xx_board_name) + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:00:00.0.bin") + case $board in + dlan-pro-1200-ac) + ath10kcal_extract "art" 20480 2116 + ;; + mc-mac1200r) + ath10kcal_extract "art" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -1) + ;; + tl-wdr6500-v2) + ath10kcal_extract "art" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2) + ;; + r6100) + ath10kcal_extract "caldata" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) +2) + ;; + qihoo-c301) + ath10kcal_extract "radiocfg" 20480 2116 + ath10kcal_patch_mac $(mtd_get_mac_ascii devdata wlan5mac) + ;; + esr1750 | \ + epg5000) + ath10kcal_extract "caldata" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +1) + ;; + mr1750) + ath10kcal_extract "ART" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16) + ;; + esac + ;; +"ath10k/cal-pci-0000:01:00.0.bin") + case $board in + archer-c5 | \ + archer-c7) + ath10kcal_extract "art" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2) + ;; + nbg6716) + ath10kcal_extract "RFdata" 20480 2116 + ;; + rb-911g-5hpacd) + ath10kcal_from_file "/sys/firmware/routerboot/ext_wlan_data" 20480 2116 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix b/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix new file mode 100644 index 0000000..1024150 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix @@ -0,0 +1,51 @@ +#!/bin/sh + +# For AR9220 and AR9223, GPIO JTAG must explicit be disabled +# before LEDs start working. Do this when wifi device is +# detected. + +# +# $DEVPATH is not valid for some boards (including WZR-HP-AG300H). +# Manipulate the $DEVPATH to reach the corresponding phyN. +# + +devdir=`dirname $DEVPATH` +devdir=`dirname $devdir` +phydir=/sys$devdir/ieee80211 +phyname=`cat $phydir/phy*/name` + +if [ -z $phyname -o $ACTION != "add" ]; then exit 0; fi + +# +# ar922x_disable_gpio_jtag(): +# +# Emulate +# REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); +# for AR9220 and AR9223. +# + +ar922x_disable_gpio_jtag() +{ + local regidx=0x4054 + + [ -f /sys/kernel/debug/ieee80211/$1/ath9k/regidx ] && { + echo $regidx > /sys/kernel/debug/ieee80211/$1/ath9k/regidx + regval=`cat /sys/kernel/debug/ieee80211/$1/ath9k/regval` + regval=$((regval | 0x20000)) + echo regval $regval + echo $regval > /sys/kernel/debug/ieee80211/$1/ath9k/regval + } +} + +if [ $phyname -a $ACTION = "add" ]; then + + . /lib/ar71xx.sh + + case $(ar71xx_board_name) in + wzr-hp-ag300h) + ar922x_disable_gpio_jtag $phyname + ;; + esac; +fi + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/inittab b/target/linux/ar71xx/base-files/etc/inittab new file mode 100644 index 0000000..7817185 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +::askconsole:/bin/ash --login diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_gpio-switches b/target/linux/ar71xx/base-files/etc/uci-defaults/01_gpio-switches new file mode 100644 index 0000000..b41f275 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_gpio-switches @@ -0,0 +1,25 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +nanostation-m) + ucidef_set_gpio_switch "poe_passthrough" "PoE Passthrough" "8" + ;; +nanostation-m-xw) + ucidef_set_gpio_switch "poe_passthrough" "PoE Passthrough" "2" + ;; +cpe510) + ucidef_set_gpio_switch "poe_passthrough" "PoE Passthrough" "20" + ;; +esac + +ucidef_commit_gpio_switches + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..fac4751 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,635 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +airgateway | \ +airgatewaypro) + ucidef_set_led_wlan "wlan" "WLAN" "ubnt:blue:wlan" "phy0tpt" + ;; +alfa-nx) + ucidef_set_led_netdev "wan" "WAN" "alfa:green:led_2" "eth0" + ucidef_set_led_netdev "lan" "LAN" "alfa:green:led_3" "eth1" + ;; + +all0258n) + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "all0258n:red:rssilow" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "all0258n:yellow:rssimedium" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "all0258n:green:rssihigh" "wlan0" "70" "100" "-69" "8" + ;; + +all0315n) + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "all0315n:red:rssilow" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "all0315n:yellow:rssimedium" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "all0315n:green:rssihigh" "wlan0" "70" "100" "-69" "8" + ;; + +antminer-s1) + ucidef_set_led_default "sys" "SYS" "bitmain:green:sys" "0" + ucidef_set_led_wlan "wlan" "WLAN" "bitmain:green:wlan" "phy0tpt" + ;; + +antminer-s3) + ucidef_set_led_wlan "wlan" "WLAN" "bitmain:green:wlan" "phy0tpt" + ucidef_set_led_default "sys" "SYS" "bitmain:green:sys" "0" + ucidef_set_led_default "lan" "LAN" "bitmain:yellow:lan" "0" + ;; + +ap113) + ucidef_set_led_usbdev "usb" "USB" "ap113:green:usb" "1-1" + ;; + +ap147-010) + ucidef_set_led_netdev "wan" "WAN" "ap147:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "ap147:green:lan1" "switch0" "0x10" + ucidef_set_led_switch "lan2" "LAN2" "ap147:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "ap147:green:lan3" "switch0" "0x04" + ucidef_set_led_switch "lan4" "LAN4" "ap147:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "ap147:green:wlan-2g" "phy0tpt" + ;; + +bsb) + ucidef_set_led_default "sys" "SYS" "bsb:red:sys" "1" + ;; + +bullet-m | \ +nanostation-m | \ +rocket-m | \ +rocket-m-xw | \ +nanostation-m-xw | \ +loco-m-xw) + ucidef_set_led_rssi "rssilow" "RSSILOW" "ubnt:red:link1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "ubnt:orange:link2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "ubnt:green:link3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "ubnt:green:link4" "wlan0" "76" "100" "-75" "13" + ;; + +rocket-m-ti) + ucidef_set_led_rssi "rssiverylow" "RSSIVERYLOW" "ubnt:green:link1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssilow" "RSSILOW" "ubnt:green:link2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "ubnt:green:link3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "ubnt:green:link4" "wlan0" "76" "100" "-75" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "ubnt:green:link5" "wlan0" "76" "100" "-75" "13" + ucidef_set_led_rssi "rssiveryhigh" "RSSIVERYHIGH" "ubnt:green:link4" "wlan0" "76" "100" "-75" "13" + ;; + +bxu2000n-2-a1) + ucidef_set_led_wlan "wlan" "WLAN" "bhu:green:wlan" "phy0tpt" + ;; + +cap4200ag) + ucidef_set_led_default "lan_green" "LAN_GREEN" "senao:green:lan" "1" + ucidef_set_led_wlan "wlan_amber" "WLAN_AMBER" "senao:amber:wlan" "phy0tpt" + ucidef_set_led_wlan "wlan_green" "WLAN_GREEN" "senao:green:wlan" "phy1tpt" + ;; + +carambola2) + ucidef_set_led_netdev "lan" "LAN" "carambola2:orange:eth0" "eth0" + ucidef_set_led_netdev "wan" "WAN" "carambola2:orange:eth1" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "carambola2:green:wlan" "phy0tpt" + ;; + +cf-e316n-v2) + ucidef_set_led_netdev "lan" "LAN" "$board:blue:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "$board:blue:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "$board:blue:wlan" "phy0tpt" + ;; + +cpe510) + ucidef_set_led_switch "lan0" "LAN0" "tp-link:green:lan0" "switch0" "0x20" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:green:link1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:green:link2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:green:link3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:green:link4" "wlan0" "76" "100" "-75" "13" + ;; + +db120) + ucidef_set_led_usbdev "usb" "USB" "db120:green:usb" "1-1" + ;; + +dragino2) + ucidef_set_led_wlan "wlan" "WLAN" "dragino2:red:wlan" "phy0tpt" + ucidef_set_led_netdev "lan" "LAN" "dragino2:red:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "dragino2:red:wan" "eth1" + ;; + +eap300v2) + ucidef_set_led_netdev "lan" "LAN" "engenius:blue:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "engenius:blue:wlan" "phy0tpt" + ;; + +f9k1115v2) + ucidef_set_led_usbdev "usb2" "USB2" "belkin:green:usb2" "1-1" + ;; + +rb-750) + ucidef_set_led_default "act" "act" "rb750:green:act" "1" + ucidef_set_led_netdev "port1" "port1" "rb750:green:port1" "eth1" + ucidef_set_led_switch "port2" "port2" "rb750:green:port2" "switch0" "0x10" + ucidef_set_led_switch "port3" "port3" "rb750:green:port3" "switch0" "0x08" + ucidef_set_led_switch "port4" "port4" "rb750:green:port4" "switch0" "0x04" + ucidef_set_led_switch "port5" "port5" "rb750:green:port5" "switch0" "0x02" + ;; + +rb-2011l|\ +rb-2011uas|\ +rb-2011uias|\ +rb-2011uas-2hnd|\ +rb-2011uias-2hnd) + ucidef_set_led_switch "eth6" "ETH6" "rb:green:eth6" "switch1" "0x20" + ucidef_set_led_switch "eth7" "ETH7" "rb:green:eth7" "switch1" "0x10" + ucidef_set_led_switch "eth8" "ETH8" "rb:green:eth8" "switch1" "0x08" + ucidef_set_led_switch "eth9" "ETH9" "rb:green:eth9" "switch1" "0x04" + ucidef_set_led_switch "eth10" "ETH10" "rb:green:eth10" "switch1" "0x02" + ;; + +dhp-1565-a1) + ucidef_set_led_switch "wan" "WAN" "d-link:green:planet" "switch0" "0x20" + ;; + +dir-505-a1) + ucidef_set_led_netdev "lan" "LAN" "d-link:green:power" "eth1" + ;; + +dir-600-a1|\ +dir-615-e1|\ +dir-615-e4) + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "d-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "d-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "d-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "d-link:green:lan4" "switch0" "0x10" + ;; + +dir-615-c1) + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "d-link:green:wlan" "phy0tpt" + ;; + +dir-825-b1) + ucidef_set_led_usbdev "usb" "USB" "d-link:blue:usb" "1-1" + ;; + +dir-615-i1) + ucidef_set_led_default "power" "POWER" "d-link:green:power" "1" + ucidef_set_led_default "diag" "DIAG" "d-link:amber:power" "0" + ucidef_set_led_default "wps" "WPS" "d-link:blue:wps" "0" + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "d-link:green:wlan" "phy0tpt" + ;; + +dir-825-c1) + ucidef_set_led_usbdev "usb" "USB" "d-link:blue:usb" "1-1" + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "d-link:blue:wlan2g" "phy0tpt" + ;; + +dlan-pro-500-wp) + ucidef_set_led_default "power" "System Power" "devolo:green:status" "1" + ucidef_set_led_netdev "lan" "Ethernet Activity" "devolo:green:eth" "br-lan" + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "devolo:green:wlan-2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "devolo:blue:wlan-5g" "none" + ;; + +dlan-pro-1200-ac) + ucidef_set_led_wlan "wlan" "WLAN" "devolo:status:wlan" "phy0radio" + ucidef_set_led_trigger_gpio "plcw" "dLAN" "devolo:status:dlan" "17" "0" + ucidef_set_led_trigger_gpio "plcr" "dLAN" "devolo:error:dlan" "16" "0" + ;; + +gl-inet) + ucidef_set_led_netdev "lan" "LAN" "gl-connect:green:lan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "gl-connect:red:wlan" "phy0tpt" + ;; + +esr900) + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "engenius:blue:wlan-2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "engenius:blue:wlan-5g" "phy1tpt" + ;; + +esr1750) + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "esr1750:blue:wlan-2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "esr1750:blue:wlan-5g" "phy0tpt" + ;; + +epg5000) + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "epg5000:blue:wlan-2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "epg5000:blue:wlan-5g" "phy0tpt" + ;; + +hiwifi-hc6361) + ucidef_set_led_netdev "inet" "INET" "hiwifi:blue:internet" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "hiwifi:blue:wlan-2p4" "phy0tpt" + ;; + +hornet-ub | \ +hornet-ub-x2) + ucidef_set_led_netdev "lan" "LAN" "alfa:blue:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "alfa:blue:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "alfa:blue:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "alfa:blue:usb" "1-1" + ;; + +mc-mac1200r) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "mercury:green:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "mercury:green:wlan5g" "phy0tpt" + ;; + +mr12) + ucidef_set_led_netdev "wan" "WAN" "mr12:green:wan" "eth0" + ucidef_set_led_wlan "wlan1" "WLAN1" "mr12:green:wifi1" "phy0assoc" + ucidef_set_led_wlan "wlan2" "WLAN2" "mr12:green:wifi2" "phy0assoc" + ucidef_set_led_wlan "wlan3" "WLAN3" "mr12:green:wifi3" "phy0assoc" + ucidef_set_led_wlan "wlan4" "WLAN4" "mr12:green:wifi4" "phy0tpt" + ;; + +mr16) + ucidef_set_led_netdev "wan" "WAN" "mr16:green:wan" "eth0" + ucidef_set_led_wlan "wlan1" "WLAN1" "mr16:green:wifi1" "phy0assoc" + ucidef_set_led_wlan "wlan2" "WLAN2" "mr16:green:wifi2" "phy0assoc" + ucidef_set_led_wlan "wlan3" "WLAN3" "mr16:green:wifi3" "phy0assoc" + ucidef_set_led_wlan "wlan4" "WLAN4" "mr16:green:wifi4" "phy0tpt" + ;; + +mr600) + ucidef_set_led_wlan "wlan58" "WLAN58" "mr600:green:wlan58" "phy0tpt" + ;; + +mr1750) + ucidef_set_led_netdev "lan" "LAN" "mr1750:blue:wan" "eth0" + ucidef_set_led_wlan "wlan58" "WLAN58" "mr1750:blue:wlan58" "phy0tpt" + ucidef_set_led_wlan "wlan24" "WLAN24" "mr1750:blue:wlan24" "phy1tpt" + ;; + +mr900 | \ +mr900v2) + ucidef_set_led_netdev "lan" "LAN" "mr900:blue:wan" "eth0" + ucidef_set_led_wlan "wlan24" "WLAN24" "mr900:blue:wlan24" "phy0tpt" + ucidef_set_led_wlan "wlan58" "WLAN58" "mr900:blue:wlan58" "phy1tpt" + ;; + +mynet-n600) + ucidef_set_led_netdev "wan" "WAN" "wd:blue:internet" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "wd:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "wd:green:lan2" "switch0" "0x10" + ucidef_set_led_switch "lan3" "LAN3" "wd:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "wd:green:lan4" "switch0" "0x04" + ;; + +mynet-rext) + ucidef_set_led_netdev "lan" "LAN" "wd:blue:ethernet" "eth0" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "wd:blue:quality1" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "wd:blue:quality2" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "wd:blue:quality3" "wlan0" "70" "100" "-69" "8" + ucidef_set_led_wlan "wlan" "WLAN" "wd:blue:wireless" "phy0tpt" + ;; + +mzk-w04u) + ucidef_set_led_usbdev "usb" "USB" "planex:green:usb" "1-1" + ;; + +mzk-w300nh) + ucidef_set_led_wlan "wlan" "WLAN" "planex:green:wlan" "phy0tpt" + ;; + +nbg460n_550n_550nh) + ucidef_set_led_wlan "wlan" "WLAN" "nbg460n:green:wlan" "phy0tpt" + ;; + +nbg6716) + ucidef_set_led_netdev "wan" "WAN" "zyxel:white:internet" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "zyxel:white:wifi2g" "phy1tpt" + ucidef_set_led_wlan "wlan5" "WLAN5" "zyxel:white:wifi5g" "phy0tpt" + ucidef_set_led_usbdev "usb1" "USB1" "zyxel:white:usb1" "2-1" + ucidef_set_led_usbdev "usb2" "USB2" "zyxel:white:usb2" "1-1" + ;; + +om2p | \ +om2pv2 | \ +om2p-hs | \ +om2p-hsv2 | \ +om2p-lc) + ucidef_set_led_netdev "port1" "port1" "om2p:blue:wan" "eth0" + ucidef_set_led_netdev "port2" "port2" "om2p:blue:lan" "eth1" + ;; + +om5p | \ +om5p-an) + ucidef_set_led_netdev "port1" "port1" "om5p:blue:wan" "eth0" + ucidef_set_led_netdev "port2" "port2" "om5p:blue:lan" "eth1" + ;; + +qihoo-c301) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "qihoo:red:status" "phy1tpt" + ;; + +smart-300) + ucidef_set_led_netdev "wan" "WAN" "nc-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "nc-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "nc-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "nc-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "nc-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "nc-link:green:wlan" "phy0tpt" + ;; + +tew-712br) + ucidef_set_led_netdev "wan" "WAN" "trendnet:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "trendnet:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "trendnet:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "trendnet:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "trendnet:green:lan4" "switch0" "0x10" + ucidef_set_led_wlan "wlan" "WLAN" "trendnet:green:wlan" "phy0tpt" + ;; + +tew-732br) + ucidef_set_led_netdev "wan" "WAN" "trendnet:green:wan" "eth1" + ;; + +tl-mr11u | \ +tl-mr3020 | \ +tl-mr3040 | \ +tl-mr3040-v2) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ;; + +tl-mr3220 | \ +tl-mr3420 ) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-mr3220-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-mr3420-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-wa7210n-v2) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:green:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:green:signal2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:green:signal3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:green:signal4" "wlan0" "76" "100" "-75" "13" + ;; + +tl-wa750re) + ucidef_set_led_netdev "lan" "LAN" "tp-link:orange:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:orange:wlan" "phy0tpt" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:orange:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:orange:signal2" "wlan0" "20" "100" "-19" "13" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "tp-link:orange:signal3" "wlan0" "40" "100" "-39" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:orange:signal4" "wlan0" "60" "100" "-59" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:orange:signal5" "wlan0" "80" "100" "-79" "13" + ;; + +tl-wa850re) + ucidef_set_led_netdev "lan" "LAN" "tp-link:blue:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:blue:wlan" "phy0tpt" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:blue:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:blue:signal2" "wlan0" "20" "100" "-19" "13" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "tp-link:blue:signal3" "wlan0" "40" "100" "-39" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:blue:signal4" "wlan0" "60" "100" "-59" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:blue:signal5" "wlan0" "80" "100" "-79" "13" + ;; + +tl-wa701nd-v2) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wa860re) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wa901nd) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ;; + +tl-wa901nd-v2) + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wdr3320-v2) + ucidef_set_led_wlan "wlan5g" "WLAN5G" "tp-link:green:wlan5g" "phy0tpt" + ;; + +tl-wdr3500) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:green:wlan2g" "phy0tpt" + ;; + +tl-wdr4300) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1.1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "1-1.2" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy0tpt" + ;; + +tl-wdr4900-v2) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "2-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "tp-link:blue:wlan5g" "phy1tpt" + ;; + +tl-wdr6500-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x10" + ;; + +archer-c5|\ +archer-c7) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "2-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "tp-link:blue:wlan5g" "phy0tpt" + ;; + +tl-wr741nd) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x10" + ;; + +tl-wr741nd-v4) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr841n-v8 | \ +tl-wr941nd-v5) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wa830re-v2) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr841n-v9) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x04" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr842n-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-wa801nd-v2 | \ +tl-wa901nd-v3) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr941nd | \ +tl-wr1041n-v2) + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr1043nd | \ +tl-wr1043nd-v2) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr2543n) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ;; + +tube2h) + ucidef_set_led_netdev "lan" "LAN" "alfa:blue:lan" "eth0" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "signal1" "SIGNAL1" "alfa:red:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "signal2" "SIGNAL2" "alfa:orange:signal2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "signal3" "SIGNAL3" "alfa:green:signal3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "signal4" "SIGNAL4" "alfa:green:signal4" "wlan0" "76" "100" "-75" "13" + ;; + +wrt160nl) + ucidef_set_led_wlan "wlan" "WLAN" "wrt160nl:blue:wlan" "phy0tpt" + ;; + +wndap360) + ucidef_set_led_power "power" "POWER GREEN" "netgear:green:power" "1" + ;; + +wndr3700) + ucidef_set_led_default "wan" "WAN LED (green)" "netgear:green:wan" "0" + ucidef_set_led_usbdev "usb" "USB" "netgear:green:usb" "1-1" + ;; + +r6100) + ucidef_set_led_netdev "wan" "WAN (green)" "netgear:green:wan" "eth0" + ucidef_set_led_usbdev "usb" "USB" "netgear:blue:usb" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "netgear:blue:wlan" "phy1tpt" + ;; + +wndr3700v4 | \ +wndr4300) + ucidef_set_led_netdev "wan" "WAN (green)" "netgear:green:wan" "eth0.2" + ucidef_set_led_usbdev "usb" "USB" "netgear:green:usb" "1-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "netgear:green:wlan2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "netgear:blue:wlan5g" "phy1tpt" + ;; + +whr-g301n |\ +whr-hp-g300n |\ +whr-hp-gn) + ucidef_set_led_netdev "wan" "WAN" "buffalo:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "buffalo:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "buffalo:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "buffalo:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "buffalo:green:lan4" "switch0" "0x10" + ;; + +wlae-ag300n) + ucidef_set_led_netdev "wireless" "WIRELESS" "buffalo:green:wireless" "wlan0" + ;; + +wnr2000-v4) + ucidef_set_led_netdev "wan" "WAN" "netgear:green:wan" "eth0" + ucidef_set_led_netdev "wlan" "WLAN" "netgear:blue:wlan" "wlan0" + ucidef_set_led_switch "lan1" "LAN1" "netgear:amber:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "netgear:amber:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "netgear:amber:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "netgear:amber:lan4" "switch0" "0x10" + ucidef_set_led_usbdev "usb" "USB" "netgear:amber:status" "1-1" + ;; + +wzr-hp-ag300h) + ucidef_set_led_default "diag" "DIAG" "buffalo:red:diag" "0" + ucidef_set_led_netdev "router" "ROUTER" "buffalo:green:router" "eth1" + ucidef_set_led_usbdev "usb" "USB" "buffalo:green:usb" "1-1" + ;; + +wzr-hp-g300nh) + ucidef_set_led_wlan "wlan" "Wireless" "buffalo:green:wireless" "phy0tpt" + ucidef_set_led_netdev "router" "Router" "buffalo:green:router" "eth1" + ucidef_set_led_usbdev "usb" "USB" "buffalo:blue:usb" "1-1" + ;; + +zcn-1523h-2) + ucidef_set_led_netdev "lan1" "lan1" "zcn-1523h:green:lan1" "eth0" + ;; + +zcn-1523h-5) + ucidef_set_led_netdev "lan1" "lan1" "zcn-1523h:green:lan1" "eth0" + ucidef_set_led_netdev "lan2" "lan2" "zcn-1523h:green:lan2" "eth1" + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..880953c --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network @@ -0,0 +1,528 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +ucidef_set_interface_loopback + +board=$(ar71xx_board_name) + +case "$board" in +all0315n |\ +all0258n |\ +ja76pf2|\ +rocket-m-ti |\ +ubnt-unifi-outdoor) + ucidef_set_interface_lan "eth0 eth1" + ;; + +ap132 |\ +wlr8100) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +esr1750 |\ +epg5000) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + ;; + +ap136-010) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +ap147-010) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +ap136-020 |\ +ap135-020 |\ +tl-wr1043nd-v2 |\ +wzr-450hp2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +archer-c5 |\ +archer-c7 |\ +tl-wdr4900-v2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "1 6" + ;; + +bsb) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 3" + ucidef_set_interface_wlan + ;; + +cpe510) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 5" + ucidef_add_switch_vlan "switch0" "2" "0t 4" + ;; + +airgatewaypro) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + ;; + +db120 |\ +rb-2011l | \ +rb-2011uas |\ +rb-2011uias |\ +rb-2011uas-2hnd|\ +rb-2011uias-2hnd) + ucidef_set_interfaces_lan_wan "eth0.1 eth1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ucidef_add_switch "switch1" "1" "1" + ucidef_add_switch_vlan "switch1" "1" "0 1 2 3 4 5" + + case "$board" in + rb-2011uas* | rb-2011uias | rb-2011uias-2hnd) + ucidef_set_interface_raw "sfp" "eth0.3" + ucidef_add_switch_vlan "switch0" "3" "0t 6" + ;; + esac + ;; + +dir-825-b1|\ +tew-673gru) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ;; + +f9k1115v2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "2 3 4 5 6" + ucidef_add_switch_vlan "switch0" "2" "0 1" + ;; + +nbg460n_550n_550nh) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "0" "0 1 2 3 5" + ;; + +nbg6716) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +ap143 |\ +rb-433 |\ +rb-433u) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 5" + ;; + +rb-435g) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2" + ;; + +rb-450) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5" + ;; + +rb-450g |\ +routerstation-pro) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +ap136 |\ +rb-750gl |\ +rb-751g |\ +rb-951g-2hnd |\ +wzr-hp-g450h) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +rb-951ui-2hnd) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + +rb-493g) + ucidef_set_interfaces_lan_wan "eth0 eth1.1" "eth1.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch "switch1" "1" "1" + ucidef_add_switch_vlan "switch1" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch1" "2" "0t 5" + ;; + +wzr-hp-g300nh2 |\ +pb92 |\ +ap113) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 2" + ;; + +el-m150) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 3" + ;; + +tl-wdr4300|\ +tl-wr1041n-v2) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +tl-wr1043nd) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 5t" + ucidef_add_switch_vlan "switch0" "2" "0 5t" + ;; + +tl-wr2543n) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 9t" + ucidef_add_switch_vlan "switch0" "2" "0 9t" + ;; + +tl-wr841n-v1|\ +tl-wr941nd) + ucidef_set_interface_raw "eth" "eth0" + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" + ;; + +dir-615-i1 |\ +r6100 |\ +smart-300 |\ +tl-mr3420-v2 |\ +tl-wr841n-v8 |\ +tl-wr842n-v2 |\ +tl-wr941nd-v5 |\ +tl-wdr6500-v2 |\ +wnr2000-v3 |\ +wnr2000-v4 |\ +wnr2200 |\ +wnr612-v2 |\ +wnr1000-v2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +uap-pro) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1" + ucidef_add_switch_vlan "switch0" "2" "0t 2" + ;; + +nanostation-m-xw) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +wrt160nl) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4 5" + ;; + +wzr-hp-g300nh) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ;; + +dgl-5500-a1 |\ +dir-825-c1) + local mac + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac=$(mtd_get_mac_ascii nvram "wan_mac") + [ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac" + ;; + +mynet-n750) + local mac + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac=$(mtd_get_mac_ascii devdata "wanmac") + [ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac" + ;; + +onion-omega) + ucidef_set_interface_lan "wlan0" + ;; + +dhp-1565-a1 |\ +dir-835-a1 |\ +wndr3700v4 | \ +wndr4300) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac_lan=$(mtd_get_mac_binary caldata 0) + [ -n "$mac_lan" ] && ucidef_set_interface_macaddr "lan" "$mac_lan" + mac_wan=$(mtd_get_mac_binary caldata 6) + [ -n "$mac_wan" ] && ucidef_set_interface_macaddr "wan" "$mac_wan" + ;; + +esr900) + local mac + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac=$(mtd_get_mac_ascii u-boot-env "wanaddr") + [ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac" + ;; + +dlan-pro-500-wp) + ucidef_set_interface_lan "eth0 eth1" + ;; + +dlan-pro-1200-ac) + ucidef_set_interface_lan "eth0" + ucidef_add_switch "switch0" "1" "0" + ucidef_add_switch_vlan "switch0" "0" "0 2 3 4" + ;; + +all0305 |\ +aw-nr580 |\ +bullet-m |\ +cap4200ag |\ +eap300v2 |\ +eap7660d |\ +el-mini |\ +loco-m-xw |\ +mr1750 |\ +mr600 |\ +mr600v2 |\ +mr900 |\ +mr900v2 |\ +rb-411 |\ +rb-911g-2hpnd |\ +rb-911g-5hpacd |\ +rb-911g-5hpnd |\ +rb-912uag-2hpnd |\ +rb-912uag-5hpnd |\ +rb-sxt2n |\ +rb-sxt5n |\ +rocket-m-xw |\ +tl-mr10u |\ +tl-mr11u |\ +tl-mr12u |\ +tl-mr13u |\ +tl-mr3020 |\ +tl-mr3040 |\ +tl-mr3040-v2 |\ +tl-wa701nd-v2 |\ +tl-wa7210n-v2 |\ +tl-wa750re |\ +tl-wa850re |\ +tl-wa830re-v2 |\ +tl-wa801nd-v2 |\ +tl-wa901nd |\ +tl-wa901nd-v2 |\ +tl-wa901nd-v3 |\ +tl-wr703n |\ +tube2h |\ +wndap360 |\ +mynet-rext |\ +wp543) + ucidef_set_interface_lan "eth0" + ;; + +antminer-s1 |\ +antminer-s3 |\ +dir-505-a1) + ucidef_set_interface_lan "eth1" + ;; + +alfa-ap96 |\ +alfa-nx |\ +ap83 |\ +gl-inet |\ +jwap003 |\ +pb42 |\ +pb44 |\ +routerstation|\ +tl-wr710n |\ +tl-wr720n-v3|\ +wpe72) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + +wpj344) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 3" + ucidef_add_switch_vlan "switch0" "2" "0t 2" + ;; + +wpj531) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; + +wpj558) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "5 6t" + ucidef_add_switch_vlan "switch0" "2" "1 6t" + ;; + +ap121 |\ +ap121-mini |\ +ap96 |\ +airrouter |\ +dir-600-a1 |\ +dir-615-c1 |\ +dir-615-e1 |\ +dir-615-e4 |\ +hiwifi-hc6361 |\ +ja76pf |\ +mc-mac1200r|\ +mynet-n600 |\ +oolite |\ +qihoo-c301 |\ +rb-750 |\ +rb-751 |\ +tew-632brp |\ +tew-712br |\ +tl-mr3220 |\ +tl-mr3220-v2 |\ +tl-mr3420 |\ +tl-wdr3320-v2 |\ +tl-wdr3500 |\ +tl-wr741nd |\ +tl-wr741nd-v4 |\ +tl-wr841n-v7 |\ +tl-wr841n-v9 |\ +whr-g301n |\ +whr-hp-g300n |\ +whr-hp-gn |\ +wzr-hp-ag300h) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +wzr-hp-g450h) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +ew-dorin) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2" + ucidef_add_switch_vlan "switch0" "2" "0t 3" + ;; + +ew-dorin-router) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 2 3" + ;; + +wndr3700) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + # Blinkrate: 0=43ms; 1=84ms; 2=120ms; 3=170ms; 4=340ms; 5=670ms + uci set network.@switch[-1].blinkrate='2' + + ucidef_add_switch_port "switch0" "1" + # Port 1 controls the GREEN configuration of LEDs for + # the switch and the section does not correspond to a real + # switch port. + # + # 0=LED off; 1=Collision/FDX; 2=Link/activity; 3=1000 Mb/s; + # 4=100 Mb/s; 5=10 Mb/s; 6=1000 Mb/s+activity; 7=100 Mb/s+activity; + # 8=10 Mb/s+activity; 9=10/100 Mb/s+activity; 10: Fiber; + # 11: Fault; 12: Link/activity(tx); 13: Link/activity(rx); + # 14: Link (master); 15: separate register + uci set network.@switch_port[-1].led='6' + + ucidef_add_switch_port "switch0" "2" + # Port 2 controls the ORANGE configuration of LEDs for + # the switch and the section does not correspond to a real + # switch port. + # + # See the key above for switch port 1 for the meaning of the + # 'led' setting below. + uci set network.@switch_port[-1].led='9' + + ucidef_add_switch_port "switch0" "5" + # Port 5 controls the configuration of the WAN LED and the + # section does not correspond to a real switch port. + # + # To toggle the use of green or orange LEDs for the WAN port, + # see the LED setting for wndr3700:green:wan in /etc/config/system. + # + # See the key above for switch port 1 for the meaning of the + # 'led' setting below. + uci set network.@switch_port[-1].led='2' + ;; + +*) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration new file mode 100644 index 0000000..aa0e1b4 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration @@ -0,0 +1,110 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +SWITCH_NAME_CHANGED= + +do_change_switch_name() { + local config="$1" + local option=$2 + local oldname=$3 + local newname=$4 + local val + + config_get val "$config" $option + [ "$val" != "$oldname" ] && return 0 + + uci_set network "$config" $option $newname + SWITCH_NAME_CHANGED=1 + + return 0 +} + +migrate_switch_name() { + local oldname=$1 + local newname=$2 + + . /lib/functions.sh + + config_load network + + logger -t migrate-switchX "Updating switch names in network configuration" + + config_foreach do_change_switch_name switch name $oldname $newname + config_foreach do_change_switch_name switch_vlan device $oldname $newname + + [ "$SWITCH_NAME_CHANGED" = "1" ] && { + logger -t migrate-switchX "Switch names updated, saving network configuration" + uci commit network + } +} + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +dir-825-c1|\ +wzr-hp-g300nh2|\ +pb92|\ +ap113|\ +tl-wdr4300|\ +tl-wr1041n-v2|\ +wrt160nl|\ +ap121|\ +ap121-mini|\ +ap96|\ +airrouter|\ +dir-600-a1|\ +dir-615-c1|\ +dir-615-e1|\ +dir-615-e4|\ +ja76pf|\ +mr-12|\ +mr-16|\ +rb-750|\ +rb-751|\ +tew-632brp|\ +tew-712br|\ +tl-mr3220|\ +tl-mr3220-v2 |\ +tl-mr3420|\ +tl-wr741nd|\ +tl-wr741nd-v4|\ +tl-wr841n-v7|\ +whr-g301n|\ +whr-hp-g300n|\ +whr-hp-gn|\ +wzr-hp-ag300h|\ +wzr-hp-g450h|\ +ew-dorin|\ +ew-dorin-router) + migrate_switch_name "eth0" "switch0" + ;; + +el-m150|\ +rb-450) + migrate_switch_name "eth1" "switch0" + ;; + +db120 |\ +rb-2011l | \ +rb-2011uas-2hnd) + migrate_switch_name "eth0" "switch0" + migrate_switch_name "eth1" "switch1" + ;; + +dir-825-b1|\ +tew-673gru|\ +nbg460n_550n_550nh) + migrate_switch_name "rtl8366s" "switch0" + ;; + +tl-wr1043nd) + migrate_switch_name "rtl8366rb" "switch0" + ;; + +esac + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration new file mode 100644 index 0000000..bea9493 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration @@ -0,0 +1,13 @@ +#!/bin/sh +# +# Copyright (C) 2010 OpenWrt.org +# + +local dev="$(uci -q get network.@switch_vlan[0].device)" +local vlan="$(uci -q get network.@switch_vlan[0].vlan)" + +if [ "$dev" = "rtl8366s" ] && [ "$vlan" = 0 ]; then + logger -t vlan-migration "VLAN 0 is invalid for RTL8366s, changing to 1" + uci set network.@switch_vlan[0].vlan=1 + uci commit network +fi diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration b/target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration new file mode 100644 index 0000000..d578f59 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration @@ -0,0 +1,90 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +LED_OPTIONS_CHANGED=0 + +. /lib/functions.sh + +do_led_update_sysfs() +{ + local cfg=$1; shift + local tuples="$@" + local sysfs + local name + + config_get sysfs $cfg sysfs + config_get name $cfg name + + [ -z "$sysfs" ] && return + + for tuple in $tuples; do + local old=${tuple%=*} + local new=${tuple#*=} + local new_sysfs + + new_sysfs=$(echo ${sysfs} | sed "s/${old}/${new}/") + + [ "$new_sysfs" = "$sysfs" ] && continue + + uci set system.${cfg}.sysfs="${new_sysfs}" + LED_OPTIONS_CHANGED=1 + + logger -t led-migration "sysfs option of LED \"${name}\" updated to ${new_sysfs}" + done; +} + +migrate_leds() +{ + config_load system + config_foreach do_led_update_sysfs led "$@" +} + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +dhp-1565-a1|\ +dir-825-c1|\ +dir-835-a1) + migrate_leds ":orange:=:amber:" ":wifi_bgn=:wlan2g" + ;; + +wndap360) + migrate_leds "wndap360:=netgear:" + ;; + +wndr3700) + migrate_leds "wndr3700:=netgear:" + ;; + +wndr3700v4 | \ +wndr4300) + migrate_leds ":orange:=:amber:" + ;; + +wnr2000) + migrate_leds "wnr2000:=netgear:" + ;; + +wnr2200) + migrate_leds "wnr2200:=netgear:" + ;; + +wnr612-v2) + migrate_leds "wnr612v2:=netgear:" + ;; + +wnr1000-v2) + migrate_leds "wnr1000v2:=netgear:" + ;; + +*) + ;; +esac + +[ "$LED_OPTIONS_CHANGED" = "1" ] && uci commit system + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header new file mode 100644 index 0000000..000b773 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header @@ -0,0 +1,21 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +. /lib/ar71xx.sh + +fix_seama_header() { + local part=$1 + + mtd fixseama $part +} + +board=$(ar71xx_board_name) + +case "$board" in +mynet-n600 | \ +mynet-n750) + fix_seama_header kernel + ;; +esac diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-trx-header b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-trx-header new file mode 100644 index 0000000..1bfd525 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-trx-header @@ -0,0 +1,19 @@ +#!/bin/sh +# +# Copyright (C) 2010 OpenWrt.org +# + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +fixtrx() { + mtd -o 32 fixtrx firmware +} + +case "$board" in +mynet-rext |\ +wrt160nl) + fixtrx + ;; +esac diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh b/target/linux/ar71xx/base-files/lib/ar71xx.sh new file mode 100755 index 0000000..ad98cfb --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh @@ -0,0 +1,990 @@ +#!/bin/sh +# +# Copyright (C) 2009-2011 OpenWrt.org +# + +AR71XX_BOARD_NAME= +AR71XX_MODEL= + +ar71xx_get_mtd_offset_size_format() { + local mtd="$1" + local offset="$2" + local size="$3" + local format="$4" + local dev + + dev=$(find_mtd_part $mtd) + [ -z "$dev" ] && return + + dd if=$dev bs=1 skip=$offset count=$size 2>/dev/null | hexdump -v -e "1/1 \"$format\"" +} + +ar71xx_get_mtd_part_magic() { + local mtd="$1" + ar71xx_get_mtd_offset_size_format "$mtd" 0 4 %02x +} + +wndr3700_board_detect() { + local machine="$1" + local magic + local name + + name="wndr3700" + + magic="$(ar71xx_get_mtd_part_magic firmware)" + case $magic in + "33373030") + machine="NETGEAR WNDR3700" + ;; + "33373031") + # Use awk to remove everything after the first zero byte + model="$(ar71xx_get_mtd_offset_size_format art 41 32 %c | LC_CTYPE=C awk -v 'FS=[^[:print:]]' '{print $1; exit}')" + case $model in + $'\xff'*) + if [ "${model:24:1}" = 'N' ]; then + machine="NETGEAR WNDRMAC" + else + machine="NETGEAR WNDR3700v2" + fi + ;; + '29763654+16+64'*) + machine="NETGEAR ${model:14}" + ;; + '29763654+16+128'*) + machine="NETGEAR ${model:15}" + ;; + *) + # Unknown ID + machine="NETGEAR $model" + esac + esac + + AR71XX_BOARD_NAME="$name" + AR71XX_MODEL="$machine" +} + +cybertan_get_hw_magic() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd bs=8 count=1 skip=0 if=$part 2>/dev/null | hexdump -v -n 8 -e '1/1 "%02x"' +} + +tplink_get_hwid() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd if=$part bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_get_mid() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd if=$part bs=4 count=1 skip=17 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_board_detect() { + local model="$1" + local hwid + local hwver + + hwid=$(tplink_get_hwid) + mid=$(tplink_get_mid) + hwver=${hwid:6:2} + hwver="v${hwver#0}" + + case "$hwid" in + "015000"*) + model="EasyLink EL-M150" + ;; + "015300"*) + model="EasyLink EL-MINI" + ;; + "04440001"*) + model="BITMAIN ANTMINER S1" + ;; + "04440003"*) + model="BITMAIN ANTMINER S3" + ;; + "120000"*) + model="MERCURY MAC1200R" + ;; + "3C0001"*) + model="OOLITE" + ;; + "070300"*) + model="TP-Link TL-WR703N" + ;; + "071000"*) + model="TP-Link TL-WR710N" + ;; + "072001"*) + model="TP-Link TL-WR720N" + ;; + "070100"*) + model="TP-Link TL-WA701N/ND" + ;; + "073000"*) + model="TP-Link TL-WA730RE" + ;; + "074000"*) + model="TP-Link TL-WR740N/ND" + ;; + "074100"*) + model="TP-Link TL-WR741N/ND" + ;; + "074300"*) + model="TP-Link TL-WR743N/ND" + ;; + "075000"*) + model="TP-Link TL-WA750RE" + ;; + "721000"*) + model="TP-Link TL-WA7210N" + ;; + "751000"*) + model="TP-Link TL-WA7510N" + ;; + "080100"*) + model="TP-Link TL-WA801N/ND" + ;; + "083000"*) + model="TP-Link TL-WA830RE" + + if [ "$hwver" = 'v10' ]; then + hwver='v1' + fi + ;; + "084100"*) + model="TP-Link TL-WR841N/ND" + ;; + "084200"*) + model="TP-Link TL-WR842N/ND" + ;; + "084300"*) + model="TP-Link TL-WR843N/ND" + ;; + "085000"*) + model="TP-Link TL-WA850RE" + ;; + "086000"*) + model="TP-Link TL-WA860RE" + ;; + "090100"*) + model="TP-Link TL-WA901N/ND" + ;; + "094100"*) + if [ "$hwid" = "09410002" -a "$mid" = "00420001" ]; then + model="Rosewill RNX-N360RT" + hwver="" + else + model="TP-Link TL-WR941N/ND" + fi + ;; + "104100"*) + model="TP-Link TL-WR1041N/ND" + ;; + "104300"*) + model="TP-Link TL-WR1043N/ND" + ;; + "254300"*) + model="TP-Link TL-WR2543N/ND" + ;; + "001001"*) + model="TP-Link TL-MR10U" + ;; + "001101"*) + model="TP-Link TL-MR11U" + ;; + "001201"*) + model="TP-Link TL-MR12U" + ;; + "001301"*) + model="TP-Link TL-MR13U" + ;; + "302000"*) + model="TP-Link TL-MR3020" + ;; + "304000"*) + model="TP-Link TL-MR3040" + ;; + "322000"*) + model="TP-Link TL-MR3220" + ;; + "342000"*) + model="TP-Link TL-MR3420" + ;; + "332000"*) + model="TP-Link TL-WDR3320" + ;; + "350000"*) + model="TP-Link TL-WDR3500" + ;; + "360000"*) + model="TP-Link TL-WDR3600" + ;; + "430000"*) + model="TP-Link TL-WDR4300" + ;; + "430080"*) + iw reg set IL + model="TP-Link TL-WDR4300 (IL)" + ;; + "431000"*) + model="TP-Link TL-WDR4310" + ;; + "49000002") + model="TP-Link TL-WDR4900" + ;; + "65000002") + model="TP-Link TL-WDR6500" + ;; + "453000"*) + model="MERCURY MW4530R" + ;; + "934100"*) + model="NC-LINK SMART-300" + ;; + "c50000"*) + model="TP-Link Archer C5" + ;; + "750000"*|\ + "c70000"*) + model="TP-Link Archer C7" + ;; + *) + hwver="" + ;; + esac + + AR71XX_MODEL="$model $hwver" +} + +tplink_pharos_get_model_string() { + local part + part=$(find_mtd_part 'product-info') + [ -z "$part" ] && return 1 + + # The returned string will end with \r\n, but we don't remove it here + # to simplify matching against it in the sysupgrade image check + dd if=$part bs=1 skip=4360 2>/dev/null | head -n 1 +} + +tplink_pharos_board_detect() { + local model_string="$(tplink_pharos_get_model_string | tr -d '\r')" + local oIFS="$IFS"; IFS=":"; set -- $model_string; IFS="$oIFS" + local model + + case "$1" in + 'CPE210(TP-LINK|UN|N300-2)') + model='TP-Link CPE210' + ;; + 'CPE220(TP-LINK|UN|N300-2)') + model='TP-Link CPE220' + ;; + 'CPE510(TP-LINK|UN|N300-5)') + model='TP-Link CPE510' + ;; + 'CPE520(TP-LINK|UN|N300-5)') + model='TP-Link CPE520' + ;; + esac + + [ -n "$model" ] && AR71XX_MODEL="$model v$2" +} + +gl_inet_board_detect() { + local size="$(mtd_get_part_size 'firmware')" + + case "$size" in + 8192000) + AR71XX_MODEL='GL-iNet 6408A v1' + ;; + 16580608) + AR71XX_MODEL='GL-iNet 6416A v1' + ;; + esac +} + +ar71xx_board_detect() { + local machine + local name + + machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo) + + case "$machine" in + *"Oolite V1.0") + name="oolite" + ;; + *"AC1750DB") + name="f9k1115v2" + ;; + *"AirGateway") + name="airgateway" + ;; + *"AirGateway Pro") + name="airgatewaypro" + ;; + *"AirRouter") + name="airrouter" + ;; + *"ALFA Network AP96") + name="alfa-ap96" + ;; + *"ALFA Network N2/N5") + name="alfa-nx" + ;; + *ALL0258N) + name="all0258n" + ;; + *ALL0305) + name="all0305" + ;; + *ALL0315N) + name="all0315n" + ;; + *AP113) + name="ap113" + ;; + *AP121) + name="ap121" + ;; + *AP121-MINI) + name="ap121-mini" + ;; + *"AP132 reference board") + name="ap132" + ;; + *"AP136-010 reference board") + name="ap136-010" + ;; + *"AP136-020 reference board") + name="ap136-020" + ;; + *"AP135-020 reference board") + name="ap135-020" + ;; + *"AP143 reference board") + name="ap143" + ;; + *"AP147-010 reference board") + name="ap147-010" + ;; + *"AP152 reference board") + name="ap152" + ;; + *AP81) + name="ap81" + ;; + *AP83) + name="ap83" + ;; + *"Archer C5") + name="archer-c5" + ;; + *"Archer C7") + name="archer-c7" + ;; + *"Atheros AP96") + name="ap96" + ;; + *AW-NR580) + name="aw-nr580" + ;; + *CAP4200AG) + name="cap4200ag" + ;; + *"COMFAST CF-E316N v2") + name="cf-e316n-v2" + ;; + *"CPE210/220/510/520") + name="cpe510" + tplink_pharos_board_detect + ;; + *"DB120 reference board") + name="db120" + ;; + *"DGL-5500 rev. A1") + name="dgl-5500-a1" + ;; + *"DHP-1565 rev. A1") + name="dhp-1565-a1" + ;; + *"DIR-505 rev. A1") + name="dir-505-a1" + ;; + *"DIR-600 rev. A1") + name="dir-600-a1" + ;; + *"DIR-615 rev. E1") + name="dir-615-e1" + ;; + *"DIR-615 rev. E4") + name="dir-615-e4" + ;; + *"DIR-615 rev. I1") + name="dir-615-i1" + ;; + *"DIR-825 rev. B1") + name="dir-825-b1" + ;; + *"DIR-825 rev. C1") + name="dir-825-c1" + ;; + *"DIR-835 rev. A1") + name="dir-835-a1" + ;; + *"dLAN pro 500 Wireless+") + name="dlan-pro-500-wp" + ;; + *"dLAN pro 1200+ WiFi ac") + name="dlan-pro-1200-ac" + ;; + *"Dragino v2") + name="dragino2" + ;; + *"EAP300 v2") + name="eap300v2" + ;; + *EAP7660D) + name="eap7660d" + ;; + *EL-M150) + name="el-m150" + ;; + *EL-MINI) + name="el-mini" + ;; + *"GL-CONNECT INET v1") + name="gl-inet" + gl_inet_board_detect + ;; + *"EnGenius EPG5000") + name="epg5000" + ;; + *"EnGenius ESR1750") + name="esr1750" + ;; + *"EnGenius ESR900") + name="esr900" + ;; + *JA76PF) + name="ja76pf" + ;; + *JA76PF2) + name="ja76pf2" + ;; + *"Bullet M") + name="bullet-m" + ;; + *"Loco M XW") + name="loco-m-xw" + ;; + *"Nanostation M") + name="nanostation-m" + ;; + *"Nanostation M XW") + name="nanostation-m-xw" + ;; + *JWAP003) + name="jwap003" + ;; + *"Hornet-UB") + local size + size=$(awk '/firmware/ { print $2 }' /proc/mtd) + + if [ "x$size" = "x00790000" ]; then + name="hornet-ub" + fi + + if [ "x$size" = "x00f90000" ]; then + name="hornet-ub-x2" + fi + ;; + *LS-SR71) + name="ls-sr71" + ;; + *"MAC1200R") + name="mc-mac1200r" + ;; + *MR12) + name="mr12" + ;; + *MR16) + name="mr16" + ;; + *MR600v2) + name="mr600v2" + ;; + *MR1750) + name="mr1750" + ;; + *MR600) + name="mr600" + ;; + *MR900) + name="mr900" + ;; + *MR900v2) + name="mr900v2" + ;; + *"My Net N600") + name="mynet-n600" + ;; + *"My Net N750") + name="mynet-n750" + ;; + *"WD My Net Wi-Fi Range Extender") + name="mynet-rext" + ;; + *MZK-W04NU) + name="mzk-w04nu" + ;; + *MZK-W300NH) + name="mzk-w300nh" + ;; + *"NBG460N/550N/550NH") + name="nbg460n_550n_550nh" + ;; + *"Zyxel NBG6716") + name="nbg6716" + ;; + *OM2P) + name="om2p" + ;; + *OM2Pv2) + name="om2pv2" + ;; + *"OM2P HS") + name="om2p-hs" + ;; + *"OM2P HSv2") + name="om2p-hsv2" + ;; + *"OM2P LC") + name="om2p-lc" + ;; + *OM5P) + name="om5p" + ;; + *"OM5P AN") + name="om5p-an" + ;; + *"Onion Omega") + name="onion-omega" + ;; + *PB42) + name="pb42" + ;; + *"PB44 reference board") + name="pb44" + ;; + *PB92) + name="pb92" + ;; + *"Qihoo 360 C301") + name="qihoo-c301" + ;; + *"RouterBOARD 411/A/AH") + name="rb-411" + ;; + *"RouterBOARD 411U") + name="rb-411u" + ;; + *"RouterBOARD 433/AH") + name="rb-433" + ;; + *"RouterBOARD 433UAH") + name="rb-433u" + ;; + *"RouterBOARD 435G") + name="rb-435g" + ;; + *"RouterBOARD 450") + name="rb-450" + ;; + *"RouterBOARD 450G") + name="rb-450g" + ;; + *"RouterBOARD 493/AH") + name="rb-493" + ;; + *"RouterBOARD 493G") + name="rb-493g" + ;; + *"RouterBOARD 750") + name="rb-750" + ;; + *"RouterBOARD 750GL") + name="rb-750gl" + ;; + *"RouterBOARD 751") + name="rb-751" + ;; + *"RouterBOARD 751G") + name="rb-751g" + ;; + *"RouterBOARD 911G-2HPnD") + name="rb-911g-2hpnd" + ;; + *"RouterBOARD 911G-5HPnD") + name="rb-911g-5hpnd" + ;; + *"RouterBOARD 911G-5HPacD") + name="rb-911g-5hpacd" + ;; + *"RouterBOARD 912UAG-2HPnD") + name="rb-912uag-2hpnd" + ;; + *"RouterBOARD 912UAG-5HPnD") + name="rb-912uag-5hpnd" + ;; + *"RouterBOARD 951G-2HnD") + name="rb-951g-2hnd" + ;; + *"RouterBOARD 951Ui-2HnD") + name="rb-951ui-2hnd" + ;; + *"RouterBOARD 2011L") + name="rb-2011l" + ;; + *"RouterBOARD 2011UAS") + name="rb-2011uas" + ;; + *"RouterBOARD 2011UiAS") + name="rb-2011uias" + ;; + *"RouterBOARD 2011UAS-2HnD") + name="rb-2011uas-2hnd" + ;; + *"RouterBOARD 2011UiAS-2HnD") + name="rb-2011uias-2hnd" + ;; + *"RouterBOARD SXT Lite2") + name="rb-sxt2n" + ;; + *"RouterBOARD SXT Lite5") + name="rb-sxt5n" + ;; + *"Rocket M") + name="rocket-m" + ;; + *"Rocket M TI") + name="rocket-m-ti" + ;; + *"Rocket M XW") + name="rocket-m-xw" + ;; + *RouterStation) + name="routerstation" + ;; + *"RouterStation Pro") + name="routerstation-pro" + ;; + *RW2458N) + name="rw2458n" + ;; + *"SMART-300") + name="smart-300" + ;; + "Smart Electronics Black Swift board"*) + name="bsb" + ;; + *TEW-632BRP) + name="tew-632brp" + ;; + *TEW-673GRU) + name="tew-673gru" + ;; + *TEW-712BR) + name="tew-712br" + ;; + *TEW-732BR) + name="tew-732br" + ;; + *"TL-WR1041N v2") + name="tl-wr1041n-v2" + ;; + *TL-WR1043ND) + name="tl-wr1043nd" + ;; + *"TL-WR1043ND v2") + name="tl-wr1043nd-v2" + ;; + *TL-WR2543N*) + name="tl-wr2543n" + ;; + *"DIR-615 rev. C1") + name="dir-615-c1" + ;; + *TL-MR3020) + name="tl-mr3020" + ;; + *TL-MR3040) + name="tl-mr3040" + ;; + *"TL-MR3040 v2") + name="tl-mr3040-v2" + ;; + *TL-MR3220) + name="tl-mr3220" + ;; + *"TL-MR3220 v2") + name="tl-mr3220-v2" + ;; + *TL-MR3420) + name="tl-mr3420" + ;; + *"TL-MR3420 v2") + name="tl-mr3420-v2" + ;; + *"TL-WA701ND v2") + name="tl-wa701nd-v2" + ;; + *"TL-WA7210N v2") + name="tl-wa7210n-v2" + ;; + *TL-WA750RE) + name="tl-wa750re" + ;; + *"TL-WA7510N v1") + name="tl-wa7510n" + ;; + *TL-WA850RE) + name="tl-wa850re" + ;; + *TL-WA860RE) + name="tl-wa860re" + ;; + *"TL-WA830RE v2") + name="tl-wa830re-v2" + ;; + *"TL-WA801ND v2") + name="tl-wa801nd-v2" + ;; + *TL-WA901ND) + name="tl-wa901nd" + ;; + *"TL-WA901ND v2") + name="tl-wa901nd-v2" + ;; + *"TL-WA901ND v3") + name="tl-wa901nd-v3" + ;; + *"TL-WDR3320 v2") + name="tl-wdr3320-v2" + ;; + *"TL-WDR3500") + name="tl-wdr3500" + ;; + *"TL-WDR3600/4300/4310") + name="tl-wdr4300" + ;; + *"TL-WDR4900 v2") + name="tl-wdr4900-v2" + ;; + *"TL-WDR6500 v2") + name="tl-wdr6500-v2" + ;; + *TL-WR741ND) + name="tl-wr741nd" + ;; + *"TL-WR741ND v4") + name="tl-wr741nd-v4" + ;; + *"TL-WR841N v1") + name="tl-wr841n-v1" + ;; + *"TL-WR841N/ND v7") + name="tl-wr841n-v7" + ;; + *"TL-WR841N/ND v8") + name="tl-wr841n-v8" + ;; + *"TL-WR841N/ND v9") + name="tl-wr841n-v9" + ;; + *"TL-WR842N/ND v2") + name="tl-wr842n-v2" + ;; + *TL-WR941ND) + name="tl-wr941nd" + ;; + *"TL-WR941N/ND v5") + name="tl-wr941nd-v5" + ;; + *"TL-WR703N v1") + name="tl-wr703n" + ;; + *"TL-WR710N v1") + name="tl-wr710n" + ;; + *"TL-WR720N"*) + name="tl-wr720n-v3" + ;; + *"TL-MR10U") + name="tl-mr10u" + ;; + *"TL-MR11U") + name="tl-mr11u" + ;; + *"TL-MR12U") + name="tl-mr12u" + ;; + *"TL-MR13U v1") + name="tl-mr13u" + ;; + *"Tube2H") + name="tube2h" + ;; + *UniFi) + name="unifi" + ;; + *"UniFi AP Pro") + name="uap-pro" + ;; + *"WeIO") + name="weio" + ;; + *WHR-G301N) + name="whr-g301n" + ;; + *WHR-HP-GN) + name="whr-hp-gn" + ;; + *WLAE-AG300N) + name="wlae-ag300n" + ;; + *"UniFiAP Outdoor") + name="unifi-outdoor" + ;; + *"UniFiAP Outdoor+") + name="unifi-outdoor-plus" + ;; + *WP543) + name="wp543" + ;; + *WPE72) + name="wpe72" + ;; + *WPJ344) + name="wpj344" + ;; + *WPJ531) + name="wpj531" + ;; + *WPJ558) + name="wpj558" + ;; + *WNDAP360) + name="wndap360" + ;; + *"WNDR3700/WNDR3800/WNDRMAC") + wndr3700_board_detect "$machine" + ;; + *"R6100") + name="r6100" + ;; + *"WNDR3700v4") + name="wndr3700v4" + ;; + *"WNDR4300") + name="wndr4300" + ;; + *"WNR2000 V4") + name="wnr2000-v4" + ;; + *"WNR2000 V3") + name="wnr2000-v3" + ;; + *WNR2000) + name="wnr2000" + ;; + *WNR2200) + name="wnr2200" + ;; + *"WNR612 V2") + name="wnr612-v2" + ;; + *"WNR1000 V2") + name="wnr1000-v2" + ;; + *WRT160NL) + name="wrt160nl" + ;; + *WRT400N) + name="wrt400n" + ;; + *"WZR-450HP2") + name="wzr-450hp2" + ;; + *"WZR-HP-AG300H/WZR-600DHP") + name="wzr-hp-ag300h" + ;; + *WZR-HP-G300NH) + name="wzr-hp-g300nh" + ;; + *WZR-HP-G450H) + name="wzr-hp-g450h" + ;; + *WZR-HP-G300NH2) + name="wzr-hp-g300nh2" + ;; + *WHR-HP-G300N) + name="whr-hp-g300n" + ;; + *ZCN-1523H-2) + name="zcn-1523h-2" + ;; + *ZCN-1523H-5) + name="zcn-1523h-5" + ;; + *EmbWir-Dorin) + name="ew-dorin" + ;; + *EmbWir-Dorin-Router) + name="ew-dorin-router" + ;; + "8devices Carambola2"*) + name="carambola2" + ;; + *"Sitecom WLR-8100") + name="wlr8100" + ;; + *"BHU BXU2000n-2 rev. A1") + name="bxu2000n-2-a1" + ;; + *"HiWiFi HC6361") + name="hiwifi-hc6361" + ;; + esac + + [ -z "$AR71XX_MODEL" ] && [ "${machine:0:8}" = 'TP-LINK ' ] && \ + tplink_board_detect "$machine" + + [ -z "$name" ] && name="unknown" + + [ -z "$AR71XX_BOARD_NAME" ] && AR71XX_BOARD_NAME="$name" + [ -z "$AR71XX_MODEL" ] && AR71XX_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$AR71XX_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$AR71XX_MODEL" > /tmp/sysinfo/model +} + +ar71xx_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh b/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh new file mode 100644 index 0000000..ff5407a --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_ar71xx() { + . /lib/ar71xx.sh + + ar71xx_board_detect +} + +boot_hook_add preinit_main do_ar71xx diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx new file mode 100644 index 0000000..92b3765 --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx @@ -0,0 +1,48 @@ +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + +fetch_mac_from_mtd() { + local mtd_part=$1 + local lan_env=$2 + local wan_env=$3 + local mtd mac + + mtd=$(grep $mtd_part /proc/mtd | cut -d: -f1) + [ -z $mtd ] && return + + mac=$(grep $lan_env /dev/$mtd | cut -d= -f2) + [ ! -z $mac ] && ifconfig eth0 hw ether $mac 2>/dev/null + + mac=$(grep $wan_env /dev/$mtd | cut -d= -f2) + [ ! -z $mac ] && ifconfig eth1 hw ether $mac 2>/dev/null +} + +preinit_set_mac_address() { + case $(ar71xx_board_name) in + dir-615-c1) + fetch_mac_from_mtd config lan_mac wan_mac + echo 1 > /sys/class/leds/dir-615-c1:green:wancpu/brightness + ;; + dir-615-i1) + fetch_mac_from_mtd nvram sys_lan_mac sys_wan_mac + ;; + r6100) + mac_lan=$(mtd_get_mac_binary caldata 0) + [ -n "$mac_lan" ] && ifconfig eth1 hw ether "$mac_lan" + mac_wan=$(mtd_get_mac_binary caldata 6) + [ -n "$mac_wan" ] && ifconfig eth0 hw ether "$mac_wan" + ;; + tew-632brp) + fetch_mac_from_mtd config lan_mac wan_mac + ;; + wrt160nl) + fetch_mac_from_mtd nvram lan_hwaddr wan_hwaddr + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address + diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx new file mode 100644 index 0000000..d214e9b --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx @@ -0,0 +1,55 @@ +#!/bin/sh + +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + +set_preinit_iface() { + case $(ar71xx_board_name) in + alfa-ap96 |\ + alfa-nx |\ + ap135-020 |\ + ap136-020 |\ + ap147-010 |\ + ap83 |\ + archer-c5 |\ + archer-c7 |\ + dir-505-a1 |\ + gl-inet |\ + jwap003 |\ + pb42 |\ + pb44 |\ + rb-433 |\ + rb-433u |\ + rb-435g |\ + rb-450 |\ + rb-450g |\ + routerstation |\ + routerstation-pro |\ + smart-300 |\ + tl-mr3420-v2 |\ + tl-wdr4900-v2 |\ + tl-wr1043nd-v2 |\ + tl-wr710n |\ + tl-wr720n-v3 |\ + tl-wr841n-v8 |\ + tl-wr842n-v2 |\ + wnr2000-v3 |\ + wnr2200 |\ + wnr612-v2 |\ + wnr1000-v2 |\ + wpe72) + ifname=eth1 + ;; + *) + ifname=eth0 + ;; + esac +} + +boot_hook_add preinit_main set_preinit_iface + + + diff --git a/target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k b/target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k new file mode 100644 index 0000000..4da611a --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k @@ -0,0 +1,51 @@ +#!/bin/sh + +. /lib/functions/system.sh +. /lib/ar71xx.sh + + +do_patch_ath10k_firmware() { + local firmware_file="/lib/firmware/ath10k/QCA988X/hw2.0/firmware-5.bin" + + # bail out if firmware does not exist + [ -f "$firmware_file" ] || { + return + } + + local firmware_md5_orig="36768dc68572b3f2660211e20e89f558" + local firmware_md5_current="$(md5sum $firmware_file)" + local firmware_md5_current="${firmware_md5_current%% *}" + + # verify md5sum before patching + [ "$firmware_md5_orig" != "$firmware_md5_current" ] || { + return + } + + # some boards have bogus mac in otp, patch the default mac in the firmware + case $(ar71xx_board_name) in + dgl-5500-a1) + local mac + mac=$(mtd_get_mac_ascii nvram wlan1_mac) + + cp $firmware_file /tmp/ath10k-firmware.bin + macaddr_2bin $mac | dd of=/tmp/ath10k-firmware.bin \ + conv=notrunc bs=1 seek=276 count=6 + + ;; + esac + [ -f /tmp/ath10k-firmware.bin ] || { + return + } + cp /tmp/ath10k-firmware.bin $firmware_file + rm /tmp/ath10k-firmware.bin +} + +check_patch_ath10k_firmware() { + case $(ar71xx_board_name) in + dgl-5500-a1) + do_patch_ath10k_firmware + ;; + esac +} + +boot_hook_add preinit_main check_patch_ath10k_firmware diff --git a/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh b/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh new file mode 100644 index 0000000..98b368d --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh @@ -0,0 +1,162 @@ +# The U-Boot loader of the some Allnet devices requires image sizes and +# checksums to be provided in the U-Boot environment. +# In case the check fails during boot, a failsafe-system is started to provide +# a minimal web-interface for flashing a new firmware. + +# make sure we got uboot-envtools and fw_env.config copied over to the ramfs +# create /var/lock for the lock "fw_setenv.lock" of fw_setenv +platform_add_ramfs_ubootenv() { + [ -e /usr/sbin/fw_printenv ] && install_bin /usr/sbin/fw_printenv /usr/sbin/fw_setenv + [ -e /etc/fw_env.config ] && install_file /etc/fw_env.config + mkdir -p $RAM_ROOT/var/lock +} +append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv + +# determine size of the main firmware partition +platform_get_firmware_size() { + local dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + firmware) + printf "%d" "0x$size" + break + ;; + esac + done < /proc/mtd +} + +# get the first 4 bytes (magic) of a given file starting at offset in hex format +get_magic_long_at() { + dd if="$1" skip=$(( $CI_BLKSZ / 4 * $2 )) bs=4 count=1 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +get_filesize() { + wc -c "$1" | while read image_size _n ; do echo $image_size ; break; done +} + +# scan through the update image pages until matching a magic +platform_get_offset() { + offsetcount=0 + magiclong="x" + if [ -n "$3" ]; then + offsetcount=$3 + fi + while magiclong=$( get_magic_long_at "$1" "$offsetcount" ) && [ -n "$magiclong" ]; do + case "$magiclong" in + "2705"*) + # U-Boot image magic + if [ "$2" = "uImage" ]; then + echo $offsetcount + return + fi + ;; + "68737173"|"73717368") + # SquashFS + if [ "$2" = "rootfs" ]; then + echo $offsetcount + return + fi + ;; + "deadc0de"|"19852003") + # JFFS2 empty page + if [ "$2" = "rootfs-data" ]; then + echo $offsetcount + return + fi + ;; + esac + offsetcount=$(( $offsetcount + 1 )) + done +} + +platform_check_image_allnet() { + local fw_printenv=/usr/sbin/fw_printenv + [ ! -n "$fw_printenv" -o ! -x "$fw_printenv" ] && { + echo "Please install uboot-envtools!" + return 1 + } + + [ ! -r "/etc/fw_env.config" ] && { + echo "/etc/fw_env.config is missing" + return 1 + } + + local image_size=$( get_filesize "$1" ) + local firmware_size=$( platform_get_firmware_size ) + [ $image_size -ge $firmware_size ] && + { + echo "upgrade image is too big (${image_size}b > ${firmware_size}b)" + } + + local vmlinux_blockoffset=$( platform_get_offset "$1" uImage ) + [ -z $vmlinux_blockoffset ] && { + echo "vmlinux-uImage not found" + return 1 + } + + local rootfs_blockoffset=$( platform_get_offset "$1" rootfs "$vmlinux_blockoffset" ) + [ -z $rootfs_blockoffset ] && { + echo "missing rootfs" + return 1 + } + + local data_blockoffset=$( platform_get_offset "$1" rootfs-data "$rootfs_blockoffset" ) + [ -z $data_blockoffset ] && { + echo "rootfs doesn't have JFFS2 end marker" + return 1 + } + + return 0 +} + +platform_do_upgrade_allnet() { + local firmware_base_addr=$( printf "%d" "$1" ) + local vmlinux_blockoffset=$( platform_get_offset "$2" uImage ) + if [ ! -n "$vmlinux_blockoffset" ]; then + echo "can't determine uImage offset" + return 1 + fi + local rootfs_blockoffset=$( platform_get_offset "$2" rootfs $(( $vmlinux_blockoffset + 1 )) ) + local vmlinux_offset=$(( $vmlinux_blockoffset * $CI_BLKSZ )) + local vmlinux_addr=$(( $firmware_base_addr + $vmlinux_offset )) + local vmlinux_hexaddr=0x$( printf "%08x" "$vmlinux_addr" ) + if [ ! -n "$rootfs_blockoffset" ]; then + echo "can't determine rootfs offset" + return 1 + fi + local rootfs_offset=$(( $rootfs_blockoffset * $CI_BLKSZ )) + local rootfs_addr=$(( $firmware_base_addr + $rootfs_offset )) + local rootfs_hexaddr=0x$( printf "%08x" "$rootfs_addr" ) + local vmlinux_blockcount=$(( $rootfs_blockoffset - $vmlinux_blockoffset )) + local vmlinux_size=$(( $rootfs_offset - $vmlinux_offset )) + local vmlinux_hexsize=0x$( printf "%08x" "$vmlinux_size" ) + local data_blockoffset=$( platform_get_offset "$2" rootfs-data $(( $rootfs_blockoffset + 1 )) ) + if [ ! -n "$data_blockoffset" ]; then + echo "can't determine rootfs size" + return 1 + fi + local data_offset=$(( $data_blockoffset * $CI_BLKSZ )) + local rootfs_blockcount=$(( $data_blockoffset - $rootfs_blockoffset )) + local rootfs_size=$(( $data_offset - $rootfs_offset )) + local rootfs_hexsize=0x$( printf "%08x" "$rootfs_size" ) + + local rootfs_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$rootfs_blockoffset count=$rootfs_blockcount 2>/dev/null | md5sum -); rootfs_md5="${rootfs_md5%% *}" + local vmlinux_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$vmlinux_blockoffset count=$vmlinux_blockcount 2>/dev/null | md5sum -); vmlinux_md5="${vmlinux_md5%% *}" + # this needs a recent version of uboot-envtools! + cat >/tmp/fw_env_upgrade </dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +dir825b_is_caldata_valid() { + local mtddev=$1 + local magic + + magic=$(get_magic_at $mtddev 4096) + [ "$magic" != "a55a" ] && return 0 + + magic=$(get_magic_at $mtddev 20480) + [ "$magic" != "a55a" ] && return 0 + + return 1 +} + +dir825b_copy_caldata() { + local cal_src=$1 + local cal_dst=$2 + local mtd_src + local mtd_dst + local md5_src + local md5_dst + + mtd_src=$(find_mtd_part $cal_src) + [ -z "$mtd_src" ] && { + echo "no $cal_src partition found" + return 1 + } + + mtd_dst=$(find_mtd_part $cal_dst) + [ -z "$mtd_dst" ] && { + echo "no $cal_dst partition found" + return 1 + } + + dir825b_is_caldata_valid "$mtd_src" && { + echo "no valid calibration data found in $cal_src" + return 1 + } + + dir825b_is_caldata_valid "$mtd_dst" && { + echo "Copying calibration data from $cal_src to $cal_dst..." + dd if="$mtd_src" 2>/dev/null | mtd -q -q write - "$cal_dst" + } + + md5_src=$(md5sum "$mtd_src") && md5_src="${md5_src%% *}" + md5_dst=$(md5sum "$mtd_dst") && md5_dst="${md5_dst%% *}" + + [ "$md5_src" != "$md5_dst" ] && { + echo "calibration data mismatch $cal_src:$md5_src $cal_dst:$md5_dst" + return 1 + } + + return 0 +} + +dir825b_do_upgrade_combined() { + local fw_part=$1 + local fw_file=$2 + local fw_mtd=$(find_mtd_part $fw_part) + local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null) + local fw_blocks=$(($fw_length / 65536)) + + if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + sync + dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \ + mtd $append write - "$fw_part" + fi +} + +dir825b_check_image() { + local magic="$(get_magic_long "$1")" + local fw_mtd=$(find_mtd_part "firmware_orig") + + case "$magic" in + "27051956") + ;; + "43493030") + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=64k skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + local fw_len=$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local fw_part_len=$(mtd_get_part_size "firmware") + + if [ -z "$fw_mtd" ]; then + ask_bool 0 "Do you have a backup of the caldata partition?" || { + echo "Warning, please make sure that you have a backup of the caldata partition." + echo "Once you have that, use 'sysupgrade -i' for upgrading to the 'fat' firmware." + return 1 + } + fi + + if [ -z "$md5_img" -o -z "$md5_chk" ]; then + echo "Unable to get image checksums. Maybe you are using a streamed image?" + return 1 + fi + + if [ "$md5_img" != "$md5_chk" ]; then + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + + fw_len=$((0x$fw_len)) + fw_part_len=${fw_part_len:-0} + + if [ $fw_part_len -lt $fw_len ]; then + echo "The upgrade image is too big (size:$fw_len available:$fw_part_len)" + return 1 + fi + ;; + *) + echo "Unsupported image format." + return 1 + ;; + esac + + return 0 +} + +platform_do_upgrade_dir825b() { + local magic="$(get_magic_long "$1")" + local fw_mtd=$(find_mtd_part "firmware_orig") + + case "$magic" in + "27051956") + if [ -n "$fw_mtd" ]; then + # restore calibration data before downgrading to + # the normal image + dir825b_copy_caldata "caldata" "caldata_orig" || { + echo "unable to restore calibration data" + exit 1 + } + PART_NAME="firmware_orig" + else + PART_NAME="firmware" + fi + default_do_upgrade "$ARGV" + ;; + "43493030") + if [ -z "$fw_mtd" ]; then + # backup calibration data before upgrading to the + # fat image + dir825b_copy_caldata "caldata" "caldata_copy" || { + echo "unable to backup calibration data" + exit 1 + } + fi + dir825b_do_upgrade_combined "firmware" "$ARGV" + ;; + esac +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh b/target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh new file mode 100644 index 0000000..9ca0f5b --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh @@ -0,0 +1,218 @@ +# The U-Boot loader of the OpenMesh devices requires image sizes and +# checksums to be provided in the U-Boot environment. +# The OpenMesh devices come with 2 main partitions - while one is active +# sysupgrade will flash the other. The boot order is changed to boot the +# newly flashed partition. If the new partition can't be booted due to +# upgrade failures the previously used partition is loaded. + +trim() +{ + echo $1 +} + +cfg_value_get() +{ + local cfg=$1 cfg_opt + local section=$2 our_section=0 + local param=$3 our_param= + + for cfg_opt in $cfg + do + [ "$cfg_opt" = "[$section]" ] && our_section=1 && continue + [ "$our_section" = "1" ] || continue + + our_param=$(echo ${cfg_opt%%=*}) + [ "$param" = "$our_param" ] && echo ${cfg_opt##*=} && break + done +} + +# make sure we got uboot-envtools and fw_env.config copied over to the ramfs +# create /var/lock for the lock "fw_setenv.lock" of fw_setenv +platform_add_ramfs_ubootenv() +{ + [ -e /usr/sbin/fw_printenv ] && install_bin /usr/sbin/fw_printenv /usr/sbin/fw_setenv + [ -e /etc/fw_env.config ] && install_file /etc/fw_env.config + mkdir -p $RAM_ROOT/var/lock +} +append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv + +platform_check_image_openmesh() +{ + local img_magic=$1 + local img_path=$2 + local fw_printenv=/usr/sbin/fw_printenv + local img_board_target= img_num_files= i=0 + local cfg_name= kernel_name= rootfs_name= + + case "$img_magic" in + # Combined Extended Image v1 + 43453031) + img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null)) + img_num_files=$(trim $(dd if="$img_path" bs=2 skip=18 count=1 2>/dev/null)) + ;; + *) + echo "Invalid image ($img_magic). Use combined extended images on this platform" + return 1 + ;; + esac + + case "$img_board_target" in + OM2P) + [ "$board" = "om2p" ] && break + [ "$board" = "om2pv2" ] && break + [ "$board" = "om2p-lc" ] && break + [ "$board" = "om2p-hs" ] && break + [ "$board" = "om2p-hsv2" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + OM5P) + [ "$board" = "om5p" ] && break + [ "$board" = "om5p-an" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + MR1750) + [ "$board" = "mr1750" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + MR600) + [ "$board" = "mr600" ] && break + [ "$board" = "mr600v2" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + MR900) + [ "$board" = "mr900" ] && break + [ "$board" = "mr900v2" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + *) + echo "Invalid board target ($img_board_target). Use the correct image for this platform" + return 1 + ;; + esac + + [ $img_num_files -ne 3 ] && { + echo "Invalid number of embedded images ($img_num_files). Use the correct image for this platform" + return 1 + } + + cfg_name=$(trim $(dd if="$img_path" bs=2 skip=19 count=16 2>/dev/null)) + + [ "$cfg_name" != "fwupgrade.cfg" ] && { + echo "Invalid embedded config file ($cfg_name). Use the correct image for this platform" + return 1 + } + + kernel_name=$(trim $(dd if="$img_path" bs=2 skip=55 count=16 2>/dev/null)) + + [ "$kernel_name" != "kernel" ] && { + echo "Invalid embedded kernel file ($kernel_name). Use the correct image for this platform" + return 1 + } + + rootfs_name=$(trim $(dd if="$img_path" bs=2 skip=91 count=16 2>/dev/null)) + + [ "$rootfs_name" != "rootfs" ] && { + echo "Invalid embedded kernel file ($rootfs_name). Use the correct image for this platform" + return 1 + } + + [ ! -x "$fw_printenv" ] && { + echo "Please install uboot-envtools!" + return 1 + } + + [ ! -r "/etc/fw_env.config" ] && { + echo "/etc/fw_env.config is missing" + return 1 + } + + return 0 +} + +platform_do_upgrade_openmesh() +{ + local img_path=$1 img_board_target= + local kernel_start_addr= kernel_start_addr1= kernel_start_addr2= + local kernel_size= kernel_md5= + local rootfs_size= rootfs_checksize= rootfs_md5= + local kernel_bsize= total_size= + local data_offset=$((64 * 1024)) block_size= offset= + local uboot_env_upgrade="/tmp/fw_env_upgrade" + local cfg_size= kernel_size= rootfs_size= + local append="" + + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + cfg_size=$(dd if="$img_path" bs=2 skip=35 count=4 2>/dev/null) + kernel_size=$(dd if="$img_path" bs=2 skip=71 count=4 2>/dev/null) + rootfs_size=$(dd if="$img_path" bs=2 skip=107 count=4 2>/dev/null) + + img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null)) + cfg_content=$(dd if="$img_path" bs=1 skip=$data_offset count=$(echo $((0x$cfg_size))) 2>/dev/null) + + case $img_board_target in + OM2P) + block_size=$((256 * 1024)) + total_size=7340032 + kernel_start_addr1=0x9f1c0000 + kernel_start_addr2=0x9f8c0000 + ;; + OM5P|MR600|MR900|MR1750) + block_size=$((64 * 1024)) + total_size=7995392 + kernel_start_addr1=0x9f0b0000 + kernel_start_addr2=0x9f850000 + ;; + esac + + kernel_md5=$(cfg_value_get "$cfg_content" "vmlinux" "md5sum") + rootfs_md5=$(cfg_value_get "$cfg_content" "rootfs" "md5sum") + rootfs_checksize=$(cfg_value_get "$cfg_content" "rootfs" "checksize") + + if [ "$((0x$kernel_size % $block_size))" = "0" ] + then + kernel_bsize=$(echo $((0x$kernel_size))) + else + kernel_bsize=$((0x$kernel_size + ($block_size - (0x$kernel_size % $block_size)))) + fi + + mtd -q erase inactive + + offset=$(echo $(($data_offset + 0x$cfg_size + 0x$kernel_size))) + dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$rootfs_size))) 2>&- | mtd -n -p $kernel_bsize $append write - "inactive" + + offset=$(echo $(($data_offset + 0x$cfg_size))) + dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$kernel_size))) 2>&- | mtd -n write - "inactive" + + rm $uboot_env_upgrade 2>&- + + if [ "$(grep 'mtd3:.*inactive' /proc/mtd)" ] + then + printf "kernel_size_1 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade + printf "rootfs_size_1 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade + printf "bootseq 1,2\n" >> $uboot_env_upgrade + kernel_start_addr=$kernel_start_addr1 + else + printf "kernel_size_2 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade + printf "rootfs_size_2 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade + printf "bootseq 2,1\n" >> $uboot_env_upgrade + kernel_start_addr=$kernel_start_addr2 + fi + + printf "vmlinux_start_addr %s\n" $kernel_start_addr >> $uboot_env_upgrade + printf "vmlinux_size 0x%s\n" $kernel_size >> $uboot_env_upgrade + printf "vmlinux_checksum %s\n" $kernel_md5 >> $uboot_env_upgrade + printf "rootfs_start_addr 0x%x\n" $(($kernel_start_addr + $kernel_bsize)) >> $uboot_env_upgrade + printf "rootfs_size %s\n" $rootfs_checksize >> $uboot_env_upgrade + printf "rootfs_checksum %s\n" $rootfs_md5 >> $uboot_env_upgrade + + fw_setenv -s $uboot_env_upgrade || { + echo "failed to update U-Boot environment" + return 1 + } +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..c947b78 --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,558 @@ +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/functions/system.sh +. /lib/ar71xx.sh + +PART_NAME=firmware +RAMFS_COPY_DATA=/lib/ar71xx.sh + +CI_BLKSZ=65536 +CI_LDADR=0x80060000 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|vmlinux|kernel|linux|linux.bin|rootfs|filesystem) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|vmlinux|kernel|linux|linux.bin) + echo "$part" + break + ;; + esac + done +} + +platform_do_upgrade_combined() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt 0 ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + ( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \ + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \ + mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions + fi +} + +tplink_get_image_hwid() { + get_image "$@" | dd bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_get_image_boot_size() { + get_image "$@" | dd bs=4 count=1 skip=37 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_pharos_check_image() { + local magic_long="$(get_magic_long "$1")" + [ "$magic_long" != "7f454c46" ] && { + echo "Invalid image magic '$magic_long'" + return 1 + } + + local model_string="$(tplink_pharos_get_model_string)" + local line + + # Here $1 is given to dd directly instead of get_image as otherwise the skip + # will take almost a second (as dd can't seek then) + # + # This will fail if the image isn't local, but that's fine: as the + # read loop won't be executed at all, it will return true, so the image + # is accepted (loading the first 1.5M of a remote image for this check seems + # a bit extreme) + dd if="$1" bs=1 skip=1511432 count=1024 2>/dev/null | while read line; do + [ "$line" == "$model_string" ] && break + done || { + echo "Unsupported image (model not in support-list)" + return 1 + } + + return 0 +} + +seama_get_type_magic() { + get_image "$@" | dd bs=1 count=4 skip=53 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +cybertan_get_image_magic() { + get_image "$@" | dd bs=8 count=1 skip=0 2>/dev/null | hexdump -v -n 8 -e '1/1 "%02x"' +} + +cybertan_check_image() { + local magic="$(cybertan_get_image_magic "$1")" + local fw_magic="$(cybertan_get_hw_magic)" + + [ "$fw_magic" != "$magic" ] && { + echo "Invalid image, ID mismatch, got:$magic, but need:$fw_magic" + return 1 + } + + return 0 +} + +platform_do_upgrade_compex() { + local fw_file=$1 + local fw_part=$PART_NAME + local fw_mtd=$(find_mtd_part $fw_part) + local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null) + local fw_blocks=$(($fw_length / 65536)) + + if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + sync + dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \ + mtd $append write - "$fw_part" + fi +} + +alfa_check_image() { + local magic_long="$(get_magic_long "$1")" + local fw_part_size=$(mtd_get_part_size firmware) + + case "$magic_long" in + "27051956") + [ "$fw_part_size" != "16318464" ] && { + echo "Invalid image magic \"$magic_long\" for $fw_part_size bytes" + return 1 + } + ;; + + "68737173") + [ "$fw_part_size" != "7929856" ] && { + echo "Invalid image magic \"$magic_long\" for $fw_part_size bytes" + return 1 + } + ;; + esac + + return 0 +} + +platform_check_image() { + local board=$(ar71xx_board_name) + local magic="$(get_magic_word "$1")" + local magic_long="$(get_magic_long "$1")" + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + all0315n | \ + all0258n | \ + cap4200ag) + platform_check_image_allnet "$1" && return 0 + return 1 + ;; + alfa-ap96 | \ + alfa-nx | \ + ap113 | \ + ap121 | \ + ap121-mini | \ + ap136-010 | \ + ap136-020 | \ + ap135-020 | \ + ap147-010 | \ + ap96 | \ + bxu2000n-2-a1 | \ + db120 | \ + f9k1115v2 |\ + hornet-ub | \ + mr12 | \ + mr16 | \ + wpj558 | \ + zcn-1523h-2 | \ + zcn-1523h-5) + [ "$magic_long" != "68737173" -a "$magic_long" != "19852003" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + ap81 | \ + ap83 | \ + ap132 | \ + cf-e316n-v2 | \ + dgl-5500-a1 |\ + dhp-1565-a1 |\ + dir-505-a1 | \ + dir-600-a1 | \ + dir-615-c1 | \ + dir-615-e1 | \ + dir-615-e4 | \ + dir-615-i1 | \ + dir-825-c1 | \ + dir-835-a1 | \ + dlan-pro-500-wp | \ + dlan-pro-1200-ac | \ + dragino2 | \ + epg5000 | \ + esr1750 | \ + esr900 | \ + ew-dorin | \ + ew-dorin-router | \ + hiwifi-hc6361 | \ + hornet-ub-x2 | \ + mzk-w04nu | \ + mzk-w300nh | \ + tew-632brp | \ + tew-712br | \ + tew-732br | \ + wrt400n | \ + airgateway | \ + airgatewaypro | \ + airrouter | \ + bullet-m | \ + loco-m-xw | \ + nanostation-m | \ + rocket-m | \ + rocket-m-xw | \ + rocket-m-ti | \ + nanostation-m-xw | \ + rw2458n | \ + wpj531 | \ + wndap360 | \ + wpj344 | \ + wzr-hp-g300nh2 | \ + wzr-hp-g300nh | \ + wzr-hp-g450h | \ + wzr-hp-ag300h | \ + wzr-450hp2 | \ + whr-g301n | \ + whr-hp-g300n | \ + whr-hp-gn | \ + wlae-ag300n | \ + nbg460n_550n_550nh | \ + unifi | \ + unifi-outdoor | \ + carambola2 | \ + weio ) + [ "$magic" != "2705" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + + cpe510) + tplink_pharos_check_image "$1" && return 0 + return 1 + ;; + + bsb | \ + dir-825-b1 | \ + tew-673gru) + dir825b_check_image "$1" && return 0 + ;; + + mynet-rext|\ + wrt160nl) + cybertan_check_image "$1" && return 0 + return 1 + ;; + + qihoo-c301 | \ + mynet-n600 | \ + mynet-n750) + [ "$magic_long" != "5ea3a417" ] && { + echo "Invalid image, bad magic: $magic_long" + return 1 + } + + local typemagic=$(seama_get_type_magic "$1") + [ "$typemagic" != "6669726d" ] && { + echo "Invalid image, bad type: $typemagic" + return 1 + } + + return 0; + ;; + mr1750 | \ + mr600 | \ + mr600v2 | \ + mr900 | \ + mr900v2 | \ + om2p | \ + om2pv2 | \ + om2p-hs | \ + om2p-hsv2 | \ + om2p-lc | \ + om5p | \ + om5p-an) + platform_check_image_openmesh "$magic_long" "$1" && return 0 + return 1 + ;; + + antminer-s1 | \ + antminer-s3 | \ + archer-c5 | \ + archer-c7 | \ + el-m150 | \ + el-mini | \ + gl-inet | \ + mc-mac1200r | \ + onion-omega | \ + oolite | \ + smart-300 | \ + tl-mr10u | \ + tl-mr11u | \ + tl-mr12u | \ + tl-mr13u | \ + tl-mr3020 | \ + tl-mr3040 | \ + tl-mr3040-v2 | \ + tl-mr3220 | \ + tl-mr3220-v2 | \ + tl-mr3420 | \ + tl-mr3420-v2 | \ + tl-wa701nd-v2 | \ + tl-wa7210n-v2 | \ + tl-wa7510n | \ + tl-wa750re | \ + tl-wa850re | \ + tl-wa860re | \ + tl-wa801nd-v2 | \ + tl-wa901nd | \ + tl-wa901nd-v2 | \ + tl-wa901nd-v3 | \ + tl-wdr3320-v2 | \ + tl-wdr3500 | \ + tl-wdr4300 | \ + tl-wdr4900-v2 | \ + tl-wdr6500-v2 | \ + tl-wr703n | \ + tl-wr710n | \ + tl-wr720n-v3 | \ + tl-wr741nd | \ + tl-wr741nd-v4 | \ + tl-wr841n-v1 | \ + tl-wa830re-v2 | \ + tl-wr841n-v7 | \ + tl-wr841n-v8 | \ + tl-wr841n-v9 | \ + tl-wr842n-v2 | \ + tl-wr941nd | \ + tl-wr941nd-v5 | \ + tl-wr1041n-v2 | \ + tl-wr1043nd | \ + tl-wr1043nd-v2 | \ + tl-wr2543n) + local magic_ver="0100" + + case "$board" in + tl-wdr6500-v2) + magic_ver="0200" + ;; + esac + + [ "$magic" != "$magic_ver" ] && { + echo "Invalid image type." + return 1 + } + + local hwid + local imageid + + hwid=$(tplink_get_hwid) + imageid=$(tplink_get_image_hwid "$1") + + [ "$hwid" != "$imageid" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hwid image:$imageid." + return 1 + } + + local boot_size + + boot_size=$(tplink_get_image_boot_size "$1") + [ "$boot_size" != "00000000" ] && { + echo "Invalid image, it contains a bootloader." + return 1 + } + + return 0 + ;; + + tube2h) + alfa_check_image "$1" && return 0 + return 1 + ;; + + unifi-outdoor-plus | \ + uap-pro) + [ "$magic_long" != "19852003" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + wndr3700 | \ + wnr2000-v3 | \ + wnr612-v2 | \ + wnr1000-v2) + local hw_magic + + hw_magic="$(ar71xx_get_mtd_part_magic firmware)" + [ "$magic_long" != "$hw_magic" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hw_magic image:$magic_long." + return 1 + } + return 0 + ;; + nbg6716 | \ + r6100 | \ + wndr3700v4 | \ + wndr4300 ) + nand_do_platform_check $board $1 + return $?; + ;; + routerstation | \ + routerstation-pro | \ + ls-sr71 | \ + pb42 | \ + pb44 | \ + all0305 | \ + eap300v2 | \ + eap7660d | \ + ja76pf | \ + ja76pf2 | \ + jwap003 | \ + wp543 | \ + wpe72) + [ "$magic" != "4349" ] && { + echo "Invalid image. Use *-sysupgrade.bin files on this board" + return 1 + } + + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + return 0 + ;; + wnr2000-v4) + [ "$magic_long" != "32303034" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_pre_upgrade() { + local board=$(ar71xx_board_name) + + case "$board" in + nbg6716 | \ + r6100 | \ + wndr3700v4 | \ + wndr4300 ) + nand_do_upgrade "$1" + ;; + esac +} + +platform_do_upgrade() { + local board=$(ar71xx_board_name) + + case "$board" in + routerstation | \ + routerstation-pro | \ + ls-sr71 | \ + all0305 | \ + eap7660d | \ + pb42 | \ + pb44 | \ + ja76pf | \ + ja76pf2 | \ + jwap003) + platform_do_upgrade_combined "$ARGV" + ;; + wp543|\ + wpe72) + platform_do_upgrade_compex "$ARGV" + ;; + all0258n ) + platform_do_upgrade_allnet "0x9f050000" "$ARGV" + ;; + all0315n ) + platform_do_upgrade_allnet "0x9f080000" "$ARGV" + ;; + eap300v2 |\ + cap4200ag) + platform_do_upgrade_allnet "0xbf0a0000" "$ARGV" + ;; + dir-825-b1 |\ + tew-673gru) + platform_do_upgrade_dir825b "$ARGV" + ;; + mr1750 | \ + mr600 | \ + mr600v2 | \ + mr900 | \ + mr900v2 | \ + om2p | \ + om2pv2 | \ + om2p-hs | \ + om2p-hsv2 | \ + om2p-lc | \ + om5p | \ + om5p-an) + platform_do_upgrade_openmesh "$ARGV" + ;; + unifi-outdoor-plus | \ + uap-pro) + MTD_CONFIG_ARGS="-s 0x180000" + default_do_upgrade "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/ar71xx/base-files/sbin/wget2nand b/target/linux/ar71xx/base-files/sbin/wget2nand new file mode 100755 index 0000000..8175a9e --- /dev/null +++ b/target/linux/ar71xx/base-files/sbin/wget2nand @@ -0,0 +1,85 @@ +#!/bin/sh +# wget2nand +# This script can be used to download a TGZ file from your build system which +# contains the files to be installed on the NAND flash on your RB1xx card. +# The one parameter is the URL of the TGZ file to be downloaded. +# Licence GPL V2 +# Author david.goodenough@linkchoose.co.uk +# Based on cf2nand from RB532 support +. /lib/functions.sh + +wget2nand_dir=/tmp/wget2nand +mnt_kernel=$wget2nand_dir/mnt_kernel +mnt_rootfs=$wget2nand_dir/mnt_rootfs +src_rootfs=$wget2nand_dir/rootfs.tgz +src_kernel=$wget2nand_dir/kernel + +[ -d "$wget2nand_dir" ] && { + echo "$wget2nand_dir already exists" + exit 1 +} + +# need to find the wget server from the command line +url=$1 +[ -z "$url" ] && { + echo "No URL specified for image TGZ" + echo "Usage : $0 URL" + exit 1 +} + +url_kernel=$url/openwrt-ar71xx-mikrotik-vmlinux-lzma.elf +url_rootfs=$url/openwrt-ar71xx-mikrotik-rootfs.tar.gz + +mtd_kernel="$(find_mtd_part 'kernel')" +mtd_rootfs="$(find_mtd_part 'rootfs')" +[ -z "$mtd_kernel" -o -z "$mtd_rootfs" ] && { + echo "Cannot find NAND Flash partitions" + exit 1 +} + +mkdir "$wget2nand_dir" +wget $url_kernel -O "$src_kernel" || { + echo "Unable to download $url_kernel" + exit 1 +} + +wget $url_rootfs -O "$src_rootfs" || { + echo "Unable to download $url_rootfs" + exit 1 +} + +echo "Erasing filesystem..." +mtd erase kernel 2>/dev/null >/dev/null +mtd erase rootfs 2>/dev/null >/dev/null + +echo "Mounting $mtd_rootfs as new root and $mtd_kernel as kernel partition" + +mkdir "$mnt_kernel" +mkdir "$mnt_rootfs" +mount -t yaffs2 "$mtd_kernel" "$mnt_kernel" +mount -t yaffs2 "$mtd_rootfs" "$mnt_rootfs" + +echo "Copying kernel..." +cp $src_kernel $mnt_kernel/kernel || { + echo "Error occured while copying the kernel" + exit 1 +} +chmod +x $mnt_kernel/kernel + +echo "Preparing filesystem..." +( cd "$mnt_rootfs"; tar xvz -f "$src_rootfs" ) + +# make sure everything is written before we unmount the partitions +echo "chmod ugo+x /" > $mnt_rootfs/etc/uci-defaults/set_root_permission +sync +ls $mnt_kernel >/dev/null +ls $mnt_rootfs >/dev/null + +echo "Cleaning up..." +# unmount the partitions and remove the directories into which they were mounted +umount $mnt_kernel +umount $mnt_rootfs +rm -rf $wget2nand_dir + +# all done +echo "Image written, you can now reboot. Remember to change the boot source to Boot from Nand" diff --git a/target/linux/ar71xx/config-4.1 b/target/linux/ar71xx/config-4.1 new file mode 100644 index 0000000..50dc7b2 --- /dev/null +++ b/target/linux/ar71xx/config-4.1 @@ -0,0 +1,354 @@ +CONFIG_AG71XX=y +CONFIG_AG71XX_AR8216_SUPPORT=y +# CONFIG_AG71XX_DEBUG is not set +# CONFIG_AG71XX_DEBUG_FS is not set +CONFIG_AR8216_PHY=y +CONFIG_AR8216_PHY_LEDS=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_AT803X_PHY=y +CONFIG_ATH79=y +CONFIG_ATH79_DEV_AP9X_PCI=y +CONFIG_ATH79_DEV_DSA=y +CONFIG_ATH79_DEV_ETH=y +CONFIG_ATH79_DEV_GPIO_BUTTONS=y +CONFIG_ATH79_DEV_LEDS_GPIO=y +CONFIG_ATH79_DEV_M25P80=y +CONFIG_ATH79_DEV_NFC=y +CONFIG_ATH79_DEV_SPI=y +CONFIG_ATH79_DEV_USB=y +CONFIG_ATH79_DEV_WMAC=y +CONFIG_ATH79_MACH_ALFA_AP96=y +CONFIG_ATH79_MACH_ALFA_NX=y +CONFIG_ATH79_MACH_ALL0258N=y +CONFIG_ATH79_MACH_ALL0315N=y +CONFIG_ATH79_MACH_ANTMINER_S1=y +CONFIG_ATH79_MACH_ANTMINER_S3=y +CONFIG_ATH79_MACH_AP113=y +CONFIG_ATH79_MACH_AP121=y +CONFIG_ATH79_MACH_AP132=y +CONFIG_ATH79_MACH_AP136=y +CONFIG_ATH79_MACH_AP143=y +CONFIG_ATH79_MACH_AP147=y +CONFIG_ATH79_MACH_AP152=y +CONFIG_ATH79_MACH_AP81=y +CONFIG_ATH79_MACH_AP83=y +CONFIG_ATH79_MACH_AP96=y +CONFIG_ATH79_MACH_ARCHER_C7=y +CONFIG_ATH79_MACH_AW_NR580=y +CONFIG_ATH79_MACH_BHU_BXU2000N2_A=y +CONFIG_ATH79_MACH_BSB=y +CONFIG_ATH79_MACH_CAP4200AG=y +CONFIG_ATH79_MACH_CARAMBOLA2=y +CONFIG_ATH79_MACH_CF_E316N_V2=y +CONFIG_ATH79_MACH_CPE510=y +CONFIG_ATH79_MACH_DB120=y +CONFIG_ATH79_MACH_DGL_5500_A1=y +CONFIG_ATH79_MACH_DHP_1565_A1=y +CONFIG_ATH79_MACH_DIR_505_A1=y +CONFIG_ATH79_MACH_DIR_600_A1=y +CONFIG_ATH79_MACH_DIR_615_C1=y +CONFIG_ATH79_MACH_DIR_615_I1=y +CONFIG_ATH79_MACH_DIR_825_B1=y +CONFIG_ATH79_MACH_DIR_825_C1=y +CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y +CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y +CONFIG_ATH79_MACH_DRAGINO2=y +CONFIG_ATH79_MACH_EAP300V2=y +CONFIG_ATH79_MACH_EAP7660D=y +CONFIG_ATH79_MACH_EL_M150=y +CONFIG_ATH79_MACH_EL_MINI=y +CONFIG_ATH79_MACH_EPG5000=y +CONFIG_ATH79_MACH_ESR1750=y +CONFIG_ATH79_MACH_ESR900=y +CONFIG_ATH79_MACH_EW_DORIN=y +CONFIG_ATH79_MACH_F9K1115V2=y +CONFIG_ATH79_MACH_GL_INET=y +CONFIG_ATH79_MACH_GS_OOLITE=y +CONFIG_ATH79_MACH_HIWIFI_HC6361=y +CONFIG_ATH79_MACH_HORNET_UB=y +CONFIG_ATH79_MACH_JA76PF=y +CONFIG_ATH79_MACH_JWAP003=y +CONFIG_ATH79_MACH_MC_MAC1200R=y +CONFIG_ATH79_MACH_MR12=y +CONFIG_ATH79_MACH_MR16=y +CONFIG_ATH79_MACH_MR1750=y +CONFIG_ATH79_MACH_MR600=y +CONFIG_ATH79_MACH_MR900=y +CONFIG_ATH79_MACH_MYNET_N600=y +CONFIG_ATH79_MACH_MYNET_N750=y +CONFIG_ATH79_MACH_MYNET_REXT=y +CONFIG_ATH79_MACH_MZK_W04NU=y +CONFIG_ATH79_MACH_MZK_W300NH=y +CONFIG_ATH79_MACH_NBG460N=y +CONFIG_ATH79_MACH_NBG6716=y +CONFIG_ATH79_MACH_OM2P=y +CONFIG_ATH79_MACH_OM5P=y +CONFIG_ATH79_MACH_ONION_OMEGA=y +CONFIG_ATH79_MACH_PB42=y +CONFIG_ATH79_MACH_PB44=y +CONFIG_ATH79_MACH_PB92=y +CONFIG_ATH79_MACH_QIHOO_C301=y +CONFIG_ATH79_MACH_R6100=y +# CONFIG_ATH79_MACH_RB2011 is not set +# CONFIG_ATH79_MACH_RB4XX is not set +# CONFIG_ATH79_MACH_RB750 is not set +# CONFIG_ATH79_MACH_RB91X is not set +# CONFIG_ATH79_MACH_RB922 is not set +# CONFIG_ATH79_MACH_RB95X is not set +# CONFIG_ATH79_MACH_RBSXTLITE is not set +CONFIG_ATH79_MACH_RW2458N=y +CONFIG_ATH79_MACH_SMART_300=y +CONFIG_ATH79_MACH_TEW_632BRP=y +CONFIG_ATH79_MACH_TEW_673GRU=y +CONFIG_ATH79_MACH_TEW_712BR=y +CONFIG_ATH79_MACH_TEW_732BR=y +CONFIG_ATH79_MACH_TL_MR11U=y +CONFIG_ATH79_MACH_TL_MR13U=y +CONFIG_ATH79_MACH_TL_MR3020=y +CONFIG_ATH79_MACH_TL_MR3X20=y +CONFIG_ATH79_MACH_TL_WA701ND_V2=y +CONFIG_ATH79_MACH_TL_WA7210N_V2=y +CONFIG_ATH79_MACH_TL_WA830RE_V2=y +CONFIG_ATH79_MACH_TL_WA901ND=y +CONFIG_ATH79_MACH_TL_WA901ND_V2=y +CONFIG_ATH79_MACH_TL_WAX50RE=y +CONFIG_ATH79_MACH_TL_WDR3320_V2=y +CONFIG_ATH79_MACH_TL_WDR3500=y +CONFIG_ATH79_MACH_TL_WDR4300=y +CONFIG_ATH79_MACH_TL_WDR6500_V2=y +CONFIG_ATH79_MACH_TL_WR1041N_V2=y +CONFIG_ATH79_MACH_TL_WR1043ND=y +CONFIG_ATH79_MACH_TL_WR1043ND_V2=y +CONFIG_ATH79_MACH_TL_WR2543N=y +CONFIG_ATH79_MACH_TL_WR703N=y +CONFIG_ATH79_MACH_TL_WR720N_V3=y +CONFIG_ATH79_MACH_TL_WR741ND=y +CONFIG_ATH79_MACH_TL_WR741ND_V4=y +CONFIG_ATH79_MACH_TL_WR841N_V1=y +CONFIG_ATH79_MACH_TL_WR841N_V8=y +CONFIG_ATH79_MACH_TL_WR841N_V9=y +CONFIG_ATH79_MACH_TL_WR941ND=y +CONFIG_ATH79_MACH_TUBE2H=y +CONFIG_ATH79_MACH_UBNT=y +CONFIG_ATH79_MACH_UBNT_XM=y +CONFIG_ATH79_MACH_WEIO=y +CONFIG_ATH79_MACH_WHR_HP_G300N=y +CONFIG_ATH79_MACH_WLAE_AG300N=y +CONFIG_ATH79_MACH_WLR8100=y +CONFIG_ATH79_MACH_WNDAP360=y +CONFIG_ATH79_MACH_WNDR3700=y +CONFIG_ATH79_MACH_WNDR4300=y +CONFIG_ATH79_MACH_WNR2000=y +CONFIG_ATH79_MACH_WNR2000_V3=y +CONFIG_ATH79_MACH_WNR2000_V4=y +CONFIG_ATH79_MACH_WNR2200=y +CONFIG_ATH79_MACH_WP543=y +CONFIG_ATH79_MACH_WPE72=y +CONFIG_ATH79_MACH_WPJ344=y +CONFIG_ATH79_MACH_WPJ531=y +CONFIG_ATH79_MACH_WPJ558=y +CONFIG_ATH79_MACH_WRT160NL=y +CONFIG_ATH79_MACH_WRT400N=y +CONFIG_ATH79_MACH_WZR_450HP2=y +CONFIG_ATH79_MACH_WZR_HP_AG300H=y +CONFIG_ATH79_MACH_WZR_HP_G300NH=y +CONFIG_ATH79_MACH_WZR_HP_G300NH2=y +CONFIG_ATH79_MACH_WZR_HP_G450H=y +CONFIG_ATH79_MACH_ZCN_1523H=y +CONFIG_ATH79_NVRAM=y +CONFIG_ATH79_PCI_ATH9K_FIXUP=y +# CONFIG_ATH79_ROUTERBOOT is not set +CONFIG_ATH79_WDT=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +# CONFIG_GPIO_LATCH is not set +CONFIG_GPIO_NXP_74HC153=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_HAS_PCI=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_GPIO=y +CONFIG_IMAGE_CMDLINE_HACK=y +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_SOURCE="../../root" +CONFIG_IP17XX_PHY=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_WNDR3700_USB is not set +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MICREL_PHY=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MACHINE=y +CONFIG_MIPS_SPRAM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CYBERTAN_PARTS=y +CONFIG_MTD_M25P80=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_MYLOADER_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_LZMA_FW=y +CONFIG_MTD_SPLIT_SEAMA_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_TPLINK_PARTS=y +CONFIG_MYLOADER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6060=y +CONFIG_NET_DSA_MV88E6063=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_AR724X=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8366_SMI=y +CONFIG_RTL8367_PHY=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_AR933X=y +CONFIG_SERIAL_AR933X_CONSOLE=y +CONFIG_SERIAL_AR933X_NR_UARTS=2 +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SOC_AR71XX=y +CONFIG_SOC_AR724X=y +CONFIG_SOC_AR913X=y +CONFIG_SOC_AR933X=y +CONFIG_SOC_AR934X=y +CONFIG_SOC_QCA953X=y +CONFIG_SOC_QCA955X=y +# CONFIG_SOC_QCA956X is not set +CONFIG_SPI=y +CONFIG_SPI_AP83=y +CONFIG_SPI_ATH79=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_VSC7385 is not set +CONFIG_SRCU=y +CONFIG_SWCONFIG=y +CONFIG_SWCONFIG_LEDS=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c new file mode 100644 index 0000000..d382453 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c @@ -0,0 +1,159 @@ +/* + * Atheros AP9X reference board PCI initialization + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "pci-ath9k-fixup.h" +#include "pci.h" + +static struct ath9k_platform_data ap9x_wmac0_data = { + .led_pin = -1, +}; +static struct ath9k_platform_data ap9x_wmac1_data = { + .led_pin = -1, +}; +static char ap9x_wmac0_mac[6]; +static char ap9x_wmac1_mac[6]; + +__init void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.led_pin = pin; + break; + case 1: + ap9x_wmac1_data.led_pin = pin; + break; + } +} + +__init struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac) +{ + switch (wmac) { + case 0: + return &ap9x_wmac0_data; + + case 1: + return &ap9x_wmac1_data; + } + + return NULL; +} + +__init void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.gpio_mask = mask; + ap9x_wmac0_data.gpio_val = val; + break; + case 1: + ap9x_wmac1_data.gpio_mask = mask; + ap9x_wmac1_data.gpio_val = val; + break; + } +} + +__init void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds, + int num_leds) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.leds = leds; + ap9x_wmac0_data.num_leds = num_leds; + break; + case 1: + ap9x_wmac1_data.leds = leds; + ap9x_wmac1_data.num_leds = num_leds; + break; + } +} + +static int ap91_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 0: + dev->dev.platform_data = &ap9x_wmac0_data; + break; + } + + return 0; +} + +__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr) +{ + if (cal_data) + memcpy(ap9x_wmac0_data.eeprom_data, cal_data, + sizeof(ap9x_wmac0_data.eeprom_data)); + + if (mac_addr) { + memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac)); + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac; + } + + ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init); + ath79_register_pci(); + + pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data); +} + +__init void ap91_pci_init_simple(void) +{ + ap91_pci_init(NULL, NULL); + ap9x_wmac0_data.eeprom_name = "pci_wmac0.eeprom"; +} + +static int ap94_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 17: + dev->dev.platform_data = &ap9x_wmac0_data; + break; + + case 18: + dev->dev.platform_data = &ap9x_wmac1_data; + break; + } + + return 0; +} + +__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ + if (cal_data0) + memcpy(ap9x_wmac0_data.eeprom_data, cal_data0, + sizeof(ap9x_wmac0_data.eeprom_data)); + + if (cal_data1) + memcpy(ap9x_wmac1_data.eeprom_data, cal_data1, + sizeof(ap9x_wmac1_data.eeprom_data)); + + if (mac_addr0) { + memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac)); + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac; + } + + if (mac_addr1) { + memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac)); + ap9x_wmac1_data.macaddr = ap9x_wmac1_mac; + } + + ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init); + ath79_register_pci(); + + pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data); + pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h new file mode 100644 index 0000000..ad288cb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h @@ -0,0 +1,48 @@ +/* + * Atheros AP9X reference board PCI initialization + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_AP9X_PCI_H +#define _ATH79_DEV_AP9X_PCI_H + +struct gpio_led; +struct ath9k_platform_data; + +#if defined(CONFIG_ATH79_DEV_AP9X_PCI) +void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin); +void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val); +void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds, + int num_leds); +struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac); + +void ap91_pci_init(u8 *cal_data, u8 *mac_addr); +void ap91_pci_init_simple(void); +void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1); + +#else +static inline void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) {} +static inline void ap9x_pci_setup_wmac_gpio(unsigned wmac, + u32 mask, u32 val) {} +static inline void ap9x_pci_setup_wmac_leds(unsigned wmac, + struct gpio_led *leds, + int num_leds) {} +static inline struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac) +{ + return NULL; +} + +static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) {} +static inline void ap91_pci_init_simple(void) {} +static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) {} +#endif + +#endif /* _ATH79_DEV_AP9X_PCI_H */ + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c new file mode 100644 index 0000000..a9bb334 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c @@ -0,0 +1,41 @@ +/* + * Atheros AR71xx DSA switch device support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-dsa.h" + +static struct platform_device ar71xx_dsa_switch_device = { + .name = "dsa", + .id = 0, +}; + +void __init ath79_register_dsa(struct device *netdev, + struct device *miidev, + struct dsa_platform_data *d) +{ + int i; + + d->netdev = netdev; + for (i = 0; i < d->nr_chips; i++) +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + d->chip[i].mii_bus = miidev; +#else + d->chip[i].host_dev = miidev; +#endif + + ar71xx_dsa_switch_device.dev.platform_data = d; + platform_device_register(&ar71xx_dsa_switch_device); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h new file mode 100644 index 0000000..3730202 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71xx DSA switch device support + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_DSA_H +#define _ATH79_DEV_DSA_H + +#include + +void ath79_register_dsa(struct device *netdev, + struct device *miidev, + struct dsa_platform_data *d); + +#endif /* _ATH79_DEV_DSA_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c new file mode 100644 index 0000000..31d2438 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -0,0 +1,1254 @@ +/* + * Atheros AR71xx SoC platform devices + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" + +unsigned char ath79_mac_base[ETH_ALEN] __initdata; + +static struct resource ath79_mdio0_resources[] = { + { + .name = "mdio_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE0_BASE, + .end = AR71XX_GE0_BASE + 0x200 - 1, + } +}; + +struct ag71xx_mdio_platform_data ath79_mdio0_data; + +struct platform_device ath79_mdio0_device = { + .name = "ag71xx-mdio", + .id = 0, + .resource = ath79_mdio0_resources, + .num_resources = ARRAY_SIZE(ath79_mdio0_resources), + .dev = { + .platform_data = &ath79_mdio0_data, + }, +}; + +static struct resource ath79_mdio1_resources[] = { + { + .name = "mdio_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE1_BASE, + .end = AR71XX_GE1_BASE + 0x200 - 1, + } +}; + +struct ag71xx_mdio_platform_data ath79_mdio1_data; + +struct platform_device ath79_mdio1_device = { + .name = "ag71xx-mdio", + .id = 1, + .resource = ath79_mdio1_resources, + .num_resources = ARRAY_SIZE(ath79_mdio1_resources), + .dev = { + .platform_data = &ath79_mdio1_data, + }, +}; + +static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) +{ + void __iomem *base; + u32 t; + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + t = __raw_readl(base + cfg_reg); + t &= ~(3 << shift); + t |= (2 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + __raw_writel(pll_val, base + pll_reg); + + t |= (3 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + t &= ~(3 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", + (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); + + iounmap(base); +} + +static void __init ath79_mii_ctrl_set_if(unsigned int reg, + unsigned int mii_if) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); + + t = __raw_readl(base + reg); + t &= ~(AR71XX_MII_CTRL_IF_MASK); + t |= (mii_if & AR71XX_MII_CTRL_IF_MASK); + __raw_writel(t, base + reg); + + iounmap(base); +} + +static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed) +{ + void __iomem *base; + unsigned int mii_speed; + u32 t; + + switch (speed) { + case SPEED_10: + mii_speed = AR71XX_MII_CTRL_SPEED_10; + break; + case SPEED_100: + mii_speed = AR71XX_MII_CTRL_SPEED_100; + break; + case SPEED_1000: + mii_speed = AR71XX_MII_CTRL_SPEED_1000; + break; + default: + BUG(); + } + + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); + + t = __raw_readl(base + reg); + t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT); + t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT; + __raw_writel(t, base + reg); + + iounmap(base); +} + +static unsigned long ar934x_get_mdio_ref_clock(void) +{ + void __iomem *base; + unsigned long ret; + u32 t; + + base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + ret = 0; + t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) { + ret = 100 * 1000 * 1000; + } else { + struct clk *clk; + + clk = clk_get(NULL, "ref"); + if (!IS_ERR(clk)) + ret = clk_get_rate(clk); + } + + iounmap(base); + + return ret; +} + +void __init ath79_register_mdio(unsigned int id, u32 phy_mask) +{ + struct platform_device *mdio_dev; + struct ag71xx_mdio_platform_data *mdio_data; + unsigned int max_id; + + if (ath79_soc == ATH79_SOC_AR9341 || + ath79_soc == ATH79_SOC_AR9342 || + ath79_soc == ATH79_SOC_AR9344 || + ath79_soc == ATH79_SOC_QCA9556 || + ath79_soc == ATH79_SOC_QCA9558) + max_id = 1; + else + max_id = 0; + + if (id > max_id) { + printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id); + return; + } + + switch (ath79_soc) { + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + mdio_dev = &ath79_mdio1_device; + mdio_data = &ath79_mdio1_data; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + if (id == 0) { + mdio_dev = &ath79_mdio0_device; + mdio_data = &ath79_mdio0_data; + } else { + mdio_dev = &ath79_mdio1_device; + mdio_data = &ath79_mdio1_data; + } + break; + + case ATH79_SOC_AR7242: + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, + AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000, + AR71XX_ETH0_PLL_SHIFT); + /* fall through */ + default: + mdio_dev = &ath79_mdio0_device; + mdio_data = &ath79_mdio0_data; + break; + } + + mdio_data->phy_mask = phy_mask; + + switch (ath79_soc) { + case ATH79_SOC_AR7240: + mdio_data->is_ar7240 = 1; + /* fall through */ + case ATH79_SOC_AR7241: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_AR9330: + mdio_data->is_ar9330 = 1; + /* fall through */ + case ATH79_SOC_AR9331: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + if (id == 1) { + mdio_data->builtin_switch = 1; + mdio_data->ref_clock = ar934x_get_mdio_ref_clock(); + mdio_data->mdio_clock = 6250000; + } + mdio_data->is_ar934x = 1; + break; + + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + mdio_data->is_ar934x = 1; + break; + + default: + break; + } + + platform_device_register(mdio_dev); +} + +struct ath79_eth_pll_data ath79_eth0_pll_data; +struct ath79_eth_pll_data ath79_eth1_pll_data; + +static u32 ath79_get_eth_pll(unsigned int mac, int speed) +{ + struct ath79_eth_pll_data *pll_data; + u32 pll_val; + + switch (mac) { + case 0: + pll_data = &ath79_eth0_pll_data; + break; + case 1: + pll_data = &ath79_eth1_pll_data; + break; + default: + BUG(); + } + + switch (speed) { + case SPEED_10: + pll_val = pll_data->pll_10; + break; + case SPEED_100: + pll_val = pll_data->pll_100; + break; + case SPEED_1000: + pll_val = pll_data->pll_1000; + break; + default: + BUG(); + } + + return pll_val; +} + +static void ath79_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, + val, AR71XX_ETH0_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed); +} + +static void ath79_set_speed_ge1(int speed) +{ + u32 val = ath79_get_eth_pll(1, speed); + + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, + val, AR71XX_ETH1_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed); +} + +static void ar7242_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + void __iomem *base; + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK); + iounmap(base); +} + +static void ar91xx_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK, + val, AR913X_ETH0_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed); +} + +static void ar91xx_set_speed_ge1(int speed) +{ + u32 val = ath79_get_eth_pll(1, speed); + + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK, + val, AR913X_ETH1_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed); +} + +static void ar934x_set_speed_ge0(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG); + iounmap(base); +} + +static void qca955x_set_speed_xmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG); + iounmap(base); +} + +static void qca955x_set_speed_sgmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(1, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); + iounmap(base); +} + +static void ath79_set_speed_dummy(int speed) +{ +} + +static void ath79_ddr_no_flush(void) +{ +} + +static void ath79_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0); +} + +static void ath79_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1); +} + +static void ar724x_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0); +} + +static void ar724x_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1); +} + +static void ar91xx_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0); +} + +static void ar91xx_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1); +} + +static void ar933x_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0); +} + +static void ar933x_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1); +} + +static struct resource ath79_eth0_resources[] = { + { + .name = "mac_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE0_BASE, + .end = AR71XX_GE0_BASE + 0x200 - 1, + }, { + .name = "mac_irq", + .flags = IORESOURCE_IRQ, + .start = ATH79_CPU_IRQ(4), + .end = ATH79_CPU_IRQ(4), + }, +}; + +struct ag71xx_platform_data ath79_eth0_data = { + .reset_bit = AR71XX_RESET_GE0_MAC, +}; + +struct platform_device ath79_eth0_device = { + .name = "ag71xx", + .id = 0, + .resource = ath79_eth0_resources, + .num_resources = ARRAY_SIZE(ath79_eth0_resources), + .dev = { + .platform_data = &ath79_eth0_data, + }, +}; + +static struct resource ath79_eth1_resources[] = { + { + .name = "mac_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE1_BASE, + .end = AR71XX_GE1_BASE + 0x200 - 1, + }, { + .name = "mac_irq", + .flags = IORESOURCE_IRQ, + .start = ATH79_CPU_IRQ(5), + .end = ATH79_CPU_IRQ(5), + }, +}; + +struct ag71xx_platform_data ath79_eth1_data = { + .reset_bit = AR71XX_RESET_GE1_MAC, +}; + +struct platform_device ath79_eth1_device = { + .name = "ag71xx", + .id = 1, + .resource = ath79_eth1_resources, + .num_resources = ARRAY_SIZE(ath79_eth1_resources), + .dev = { + .platform_data = &ath79_eth1_data, + }, +}; + +struct ag71xx_switch_platform_data ath79_switch_data; + +#define AR71XX_PLL_VAL_1000 0x00110000 +#define AR71XX_PLL_VAL_100 0x00001099 +#define AR71XX_PLL_VAL_10 0x00991099 + +#define AR724X_PLL_VAL_1000 0x00110000 +#define AR724X_PLL_VAL_100 0x00001099 +#define AR724X_PLL_VAL_10 0x00991099 + +#define AR7242_PLL_VAL_1000 0x16000000 +#define AR7242_PLL_VAL_100 0x00000101 +#define AR7242_PLL_VAL_10 0x00001616 + +#define AR913X_PLL_VAL_1000 0x1a000000 +#define AR913X_PLL_VAL_100 0x13000a44 +#define AR913X_PLL_VAL_10 0x00441099 + +#define AR933X_PLL_VAL_1000 0x00110000 +#define AR933X_PLL_VAL_100 0x00001099 +#define AR933X_PLL_VAL_10 0x00991099 + +#define AR934X_PLL_VAL_1000 0x16000000 +#define AR934X_PLL_VAL_100 0x00000101 +#define AR934X_PLL_VAL_10 0x00001616 + +static void __init ath79_init_eth_pll_data(unsigned int id) +{ + struct ath79_eth_pll_data *pll_data; + u32 pll_10, pll_100, pll_1000; + + switch (id) { + case 0: + pll_data = &ath79_eth0_pll_data; + break; + case 1: + pll_data = &ath79_eth1_pll_data; + break; + default: + BUG(); + } + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + pll_10 = AR71XX_PLL_VAL_10; + pll_100 = AR71XX_PLL_VAL_100; + pll_1000 = AR71XX_PLL_VAL_1000; + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + pll_10 = AR724X_PLL_VAL_10; + pll_100 = AR724X_PLL_VAL_100; + pll_1000 = AR724X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR7242: + pll_10 = AR7242_PLL_VAL_10; + pll_100 = AR7242_PLL_VAL_100; + pll_1000 = AR7242_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + pll_10 = AR913X_PLL_VAL_10; + pll_100 = AR913X_PLL_VAL_100; + pll_1000 = AR913X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + pll_10 = AR933X_PLL_VAL_10; + pll_100 = AR933X_PLL_VAL_100; + pll_1000 = AR933X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + pll_10 = AR934X_PLL_VAL_10; + pll_100 = AR934X_PLL_VAL_100; + pll_1000 = AR934X_PLL_VAL_1000; + break; + + default: + BUG(); + } + + if (!pll_data->pll_10) + pll_data->pll_10 = pll_10; + + if (!pll_data->pll_100) + pll_data->pll_100 = pll_100; + + if (!pll_data->pll_1000) + pll_data->pll_1000 = pll_1000; +} + +static int __init ath79_setup_phy_if_mode(unsigned int id, + struct ag71xx_platform_data *pdata) +{ + unsigned int mii_if; + + switch (id) { + case 0: + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + mii_if = AR71XX_MII0_CTRL_IF_MII; + break; + case PHY_INTERFACE_MODE_GMII: + mii_if = AR71XX_MII0_CTRL_IF_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + mii_if = AR71XX_MII0_CTRL_IF_RGMII; + break; + case PHY_INTERFACE_MODE_RMII: + mii_if = AR71XX_MII0_CTRL_IF_RMII; + break; + default: + return -EINVAL; + } + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if); + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_TP9343: + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; + break; + + case ATH79_SOC_AR7242: + /* FIXME */ + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RMII: + break; + default: + return -EINVAL; + } + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + break; + default: + return -EINVAL; + } + break; + + case ATH79_SOC_QCA9561: + if (!pdata->phy_if_mode) + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; + break; + + default: + BUG(); + } + break; + case 1: + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_RMII: + mii_if = AR71XX_MII1_CTRL_IF_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + mii_if = AR71XX_MII1_CTRL_IF_RGMII; + break; + default: + return -EINVAL; + } + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if); + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; + break; + + case ATH79_SOC_AR7242: + /* FIXME */ + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + break; + default: + return -EINVAL; + } + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + break; + default: + return -EINVAL; + } + break; + + default: + BUG(); + } + break; + } + + return 0; +} + +void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE); + + t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG); + t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP); + if (mac) + t |= AR933X_ETH_CFG_SW_PHY_SWAP; + if (mdio) + t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP; + __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_ar934x_eth_cfg(u32 mask) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + t |= mask; + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + /* flush write */ + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, + unsigned int rxdv) +{ + void __iomem *base; + u32 t; + + rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK; + rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT | + AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT); + + t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT | + rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT); + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + /* flush write */ + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_qca955x_eth_cfg(u32 mask) +{ + void __iomem *base; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); + + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); + + t |= mask; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static int ath79_eth_instance __initdata; +void __init ath79_register_eth(unsigned int id) +{ + struct platform_device *pdev; + struct ag71xx_platform_data *pdata; + int err; + + if (id > 1) { + printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); + return; + } + + ath79_init_eth_pll_data(id); + + if (id == 0) + pdev = &ath79_eth0_device; + else + pdev = &ath79_eth1_device; + + pdata = pdev->dev.platform_data; + + pdata->max_frame_len = 1540; + pdata->desc_pktlen_mask = 0xfff; + + err = ath79_setup_phy_if_mode(id, pdata); + if (err) { + printk(KERN_ERR + "ar71xx: invalid PHY interface mode for GE%u\n", id); + return; + } + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + if (id == 0) { + pdata->ddr_flush = ath79_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->ddr_flush = ath79_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_ge1; + } + break; + + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + if (id == 0) { + pdata->ddr_flush = ath79_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->ddr_flush = ath79_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_ge1; + } + pdata->has_gbit = 1; + break; + + case ATH79_SOC_AR7242: + if (id == 0) { + pdata->reset_bit |= AR724X_RESET_GE0_MDIO | + AR71XX_RESET_GE0_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge0; + pdata->set_speed = ar7242_set_speed_ge0; + } else { + pdata->reset_bit |= AR724X_RESET_GE1_MDIO | + AR71XX_RESET_GE1_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + } + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR7241: + if (id == 0) + pdata->reset_bit |= AR724X_RESET_GE0_MDIO; + else + pdata->reset_bit |= AR724X_RESET_GE1_MDIO; + /* fall through */ + case ATH79_SOC_AR7240: + if (id == 0) { + pdata->reset_bit |= AR71XX_RESET_GE0_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit |= AR71XX_RESET_GE1_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + if (ath79_soc == ATH79_SOC_AR7240) + pdata->is_ar7240 = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR9130: + if (id == 0) { + pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->set_speed = ar91xx_set_speed_ge0; + } else { + pdata->ddr_flush = ar91xx_ddr_flush_ge1; + pdata->set_speed = ar91xx_set_speed_ge1; + } + pdata->is_ar91xx = 1; + break; + + case ATH79_SOC_AR9132: + if (id == 0) { + pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->set_speed = ar91xx_set_speed_ge0; + } else { + pdata->ddr_flush = ar91xx_ddr_flush_ge1; + pdata->set_speed = ar91xx_set_speed_ge1; + } + pdata->is_ar91xx = 1; + pdata->has_gbit = 1; + break; + + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->ddr_flush = ar933x_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->ddr_flush = ar933x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->has_gbit = 1; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + if (id == 0) { + pdata->reset_bit = AR934X_RESET_GE0_MAC | + AR934X_RESET_GE0_MDIO; + pdata->set_speed = ar934x_set_speed_ge0; + } else { + pdata->reset_bit = AR934X_RESET_GE1_MAC | + AR934X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->switch_data = &ath79_switch_data; + + /* reset the built-in switch */ + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH); + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + pdata->max_frame_len = SZ_16K - 1; + pdata->desc_pktlen_mask = SZ_16K - 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + if (!pdata->phy_mask) + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + if (id == 0) { + pdata->reset_bit = QCA955X_RESET_GE0_MAC | + QCA955X_RESET_GE0_MDIO; + pdata->set_speed = qca955x_set_speed_xmii; + } else { + pdata->reset_bit = QCA955X_RESET_GE1_MAC | + QCA955X_RESET_GE1_MDIO; + pdata->set_speed = qca955x_set_speed_sgmii; + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + /* + * Limit the maximum frame length to 4095 bytes. + * Although the documentation says that the hardware + * limit is 16383 bytes but that does not work in + * practice. It seems that the hardware only updates + * the lowest 12 bits of the packet length field + * in the RX descriptor. + */ + pdata->max_frame_len = SZ_4K - 1; + pdata->desc_pktlen_mask = SZ_16K - 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + default: + BUG(); + } + + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + if (!pdata->has_gbit) { + printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", + id); + return; + } + /* fallthrough */ + default: + break; + } + + if (!is_valid_ether_addr(pdata->mac_addr)) { + random_ether_addr(pdata->mac_addr); + printk(KERN_DEBUG + "ar71xx: using random MAC address for eth%d\n", + ath79_eth_instance); + } + + if (pdata->mii_bus_dev == NULL) { + switch (ath79_soc) { + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + if (id == 0) + pdata->mii_bus_dev = &ath79_mdio0_device.dev; + else + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + /* don't assign any MDIO device by default */ + break; + + default: + pdata->mii_bus_dev = &ath79_mdio0_device.dev; + break; + } + } + + /* Reset the device */ + ath79_device_reset_set(pdata->reset_bit); + msleep(100); + + ath79_device_reset_clear(pdata->reset_bit); + msleep(100); + + platform_device_register(pdev); + ath79_eth_instance++; +} + +void __init ath79_set_mac_base(unsigned char *mac) +{ + memcpy(ath79_mac_base, mac, ETH_ALEN); +} + +void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac) +{ + int t; + + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != ETH_ALEN) + t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != ETH_ALEN || !is_valid_ether_addr(mac)) { + memset(mac, 0, ETH_ALEN); + printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n", + mac_str); + } +} + +static void __init ath79_set_mac_base_ascii(char *str) +{ + u8 mac[ETH_ALEN]; + + ath79_parse_ascii_mac(str, mac); + ath79_set_mac_base(mac); +} + +static int __init ath79_ethaddr_setup(char *str) +{ + ath79_set_mac_base_ascii(str); + return 1; +} +__setup("ethaddr=", ath79_ethaddr_setup); + +static int __init ath79_kmac_setup(char *str) +{ + ath79_set_mac_base_ascii(str); + return 1; +} +__setup("kmac=", ath79_kmac_setup); + +void __init ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset) +{ + int t; + + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { + memset(dst, '\0', ETH_ALEN); + return; + } + + t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]); + t += offset; + + dst[0] = src[0]; + dst[1] = src[1]; + dst[2] = src[2]; + dst[3] = (t >> 16) & 0xff; + dst[4] = (t >> 8) & 0xff; + dst[5] = t & 0xff; +} + +void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src) +{ + int i; + + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { + memset(dst, '\0', ETH_ALEN); + return; + } + + for (i = 0; i < ETH_ALEN; i++) + dst[i] = src[i]; + dst[0] |= 0x02; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h new file mode 100644 index 0000000..5a226e4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h @@ -0,0 +1,53 @@ +/* + * Atheros AR71xx SoC device definitions + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_ETH_H +#define _ATH79_DEV_ETH_H + +#include + +struct platform_device; + +extern unsigned char ath79_mac_base[] __initdata; +void ath79_parse_ascii_mac(char *mac_str, u8 *mac); +void ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset); +void ath79_init_local_mac(unsigned char *dst, const unsigned char *src); + +struct ath79_eth_pll_data { + u32 pll_10; + u32 pll_100; + u32 pll_1000; +}; + +extern struct ath79_eth_pll_data ath79_eth0_pll_data; +extern struct ath79_eth_pll_data ath79_eth1_pll_data; + +extern struct ag71xx_platform_data ath79_eth0_data; +extern struct ag71xx_platform_data ath79_eth1_data; +extern struct platform_device ath79_eth0_device; +extern struct platform_device ath79_eth1_device; +void ath79_register_eth(unsigned int id); + +extern struct ag71xx_switch_platform_data ath79_switch_data; + +extern struct ag71xx_mdio_platform_data ath79_mdio0_data; +extern struct ag71xx_mdio_platform_data ath79_mdio1_data; +extern struct platform_device ath79_mdio0_device; +extern struct platform_device ath79_mdio1_device; +void ath79_register_mdio(unsigned int id, u32 phy_mask); + +void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio); +void ath79_setup_ar934x_eth_cfg(u32 mask); +void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv); +void ath79_setup_qca955x_eth_cfg(u32 mask); + +#endif /* _ATH79_DEV_ETH_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c new file mode 100644 index 0000000..9323b31 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "dev-spi.h" +#include "dev-m25p80.h" + +static struct ath79_spi_controller_data ath79_spi0_cdata = +{ + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, +}; + +static struct ath79_spi_controller_data ath79_spi1_cdata = +{ + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 1, +}; + +static struct spi_board_info ath79_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ath79_spi0_cdata, + }, + { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ath79_spi1_cdata, + } +}; + +static struct ath79_spi_platform_data ath79_spi_data; + +void __init ath79_register_m25p80(struct flash_platform_data *pdata) +{ + ath79_spi_data.bus_num = 0; + ath79_spi_data.num_chipselect = 1; + ath79_spi0_cdata.is_flash = true; + ath79_spi_info[0].platform_data = pdata; + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1); +} + +static struct flash_platform_data *multi_pdata; + +static struct mtd_info *concat_devs[2] = { NULL, NULL }; +static struct work_struct mtd_concat_work; + +static void mtd_concat_add_work(struct work_struct *work) +{ + struct mtd_info *mtd; + + mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash"); + + mtd_device_register(mtd, multi_pdata->parts, multi_pdata->nr_parts); +} + +static void mtd_concat_add(struct mtd_info *mtd) +{ + static bool registered = false; + + if (registered) + return; + + if (!strcmp(mtd->name, "spi0.0")) + concat_devs[0] = mtd; + else if (!strcmp(mtd->name, "spi0.1")) + concat_devs[1] = mtd; + else + return; + + if (!concat_devs[0] || !concat_devs[1]) + return; + + registered = true; + INIT_WORK(&mtd_concat_work, mtd_concat_add_work); + schedule_work(&mtd_concat_work); +} + +static void mtd_concat_remove(struct mtd_info *mtd) +{ +} + +static void add_mtd_concat_notifier(void) +{ + static struct mtd_notifier not = { + .add = mtd_concat_add, + .remove = mtd_concat_remove, + }; + + register_mtd_user(¬); +} + + +void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata) +{ + multi_pdata = pdata; + add_mtd_concat_notifier(); + ath79_spi_data.bus_num = 0; + ath79_spi_data.num_chipselect = 2; + ath79_spi0_cdata.is_flash = true; + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 2); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h new file mode 100644 index 0000000..637b41a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_M25P80_H +#define _ATH79_DEV_M25P80_H + +#include + +void ath79_register_m25p80(struct flash_platform_data *pdata) __init; +void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init; + +#endif /* _ATH79_DEV_M25P80_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c new file mode 100644 index 0000000..9b5256e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c @@ -0,0 +1,141 @@ +/* + * Atheros AR934X SoCs built-in NAND flash controller support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "dev-nfc.h" + +static struct resource ath79_nfc_resources[2]; +static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32); +static struct ar934x_nfc_platform_data ath79_nfc_data; + +static struct platform_device ath79_nfc_device = { + .name = AR934X_NFC_DRIVER_NAME, + .id = -1, + .resource = ath79_nfc_resources, + .num_resources = ARRAY_SIZE(ath79_nfc_resources), + .dev = { + .dma_mask = &ar934x_nfc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_nfc_data, + }, +}; + +static void __init ath79_nfc_init_resource(struct resource res[2], + unsigned long base, + unsigned long size, + int irq) +{ + memset(res, 0, sizeof(struct resource) * 2); + + res[0].flags = IORESOURCE_MEM; + res[0].start = base; + res[0].end = base + size - 1; + + res[1].flags = IORESOURCE_IRQ; + res[1].start = irq; + res[1].end = irq; +} + +static void ar934x_nfc_hw_reset(bool active) +{ + if (active) { + ath79_device_reset_set(AR934X_RESET_NANDF); + udelay(100); + + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG); + udelay(250); + } else { + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG); + udelay(250); + + ath79_device_reset_clear(AR934X_RESET_NANDF); + udelay(100); + } +} + +static void ar934x_nfc_setup(void) +{ + ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset; + + ath79_nfc_init_resource(ath79_nfc_resources, + AR934X_NFC_BASE, AR934X_NFC_SIZE, + ATH79_MISC_IRQ(21)); + + platform_device_register(&ath79_nfc_device); +} + +static void qca955x_nfc_hw_reset(bool active) +{ + if (active) { + ath79_device_reset_set(QCA955X_RESET_NANDF); + udelay(250); + } else { + ath79_device_reset_clear(QCA955X_RESET_NANDF); + udelay(100); + } +} + +static void qca955x_nfc_setup(void) +{ + ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset; + + ath79_nfc_init_resource(ath79_nfc_resources, + QCA955X_NFC_BASE, QCA955X_NFC_SIZE, + ATH79_MISC_IRQ(21)); + + platform_device_register(&ath79_nfc_device); +} + +void __init ath79_nfc_set_select_chip(void (*f)(int chip_no)) +{ + ath79_nfc_data.select_chip = f; +} + +void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) +{ + ath79_nfc_data.scan_fixup = f; +} + +void __init ath79_nfc_set_swap_dma(bool enable) +{ + ath79_nfc_data.swap_dma = enable; +} + +void __init ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode) +{ + ath79_nfc_data.ecc_mode = mode; +} + +void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts) +{ + ath79_nfc_data.parts = parts; + ath79_nfc_data.nr_parts = nr_parts; +} + +void __init ath79_register_nfc(void) +{ + if (soc_is_ar934x()) + ar934x_nfc_setup(); + else if (soc_is_qca955x()) + qca955x_nfc_setup(); + else + BUG(); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h new file mode 100644 index 0000000..3a1c88f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h @@ -0,0 +1,34 @@ +/* + * Atheros AR934X SoCs built-in NAND Flash Controller support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_NFC_H +#define _ATH79_DEV_NFC_H + +struct mtd_partition; +enum ar934x_nfc_ecc_mode; + +#ifdef CONFIG_ATH79_DEV_NFC +void ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts); +void ath79_nfc_set_select_chip(void (*f)(int chip_no)); +void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)); +void ath79_nfc_set_swap_dma(bool enable); +void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode); +void ath79_register_nfc(void); +#else +static inline void ath79_nfc_set_parts(struct mtd_partition *parts, + int nr_parts) {} +static inline void ath79_nfc_set_select_chip(void (*f)(int chip_no)) {} +static inline void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) {} +static inline void ath79_nfc_set_swap_dma(bool enable) {} +static inline void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode) {} +static inline void ath79_register_nfc(void) {} +#endif + +#endif /* _ATH79_DEV_NFC_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c new file mode 100644 index 0000000..f7cd6ae --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c @@ -0,0 +1,151 @@ +/* + * ALFA Network AP96 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define ALFA_AP96_GPIO_PCIE_RESET 2 +#define ALFA_AP96_GPIO_SIM_DETECT 3 +#define ALFA_AP96_GPIO_MICROSD_CD 4 +#define ALFA_AP96_GPIO_PCIE_W_DISABLE 5 + +#define ALFA_AP96_GPIO_BUTTON_RESET 11 + +#define ALFA_AP96_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP96_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALFA_AP96_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static struct mmc_spi_platform_data alfa_ap96_mmc_data = { + .flags = MMC_SPI_USE_CD_GPIO, + .cd_gpio = ALFA_AP96_GPIO_MICROSD_CD, + .cd_debounce = 1, + .caps = MMC_CAP_NEEDS_POLL, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct ath79_spi_controller_data ap96_spi0_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, + .is_flash = true, +}; + +static struct ath79_spi_controller_data ap96_spi1_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 1, +}; + +static struct ath79_spi_controller_data ap96_spi2_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 2, +}; + +static struct spi_board_info alfa_ap96_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ap96_spi0_cdata + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "mmc_spi", + .platform_data = &alfa_ap96_mmc_data, + .controller_data = &ap96_spi1_cdata + }, { + .bus_num = 0, + .chip_select = 2, + .max_speed_hz = 6250000, + .modalias = "rtc-pcf2123", + .controller_data = &ap96_spi2_cdata + }, +}; + +static struct ath79_spi_platform_data alfa_ap96_spi_data = { + .bus_num = 0, + .num_chipselect = 3, +}; + +static void __init alfa_ap96_gpio_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD"); + gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD); + gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset"); + gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1); + gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable"); + gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1); +} + +#define ALFA_AP96_WAN_PHYMASK BIT(4) +#define ALFA_AP96_LAN_PHYMASK BIT(5) +#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK) + +static void __init alfa_ap96_init(void) +{ + alfa_ap96_gpio_setup(); + + ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK; + ath79_eth1_pll_data.pll_1000 = 0x110000; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK; + ath79_eth1_pll_data.pll_1000 = 0x110000; + + ath79_register_eth(1); + + ath79_register_pci(); + ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info, + ARRAY_SIZE(alfa_ap96_spi_info)); + + ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL, + ARRAY_SIZE(alfa_ap96_gpio_keys), + alfa_ap96_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96", + alfa_ap96_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c new file mode 100644 index 0000000..a515f4f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c @@ -0,0 +1,113 @@ +/* + * ALFA Network N2/N5 board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define ALFA_NX_GPIO_LED_2 17 +#define ALFA_NX_GPIO_LED_3 16 +#define ALFA_NX_GPIO_LED_5 12 +#define ALFA_NX_GPIO_LED_6 8 +#define ALFA_NX_GPIO_LED_7 6 +#define ALFA_NX_GPIO_LED_8 7 + +#define ALFA_NX_GPIO_BTN_RESET 11 + +#define ALFA_NX_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL) + +#define ALFA_NX_MAC0_OFFSET 0 +#define ALFA_NX_MAC1_OFFSET 6 +#define ALFA_NX_CALDATA_OFFSET 0x1000 + +static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALFA_NX_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct gpio_led alfa_nx_leds_gpio[] __initdata = { + { + .name = "alfa:green:led_2", + .gpio = ALFA_NX_GPIO_LED_2, + .active_low = 1, + }, { + .name = "alfa:green:led_3", + .gpio = ALFA_NX_GPIO_LED_3, + .active_low = 1, + }, { + .name = "alfa:red:led_5", + .gpio = ALFA_NX_GPIO_LED_5, + .active_low = 1, + }, { + .name = "alfa:amber:led_6", + .gpio = ALFA_NX_GPIO_LED_6, + .active_low = 1, + }, { + .name = "alfa:green:led_7", + .gpio = ALFA_NX_GPIO_LED_7, + .active_low = 1, + }, { + .name = "alfa:green:led_8", + .gpio = ALFA_NX_GPIO_LED_8, + .active_low = 1, + } +}; + +static void __init alfa_nx_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio), + alfa_nx_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(alfa_nx_gpio_keys), + alfa_nx_gpio_keys); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + ALFA_NX_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, + art + ALFA_NX_MAC1_OFFSET, 0); + + /* WAN port */ + ath79_register_eth(0); + /* LAN port */ + ath79_register_eth(1); + + ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5", + alfa_nx_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c new file mode 100644 index 0000000..2495bcb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c @@ -0,0 +1,88 @@ +/* + * Allnet ALL0258N support + * + * Copyright (C) 2011 Daniel Golle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +/* found via /sys/gpio/... try and error */ +#define ALL0258N_GPIO_BTN_RESET 1 +#define ALL0258N_GPIO_LED_RSSIHIGH 13 +#define ALL0258N_GPIO_LED_RSSIMEDIUM 15 +#define ALL0258N_GPIO_LED_RSSILOW 14 + +/* defaults taken from others machs */ +#define ALL0258N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL) + +/* showed up in the original firmware's bootlog */ +#define ALL0258N_SEC_PHYMASK BIT(3) + +static struct gpio_led all0258n_leds_gpio[] __initdata = { + { + .name = "all0258n:green:rssihigh", + .gpio = ALL0258N_GPIO_LED_RSSIHIGH, + .active_low = 1, + }, { + .name = "all0258n:yellow:rssimedium", + .gpio = ALL0258N_GPIO_LED_RSSIMEDIUM, + .active_low = 1, + }, { + .name = "all0258n:red:rssilow", + .gpio = ALL0258N_GPIO_LED_RSSILOW, + .active_low = 1, + } +}; + +static struct gpio_keys_button all0258n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0258N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init all0258n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1f7f1000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio), + all0258n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0258n_gpio_keys), + all0258n_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK; + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N", + all0258n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c new file mode 100644 index 0000000..387ee7f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c @@ -0,0 +1,85 @@ +/* + * Allnet ALL0315N support + * + * Copyright (C) 2012 Daniel Golle + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" +#include "pci.h" + +#define ALL0315N_GPIO_BTN_RESET 0 +#define ALL0315N_GPIO_LED_RSSIHIGH 14 +#define ALL0315N_GPIO_LED_RSSIMEDIUM 15 +#define ALL0315N_GPIO_LED_RSSILOW 16 + +#define ALL0315N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALL0315N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0315N_KEYS_POLL_INTERVAL) + +static struct gpio_led all0315n_leds_gpio[] __initdata = { + { + .name = "all0315n:green:rssihigh", + .gpio = ALL0315N_GPIO_LED_RSSIHIGH, + .active_low = 1, + }, { + .name = "all0315n:yellow:rssimedium", + .gpio = ALL0315N_GPIO_LED_RSSIMEDIUM, + .active_low = 1, + }, { + .name = "all0315n:red:rssilow", + .gpio = ALL0315N_GPIO_LED_RSSILOW, + .active_low = 1, + } +}; + +static struct gpio_keys_button all0315n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0315N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0315N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init all0315n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffc0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1ffc1000); + + ath79_register_m25p80(NULL); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0315n_leds_gpio), + all0315n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALL0315N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0315n_gpio_keys), + all0315n_gpio_keys); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap91_pci_init(ee, NULL); +} + +MIPS_MACHINE(ATH79_MACH_ALL0315N, "ALL0315N", "Allnet ALL0315N", + all0315n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c new file mode 100644 index 0000000..27ed760 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c @@ -0,0 +1,98 @@ +/* + * Bitmain Antminer S1 board support + * + * Copyright (C) 2015 L. D. Pinney + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define ANTMINER_S1_GPIO_BTN_RESET 11 + +#define ANTMINER_S1_GPIO_LED_SYSTEM 23 +#define ANTMINER_S1_GPIO_LED_WLAN 0 +#define ANTMINER_S1_GPIO_USB_POWER 8 + +#define ANTMINER_S1_KEYSPOLL_INTERVAL 20 /* msecs */ +#define ANTMINER_S1_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S1_KEYSPOLL_INTERVAL) + +static const char *ANTMINER_S1_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data ANTMINER_S1_flash_data = { + .part_probes = ANTMINER_S1_part_probes, +}; + +static struct gpio_led ANTMINER_S1_leds_gpio[] __initdata = { + { + .name = "bitmain:green:system", + .gpio = ANTMINER_S1_GPIO_LED_SYSTEM, + .active_low = 0, + },{ + .name = "bitmain:green:wlan", + .gpio = ANTMINER_S1_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ANTMINER_S1_GPIO_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ANTMINER_S1_KEYSDEBOUNCE_INTERVAL, + .gpio = ANTMINER_S1_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static void __init antminer_s1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S1_leds_gpio), + ANTMINER_S1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ANTMINER_S1_KEYSPOLL_INTERVAL, + ARRAY_SIZE(ANTMINER_S1_GPIO_keys), + ANTMINER_S1_GPIO_keys); + + gpio_request_one(ANTMINER_S1_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&ANTMINER_S1_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ANTMINER_S1, "ANTMINER-S1", + "Bitmain Antminer S1", antminer_s1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c new file mode 100644 index 0000000..010c461 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c @@ -0,0 +1,98 @@ +/* + * Bitmain Antminer S3 board support + * + * Copyright (C) 2015 L. D. Pinney + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define ANTMINER_S3_GPIO_LED_WLAN 0 +#define ANTMINER_S3_GPIO_LED_SYSTEM 17 +#define ANTMINER_S3_GPIO_LED_LAN 22 + +#define ANTMINER_S3_GPIO_BTN_RESET 11 + +#define ANTMINER_S3_KEYSPOLL_INTERVAL 88 /* msecs */ +#define ANTMINER_S3_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S3_KEYSPOLL_INTERVAL) + +static const char *ANTMINER_S3_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data ANTMINER_S3_flash_data = { + .part_probes = ANTMINER_S3_part_probes, +}; + +static struct gpio_led ANTMINER_S3_leds_gpio[] __initdata = { + { + .name = "bitmain:green:wlan", + .gpio = ANTMINER_S3_GPIO_LED_WLAN, + .active_low = 0, + },{ + .name = "bitmain:green:system", + .gpio = ANTMINER_S3_GPIO_LED_SYSTEM, + .active_low = 0, + },{ + .name = "bitmain:yellow:lan", + .gpio = ANTMINER_S3_GPIO_LED_LAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ANTMINER_S3_GPIO_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ANTMINER_S3_KEYSDEBOUNCE_INTERVAL, + .gpio = ANTMINER_S3_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static void __init antminer_s3_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S3_leds_gpio), + ANTMINER_S3_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ANTMINER_S3_KEYSPOLL_INTERVAL, + ARRAY_SIZE(ANTMINER_S3_GPIO_keys), + ANTMINER_S3_GPIO_keys); + ath79_register_usb(); + + ath79_register_m25p80(&ANTMINER_S3_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ANTMINER_S3, "ANTMINER-S3", + "Bitmain Antminer S3", antminer_s3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c new file mode 100644 index 0000000..9b38faa --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c @@ -0,0 +1,84 @@ +/* + * Atheros AP113 board support + * + * Copyright (C) 2011 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "pci.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define AP113_GPIO_LED_USB 0 +#define AP113_GPIO_LED_STATUS 1 +#define AP113_GPIO_LED_ST 11 + +#define AP113_GPIO_BTN_JUMPSTART 12 + +#define AP113_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP113_KEYS_DEBOUNCE_INTERVAL (3 * AP113_KEYS_POLL_INTERVAL) + +static struct gpio_led ap113_leds_gpio[] __initdata = { + { + .name = "ap113:green:usb", + .gpio = AP113_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "ap113:green:status", + .gpio = AP113_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "ap113:green:st", + .gpio = AP113_GPIO_LED_ST, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap113_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP113_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP113_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, +}; + +static void __init ap113_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + ath79_register_gpio_keys_polled(-1, AP113_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap113_gpio_keys), + ap113_gpio_keys); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap113_leds_gpio), + ap113_leds_gpio); + + ath79_register_pci(); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_AP113, "AP113", "Atheros AP113", + ap113_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c new file mode 100644 index 0000000..86fd8bd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c @@ -0,0 +1,189 @@ +/* + * Atheros AP132 reference board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos + * Copyright (c) 2013 Embedded Wireless GmbH + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP132_GPIO_LED_USB 4 +#define AP132_GPIO_LED_WLAN_5G 12 +#define AP132_GPIO_LED_WLAN_2G 13 +#define AP132_GPIO_LED_STATUS_RED 14 +#define AP132_GPIO_LED_WPS_RED 15 + +#define AP132_GPIO_BTN_WPS 16 + +#define AP132_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL) + +#define AP132_MAC0_OFFSET 0 +#define AP132_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led ap132_leds_gpio[] __initdata = { + { + .name = "ap132:red:status", + .gpio = AP132_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { + .name = "ap132:red:wps", + .gpio = AP132_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { + .name = "ap132:red:wlan-2g", + .gpio = AP132_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "ap132:red:usb", + .gpio = AP132_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap132_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP132_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg; + +static struct ar8327_platform_data ap132_ar8327_data = { + .pad0_cfg = &ap132_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info ap132_mdio1_info[] = { + { + .bus_id = "ag71xx-mdio.1", + .phy_addr = 0, + .platform_data = &ap132_ar8327_data, + }, +}; + +static void __init ap132_mdio_setup(void) +{ + void __iomem *base; + u32 t; + +#define GPIO_IN_ENABLE3_ADDRESS 0x0050 +#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000 +#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16 +#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) +#define GPIO_OUT_FUNCTION4_ADDRESS 0x003c +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK) +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) + + base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + + t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS); + t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK; + t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19); + __raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS); + + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base + AR71XX_GPIO_REG_OE); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base + AR71XX_GPIO_REG_OE); + + + t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS); + t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK); + t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21); + __raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS); + + iounmap(base); + +} + +static void __init ap132_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio), + ap132_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap132_gpio_keys), + ap132_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL); + + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap132_ar8327_pad0_cfg.sgmii_delay_en = true; + + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ap132_mdio_setup(); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0); + + mdiobus_register_board_info(ap132_mdio1_info, + ARRAY_SIZE(ap132_mdio1_info)); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_data.phy_mask = BIT(0); + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_AP132, "AP132", + "Atheros AP132 reference board", + ap132_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c new file mode 100644 index 0000000..098420b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c @@ -0,0 +1,142 @@ +/* + * Atheros AP143 reference board support + * + * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved. + * Copyright (c) 2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP143_GPIO_LED_WLAN 12 +#define AP143_GPIO_LED_WPS 13 +#define AP143_GPIO_LED_STATUS 13 + +#define AP143_GPIO_LED_WAN 4 +#define AP143_GPIO_LED_LAN1 16 +#define AP143_GPIO_LED_LAN2 15 +#define AP143_GPIO_LED_LAN3 14 +#define AP143_GPIO_LED_LAN4 11 + +#define AP143_GPIO_BTN_WPS 17 + +#define AP143_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP143_KEYS_DEBOUNCE_INTERVAL (3 * AP143_KEYS_POLL_INTERVAL) + +#define AP143_MAC0_OFFSET 0 +#define AP143_MAC1_OFFSET 6 +#define AP143_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led ap143_leds_gpio[] __initdata = { + { + .name = "ap143:green:status", + .gpio = AP143_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "ap143:green:wlan", + .gpio = AP143_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap143_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP143_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP143_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void __init ap143_gpio_led_setup(void) +{ + ath79_gpio_direction_select(AP143_GPIO_LED_WAN, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN1, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN2, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN3, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN4, true); + + ath79_gpio_output_select(AP143_GPIO_LED_WAN, + QCA953X_GPIO_OUT_MUX_LED_LINK5); + ath79_gpio_output_select(AP143_GPIO_LED_LAN1, + QCA953X_GPIO_OUT_MUX_LED_LINK1); + ath79_gpio_output_select(AP143_GPIO_LED_LAN2, + QCA953X_GPIO_OUT_MUX_LED_LINK2); + ath79_gpio_output_select(AP143_GPIO_LED_LAN3, + QCA953X_GPIO_OUT_MUX_LED_LINK3); + ath79_gpio_output_select(AP143_GPIO_LED_LAN4, + QCA953X_GPIO_OUT_MUX_LED_LINK4); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap143_leds_gpio), + ap143_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP143_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap143_gpio_keys), + ap143_gpio_keys); +} + +static void __init ap143_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ap143_gpio_led_setup(); + + ath79_register_usb(); + + ath79_wmac_set_led_pin(AP143_GPIO_LED_WLAN); + ath79_register_wmac(art + AP143_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP143_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP143_MAC1_OFFSET, 0); + + /* WAN port */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(4); + ath79_register_eth(0); + + /* LAN ports */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_switch_data.phy4_mii_en = 1; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_AP143, "AP143", "Qualcomm Atheros AP143 reference board", + ap143_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c new file mode 100644 index 0000000..7b45da4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c @@ -0,0 +1,125 @@ +/* + * Atheros AP147 reference board support + * + * Copyright (C) 2014 Matthias Schiffer + * Copyright (C) 2015 Sven Eckelmann + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define AP147_GPIO_LED_WAN 4 +#define AP147_GPIO_LED_LAN1 16 +#define AP147_GPIO_LED_LAN2 15 +#define AP147_GPIO_LED_LAN3 14 +#define AP147_GPIO_LED_LAN4 11 +#define AP147_GPIO_LED_STATUS 13 +#define AP147_GPIO_LED_WLAN_2G 12 + +#define AP147_GPIO_BTN_WPS 17 + +#define AP147_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP147_KEYS_DEBOUNCE_INTERVAL (3 * AP147_KEYS_POLL_INTERVAL) + +#define AP147_MAC0_OFFSET 0x1000 + +static struct gpio_led ap147_leds_gpio[] __initdata = { + { + .name = "ap147:green:status", + .gpio = AP147_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "ap147:green:wlan-2g", + .gpio = AP147_GPIO_LED_WLAN_2G, + .active_low = 1, + }, { + .name = "ap147:green:lan1", + .gpio = AP147_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "ap147:green:lan2", + .gpio = AP147_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "ap147:green:lan3", + .gpio = AP147_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "ap147:green:lan4", + .gpio = AP147_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "ap147:green:wan", + .gpio = AP147_GPIO_LED_WAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button ap147_gpio_keys[] __initdata = { + { + .desc = "wps button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP147_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP147_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init ap147_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap147_leds_gpio), + ap147_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP147_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap147_gpio_keys), + ap147_gpio_keys); + + ath79_register_usb(); + + ath79_register_pci(); + + ath79_register_wmac(art + AP147_MAC0_OFFSET, NULL); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0); + ath79_register_eth(1); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, art, 1); + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_AP147_010, "AP147-010", "Atheros AP147-010 reference board", ap147_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c new file mode 100644 index 0000000..a1eb06b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c @@ -0,0 +1,141 @@ + +/* + * Qualcomm Atheros AP152 reference board support + * + * Copyright (c) 2015 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include "common.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" + +#define AP152_GPIO_LED_USB0 7 +#define AP152_GPIO_LED_USB1 8 + +#define AP152_GPIO_BTN_RESET 2 +#define AP152_GPIO_BTN_WPS 1 +#define AP152_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP152_KEYS_DEBOUNCE_INTERVAL (3 * AP152_KEYS_POLL_INTERVAL) + +#define AP152_MAC0_OFFSET 0 +#define AP152_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led ap152_leds_gpio[] __initdata = { + { + .name = "ap152:green:usb0", + .gpio = AP152_GPIO_LED_USB0, + .active_low = 1, + }, + { + .name = "ap152:green:usb1", + .gpio = AP152_GPIO_LED_USB1, + .active_low = 1, + }, +}; + +static struct gpio_keys_button ap152_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP152_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP152_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg ap152_ar8337_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_platform_data ap152_ar8337_data = { + .pad0_cfg = &ap152_ar8337_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info ap152_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &ap152_ar8337_data, + }, +}; + +static void __init ap152_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap152_leds_gpio), + ap152_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP152_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap152_gpio_keys), + ap152_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&ath79_mdio0_device); + + mdiobus_register_board_info(ap152_mdio0_info, + ARRAY_SIZE(ap152_mdio0_info)); + + ath79_register_wmac(art + AP152_WMAC_CALDATA_OFFSET, NULL); + ath79_register_pci(); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP152_MAC0_OFFSET, 0); + + /* GMAC0 is connected to an AR8337 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_AP152, "AP152", "Qualcomm Atheros AP152 reference board", + ap152_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c new file mode 100644 index 0000000..8519a9d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c @@ -0,0 +1,275 @@ +/* + * Atheros AP83 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP83_GPIO_LED_WLAN 6 +#define AP83_GPIO_LED_POWER 14 +#define AP83_GPIO_LED_JUMPSTART 15 +#define AP83_GPIO_BTN_JUMPSTART 12 +#define AP83_GPIO_BTN_RESET 21 + +#define AP83_050_GPIO_VSC7385_CS 1 +#define AP83_050_GPIO_VSC7385_MISO 3 +#define AP83_050_GPIO_VSC7385_MOSI 16 +#define AP83_050_GPIO_VSC7385_SCK 17 + +#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) + +static struct mtd_partition ap83_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x040000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x060000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x1a0000, + .size = 0x650000, + }, { + .name = "art", + .offset = 0x7f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x060000, + .size = 0x790000, + } +}; + +static struct physmap_flash_data ap83_flash_data = { + .width = 2, + .parts = ap83_flash_partitions, + .nr_parts = ARRAY_SIZE(ap83_flash_partitions), +}; + +static struct resource ap83_flash_resources[] = { + [0] = { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ap83_flash_device = { + .name = "ar91xx-flash", + .id = -1, + .resource = ap83_flash_resources, + .num_resources = ARRAY_SIZE(ap83_flash_resources), + .dev = { + .platform_data = &ap83_flash_data, + } +}; + +static struct gpio_led ap83_leds_gpio[] __initdata = { + { + .name = "ap83:green:jumpstart", + .gpio = AP83_GPIO_LED_JUMPSTART, + .active_low = 0, + }, { + .name = "ap83:green:power", + .gpio = AP83_GPIO_LED_POWER, + .active_low = 0, + }, { + .name = "ap83:green:wlan", + .gpio = AP83_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ap83_gpio_keys[] __initdata = { + { + .desc = "soft_reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP83_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "jumpstart", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP83_GPIO_BTN_JUMPSTART, + .active_low = 1, + } +}; + +static struct resource ap83_040_spi_resources[] = { + [0] = { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ap83_040_spi_device = { + .name = "ap83-spi", + .id = 0, + .resource = ap83_040_spi_resources, + .num_resources = ARRAY_SIZE(ap83_040_spi_resources), +}; + +static struct spi_gpio_platform_data ap83_050_spi_data = { + .miso = AP83_050_GPIO_VSC7385_MISO, + .mosi = AP83_050_GPIO_VSC7385_MOSI, + .sck = AP83_050_GPIO_VSC7385_SCK, + .num_chipselect = 1, +}; + +static struct platform_device ap83_050_spi_device = { + .name = "spi_gpio", + .id = 0, + .dev = { + .platform_data = &ap83_050_spi_data, + } +}; + +static void ap83_vsc7385_reset(void) +{ + ath79_device_reset_set(AR71XX_RESET_GE1_PHY); + udelay(10); + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); + mdelay(50); +} + +static struct vsc7385_platform_data ap83_vsc7385_data = { + .reset = ap83_vsc7385_reset, + .ucode_name = "vsc7385_ucode_ap83.bin", + .mac_cfg = { + .tx_ipg = 6, + .bit2 = 0, + .clk_sel = 3, + }, +}; + +static struct spi_board_info ap83_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "spi-vsc7385", + .platform_data = &ap83_vsc7385_data, + .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, + } +}; + +static void __init ap83_generic_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0xfffffffe); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = 0x1; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_eth1_pll_data.pll_1000 = 0x1f000000; + + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), + ap83_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap83_gpio_keys), + ap83_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(eeprom, NULL); + + platform_device_register(&ap83_flash_device); + + spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); +} + +static void ap83_040_flash_lock(struct platform_device *pdev) +{ + ath79_flash_acquire(); +} + +static void ap83_040_flash_unlock(struct platform_device *pdev) +{ + ath79_flash_release(); +} + +static void __init ap83_040_setup(void) +{ + ap83_flash_data.lock = ap83_040_flash_lock; + ap83_flash_data.unlock = ap83_040_flash_unlock; + ap83_generic_setup(); + platform_device_register(&ap83_040_spi_device); +} + +static void __init ap83_050_setup(void) +{ + ap83_generic_setup(); + platform_device_register(&ap83_050_spi_device); +} + +static void __init ap83_setup(void) +{ + u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); + unsigned int board_version; + + board_version = (unsigned int)(board_id[0] - '0'); + board_version += ((unsigned int)(board_id[1] - '0')) * 10; + + switch (board_version) { + case 40: + ap83_040_setup(); + break; + case 50: + ap83_050_setup(); + break; + default: + printk(KERN_WARNING "AP83-%03u board is not yet supported\n", + board_version); + } +} + +MIPS_MACHINE(ATH79_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c new file mode 100644 index 0000000..35120d3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c @@ -0,0 +1,142 @@ +/* + * Atheros AP96 board support + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define AP96_GPIO_LED_12_GREEN 0 +#define AP96_GPIO_LED_3_GREEN 1 +#define AP96_GPIO_LED_2_GREEN 2 +#define AP96_GPIO_LED_WPS_GREEN 4 +#define AP96_GPIO_LED_5_GREEN 5 +#define AP96_GPIO_LED_4_ORANGE 6 + +/* Reset button - next to the power connector */ +#define AP96_GPIO_BTN_RESET 3 +/* WPS button - next to a led on right */ +#define AP96_GPIO_BTN_WPS 8 + +#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL) + +#define AP96_WMAC0_MAC_OFFSET 0x120c +#define AP96_WMAC1_MAC_OFFSET 0x520c +#define AP96_CALDATA0_OFFSET 0x1000 +#define AP96_CALDATA1_OFFSET 0x5000 + +/* + * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12 + * below (from left to right on the board). Led 1 seems to be on whenever the + * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange; + * others are green. + * + * In addition, there is one led next to a button on the right side for WPS. + */ +static struct gpio_led ap96_leds_gpio[] __initdata = { + { + .name = "ap96:green:led2", + .gpio = AP96_GPIO_LED_2_GREEN, + .active_low = 1, + }, { + .name = "ap96:green:led3", + .gpio = AP96_GPIO_LED_3_GREEN, + .active_low = 1, + }, { + .name = "ap96:orange:led4", + .gpio = AP96_GPIO_LED_4_ORANGE, + .active_low = 1, + }, { + .name = "ap96:green:led5", + .gpio = AP96_GPIO_LED_5_GREEN, + .active_low = 1, + }, { + .name = "ap96:green:led12", + .gpio = AP96_GPIO_LED_12_GREEN, + .active_low = 1, + }, { /* next to a button on right */ + .name = "ap96:green:wps", + .gpio = AP96_GPIO_LED_WPS_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap96_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP96_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP96_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +#define AP96_WAN_PHYMASK 0x10 +#define AP96_LAN_PHYMASK 0x0f + +static void __init ap96_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK; + + ath79_eth1_pll_data.pll_1000 = 0x1f000000; + + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio), + ap96_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap96_gpio_keys), + ap96_gpio_keys); + + ap94_pci_init(art + AP96_CALDATA0_OFFSET, + art + AP96_WMAC0_MAC_OFFSET, + art + AP96_CALDATA1_OFFSET, + art + AP96_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c new file mode 100644 index 0000000..fc12513 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c @@ -0,0 +1,266 @@ +/* + * TP-LINK Archer C5/C7/TL-WDR4900 v2 board support + * + * Copyright (c) 2013 Gabor Juhos + * Copyright (c) 2014 施康成 + * Copyright (c) 2014 Imre Kaloz + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define ARCHER_C7_GPIO_LED_WLAN2G 12 +#define ARCHER_C7_GPIO_LED_SYSTEM 14 +#define ARCHER_C7_GPIO_LED_QSS 15 +#define ARCHER_C7_GPIO_LED_WLAN5G 17 +#define ARCHER_C7_GPIO_LED_USB1 18 +#define ARCHER_C7_GPIO_LED_USB2 19 + +#define ARCHER_C7_GPIO_BTN_RFKILL 13 +#define ARCHER_C7_GPIO_BTN_RESET 16 + +#define ARCHER_C7_GPIO_USB1_POWER 22 +#define ARCHER_C7_GPIO_USB2_POWER 21 + +#define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL) + +#define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000 +#define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000 + +static const char *archer_c7_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data archer_c7_flash_data = { + .part_probes = archer_c7_part_probes, +}; + +static struct gpio_led archer_c7_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:qss", + .gpio = ARCHER_C7_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:blue:system", + .gpio = ARCHER_C7_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan2g", + .gpio = ARCHER_C7_GPIO_LED_WLAN2G, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan5g", + .gpio = ARCHER_C7_GPIO_LED_WLAN5G, + .active_low = 1, + }, + { + .name = "tp-link:green:usb1", + .gpio = ARCHER_C7_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "tp-link:green:usb2", + .gpio = ARCHER_C7_GPIO_LED_USB2, + .active_low = 1, + }, +}; + +static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARCHER_C7_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARCHER_C7_GPIO_BTN_RFKILL, + }, +}; + +static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"), + AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"), + AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"), + AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"), + AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"), +}; + +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ +static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ +static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data archer_c7_ar8327_data = { + .pad0_cfg = &archer_c7_ar8327_pad0_cfg, + .pad6_cfg = &archer_c7_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &archer_c7_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327), + .leds = archer_c7_leds_ar8327, +}; + +static struct mdio_board_info archer_c7_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &archer_c7_ar8327_data, + }, +}; + +static void __init common_setup(bool pcie_slot) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&archer_c7_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), + archer_c7_leds_gpio); + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, + ARRAY_SIZE(archer_c7_gpio_keys), + archer_c7_gpio_keys); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); + + if (pcie_slot) { + ath79_register_pci(); + } else { + ath79_init_mac(tmpmac, mac, -1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac); + } + + mdiobus_register_board_info(archer_c7_mdio0_info, + ARRAY_SIZE(archer_c7_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + gpio_request_one(ARCHER_C7_GPIO_USB1_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB1 power"); + gpio_request_one(ARCHER_C7_GPIO_USB2_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB2 power"); + ath79_register_usb(); +} + +static void __init archer_c5_setup(void) +{ + common_setup(true); +} + +MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5", + archer_c5_setup); + +static void __init archer_c7_setup(void) +{ + common_setup(true); +} + +MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7", + archer_c7_setup); + +static void __init tl_wdr4900_v2_setup(void) +{ + common_setup(false); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2", + tl_wdr4900_v2_setup) + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c new file mode 100644 index 0000000..281129b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c @@ -0,0 +1,107 @@ +/* + * AzureWave AW-NR580 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" +#include "pci.h" + +#define AW_NR580_GPIO_LED_READY_RED 0 +#define AW_NR580_GPIO_LED_WLAN 1 +#define AW_NR580_GPIO_LED_READY_GREEN 2 +#define AW_NR580_GPIO_LED_WPS_GREEN 4 +#define AW_NR580_GPIO_LED_WPS_AMBER 5 + +#define AW_NR580_GPIO_BTN_WPS 3 +#define AW_NR580_GPIO_BTN_RESET 11 + +#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL) + +static struct gpio_led aw_nr580_leds_gpio[] __initdata = { + { + .name = "aw-nr580:red:ready", + .gpio = AW_NR580_GPIO_LED_READY_RED, + .active_low = 0, + }, { + .name = "aw-nr580:green:ready", + .gpio = AW_NR580_GPIO_LED_READY_GREEN, + .active_low = 0, + }, { + .name = "aw-nr580:green:wps", + .gpio = AW_NR580_GPIO_LED_WPS_GREEN, + .active_low = 0, + }, { + .name = "aw-nr580:amber:wps", + .gpio = AW_NR580_GPIO_LED_WPS_AMBER, + .active_low = 0, + }, { + .name = "aw-nr580:green:wlan", + .gpio = AW_NR580_GPIO_LED_WLAN, + .active_low = 0, + } +}; + +static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, + .gpio = AW_NR580_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, + .gpio = AW_NR580_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static const char *aw_nr580_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data aw_nr580_flash_data = { + .part_probes = aw_nr580_part_probes, +}; + +static void __init aw_nr580_setup(void) +{ + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_register_pci(); + + ath79_register_m25p80(&aw_nr580_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), + aw_nr580_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL, + ARRAY_SIZE(aw_nr580_gpio_keys), + aw_nr580_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", + aw_nr580_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-bhu-bxu2000n2-a.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-bhu-bxu2000n2-a.c new file mode 100644 index 0000000..8d7c611 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-bhu-bxu2000n2-a.c @@ -0,0 +1,120 @@ +/* + * BHU BXU2000n-2 A1 board support + * + * Copyright (C) 2013 Terry Yang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define BHU_BXU2000N2_A1_GPIO_LED_WLAN 13 +#define BHU_BXU2000N2_A1_GPIO_LED_WAN 19 +#define BHU_BXU2000N2_A1_GPIO_LED_LAN 21 +#define BHU_BXU2000N2_A1_GPIO_LED_SYSTEM 14 + +#define BHU_BXU2000N2_A1_GPIO_BTN_RESET 17 + +#define BHU_BXU2000N2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define BHU_BXU2000N2_KEYS_DEBOUNCE_INTERVAL \ + (3 * BHU_BXU2000N2_KEYS_POLL_INTERVAL) + +static const char *bhu_bxu2000n2_part_probes[] = { + "cmdlinepart", + NULL, +}; + +static struct flash_platform_data bhu_bxu2000n2_flash_data = { + .part_probes = bhu_bxu2000n2_part_probes, +}; + +static struct gpio_led bhu_bxu2000n2_a1_leds_gpio[] __initdata = { + { + .name = "bhu:green:status", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "bhu:green:lan", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "bhu:green:wan", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "bhu:green:wlan", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button bhu_bxu2000n2_a1_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BHU_BXU2000N2_KEYS_DEBOUNCE_INTERVAL, + .gpio = BHU_BXU2000N2_A1_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init bhu_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&bhu_bxu2000n2_flash_data); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch. Only use PHY3 */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.phy_mask = BIT(3); + ath79_register_eth(1); + + ath79_register_wmac(ee, ee+2); +} + +static void __init bhu_bxu2000n2_a1_setup(void) +{ + bhu_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(bhu_bxu2000n2_a1_leds_gpio), + bhu_bxu2000n2_a1_leds_gpio); + + ath79_register_gpio_keys_polled(1, BHU_BXU2000N2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(bhu_bxu2000n2_a1_gpio_keys), + bhu_bxu2000n2_a1_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_BHU_BXU2000N2_A1, "BXU2000n-2-A1", + "BHU BXU2000n-2 rev. A1", + bhu_bxu2000n2_a1_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-bsb.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-bsb.c new file mode 100644 index 0000000..9f9be02 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-bsb.c @@ -0,0 +1,83 @@ +/* + * Smart Electronics Black Swift board support + * + * Copyright (C) 2014 Dmitriy Zherebkov dzh@black-swift.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define BSB_GPIO_LED_SYS 27 + +#define BSB_GPIO_BTN_RESET 11 + +#define BSB_KEYS_POLL_INTERVAL 20 /* msecs */ +#define BSB_KEYS_DEBOUNCE_INTERVAL (3 * BSB_KEYS_POLL_INTERVAL) + +#define BSB_MAC_OFFSET 0x0000 +#define BSB_CALDATA_OFFSET 0x1000 + +static struct gpio_led bsb_leds_gpio[] __initdata = { + { + .name = "bsb:red:sys", + .gpio = BSB_GPIO_LED_SYS, + .active_low = 1, + } +}; + +static struct gpio_keys_button bsb_gpio_keys[] __initdata = { + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BSB_KEYS_DEBOUNCE_INTERVAL, + .gpio = BSB_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init bsb_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false,false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(bsb_leds_gpio), + bsb_leds_gpio); + ath79_register_gpio_keys_polled(-1, BSB_KEYS_POLL_INTERVAL, + ARRAY_SIZE(bsb_gpio_keys), + bsb_gpio_keys); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + BSB_MAC_OFFSET, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, art + BSB_MAC_OFFSET, 2); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(art + BSB_CALDATA_OFFSET, + art + BSB_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_BSB, "BSB", "Smart Electronics Black Swift board", + bsb_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cap4200ag.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cap4200ag.c new file mode 100644 index 0000000..18944c4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cap4200ag.c @@ -0,0 +1,131 @@ +/* + * Senao CAP4200AG board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define CAP4200AG_GPIO_LED_PWR_GREEN 12 +#define CAP4200AG_GPIO_LED_PWR_AMBER 13 +#define CAP4200AG_GPIO_LED_LAN_GREEN 14 +#define CAP4200AG_GPIO_LED_LAN_AMBER 15 +#define CAP4200AG_GPIO_LED_WLAN_GREEN 18 +#define CAP4200AG_GPIO_LED_WLAN_AMBER 19 + +#define CAP4200AG_GPIO_BTN_RESET 17 + +#define CAP4200AG_KEYS_POLL_INTERVAL 20 /* msecs */ +#define CAP4200AG_KEYS_DEBOUNCE_INTERVAL (3 * CAP4200AG_KEYS_POLL_INTERVAL) + +#define CAP4200AG_MAC_OFFSET 0 +#define CAP4200AG_WMAC_CALDATA_OFFSET 0x1000 +#define CAP4200AG_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led cap4200ag_leds_gpio[] __initdata = { + { + .name = "senao:green:pwr", + .gpio = CAP4200AG_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, + { + .name = "senao:amber:pwr", + .gpio = CAP4200AG_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, + { + .name = "senao:green:lan", + .gpio = CAP4200AG_GPIO_LED_LAN_GREEN, + .active_low = 1, + }, + { + .name = "senao:amber:lan", + .gpio = CAP4200AG_GPIO_LED_LAN_AMBER, + .active_low = 1, + }, + { + .name = "senao:green:wlan", + .gpio = CAP4200AG_GPIO_LED_WLAN_GREEN, + .active_low = 1, + }, + { + .name = "senao:amber:wlan", + .gpio = CAP4200AG_GPIO_LED_WLAN_AMBER, + .active_low = 1, + }, +}; + +static struct gpio_keys_button cap4200ag_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = CAP4200AG_KEYS_DEBOUNCE_INTERVAL, + .gpio = CAP4200AG_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init cap4200ag_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER, + AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio), + cap4200ag_leds_gpio); + ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL, + ARRAY_SIZE(cap4200ag_gpio_keys), + cap4200ag_gpio_keys); + + ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1); + ath79_wmac_disable_2ghz(); + ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac); + + ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2); + ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + CAP4200AG_MAC_OFFSET, -2); + + /* GMAC0 is connected to an external PHY */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_CAP4200AG, "CAP4200AG", "Senao CAP4200AG", + cap4200ag_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-carambola2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-carambola2.c new file mode 100644 index 0000000..babe101 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-carambola2.c @@ -0,0 +1,105 @@ +/* + * 8devices Carambola2 board support + * + * Copyright (C) 2013 Darius Augulis + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define CARAMBOLA2_GPIO_LED_WLAN 0 +#define CARAMBOLA2_GPIO_LED_ETH0 14 +#define CARAMBOLA2_GPIO_LED_ETH1 13 + +#define CARAMBOLA2_GPIO_BTN_JUMPSTART 11 + +#define CARAMBOLA2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define CARAMBOLA2_KEYS_DEBOUNCE_INTERVAL (3 * CARAMBOLA2_KEYS_POLL_INTERVAL) + +#define CARAMBOLA2_MAC0_OFFSET 0x0000 +#define CARAMBOLA2_MAC1_OFFSET 0x0006 +#define CARAMBOLA2_CALDATA_OFFSET 0x1000 +#define CARAMBOLA2_WMAC_MAC_OFFSET 0x1002 + +static struct gpio_led carambola2_leds_gpio[] __initdata = { + { + .name = "carambola2:green:wlan", + .gpio = CARAMBOLA2_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "carambola2:orange:eth0", + .gpio = CARAMBOLA2_GPIO_LED_ETH0, + .active_low = 0, + }, { + .name = "carambola2:orange:eth1", + .gpio = CARAMBOLA2_GPIO_LED_ETH1, + .active_low = 0, + } +}; + +static struct gpio_keys_button carambola2_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = CARAMBOLA2_KEYS_DEBOUNCE_INTERVAL, + .gpio = CARAMBOLA2_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, +}; + +static void __init carambola2_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art + CARAMBOLA2_CALDATA_OFFSET, + art + CARAMBOLA2_WMAC_MAC_OFFSET); + + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + CARAMBOLA2_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + CARAMBOLA2_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); +} + +static void __init carambola2_setup(void) +{ + carambola2_common_setup(); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(carambola2_leds_gpio), + carambola2_leds_gpio); + ath79_register_gpio_keys_polled(-1, CARAMBOLA2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(carambola2_gpio_keys), + carambola2_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_CARAMBOLA2, "CARAMBOLA2", "8devices Carambola2 board", + carambola2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cf-e316n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cf-e316n-v2.c new file mode 100644 index 0000000..cf3d33a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cf-e316n-v2.c @@ -0,0 +1,132 @@ +/* + * COMFAST CF-E316N v2 + * by Shenzhen Four Seas Global Link Network Technology Co., Ltd + * + * aka CF-E316V2, CF-E316N-V2 and CF-E316Nv2.0 (no FCC ID) + * + * Copyright (C) 2015 Paul Fertser + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "dev-usb.h" +#include "machtypes.h" + +static struct gpio_led cf_e316n_v2_leds_gpio[] __initdata = { + { + .name = "cf-e316n-v2:blue:diag", + .gpio = 0, + .active_low = 0, + }, { + .name = "cf-e316n-v2:red:diag", + .gpio = 2, + .active_low = 0, + }, { + .name = "cf-e316n-v2:green:diag", + .gpio = 3, + .active_low = 0, + }, { + .name = "cf-e316n-v2:blue:wlan", + .gpio = 12, + .active_low = 1, + }, { + .name = "cf-e316n-v2:blue:wan", + .gpio = 17, + .active_low = 1, + }, { + .name = "cf-e316n-v2:blue:lan", + .gpio = 19, + .active_low = 1, + }, +}; + +static struct gpio_keys_button cf_e316n_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = 60, + .gpio = 20, + .active_low = 1, + }, +}; + +/* There's a Pericon Technology PT7A7514 connected to GPIO 16 */ +#define EXT_WATCHDOG_GPIO 16 +static struct timer_list gpio_wdt_timer; + +static void gpio_wdt_toggle(unsigned long period) +{ + static int state; + state = !state; + gpio_set_value(EXT_WATCHDOG_GPIO, state); + mod_timer(&gpio_wdt_timer, jiffies + period); +} + +static void __init cf_e316n_v2_setup(void) +{ + u8 *maclan = (u8 *) KSEG1ADDR(0x1f010000); + u8 *macwlan = (u8 *) KSEG1ADDR(0x1f011002); + u8 *ee = (u8 *) KSEG1ADDR(0x1f011000); + u8 tmpmac[ETH_ALEN]; + + gpio_request(EXT_WATCHDOG_GPIO, "PT7A7514 watchdog"); + gpio_direction_output(EXT_WATCHDOG_GPIO, 0); + setup_timer(&gpio_wdt_timer, gpio_wdt_toggle, msecs_to_jiffies(500)); + gpio_wdt_toggle(msecs_to_jiffies(1)); + + ath79_register_m25p80(NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + ath79_register_mdio(1, 0x0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_init_mac(ath79_eth0_data.mac_addr, maclan, 0); + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_init_mac(ath79_eth1_data.mac_addr, maclan, 2); + ath79_register_eth(1); + + /* Enable 2x Skyworks SE2576L WLAN power amplifiers */ + gpio_request(13, "RF Amp 1"); + gpio_direction_output(13, 1); + gpio_request(14, "RF Amp 2"); + gpio_direction_output(14, 1); + ath79_init_mac(tmpmac, macwlan, 0); + ath79_register_wmac(ee, tmpmac); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e316n_v2_leds_gpio), + cf_e316n_v2_leds_gpio); + + ath79_register_gpio_keys_polled(1, 20, + ARRAY_SIZE(cf_e316n_v2_gpio_keys), + cf_e316n_v2_gpio_keys); + + /* J1 is a High-Speed USB port, pin 1 is Vcc */ + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_CF_E316N_V2, "CF-E316N-V2", "COMFAST CF-E316N v2", + cf_e316n_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c new file mode 100644 index 0000000..8bf5c0f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c @@ -0,0 +1,107 @@ +/* + * TP-LINK CPE210/220/510/520 board support + * + * Copyright (C) 2014 Matthias Schiffer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + + +#define CPE510_GPIO_LED_LAN0 11 +#define CPE510_GPIO_LED_LAN1 12 +#define CPE510_GPIO_LED_L1 13 +#define CPE510_GPIO_LED_L2 14 +#define CPE510_GPIO_LED_L3 15 +#define CPE510_GPIO_LED_L4 16 + +#define CPE510_GPIO_BTN_RESET 4 + +#define CPE510_KEYS_POLL_INTERVAL 20 /* msecs */ +#define CPE510_KEYS_DEBOUNCE_INTERVAL (3 * CPE510_KEYS_POLL_INTERVAL) + + +static struct gpio_led cpe510_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan0", + .gpio = CPE510_GPIO_LED_LAN0, + .active_low = 1, + }, { + .name = "tp-link:green:lan1", + .gpio = CPE510_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:link1", + .gpio = CPE510_GPIO_LED_L1, + .active_low = 1, + }, { + .name = "tp-link:green:link2", + .gpio = CPE510_GPIO_LED_L2, + .active_low = 1, + }, { + .name = "tp-link:green:link3", + .gpio = CPE510_GPIO_LED_L3, + .active_low = 1, + }, { + .name = "tp-link:green:link4", + .gpio = CPE510_GPIO_LED_L4, + .active_low = 1, + }, +}; + +static struct gpio_keys_button cpe510_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = CPE510_KEYS_DEBOUNCE_INTERVAL, + .gpio = CPE510_GPIO_BTN_RESET, + .active_low = 1, + } +}; + + +static void __init cpe510_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f830008); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe510_leds_gpio), + cpe510_leds_gpio); + + ath79_register_gpio_keys_polled(1, CPE510_KEYS_POLL_INTERVAL, + ARRAY_SIZE(cpe510_gpio_keys), + cpe510_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_CPE510, "CPE510", "TP-LINK CPE210/220/510/520", + cpe510_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c new file mode 100644 index 0000000..91b554e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c @@ -0,0 +1,150 @@ +/* + * D-Link DGL-5500 board support + * + * Copyright (C) 2014 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DGL_5500_A1_GPIO_LED_POWER_ORANGE 14 +#define DGL_5500_A1_GPIO_LED_POWER_GREEN 19 +#define DGL_5500_A1_GPIO_LED_PLANET_GREEN 22 +#define DGL_5500_A1_GPIO_LED_PLANET_ORANGE 23 + +#define DGL_5500_A1_GPIO_BTN_WPS 16 +#define DGL_5500_A1_GPIO_BTN_RESET 17 + +#define DGL_5500_A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL \ + (3 * DGL_5500_A1_KEYS_POLL_INTERVAL) + +#define DGL_5500_A1_WMAC_CALDATA_OFFSET 0x1000 + +#define DGL_5500_A1_LAN_MAC_OFFSET 0x04 +#define DGL_5500_A1_WAN_MAC_OFFSET 0x16 + +static struct gpio_led dgl_5500_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DGL_5500_A1_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, + { + .name = "d-link:orange:power", + .gpio = DGL_5500_A1_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, + { + .name = "d-link:green:planet", + .gpio = DGL_5500_A1_GPIO_LED_PLANET_GREEN, + .active_low = 1, + }, + { + .name = "d-link:orange:planet", + .gpio = DGL_5500_A1_GPIO_LED_PLANET_ORANGE, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dgl_5500_a1_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DGL_5500_A1_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DGL_5500_A1_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dgl_5500_a1_ar8327_pad0_cfg = { + /* Use the SGMII interface for the GMAC0 of the AR8327 switch */ + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_platform_data dgl_5500_a1_ar8327_data = { + .pad0_cfg = &dgl_5500_a1_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info dgl_5500_a1_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dgl_5500_a1_ar8327_data, + }, +}; + +static void __init dgl_5500_a1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 lan_mac[ETH_ALEN]; + + ath79_parse_ascii_mac(mac + DGL_5500_A1_LAN_MAC_OFFSET, lan_mac); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dgl_5500_a1_leds_gpio), + dgl_5500_a1_leds_gpio); + ath79_register_gpio_keys_polled(-1, DGL_5500_A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dgl_5500_a1_gpio_keys), + dgl_5500_a1_gpio_keys); + + ath79_register_wmac(art + DGL_5500_A1_WMAC_CALDATA_OFFSET, lan_mac); + + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(dgl_5500_a1_mdio0_info, + ARRAY_SIZE(dgl_5500_a1_mdio0_info)); + + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + /* GMAC1 is connected to an AR8327N switch via the SMGII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.phy_mask = BIT(0); + ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_DGL_5500_A1, "DGL-5500-A1", "D-Link DGL-5500 rev. A1", + dgl_5500_a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c new file mode 100644 index 0000000..ae47764 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c @@ -0,0 +1,170 @@ +/* + * D-Link DHP-1565 rev. A1 board support + * + * Copyright (C) 2014 Jacek Kikiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DHP1565A1_GPIO_LED_BLUE_USB 11 +#define DHP1565A1_GPIO_LED_AMBER_POWER 14 +#define DHP1565A1_GPIO_LED_BLUE_POWER 22 +#define DHP1565A1_GPIO_LED_BLUE_WPS 15 +#define DHP1565A1_GPIO_LED_AMBER_PLANET 19 +#define DHP1565A1_GPIO_LED_BLUE_PLANET 18 +#define DHP1565A1_GPIO_LED_WLAN_2G 13 + +#define DHP1565A1_GPIO_WAN_LED_ENABLE 20 + +#define DHP1565A1_GPIO_BTN_RESET 17 +#define DHP1565A1_GPIO_BTN_WPS 16 + +#define DHP1565A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DHP1565A1_KEYS_DEBOUNCE_INTERVAL (3 * DHP1565A1_KEYS_POLL_INTERVAL) + +#define DHP1565A1_MAC0_OFFSET 0xFFA0 +#define DHP1565A1_MAC1_OFFSET 0xFFB4 +#define DHP1565A1_WMAC0_OFFSET 0x5 +#define DHP1565A1_WMAC_CALDATA_OFFSET 0x1000 +#define DHP1565A1_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dhp1565a1_leds_gpio[] __initdata = { + { + .name = "d-link:amber:power", + .gpio = DHP1565A1_GPIO_LED_AMBER_POWER, + .active_low = 1, + }, + { + .name = "d-link:green:power", + .gpio = DHP1565A1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, + { + .name = "d-link:amber:planet", + .gpio = DHP1565A1_GPIO_LED_AMBER_PLANET, + .active_low = 1, + }, + { + .name = "d-link:green:planet", + .gpio = DHP1565A1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dhp1565a1_gpio_keys[] __initdata = { + { + .desc = "Soft reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DHP1565A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DHP1565A1_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DHP1565A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DHP1565A1_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dhp1565a1_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data dhp1565a1_ar8327_data = { + .pad0_cfg = &dhp1565a1_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info dhp1565a1_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dhp1565a1_ar8327_data, + }, +}; + +static void __init dhp1565a1_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 mac0[ETH_ALEN], mac1[ETH_ALEN]; + u8 wmac0[ETH_ALEN]; + + ath79_parse_ascii_mac(mac + DHP1565A1_MAC0_OFFSET, mac0); + ath79_parse_ascii_mac(mac + DHP1565A1_MAC1_OFFSET, mac1); + + ath79_register_m25p80(NULL); + + ath79_register_gpio_keys_polled(-1, DHP1565A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dhp1565a1_gpio_keys), + dhp1565a1_gpio_keys); + + ath79_init_mac(wmac0, mac0, 0); + ath79_register_wmac(art + DHP1565A1_WMAC_CALDATA_OFFSET, wmac0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(dhp1565a1_mdio0_info, + ARRAY_SIZE(dhp1565a1_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 1); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_register_usb(); +} + +static void __init dhp1565a1_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(dhp1565a1_leds_gpio), + dhp1565a1_leds_gpio); + + dhp1565a1_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_DHP_1565_A1, "DHP-1565-A1", + "D-Link DHP-1565 rev. A1", + dhp1565a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-505-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-505-a1.c new file mode 100644 index 0000000..1367b64 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-505-a1.c @@ -0,0 +1,116 @@ +/* + * DLink DIR-505 A1 board support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define DIR_505A1_GPIO_BTN_WPS 11 /* verify */ +#define DIR_505A1_GPIO_BTN_RESET 12 /* verify */ + +#define DIR_505A1_GPIO_LED_RED 26 /* unused, fyi */ +#define DIR_505A1_GPIO_LED_GREEN 27 + +#define DIR_505A1_GPIO_WAN_LED_ENABLE 1 + +#define DIR_505A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_505A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_505A1_KEYS_POLL_INTERVAL) + +#define DIR_505A1_ART_ADDRESS 0x1f010000 +#define DIR_505A1_CALDATA_OFFSET 0x1000 + +#define DIR_505A1_MAC_PART_ADDRESS 0x1f020000 +#define DIR_505A1_LAN_MAC_OFFSET 0x04 +#define DIR_505A1_WAN_MAC_OFFSET 0x16 + +static struct gpio_led dir_505_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_505A1_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "d-link:red:status", + .gpio = DIR_505A1_GPIO_LED_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dir_505_a1_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_505A1_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_505A1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_505_a1_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(DIR_505A1_ART_ADDRESS); + u8 *mac = (u8 *) KSEG1ADDR(DIR_505A1_MAC_PART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + gpio_request_one(DIR_505A1_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_505_a1_leds_gpio), + dir_505_a1_leds_gpio); + + ath79_register_gpio_keys_polled(1, DIR_505A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_505_a1_gpio_keys), + dir_505_a1_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + ath79_parse_ascii_mac(mac + DIR_505A1_LAN_MAC_OFFSET, lan_mac); + ath79_parse_ascii_mac(mac + DIR_505A1_WAN_MAC_OFFSET, wan_mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + DIR_505A1_CALDATA_OFFSET, lan_mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_505_A1, "DIR-505-A1", + "D-Link DIR-505 rev. A1", dir_505_a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c new file mode 100644 index 0000000..321fdce --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c @@ -0,0 +1,159 @@ +/* + * D-Link DIR-600 rev. A1 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * Copyright (C) 2012 Vadim Girlin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "nvram.h" + +#define DIR_600_A1_GPIO_LED_WPS 0 +#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 +#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 +#define DIR_600_A1_GPIO_LED_LAN1 13 +#define DIR_600_A1_GPIO_LED_LAN2 14 +#define DIR_600_A1_GPIO_LED_LAN3 15 +#define DIR_600_A1_GPIO_LED_LAN4 16 +#define DIR_600_A1_GPIO_LED_WAN_AMBER 7 +#define DIR_600_A1_GPIO_LED_WAN_GREEN 17 + +#define DIR_600_A1_GPIO_BTN_RESET 8 +#define DIR_600_A1_GPIO_BTN_WPS 12 + +#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL) + +#define DIR_600_A1_NVRAM_ADDR 0x1f030000 +#define DIR_600_A1_NVRAM_SIZE 0x10000 + +static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, + }, { + .name = "d-link:amber:power", + .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_600_A1_GPIO_LED_WAN_AMBER, + }, { + .name = "d-link:green:wan", + .gpio = DIR_600_A1_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:green:lan1", + .gpio = DIR_600_A1_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "d-link:green:lan2", + .gpio = DIR_600_A1_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "d-link:green:lan3", + .gpio = DIR_600_A1_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "d-link:green:lan4", + .gpio = DIR_600_A1_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_600_A1_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_600_A1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_600_A1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_600_a1_setup(void) +{ + const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac_buff[6]; + u8 *mac = NULL; + + if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, + "lan_mac=", mac_buff) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1); + mac = mac_buff; + } + + ath79_register_m25p80(NULL); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), + dir_600_a1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_600_a1_gpio_keys), + dir_600_a1_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", + dir_600_a1_setup); + +static void __init dir_615_e1_setup(void) +{ + dir_600_a1_setup(); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_E1, "DIR-615-E1", "D-Link DIR-615 rev. E1", + dir_615_e1_setup); + +static void __init dir_615_e4_setup(void) +{ + dir_600_a1_setup(); + ap9x_pci_setup_wmac_led_pin(0, 1); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4", + dir_615_e4_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c new file mode 100644 index 0000000..e55a43f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c @@ -0,0 +1,135 @@ +/* + * D-Link DIR-615 rev C1 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ +#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ +#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ +#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ +#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ +#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ +#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ + +/* buttons may need refinement */ + +#define DIR_615C1_GPIO_BTN_WPS 12 +#define DIR_615C1_GPIO_BTN_RESET 21 + +#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL) + +#define DIR_615C1_CONFIG_ADDR 0x1f020000 +#define DIR_615C1_CONFIG_SIZE 0x10000 + +#define DIR_615C1_WLAN_MAC_ADDR 0x1f3fffb4 + +static struct gpio_led dir_615c1_leds_gpio[] __initdata = { + { + .name = "d-link:orange:status", + .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, { + .name = "d-link:green:wan", + .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, + .active_low = 1, + }, { + .name = "d-link:green:wancpu", + .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, + .active_low = 1, + }, { + .name = "d-link:green:wlan", + .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, + .active_low = 1, + }, { + .name = "d-link:green:status", + .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, + .active_low = 1, + }, { + .name = "d-link:orange:wan", + .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, + .active_low = 1, + } + +}; + +static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615C1_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615C1_GPIO_BTN_WPS, + } +}; + +#define DIR_615C1_LAN_PHYMASK BIT(0) +#define DIR_615C1_WAN_PHYMASK BIT(4) +#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ + DIR_615C1_WAN_PHYMASK)) + +static void __init dir_615c1_setup(void) +{ + const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[ETH_ALEN], wlan_mac[ETH_ALEN]; + + if (ath79_nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, + "lan_mac=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + } + + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615C1_WLAN_MAC_ADDR), wlan_mac); + + ath79_register_mdio(0, DIR_615C1_MDIO_MASK); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), + dir_615c1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_615c1_gpio_keys), + dir_615c1_gpio_keys); + + ath79_register_wmac(eeprom, wlan_mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", + dir_615c1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-i1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-i1.c new file mode 100644 index 0000000..64fe438 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-i1.c @@ -0,0 +1,133 @@ +/* + * D-Link DIR-615 rev. I1 board support + * Copyright (C) 2013-2015 Jaehoon You + * + * based on the DIR-600 rev. A1 board support code + * Copyright (C) 2010-2012 Gabor Juhos + * Copyright (C) 2012 Vadim Girlin + * + * based on the TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 board support code + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DIR_615_I1_GPIO_LED_WPS 15 +#define DIR_615_I1_GPIO_LED_POWER_AMBER 14 +#define DIR_615_I1_GPIO_LED_POWER_GREEN 4 +#define DIR_615_I1_GPIO_LED_WAN_AMBER 22 +#define DIR_615_I1_GPIO_LED_WAN_GREEN 12 +#define DIR_615_I1_GPIO_LED_WLAN_GREEN 13 + +#define DIR_615_I1_GPIO_BTN_WPS 16 +#define DIR_615_I1_GPIO_BTN_RESET 17 + +#define DIR_615_I1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_615_I1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_I1_KEYS_POLL_INTERVAL) + +#define DIR_615_I1_LAN_PHYMASK BIT(0) +#define DIR_615_I1_WAN_PHYMASK BIT(4) +#define DIR_615_I1_WLAN_MAC_ADDR 0x1fffffb4 + +static struct gpio_led dir_615_i1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_615_I1_GPIO_LED_POWER_GREEN, + }, { + .name = "d-link:amber:power", + .gpio = DIR_615_I1_GPIO_LED_POWER_AMBER, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_615_I1_GPIO_LED_WAN_AMBER, + }, { + .name = "d-link:green:wan", + .gpio = DIR_615_I1_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:green:wlan", + .gpio = DIR_615_I1_GPIO_LED_WLAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_615_I1_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_615_i1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_615_I1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615_I1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_615_I1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615_I1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_615_i1_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[ETH_ALEN]; + + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, ~(DIR_615_I1_WAN_PHYMASK)); + + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615_I1_WLAN_MAC_ADDR), mac); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = DIR_615_I1_WAN_PHYMASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_mask = DIR_615_I1_LAN_PHYMASK; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615_i1_leds_gpio), + dir_615_i1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_615_I1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_615_i1_gpio_keys), + dir_615_i1_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_I1, "DIR-615-I1", "D-Link DIR-615 rev. I1", + dir_615_i1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c new file mode 100644 index 0000000..9b82990 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c @@ -0,0 +1,191 @@ +/* + * D-Link DIR-825 rev. B1 board support + * + * Copyright (C) 2009-2011 Lukas Kuna, Evkanet, s.r.o. + * + * based on mach-wndr3700.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define DIR825B1_GPIO_LED_BLUE_USB 0 +#define DIR825B1_GPIO_LED_ORANGE_POWER 1 +#define DIR825B1_GPIO_LED_BLUE_POWER 2 +#define DIR825B1_GPIO_LED_BLUE_WPS 4 +#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 +#define DIR825B1_GPIO_LED_BLUE_PLANET 11 + +#define DIR825B1_GPIO_BTN_RESET 3 +#define DIR825B1_GPIO_BTN_WPS 8 + +#define DIR825B1_GPIO_RTL8366_SDA 5 +#define DIR825B1_GPIO_RTL8366_SCK 7 + +#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL) + +#define DIR825B1_CAL0_OFFSET 0x1000 +#define DIR825B1_CAL1_OFFSET 0x5000 +#define DIR825B1_MAC0_OFFSET 0xffa0 +#define DIR825B1_MAC1_OFFSET 0xffb4 + +#define DIR825B1_CAL_LOCATION_0 0x1f660000 +#define DIR825B1_CAL_LOCATION_1 0x1f7f0000 + +static struct gpio_led dir825b1_leds_gpio[] __initdata = { + { + .name = "d-link:blue:usb", + .gpio = DIR825B1_GPIO_LED_BLUE_USB, + .active_low = 1, + }, { + .name = "d-link:orange:power", + .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, + .active_low = 1, + }, { + .name = "d-link:blue:power", + .gpio = DIR825B1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR825B1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, { + .name = "d-link:orange:planet", + .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, + .active_low = 1, + }, { + .name = "d-link:blue:planet", + .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825B1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825B1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = { + { .reg = 0x06, .val = 0x0108 }, +}; + +static struct rtl8366_platform_data dir825b1_rtl8366s_data = { + .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, + .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, + .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals), + .initvals = dir825b1_rtl8366s_initvals, +}; + +static struct platform_device dir825b1_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &dir825b1_rtl8366s_data, + } +}; + +static bool __init dir825b1_is_caldata_valid(u8 *p) +{ + u16 *magic0, *magic1; + + magic0 = (u16 *)(p + DIR825B1_CAL0_OFFSET); + magic1 = (u16 *)(p + DIR825B1_CAL1_OFFSET); + + return (*magic0 == 0xa55a && *magic1 == 0xa55a); +} + +static void __init dir825b1_wlan_init(void) +{ + u8 *caldata; + u8 mac0[ETH_ALEN], mac1[ETH_ALEN]; + u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN]; + + caldata = (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0); + if (!dir825b1_is_caldata_valid(caldata)) { + caldata = (u8 *)KSEG1ADDR(DIR825B1_CAL_LOCATION_1); + if (!dir825b1_is_caldata_valid(caldata)) { + pr_err("no calibration data found\n"); + return; + } + } + + ath79_parse_ascii_mac(caldata + DIR825B1_MAC0_OFFSET, mac0); + ath79_parse_ascii_mac(caldata + DIR825B1_MAC1_OFFSET, mac1); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0); + ath79_init_mac(wmac0, mac0, 0); + ath79_init_mac(wmac1, mac1, 1); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(caldata + DIR825B1_CAL0_OFFSET, wmac0, + caldata + DIR825B1_CAL1_OFFSET, wmac1); +} + +static void __init dir825b1_setup(void) +{ + dir825b1_wlan_init(); + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x11110000; + + ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + ath79_eth1_pll_data.pll_1000 = 0x11110000; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), + dir825b1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir825b1_gpio_keys), + dir825b1_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&dir825b1_rtl8366s_device); +} + +MIPS_MACHINE(ATH79_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", + dir825b1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c new file mode 100644 index 0000000..9c4c1a8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c @@ -0,0 +1,241 @@ +/* + * D-Link DIR-825 rev. C1 board support + * + * Copyright (C) 2013 Alexander Stadler + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DIR825C1_GPIO_LED_BLUE_USB 11 +#define DIR825C1_GPIO_LED_AMBER_POWER 14 +#define DIR825C1_GPIO_LED_BLUE_POWER 22 +#define DIR825C1_GPIO_LED_BLUE_WPS 15 +#define DIR825C1_GPIO_LED_AMBER_PLANET 19 +#define DIR825C1_GPIO_LED_BLUE_PLANET 18 +#define DIR825C1_GPIO_LED_WLAN_2G 13 + +#define DIR825C1_GPIO_WAN_LED_ENABLE 20 + +#define DIR825C1_GPIO_BTN_RESET 17 +#define DIR825C1_GPIO_BTN_WPS 16 + +#define DIR825C1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR825C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825C1_KEYS_POLL_INTERVAL) + +#define DIR825C1_MAC0_OFFSET 0x4 +#define DIR825C1_MAC1_OFFSET 0x18 +#define DIR825C1_WMAC_CALDATA_OFFSET 0x1000 +#define DIR825C1_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dir825c1_leds_gpio[] __initdata = { + { + .name = "d-link:blue:usb", + .gpio = DIR825C1_GPIO_LED_BLUE_USB, + .active_low = 1, + }, + { + .name = "d-link:amber:power", + .gpio = DIR825C1_GPIO_LED_AMBER_POWER, + .active_low = 1, + }, + { + .name = "d-link:blue:power", + .gpio = DIR825C1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, + { + .name = "d-link:blue:wps", + .gpio = DIR825C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, + { + .name = "d-link:amber:planet", + .gpio = DIR825C1_GPIO_LED_AMBER_PLANET, + .active_low = 1, + }, + { + .name = "d-link:blue:wlan2g", + .gpio = DIR825C1_GPIO_LED_WLAN_2G, + .active_low = 1, + }, +}; + +static struct gpio_led dir835a1_leds_gpio[] __initdata = { + { + .name = "d-link:amber:power", + .gpio = DIR825C1_GPIO_LED_AMBER_POWER, + .active_low = 1, + }, + { + .name = "d-link:green:power", + .gpio = DIR825C1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, + { + .name = "d-link:blue:wps", + .gpio = DIR825C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, + { + .name = "d-link:amber:planet", + .gpio = DIR825C1_GPIO_LED_AMBER_PLANET, + .active_low = 1, + }, + { + .name = "d-link:green:planet", + .gpio = DIR825C1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = { + { + .desc = "Soft reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825C1_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825C1_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data dir825c1_ar8327_data = { + .pad0_cfg = &dir825c1_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &dir825c1_ar8327_led_cfg, +}; + +static struct mdio_board_info dir825c1_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dir825c1_ar8327_data, + }, +}; + +static void __init dir825c1_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 mac0[ETH_ALEN], mac1[ETH_ALEN]; + u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN]; + + ath79_parse_ascii_mac(mac + DIR825C1_MAC0_OFFSET, mac0); + ath79_parse_ascii_mac(mac + DIR825C1_MAC1_OFFSET, mac1); + + ath79_register_m25p80(NULL); + + ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir825c1_gpio_keys), + dir825c1_gpio_keys); + + ath79_init_mac(wmac0, mac0, 0); + ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, wmac0); + + ath79_init_mac(wmac1, mac1, 1); + ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, wmac1); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(dir825c1_mdio0_info, + ARRAY_SIZE(dir825c1_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_register_usb(); +} + +static void __init dir825c1_setup(void) +{ + ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, + AR934X_GPIO_OUT_GPIO); + + gpio_request_one(DIR825C1_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio), + dir825c1_leds_gpio); + + ap9x_pci_setup_wmac_led_pin(0, 0); + + dir825c1_generic_setup(); +} + +static void __init dir835a1_setup(void) +{ + dir825c1_ar8327_data.led_cfg = NULL; + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir835a1_leds_gpio), + dir835a1_leds_gpio); + + dir825c1_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1", + "D-Link DIR-825 rev. C1", + dir825c1_setup); + +MIPS_MACHINE(ATH79_MACH_DIR_835_A1, "DIR-835-A1", + "D-Link DIR-835 rev. A1", + dir835a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c new file mode 100644 index 0000000..03b9f19 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c @@ -0,0 +1,189 @@ +/* + * devolo dLAN pro 500 Wireless+ support + * + * Copyright (c) 2013-2015 devolo AG + * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE 13 +#define DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE 21 +#define DLAN_PRO_1200_AC_GPIO_LED_WLAN 12 +#define DLAN_PRO_1200_AC_GPIO_LED_DLAN 14 +#define DLAN_PRO_1200_AC_GPIO_LED_DLAN_ERR 15 + +#define DLAN_PRO_1200_AC_GPIO_BTN_WLAN 20 +#define DLAN_PRO_1200_AC_GPIO_BTN_DLAN 22 +#define DLAN_PRO_1200_AC_GPIO_BTN_RESET 4 +#define DLAN_PRO_1200_AC_GPIO_DLAN_IND 17 +#define DLAN_PRO_1200_AC_GPIO_DLAN_ERR_IND 16 + +#define DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL) + +#define DLAN_PRO_1200_AC_ART_ADDRESS 0x1fff0000 +#define DLAN_PRO_1200_AC_CALDATA_OFFSET 0x1000 +#define DLAN_PRO_1200_AC_WIFIMAC_OFFSET 0x1002 +#define DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dlan_pro_1200_ac_leds_gpio[] __initdata = { + { + .name = "devolo:status:wlan", + .gpio = DLAN_PRO_1200_AC_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "devolo:status:dlan", + .gpio = DLAN_PRO_1200_AC_GPIO_LED_DLAN, + .active_low = 1, + }, + { + .name = "devolo:error:dlan", + .gpio = DLAN_PRO_1200_AC_GPIO_LED_DLAN_ERR, + .active_low = 0, + } +}; + +static struct gpio_keys_button dlan_pro_1200_ac_gpio_keys[] __initdata = { + { + .desc = "dLAN button", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_DLAN, + .active_low = 1, + }, + { + .desc = "WLAN button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_WLAN, + .active_low = 0, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg dlan_pro_1200_ac_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = false, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_pad_cfg dlan_pro_1200_ac_ar8327_pad5_cfg = { + .mode = 0, + .txclk_delay_en = 0, + .rxclk_delay_en = 0, + .txclk_delay_sel = 0, + .rxclk_delay_sel = 0, +}; + +static struct ar8327_platform_data dlan_pro_1200_ac_ar8327_data = { + .pad0_cfg = &dlan_pro_1200_ac_ar8327_pad0_cfg, + .pad5_cfg = &dlan_pro_1200_ac_ar8327_pad5_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info dlan_pro_1200_ac_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dlan_pro_1200_ac_ar8327_data, + }, +}; + +static void __init dlan_pro_1200_ac_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_1200_AC_ART_ADDRESS); + u8 *cal = art + DLAN_PRO_1200_AC_CALDATA_OFFSET; + u8 *wifi_mac = art + DLAN_PRO_1200_AC_WIFIMAC_OFFSET; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_1200_ac_leds_gpio), + dlan_pro_1200_ac_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dlan_pro_1200_ac_gpio_keys), + dlan_pro_1200_ac_gpio_keys); + + /* dLAN power must be enabled from user-space as soon as the boot-from-host daemon is running */ + gpio_request_one(DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "dLAN power"); + + /* WLAN power is turned on initially to allow the PCI bus scan to succeed */ + gpio_request_one(DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "WLAN power"); + + ath79_register_wmac(cal, wifi_mac); + ap91_pci_init(art + DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET, NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2); + + mdiobus_register_board_info(dlan_pro_1200_ac_mdio0_info, + ARRAY_SIZE(dlan_pro_1200_ac_mdio0_info)); + + /* GMAC0 is connected to an AR8337 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x02000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_DLAN_PRO_1200_AC, "dLAN-pro-1200-ac", "devolo dLAN pro 1200+ WiFi ac", + dlan_pro_1200_ac_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c new file mode 100644 index 0000000..ae6f443 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c @@ -0,0 +1,203 @@ +/* + * devolo dLAN pro 500 Wireless+ support + * + * Copyright (c) 2013-2015 devolo AG + * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DLAN_PRO_500_WP_GPIO_DLAN_POWER_ENABLE 13 +#define DLAN_PRO_500_WP_GPIO_DLAN_LED_ENABLE 17 +#define DLAN_PRO_500_WP_GPIO_LED_WLAN_5G 11 +#define DLAN_PRO_500_WP_GPIO_LED_WLAN_2G 12 +#define DLAN_PRO_500_WP_GPIO_LED_STATUS 16 +#define DLAN_PRO_500_WP_GPIO_LED_ETH 14 + +#define DLAN_PRO_500_WP_GPIO_BTN_WPS 20 +#define DLAN_PRO_500_WP_GPIO_BTN_WLAN 22 +#define DLAN_PRO_500_WP_GPIO_BTN_DLAN 21 +#define DLAN_PRO_500_WP_GPIO_BTN_RESET 4 + +#define DLAN_PRO_500_WP_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_PRO_500_WP_KEYS_POLL_INTERVAL) + +#define DLAN_PRO_500_WP_ART_ADDRESS 0x1fff0000 +#define DLAN_PRO_500_WP_CALDATA_OFFSET 0x1000 +#define DLAN_PRO_500_WP_MAC_ADDRESS_OFFSET 0x1002 +#define DLAN_PRO_500_WP_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dlan_pro_500_wp_leds_gpio[] __initdata = { + { + .name = "devolo:green:status", + .gpio = DLAN_PRO_500_WP_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "devolo:green:eth", + .gpio = DLAN_PRO_500_WP_GPIO_LED_ETH, + .active_low = 1, + }, + { + .name = "devolo:blue:wlan-5g", + .gpio = DLAN_PRO_500_WP_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "devolo:green:wlan-2g", + .gpio = DLAN_PRO_500_WP_GPIO_LED_WLAN_2G, + .active_low = 1, + } +}; + +static struct gpio_keys_button dlan_pro_500_wp_gpio_keys[] __initdata = { + { + .desc = "dLAN button", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_DLAN, + .active_low = 0, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "WLAN button", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_WLAN, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg dlan_pro_500_wp_ar8327_pad0_cfg = { + .mode = AR8327_PAD_PHY_RGMII, + .txclk_delay_en = false, + .rxclk_delay_en = false, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL0, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_led_cfg dlan_pro_500_wp_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data dlan_pro_500_wp_ar8327_data = { + .pad0_cfg = &dlan_pro_500_wp_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 0, + .rxpause = 0, + }, + .led_cfg = &dlan_pro_500_wp_ar8327_led_cfg, +}; + +static struct mdio_board_info dlan_pro_500_wp_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dlan_pro_500_wp_ar8327_data, + }, +}; + +static void __init dlan_pro_500_wp_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_500_WP_ART_ADDRESS); + u8 *cal = art + DLAN_PRO_500_WP_CALDATA_OFFSET; + u8 *wifi_mac = art + DLAN_PRO_500_WP_MAC_ADDRESS_OFFSET; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_500_wp_leds_gpio), + dlan_pro_500_wp_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DLAN_PRO_500_WP_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dlan_pro_500_wp_gpio_keys), + dlan_pro_500_wp_gpio_keys); + + gpio_request_one(DLAN_PRO_500_WP_GPIO_DLAN_POWER_ENABLE, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "PLC power"); + gpio_request_one(DLAN_PRO_500_WP_GPIO_DLAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "PLC LEDs"); + + ath79_register_wmac(cal, wifi_mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(dlan_pro_500_wp_mdio0_info, + ARRAY_SIZE(dlan_pro_500_wp_mdio0_info)); + + /* GMAC0 is connected to a AR7400 PLC in PHY mode */ + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_pll_data.pll_1000 = 0x0e000000; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, wifi_mac, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_DLAN_PRO_500_WP, "dLAN-pro-500-wp", "devolo dLAN pro 500 Wireless+", + dlan_pro_500_wp_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dragino2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dragino2.c new file mode 100644 index 0000000..95bd6f4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dragino2.c @@ -0,0 +1,136 @@ +/* + * DRAGINO V2 board support, based on Atheros AP121 board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2012 Elektra Wagenrad + * Copyright (C) 2014 Vittorio Gambaletta + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DRAGINO2_GPIO_LED_WLAN 0 +#define DRAGINO2_GPIO_LED_LAN 13 +#define DRAGINO2_GPIO_LED_WAN 17 + +/* + * The following GPIO is named "SYS" on newer revisions of the the board. + * It was previously used to indicate USB activity, even though it was + * named "Router". + */ + +#define DRAGINO2_GPIO_LED_SYS 28 +#define DRAGINO2_GPIO_BTN_JUMPSTART 11 +#define DRAGINO2_GPIO_BTN_RESET 12 + +#define DRAGINO2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DRAGINO2_KEYS_DEBOUNCE_INTERVAL (3 * DRAGINO2_KEYS_POLL_INTERVAL) + +#define DRAGINO2_MAC0_OFFSET 0x0000 +#define DRAGINO2_MAC1_OFFSET 0x0006 +#define DRAGINO2_CALDATA_OFFSET 0x1000 +#define DRAGINO2_WMAC_MAC_OFFSET 0x1002 + +static struct gpio_led dragino2_leds_gpio[] __initdata = { + { + .name = "dragino2:red:wlan", + .gpio = DRAGINO2_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "dragino2:red:wan", + .gpio = DRAGINO2_GPIO_LED_WAN, + .active_low = 1, + }, + { + .name = "dragino2:red:lan", + .gpio = DRAGINO2_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "dragino2:red:system", + .gpio = DRAGINO2_GPIO_LED_SYS, + .active_low = 0, + }, +}; + +static struct gpio_keys_button dragino2_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DRAGINO2_KEYS_DEBOUNCE_INTERVAL, + .gpio = DRAGINO2_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DRAGINO2_KEYS_DEBOUNCE_INTERVAL, + .gpio = DRAGINO2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init dragino2_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art + DRAGINO2_CALDATA_OFFSET, + art + DRAGINO2_WMAC_MAC_OFFSET); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + DRAGINO2_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + DRAGINO2_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + /* Enable GPIO13, GPIO14, GPIO15, GPIO16 and GPIO17 */ + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + /* LAN port */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + /* Enable GPIO26 and GPIO27 */ + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, + ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) | + AR933X_BOOTSTRAP_MDIO_GPIO_EN); +} + +static void __init dragino2_setup(void) +{ + dragino2_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dragino2_leds_gpio), + dragino2_leds_gpio); + ath79_register_gpio_keys_polled(-1, DRAGINO2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dragino2_gpio_keys), + dragino2_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_DRAGINO2, "DRAGINO2", "Dragino Dragino v2", + dragino2_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-eap300v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap300v2.c new file mode 100644 index 0000000..ba577e2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap300v2.c @@ -0,0 +1,101 @@ +/* + * EnGenius EAP300 v2 board support + * + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define EAP300V2_GPIO_LED_POWER 0 +#define EAP300V2_GPIO_LED_LAN 16 +#define EAP300V2_GPIO_LED_WLAN 17 + +#define EAP300V2_GPIO_BTN_RESET 1 + +#define EAP300V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EAP300V2_KEYS_DEBOUNCE_INTERVAL (3 * EAP300V2_KEYS_POLL_INTERVAL) + +static struct gpio_led eap300v2_leds_gpio[] __initdata = { + { + .name = "engenius:blue:power", + .gpio = EAP300V2_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "engenius:blue:lan", + .gpio = EAP300V2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "engenius:blue:wlan", + .gpio = EAP300V2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button eap300v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EAP300V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP300V2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define EAP300V2_ART_MAC_OFFSET 2 + +#define EAP300V2_LAN_PHYMASK BIT(0) + +static void __init eap300v2_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + + ath79_gpio_output_select(EAP300V2_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(EAP300V2_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(EAP300V2_GPIO_LED_WLAN, AR934X_GPIO_OUT_GPIO); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap300v2_leds_gpio), + eap300v2_leds_gpio); + ath79_register_gpio_keys_polled(-1, EAP300V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(eap300v2_gpio_keys), + eap300v2_gpio_keys); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art, NULL); + ath79_register_mdio(1, 0x0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + EAP300V2_ART_MAC_OFFSET, 0); + + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = EAP300V2_LAN_PHYMASK; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = EAP300V2_LAN_PHYMASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_EAP300V2, "EAP300V2", "EnGenius EAP300 v2", + eap300v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c new file mode 100644 index 0000000..787e627 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c @@ -0,0 +1,181 @@ +/* + * Senao EAP7660D board support + * + * Copyright (C) 2010 Daniel Golle + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL) + +#define EAP7660D_GPIO_DS4 7 +#define EAP7660D_GPIO_DS5 2 +#define EAP7660D_GPIO_DS7 0 +#define EAP7660D_GPIO_DS8 4 +#define EAP7660D_GPIO_SW1 3 +#define EAP7660D_GPIO_SW3 8 +#define EAP7660D_PHYMASK BIT(20) +#define EAP7660D_BOARDCONFIG 0x1F7F0000 +#define EAP7660D_GBIC_MAC_OFFSET 0x1000 +#define EAP7660D_WMAC0_MAC_OFFSET 0x1010 +#define EAP7660D_WMAC1_MAC_OFFSET 0x1016 +#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000 +#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000 + +#ifdef CONFIG_PCI +static struct ath5k_platform_data eap7660d_wmac0_data; +static struct ath5k_platform_data eap7660d_wmac1_data; +static char eap7660d_wmac0_mac[6]; +static char eap7660d_wmac1_mac[6]; +static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; +static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; + +static int eap7660d_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 17: + dev->dev.platform_data = &eap7660d_wmac0_data; + break; + + case 18: + dev->dev.platform_data = &eap7660d_wmac1_data; + break; + } + + return 0; +} + +void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ + if (cal_data0 && *cal_data0 == 0xa55a) { + memcpy(eap7660d_wmac0_eeprom, cal_data0, + ATH5K_PLAT_EEP_MAX_WORDS); + eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom; + } + + if (cal_data1 && *cal_data1 == 0xa55a) { + memcpy(eap7660d_wmac1_eeprom, cal_data1, + ATH5K_PLAT_EEP_MAX_WORDS); + eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom; + } + + if (mac_addr0) { + memcpy(eap7660d_wmac0_mac, mac_addr0, + sizeof(eap7660d_wmac0_mac)); + eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac; + } + + if (mac_addr1) { + memcpy(eap7660d_wmac1_mac, mac_addr1, + sizeof(eap7660d_wmac1_mac)); + eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac; + } + + ath79_pci_set_plat_dev_init(eap7660d_pci_plat_dev_init); + ath79_register_pci(); +} +#else +static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ +} +#endif /* CONFIG_PCI */ + +static struct gpio_led eap7660d_leds_gpio[] __initdata = { + { + .name = "eap7660d:green:ds8", + .gpio = EAP7660D_GPIO_DS8, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds5", + .gpio = EAP7660D_GPIO_DS5, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds7", + .gpio = EAP7660D_GPIO_DS7, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds4", + .gpio = EAP7660D_GPIO_DS4, + .active_low = 0, + } +}; + +static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP7660D_GPIO_SW1, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP7660D_GPIO_SW3, + .active_low = 1, + } +}; + +static const char *eap7660d_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data eap7660d_flash_data = { + .part_probes = eap7660d_part_probes, +}; + +static void __init eap7660d_setup(void) +{ + u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG); + + ath79_register_mdio(0, ~EAP7660D_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, + boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = EAP7660D_PHYMASK; + ath79_register_eth(0); + ath79_register_m25p80(&eap7660d_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio), + eap7660d_leds_gpio); + ath79_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL, + ARRAY_SIZE(eap7660d_gpio_keys), + eap7660d_gpio_keys); + eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET, + boardconfig + EAP7660D_WMAC0_MAC_OFFSET, + boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET, + boardconfig + EAP7660D_WMAC1_MAC_OFFSET); +}; + +MIPS_MACHINE(ATH79_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D", + eap7660d_setup); + +MIPS_MACHINE(ATH79_MACH_ALL0305, "ALL0305", "Allnet ALL0305", + eap7660d_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-el-m150.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-m150.c new file mode 100644 index 0000000..b95d6c2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-m150.c @@ -0,0 +1,112 @@ +/* + * Easy-Link EL-M150 board support + * + * Copyright (C) 2012 huangfc + * Copyright (C) 2012 HYS <550663898@qq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define EL_M150_GPIO_BTN6 6 +#define EL_M150_GPIO_BTN7 7 +#define EL_M150_GPIO_BTN_RESET 11 + +#define EL_M150_GPIO_LED_SYSTEM 27 +#define EL_M150_GPIO_USB_POWER 8 + +#define EL_M150_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EL_M150_KEYS_DEBOUNCE_INTERVAL (3 * EL_M150_KEYS_POLL_INTERVAL) + +static const char *EL_M150_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data EL_M150_flash_data = { + .part_probes = EL_M150_part_probes, +}; + +static struct gpio_led EL_M150_leds_gpio[] __initdata = { + { + .name = "easylink:green:system", + .gpio = EL_M150_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button EL_M150_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL, + .gpio = EL_M150_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "BTN_6", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL, + .gpio = EL_M150_GPIO_BTN6, + .active_low = 1, + }, + { + .desc = "BTN_7", + .type = EV_KEY, + .code = BTN_7, + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL, + .gpio = EL_M150_GPIO_BTN7, + .active_low = 1, + }, +}; + +static void __init el_m150_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(EL_M150_leds_gpio), + EL_M150_leds_gpio); + + ath79_register_gpio_keys_polled(-1, EL_M150_KEYS_POLL_INTERVAL, + ARRAY_SIZE(EL_M150_gpio_keys), + EL_M150_gpio_keys); + + gpio_request_one(EL_M150_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&EL_M150_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_EL_M150, "EL-M150", + "EasyLink EL-M150", el_m150_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-el-mini.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-mini.c new file mode 100644 index 0000000..9879b18 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-mini.c @@ -0,0 +1,86 @@ +/* + * Easy-Link EL-MINI board support + * + * Copyright (C) 2012 huangfc + * Copyright (C) 2011 hys <550663898@qq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MINI_GPIO_LED_SYSTEM 27 +#define MINI_GPIO_BTN_RESET 11 + +#define MINI_GPIO_USB_POWER 8 + +#define MINI_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MINI_KEYS_DEBOUNCE_INTERVAL (3 * MINI_KEYS_POLL_INTERVAL) + +static const char *mini_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data mini_flash_data = { + .part_probes = mini_part_probes, +}; + +static struct gpio_led mini_leds_gpio[] __initdata = { + { + .name = "easylink:green:system", + .gpio = MINI_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mini_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MINI_KEYS_DEBOUNCE_INTERVAL, + .gpio = MINI_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init el_mini_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&mini_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mini_leds_gpio), + mini_leds_gpio); + ath79_register_gpio_keys_polled(-1, MINI_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mini_gpio_keys), + mini_gpio_keys); + + gpio_request_one(MINI_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_EL_MINI, "EL-MINI", "EasyLink EL-MINI", + el_mini_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c new file mode 100644 index 0000000..b049f5d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c @@ -0,0 +1,178 @@ +/* + * EnGenius EPG5000 board support + * + * Copyright (c) 2014 Jon Suphammer + * Copyright (c) 2015 Christian Beier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define EPG5000_GPIO_LED_WLAN_5G 23 +#define EPG5000_GPIO_LED_WLAN_2G 13 +#define EPG5000_GPIO_LED_POWER_AMBER 2 +#define EPG5000_GPIO_LED_WPS_AMBER 22 +#define EPG5000_GPIO_LED_WPS_BLUE 19 + +#define EPG5000_GPIO_BTN_WPS 16 +#define EPG5000_GPIO_BTN_RESET 17 + +#define EPG5000_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EPG5000_KEYS_DEBOUNCE_INTERVAL (3 * EPG5000_KEYS_POLL_INTERVAL) + +#define EPG5000_CALDATA_ADDR 0x1fff0000 +#define EPG5000_WMAC_CALDATA_OFFSET 0x1000 +#define EPG5000_PCIE_CALDATA_OFFSET 0x5000 + +#define EPG5000_NVRAM_ADDR 0x1f030000 +#define EPG5000_NVRAM_SIZE 0x10000 + +static struct gpio_led epg5000_leds_gpio[] __initdata = { + { + .name = "epg5000:amber:power", + .gpio = EPG5000_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "epg5000:blue:wps", + .gpio = EPG5000_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "epg5000:amber:wps", + .gpio = EPG5000_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "epg5000:blue:wlan-2g", + .gpio = EPG5000_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "epg5000:blue:wlan-5g", + .gpio = EPG5000_GPIO_LED_WLAN_5G, + .active_low = 1, + } +}; + +static struct gpio_keys_button epg5000_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = EPG5000_KEYS_DEBOUNCE_INTERVAL, + .gpio = EPG5000_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EPG5000_KEYS_DEBOUNCE_INTERVAL, + .gpio = EPG5000_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg epg5000_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_en = true, +}; + +static struct ar8327_platform_data epg5000_ar8327_data = { + .pad0_cfg = &epg5000_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info epg5000_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &epg5000_ar8327_data, + }, +}; + +static int epg5000_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(EPG5000_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, EPG5000_NVRAM_SIZE, + name, mac); + if (err) { + pr_err("no MAC address found for %s\n", name); + return false; + } + + return true; +} + +static void __init epg5000_setup(void) +{ + u8 *caldata = (u8 *) KSEG1ADDR(EPG5000_CALDATA_ADDR); + u8 mac1[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(epg5000_leds_gpio), + epg5000_leds_gpio); + ath79_register_gpio_keys_polled(-1, EPG5000_KEYS_POLL_INTERVAL, + ARRAY_SIZE(epg5000_gpio_keys), + epg5000_gpio_keys); + + ath79_register_usb(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(epg5000_mdio0_info, + ARRAY_SIZE(epg5000_mdio0_info)); + + /* GMAC0 is connected to an QCA8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + if (epg5000_get_mac("ethaddr=", mac1)) + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_register_eth(0); + + ath79_register_wmac(caldata + EPG5000_WMAC_CALDATA_OFFSET, mac1); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_EPG5000, "EPG5000", + "EnGenius EPG5000", + epg5000_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c new file mode 100644 index 0000000..d2bc177 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c @@ -0,0 +1,177 @@ +/* + * EnGenius ESR1750 board support + * + * Copyright (c) 2014 Jon Suphammer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define ESR1750_GPIO_LED_WLAN_5G 23 +#define ESR1750_GPIO_LED_WLAN_2G 13 +#define ESR1750_GPIO_LED_POWER_AMBER 2 +#define ESR1750_GPIO_LED_WPS_AMBER 22 +#define ESR1750_GPIO_LED_WPS_BLUE 19 + +#define ESR1750_GPIO_BTN_WPS 16 +#define ESR1750_GPIO_BTN_RESET 17 + +#define ESR1750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ESR1750_KEYS_DEBOUNCE_INTERVAL (3 * ESR1750_KEYS_POLL_INTERVAL) + +#define ESR1750_CALDATA_ADDR 0x1fff0000 +#define ESR1750_WMAC_CALDATA_OFFSET 0x1000 +#define ESR1750_PCIE_CALDATA_OFFSET 0x5000 + +#define ESR1750_NVRAM_ADDR 0x1f030000 +#define ESR1750_NVRAM_SIZE 0x10000 + +static struct gpio_led esr1750_leds_gpio[] __initdata = { + { + .name = "esr1750:amber:power", + .gpio = ESR1750_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "esr1750:blue:wps", + .gpio = ESR1750_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "esr1750:amber:wps", + .gpio = ESR1750_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "esr1750:blue:wlan-2g", + .gpio = ESR1750_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "esr1750:blue:wlan-5g", + .gpio = ESR1750_GPIO_LED_WLAN_5G, + .active_low = 1, + } +}; + +static struct gpio_keys_button esr1750_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ESR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR1750_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ESR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR1750_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg esr1750_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_en = true, +}; + +static struct ar8327_platform_data esr1750_ar8327_data = { + .pad0_cfg = &esr1750_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info esr1750_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &esr1750_ar8327_data, + }, +}; + +static int esr1750_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(ESR1750_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, ESR1750_NVRAM_SIZE, + name, mac); + if (err) { + pr_err("no MAC address found for %s\n", name); + return false; + } + + return true; +} + +static void __init esr1750_setup(void) +{ + u8 *caldata = (u8 *) KSEG1ADDR(ESR1750_CALDATA_ADDR); + u8 mac1[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(esr1750_leds_gpio), + esr1750_leds_gpio); + ath79_register_gpio_keys_polled(-1, ESR1750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(esr1750_gpio_keys), + esr1750_gpio_keys); + + ath79_register_usb(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(esr1750_mdio0_info, + ARRAY_SIZE(esr1750_mdio0_info)); + + /* GMAC0 is connected to an QCA8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + if (esr1750_get_mac("ethaddr=", mac1)) + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_register_eth(0); + + ath79_register_wmac(caldata + ESR1750_WMAC_CALDATA_OFFSET, mac1); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_ESR1750, "ESR1750", + "EnGenius ESR1750", + esr1750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c new file mode 100644 index 0000000..aa2e7f7 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c @@ -0,0 +1,200 @@ +/* + * EnGenius ESR900 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "esr900: " fmt + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define ESR900_GPIO_LED_POWER 2 +#define ESR900_GPIO_LED_WLAN_2G 13 +#define ESR900_GPIO_LED_WPS_BLUE 19 +#define ESR900_GPIO_LED_WPS_AMBER 22 +#define ESR900_GPIO_LED_WLAN_5G 23 + +#define ESR900_GPIO_BTN_WPS 16 +#define ESR900_GPIO_BTN_RESET 17 + +#define ESR900_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ESR900_KEYS_DEBOUNCE_INTERVAL (3 * ESR900_KEYS_POLL_INTERVAL) + +#define ESR900_CALDATA_ADDR 0x1fff0000 +#define ESR900_WMAC_CALDATA_OFFSET 0x1000 +#define ESR900_PCIE_CALDATA_OFFSET 0x5000 + +#define ESR900_CONFIG_ADDR 0x1f030000 +#define ESR900_CONFIG_SIZE 0x10000 + +#define ESR900_LAN_PHYMASK BIT(0) +#define ESR900_WAN_PHYMASK BIT(5) +#define ESR900_MDIO_MASK (~(ESR900_LAN_PHYMASK | ESR900_WAN_PHYMASK)) + +static struct gpio_led esr900_leds_gpio[] __initdata = { + { + .name = "engenius:amber:power", + .gpio = ESR900_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "engenius:blue:wlan-2g", + .gpio = ESR900_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "engenius:blue:wps", + .gpio = ESR900_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "engenius:amber:wps", + .gpio = ESR900_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "engenius:blue:wlan-5g", + .gpio = ESR900_GPIO_LED_WLAN_5G, + .active_low = 1, + } +}; + +static struct gpio_keys_button esr900_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR900_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR900_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg esr900_ar8327_pad0_cfg = { + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_pad_cfg esr900_ar8327_pad6_cfg = { + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ + .mode = AR8327_PAD_MAC_SGMII, + .rxclk_delay_en = true, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_platform_data esr900_ar8327_data = { + .pad0_cfg = &esr900_ar8327_pad0_cfg, + .pad6_cfg = &esr900_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info esr900_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &esr900_ar8327_data, + }, +}; + +static void __init esr900_setup(void) +{ + const char *config = (char *) KSEG1ADDR(ESR900_CONFIG_ADDR); + u8 *art = (u8 *) KSEG1ADDR(ESR900_CALDATA_ADDR); + u8 lan_mac[ETH_ALEN]; + u8 wlan0_mac[ETH_ALEN]; + u8 wlan1_mac[ETH_ALEN]; + + if (ath79_nvram_parse_mac_addr(config, ESR900_CONFIG_SIZE, + "ethaddr=", lan_mac) == 0) { + ath79_init_local_mac(ath79_eth0_data.mac_addr, lan_mac); + ath79_init_mac(wlan0_mac, lan_mac, 0); + ath79_init_mac(wlan1_mac, lan_mac, 1); + } else { + pr_err("could not find ethaddr in u-boot environment\n"); + } + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(esr900_leds_gpio), + esr900_leds_gpio); + ath79_register_gpio_keys_polled(-1, ESR900_KEYS_POLL_INTERVAL, + ARRAY_SIZE(esr900_gpio_keys), + esr900_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(esr900_mdio0_info, + ARRAY_SIZE(esr900_mdio0_info)); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = ESR900_LAN_PHYMASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_eth1_pll_data.pll_1000 = 0x03000101; + ath79_register_eth(1); + + ap91_pci_init(art + ESR900_PCIE_CALDATA_OFFSET, wlan1_mac); +} + +MIPS_MACHINE(ATH79_MACH_ESR900, "ESR900", "EnGenius ESR900", esr900_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c new file mode 100644 index 0000000..e686b5f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c @@ -0,0 +1,150 @@ +/* + * EW Dorin board support + * (based on Atheros Ref. Design AP121) + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2012-2015 Embedded Wireless GmbH www.80211.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DORIN_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DORIN_KEYS_DEBOUNCE_INTERVAL (3 * DORIN_KEYS_POLL_INTERVAL) + +#define DORIN_CALDATA_OFFSET 0x1000 +#define DORIN_WMAC_MAC_OFFSET 0x1002 + +#define DORIN_GPIO_LED_21 21 +#define DORIN_GPIO_LED_22 22 +#define DORIN_GPIO_LED_STATUS 23 + +#define DORIN_GPIO_BTN_JUMPSTART 11 +#define DORIN_GPIO_BTN_RESET 6 + +static struct gpio_led dorin_leds_gpio[] __initdata = { + { + .name = "dorin:green:led21", + .gpio = DORIN_GPIO_LED_21, + .active_low = 1, + }, + { + .name = "dorin:green:led22", + .gpio = DORIN_GPIO_LED_22, + .active_low = 1, + }, + { + .name = "dorin:green:status", + .gpio = DORIN_GPIO_LED_STATUS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dorin_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL, + .gpio = DORIN_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL, + .gpio = DORIN_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init ew_dorin_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + static u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + if (ar93xx_wmac_read_mac_address(mac)) { + ath79_register_wmac(NULL, NULL); + } else { + ath79_register_wmac(art + DORIN_CALDATA_OFFSET, + art + DORIN_WMAC_MAC_OFFSET); + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac)); + } + + mac[3] |= 0x40; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio), + dorin_leds_gpio); + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dorin_gpio_keys), + dorin_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_EW_DORIN, "EW-DORIN", "EmbWir-Dorin", + ew_dorin_setup); + + +static void __init ew_dorin_router_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + static u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + if (ar93xx_wmac_read_mac_address(mac)) { + ath79_register_wmac(NULL, NULL); + } else { + ath79_register_wmac(art + DORIN_CALDATA_OFFSET, + art + DORIN_WMAC_MAC_OFFSET); + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac)); + } + + mac[3] |= 0x40; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + mac[3] &= 0x3F; + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio), + dorin_leds_gpio); + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dorin_gpio_keys), + dorin_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_EW_DORIN_ROUTER, "EW-DORIN-ROUTER", + "EmbWir-Dorin-Router", ew_dorin_router_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c new file mode 100644 index 0000000..9e86e9a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c @@ -0,0 +1,190 @@ +/* + * Belkin AC1750DB (F9K1115V2) board support + * + * Copyright (C) 2014 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define F9K1115V2_GPIO_LED_USB2 4 +#define F9K1115V2_GPIO_LED_WPS_AMBER 14 +#define F9K1115V2_GPIO_LED_STATUS_AMBER 15 +#define F9K1115V2_GPIO_LED_WPS_BLUE 19 +#define F9K1115V2_GPIO_LED_STATUS_BLUE 20 + +#define F9K1115V2_GPIO_BTN_WPS 16 +#define F9K1115V2_GPIO_BTN_RESET 17 + +#define F9K1115V2_GPIO_USB2_POWER 21 + +#define F9K1115V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define F9K1115V2_KEYS_DEBOUNCE_INTERVAL (3 * F9K1115V2_KEYS_POLL_INTERVAL) + +#define F9K1115V2_WAN_MAC_OFFSET 0 +#define F9K1115V2_LAN_MAC_OFFSET 6 +#define F9K1115V2_WMAC_CALDATA_OFFSET 0x1000 +#define F9K1115V2_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led f9k1115v2_leds_gpio[] __initdata = { + { + .name = "belkin:amber:status", + .gpio = F9K1115V2_GPIO_LED_STATUS_AMBER, + .active_low = 1, + }, + { + .name = "belkin:blue:status", + .gpio = F9K1115V2_GPIO_LED_STATUS_BLUE, + .active_low = 1, + }, + { + .name = "belkin:blue:wps", + .gpio = F9K1115V2_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "belkin:amber:wps", + .gpio = F9K1115V2_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "belkin:green:usb2", + .gpio = F9K1115V2_GPIO_LED_USB2, + .active_low = 1, + }, +}; + +static struct gpio_keys_button f9k1115v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = F9K1115V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = F9K1115V2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = F9K1115V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = F9K1115V2_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg f9k1115v2_ar8327_pad0_cfg = { + /* Use the RGMII interface for the GMAC0 of the AR8337 switch */ + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_en = true, +}; + +static struct ar8327_pad_cfg f9k1115v2_ar8327_pad6_cfg = { + /* Use the SGMII interface for the GMAC6 of the AR8337 switch */ + .mode = AR8327_PAD_MAC_SGMII, + .rxclk_delay_en = true, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_platform_data f9k1115v2_ar8327_data = { + .pad0_cfg = &f9k1115v2_ar8327_pad0_cfg, + .pad6_cfg = &f9k1115v2_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info f9k1115v2_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &f9k1115v2_ar8327_data, + }, +}; + +static void __init f9k1115v2_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(f9k1115v2_leds_gpio), + f9k1115v2_leds_gpio); + ath79_register_gpio_keys_polled(-1, F9K1115V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(f9k1115v2_gpio_keys), + f9k1115v2_gpio_keys); + + ath79_register_wmac(art + F9K1115V2_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(f9k1115v2_mdio0_info, + ARRAY_SIZE(f9k1115v2_mdio0_info)); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + F9K1115V2_WAN_MAC_OFFSET, 0); + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + F9K1115V2_LAN_MAC_OFFSET, 0); + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); + + ath79_register_pci(); + + ath79_register_usb(); + gpio_request_one(F9K1115V2_GPIO_USB2_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB2 power"); +} + +MIPS_MACHINE(ATH79_MACH_F9K1115V2, "F9K1115V2", "Belkin AC1750DB", + f9k1115v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-gl-inet.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-gl-inet.c new file mode 100644 index 0000000..0713f14 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-gl-inet.c @@ -0,0 +1,104 @@ +/* + * GL-CONNECT iNet board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2013 alzhao + * Copyright (C) 2014 Michel Stempin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define GL_INET_GPIO_LED_WLAN 0 +#define GL_INET_GPIO_LED_LAN 13 +#define GL_INET_GPIO_BTN_RESET 11 + +#define GL_INET_KEYS_POLL_INTERVAL 20 /* msecs */ +#define GL_INET_KEYS_DEBOUNCE_INTERVAL (3 * GL_INET_KEYS_POLL_INTERVAL) + +static const char * gl_inet_part_probes[] = { + "tp-link", /* dont change, this will use tplink parser */ + NULL , +}; + +static struct flash_platform_data gl_inet_flash_data = { + .part_probes = gl_inet_part_probes, +}; + +static struct gpio_led gl_inet_leds_gpio[] __initdata = { + { + .name = "gl-connect:red:wlan", + .gpio = GL_INET_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "gl-connect:green:lan", + .gpio = GL_INET_GPIO_LED_LAN, + .active_low = 0, + .default_state = 1, + }, +}; + +static struct gpio_keys_button gl_inet_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = GL_INET_KEYS_DEBOUNCE_INTERVAL, + .gpio = GL_INET_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init gl_inet_setup(void) +{ + /* get the mac address which is stored in the 1st 64k uboot MTD */ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + /* get the art address, which is the last 64K. By using + 0x1fff1000, it doesn't matter it is 4M, 8M or 16M flash */ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + /* register flash. MTD will use tp-link parser to parser MTD */ + ath79_register_m25p80(&gl_inet_flash_data); + + /* register gpio LEDs and keys */ + ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_inet_leds_gpio), + gl_inet_leds_gpio); + ath79_register_gpio_keys_polled(-1, GL_INET_KEYS_POLL_INTERVAL, + ARRAY_SIZE(gl_inet_gpio_keys), + gl_inet_gpio_keys); + + /* enable usb */ + ath79_register_usb(); + + /* register eth0 as WAN, eth1 as LAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + /* register wireless mac with cal data */ + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_GL_INET, "GL-INET", "GL-CONNECT INET v1", + gl_inet_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-oolite.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-oolite.c new file mode 100644 index 0000000..c6cb61c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-oolite.c @@ -0,0 +1,103 @@ +/* + * Oolite board support + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define GS_OOLITE_GPIO_BTN6 6 +#define GS_OOLITE_GPIO_BTN7 7 +#define GS_OOLITE_GPIO_BTN_RESET 11 + +#define GS_OOLITE_GPIO_LED_SYSTEM 27 + +#define GS_OOLITE_KEYS_POLL_INTERVAL 20 /* msecs */ +#define GS_OOLITE_KEYS_DEBOUNCE_INTERVAL (3 * GS_OOLITE_KEYS_POLL_INTERVAL) + +static const char *gs_oolite_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data gs_oolite_flash_data = { + .part_probes = gs_oolite_part_probes, +}; + +static struct gpio_led gs_oolite_leds_gpio[] __initdata = { + { + .name = "oolite:red:system", + .gpio = GS_OOLITE_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button gs_oolite_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_OOLITE_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "BTN_6", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_OOLITE_GPIO_BTN6, + .active_low = 0, + }, + { + .desc = "BTN_7", + .type = EV_KEY, + .code = BTN_7, + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_OOLITE_GPIO_BTN7, + .active_low = 0, + }, +}; + +static void __init gs_oolite_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(gs_oolite_leds_gpio), + gs_oolite_leds_gpio); + + ath79_register_gpio_keys_polled(-1, GS_OOLITE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(gs_oolite_gpio_keys), + gs_oolite_gpio_keys); + + ath79_register_usb(); + + ath79_register_m25p80(&gs_oolite_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_GS_OOLITE, "GS-OOLITE", + "Oolite V1.0", gs_oolite_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-hiwifi-hc6361.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-hiwifi-hc6361.c new file mode 100644 index 0000000..6600595 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-hiwifi-hc6361.c @@ -0,0 +1,115 @@ +/* + * HiWiFi HC6361 board support + * + * Copyright (C) 2012-2013 eric + * Copyright (C) 2014 Yousong Zhou + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define HIWIFI_HC6361_GPIO_LED_WLAN_2P4 0 /* 2.4G WLAN LED */ +#define HIWIFI_HC6361_GPIO_LED_SYSTEM 1 /* System LED */ +#define HIWIFI_HC6361_GPIO_LED_INTERNET 27 /* Internet LED */ + +#define HIWIFI_HC6361_GPIO_USBPOWER 20 /* USB power control */ +#define HIWIFI_HC6361_GPIO_BTN_RST 11 /* Reset button */ + +#define HIWIFI_HC6361_KEYS_POLL_INTERVAL 20 /* msecs */ +#define HIWIFI_HC6361_KEYS_DEBOUNCE_INTERVAL \ + (3 * HIWIFI_HC6361_KEYS_POLL_INTERVAL) + +static struct gpio_led hiwifi_leds_gpio[] __initdata = { + { + .name = "hiwifi:blue:wlan-2p4", + .gpio = HIWIFI_HC6361_GPIO_LED_WLAN_2P4, + .active_low = 1, + }, { + .name = "hiwifi:blue:system", + .gpio = HIWIFI_HC6361_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "hiwifi:blue:internet", + .gpio = HIWIFI_HC6361_GPIO_LED_INTERNET, + .active_low = 1, + } +}; + +static struct gpio_keys_button hiwifi_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = HIWIFI_HC6361_KEYS_DEBOUNCE_INTERVAL, + .gpio = HIWIFI_HC6361_GPIO_BTN_RST, + .active_low = 1, + } +}; + +static void __init get_mac_from_bdinfo(u8 *mac, void *bdinfo) +{ + if (sscanf(bdinfo, "fac_mac = %2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx", + &mac[0], &mac[1], &mac[2], &mac[3], + &mac[4], &mac[5]) == 6) { + return; + } + + printk(KERN_WARNING "Parsing MAC address failed.\n"); + memcpy(mac, "\x00\xba\xbe\x00\x00\x00", 6); +} + +static void __init hiwifi_hc6361_setup(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(NULL); + ath79_gpio_function_enable( + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(hiwifi_leds_gpio), + hiwifi_leds_gpio); + ath79_register_gpio_keys_polled(-1, HIWIFI_HC6361_KEYS_POLL_INTERVAL, + ARRAY_SIZE(hiwifi_gpio_keys), + hiwifi_gpio_keys); + gpio_request_one(HIWIFI_HC6361_GPIO_USBPOWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + get_mac_from_bdinfo(mac, (void *) KSEG1ADDR(0x1f010180)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_HIWIFI_HC6361, "HiWiFi-HC6361", + "HiWiFi HC6361", hiwifi_hc6361_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c new file mode 100644 index 0000000..1d21424 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c @@ -0,0 +1,142 @@ +/* + * ALFA NETWORK Hornet-UB board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define HORNET_UB_GPIO_LED_WLAN 0 +#define HORNET_UB_GPIO_LED_USB 1 +#define HORNET_UB_GPIO_LED_LAN 13 +#define HORNET_UB_GPIO_LED_WAN 17 +#define HORNET_UB_GPIO_LED_WPS 27 +#define HORNET_UB_GPIO_EXT_LNA 28 + +#define HORNET_UB_GPIO_BTN_RESET 12 +#define HORNET_UB_GPIO_BTN_WPS 11 + +#define HORNET_UB_GPIO_USB_POWER 26 + +#define HORNET_UB_KEYS_POLL_INTERVAL 20 /* msecs */ +#define HORNET_UB_KEYS_DEBOUNCE_INTERVAL (3 * HORNET_UB_KEYS_POLL_INTERVAL) + +#define HORNET_UB_MAC0_OFFSET 0x0000 +#define HORNET_UB_MAC1_OFFSET 0x0006 +#define HORNET_UB_CALDATA_OFFSET 0x1000 + +static struct gpio_led hornet_ub_leds_gpio[] __initdata = { + { + .name = "alfa:blue:lan", + .gpio = HORNET_UB_GPIO_LED_LAN, + .active_low = 0, + }, + { + .name = "alfa:blue:usb", + .gpio = HORNET_UB_GPIO_LED_USB, + .active_low = 0, + }, + { + .name = "alfa:blue:wan", + .gpio = HORNET_UB_GPIO_LED_WAN, + .active_low = 1, + }, + { + .name = "alfa:blue:wlan", + .gpio = HORNET_UB_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "alfa:blue:wps", + .gpio = HORNET_UB_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button hornet_ub_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL, + .gpio = HORNET_UB_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL, + .gpio = HORNET_UB_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init hornet_ub_gpio_setup(void) +{ + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + gpio_request_one(HORNET_UB_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + gpio_request_one(HORNET_UB_GPIO_EXT_LNA, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "external LNA0"); + +} + +static void __init hornet_ub_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + hornet_ub_gpio_setup(); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio), + hornet_ub_leds_gpio); + ath79_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL, + ARRAY_SIZE(hornet_ub_gpio_keys), + hornet_ub_gpio_keys); + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + HORNET_UB_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, + art + HORNET_UB_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_HORNET_UB, "HORNET-UB", "ALFA NETWORK Hornet-UB", + hornet_ub_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c new file mode 100644 index 0000000..d1fe0f8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c @@ -0,0 +1,190 @@ +/* + * jjPlus JA76PF board support + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */ +#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL) + +#define JA76PF_GPIO_I2C_SCL 0 +#define JA76PF_GPIO_I2C_SDA 1 +#define JA76PF_GPIO_LED_1 5 +#define JA76PF_GPIO_LED_2 4 +#define JA76PF_GPIO_LED_3 3 +#define JA76PF_GPIO_BTN_RESET 11 + +static struct gpio_led ja76pf_leds_gpio[] __initdata = { + { + .name = "jjplus:green:led1", + .gpio = JA76PF_GPIO_LED_1, + .active_low = 1, + }, { + .name = "jjplus:green:led2", + .gpio = JA76PF_GPIO_LED_2, + .active_low = 1, + }, { + .name = "jjplus:green:led3", + .gpio = JA76PF_GPIO_LED_3, + .active_low = 1, + } +}; + +static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = { + .sda_pin = JA76PF_GPIO_I2C_SDA, + .scl_pin = JA76PF_GPIO_I2C_SCL, +}; + +static struct platform_device ja76pf_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &ja76pf_i2c_gpio_data, + } +}; + +static const char *ja76pf_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data ja76pf_flash_data = { + .part_probes = ja76pf_part_probes, +}; + +#define JA76PF_WAN_PHYMASK (1 << 4) +#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3)) +#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK) + +static void __init ja76pf_init(void) +{ + ath79_register_m25p80(&ja76pf_flash_data); + + ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + platform_device_register(&ja76pf_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio), + ja76pf_leds_gpio); + + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ja76pf_gpio_keys), + ja76pf_gpio_keys); + + ath79_register_usb(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init); + +#define JA76PF2_GPIO_LED_D2 5 +#define JA76PF2_GPIO_LED_D3 4 +#define JA76PF2_GPIO_LED_D4 3 +#define JA76PF2_GPIO_BTN_RESET 7 +#define JA76PF2_GPIO_BTN_WPS 8 + +static struct gpio_led ja76pf2_leds_gpio[] __initdata = { + { + .name = "jjplus:green:led1", + .gpio = JA76PF2_GPIO_LED_D2, + .active_low = 1, + }, { + .name = "jjplus:green:led2", + .gpio = JA76PF2_GPIO_LED_D3, + .active_low = 0, + }, { + .name = "jjplus:green:led3", + .gpio = JA76PF2_GPIO_LED_D4, + .active_low = 0, + } +}; + +static struct gpio_keys_button ja76pf2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF2_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +#define JA76PF2_LAN_PHYMASK BIT(0) +#define JA76PF2_WAN_PHYMASK BIT(4) +#define JA76PF2_MDIO_PHYMASK (JA76PF2_LAN_PHYMASK | JA76PF2_WAN_PHYMASK) + +static void __init ja76pf2_init(void) +{ + ath79_register_m25p80(&ja76pf_flash_data); + + ath79_register_mdio(0, ~JA76PF2_MDIO_PHYMASK); + + /* MAC0 is connected to the CPU port of the AR8316 switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + /* MAC1 is connected to the PHY4 of the AR8316 switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf2_leds_gpio), + ja76pf2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ja76pf2_gpio_keys), + ja76pf2_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JA76PF2, "JA76PF2", "jjPlus JA76PF2", ja76pf2_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c new file mode 100644 index 0000000..a3c93cc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c @@ -0,0 +1,95 @@ +/* + * jjPlus JWAP003 board support + * + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */ +#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL) + +#define JWAP003_GPIO_WPS 11 +#define JWAP003_GPIO_I2C_SCL 0 +#define JWAP003_GPIO_I2C_SDA 1 + +static struct gpio_keys_button jwap003_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL, + .gpio = JWAP003_GPIO_WPS, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = { + .sda_pin = JWAP003_GPIO_I2C_SDA, + .scl_pin = JWAP003_GPIO_I2C_SCL, +}; + +static struct platform_device jwap003_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &jwap003_i2c_gpio_data, + } +}; + +static const char *jwap003_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data jwap003_flash_data = { + .part_probes = jwap003_part_probes, +}; + +#define JWAP003_WAN_PHYMASK BIT(0) +#define JWAP003_LAN_PHYMASK BIT(4) + +static void __init jwap003_init(void) +{ + ath79_register_m25p80(&jwap003_flash_data); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = JWAP003_WAN_PHYMASK; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = JWAP003_LAN_PHYMASK; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + platform_device_register(&jwap003_i2c_gpio_device); + + ath79_register_usb(); + + ath79_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL, + ARRAY_SIZE(jwap003_gpio_keys), + jwap003_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mc-mac1200r.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mc-mac1200r.c new file mode 100644 index 0000000..70051cf --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mc-mac1200r.c @@ -0,0 +1,155 @@ +/* + * MERCURY MAC1200R board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Gui Iribarren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MAC1200R_GPIO_LED_WLAN2G 13 +#define MAC1200R_GPIO_LED_WLAN5G 17 +#define MAC1200R_GPIO_LED_SYSTEM 14 +#define MAC1200R_GPIO_LED_WPS 11 +#define MAC1200R_GPIO_LED_WAN 12 +#define MAC1200R_GPIO_LED_LAN1 15 +#define MAC1200R_GPIO_LED_LAN2 21 +#define MAC1200R_GPIO_LED_LAN3 22 +#define MAC1200R_GPIO_LED_LAN4 20 + +#define MAC1200R_GPIO_BTN_WPS 16 + +#define MAC1200R_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MAC1200R_KEYS_DEBOUNCE_INTERVAL (3 * MAC1200R_KEYS_POLL_INTERVAL) + +#define MAC1200R_MAC0_OFFSET 0 +#define MAC1200R_MAC1_OFFSET 6 +#define MAC1200R_WMAC_CALDATA_OFFSET 0x1000 +#define MAC1200R_PCIE_CALDATA_OFFSET 0x5000 + +static const char *mac1200r_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data mac1200r_flash_data = { + .part_probes = mac1200r_part_probes, +}; + +static struct gpio_led mac1200r_leds_gpio[] __initdata = { + { + .name = "mercury:green:wps", + .gpio = MAC1200R_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "mercury:green:system", + .gpio = MAC1200R_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "mercury:green:wlan2g", + .gpio = MAC1200R_GPIO_LED_WLAN2G, + .active_low = 1, + }, + { + .name = "mercury:green:wlan5g", + .gpio = MAC1200R_GPIO_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mac1200r_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MAC1200R_KEYS_DEBOUNCE_INTERVAL, + .gpio = MAC1200R_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + + +static void __init mac1200r_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&mac1200r_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mac1200r_leds_gpio), + mac1200r_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MAC1200R_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mac1200r_gpio_keys), + mac1200r_gpio_keys); + + ath79_init_mac(tmpmac, mac, 0); + ath79_wmac_disable_5ghz(); + ath79_register_wmac(art + MAC1200R_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 1); + ap91_pci_init(art + MAC1200R_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK3); + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK2); + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN3, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN4, + AR934X_GPIO_OUT_LED_LINK0); + ath79_gpio_output_select(MAC1200R_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); +} + +MIPS_MACHINE(ATH79_MACH_MC_MAC1200R, "MC-MAC1200R", + "MERCURY MAC1200R", + mac1200r_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr12.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr12.c new file mode 100644 index 0000000..12c9a1c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr12.c @@ -0,0 +1,115 @@ +/* + * Cisco Meraki MR12 board support + * + * Copyright (C) 2014-2015 Chris Blake + * + * Based on Atheros AP96 board support configuration + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define MR12_GPIO_LED_W4_GREEN 14 +#define MR12_GPIO_LED_W3_GREEN 13 +#define MR12_GPIO_LED_W2_GREEN 12 +#define MR12_GPIO_LED_W1_GREEN 11 + +#define MR12_GPIO_LED_WAN 15 + +#define MR12_GPIO_LED_POWER_ORANGE 16 +#define MR12_GPIO_LED_POWER_GREEN 17 + +#define MR12_GPIO_BTN_RESET 8 +#define MR12_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR12_KEYS_DEBOUNCE_INTERVAL (3 * MR12_KEYS_POLL_INTERVAL) + +#define MR12_WAN_PHYMASK BIT(4) + +#define MR12_WMAC0_MAC_OFFSET 0x120c +#define MR12_CALDATA0_OFFSET 0x1000 + +static struct gpio_led MR12_leds_gpio[] __initdata = { + { + .name = "mr12:green:wan", + .gpio = MR12_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "mr12:orange:power", + .gpio = MR12_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "mr12:green:power", + .gpio = MR12_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi4", + .gpio = MR12_GPIO_LED_W4_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi3", + .gpio = MR12_GPIO_LED_W3_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi2", + .gpio = MR12_GPIO_LED_W2_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi1", + .gpio = MR12_GPIO_LED_W1_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button MR12_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR12_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR12_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init MR12_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0xbfff0000); + + ath79_register_mdio(0,0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = MR12_WAN_PHYMASK; + ath79_register_eth(0); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(MR12_leds_gpio), + MR12_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR12_KEYS_POLL_INTERVAL, + ARRAY_SIZE(MR12_gpio_keys), + MR12_gpio_keys); + + ap91_pci_init(mac + MR12_CALDATA0_OFFSET, + mac + MR12_WMAC0_MAC_OFFSET); + +} + +MIPS_MACHINE(ATH79_MACH_MR12, "MR12", "Meraki MR12", MR12_setup); \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr16.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr16.c new file mode 100644 index 0000000..9f08e3d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr16.c @@ -0,0 +1,118 @@ +/* + * Cisco Meraki MR16 board support + * + * Copyright (C) 2015 Chris Blake + * + * Based on Atheros AP96 board support configuration + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define MR16_GPIO_LED_W4_GREEN 3 +#define MR16_GPIO_LED_W3_GREEN 2 +#define MR16_GPIO_LED_W2_GREEN 1 +#define MR16_GPIO_LED_W1_GREEN 0 + +#define MR16_GPIO_LED_WAN 4 + +#define MR16_GPIO_LED_POWER_ORANGE 5 +#define MR16_GPIO_LED_POWER_GREEN 6 + +#define MR16_GPIO_BTN_RESET 7 +#define MR16_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR16_KEYS_DEBOUNCE_INTERVAL (3 * MR16_KEYS_POLL_INTERVAL) + +#define MR16_WAN_PHYMASK BIT(0) + +#define MR16_WMAC0_MAC_OFFSET 0x120c +#define MR16_WMAC1_MAC_OFFSET 0x520c +#define MR16_CALDATA0_OFFSET 0x1000 +#define MR16_CALDATA1_OFFSET 0x5000 + +static struct gpio_led MR16_leds_gpio[] __initdata = { + { + .name = "mr16:green:wan", + .gpio = MR16_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "mr16:orange:power", + .gpio = MR16_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "mr16:green:power", + .gpio = MR16_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi4", + .gpio = MR16_GPIO_LED_W4_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi3", + .gpio = MR16_GPIO_LED_W3_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi2", + .gpio = MR16_GPIO_LED_W2_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi1", + .gpio = MR16_GPIO_LED_W1_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button MR16_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR16_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR16_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init MR16_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0xbfff0000); + + ath79_register_mdio(0,0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = MR16_WAN_PHYMASK; + ath79_register_eth(0); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(MR16_leds_gpio), + MR16_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR16_KEYS_POLL_INTERVAL, + ARRAY_SIZE(MR16_gpio_keys), + MR16_gpio_keys); + + ap94_pci_init(mac + MR16_CALDATA0_OFFSET, + mac + MR16_WMAC0_MAC_OFFSET, + mac + MR16_CALDATA1_OFFSET, + mac + MR16_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_MR16, "MR16", "Meraki MR16", MR16_setup); \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c new file mode 100644 index 0000000..8ace02f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c @@ -0,0 +1,129 @@ +/* + * MR1750 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Marek Lindner + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define MR1750_GPIO_LED_LAN 12 +#define MR1750_GPIO_LED_WLAN_2G 13 +#define MR1750_GPIO_LED_STATUS_GREEN 19 +#define MR1750_GPIO_LED_STATUS_RED 21 +#define MR1750_GPIO_LED_POWER 22 +#define MR1750_GPIO_LED_WLAN_5G 23 + +#define MR1750_GPIO_BTN_RESET 17 + +#define MR1750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR1750_KEYS_DEBOUNCE_INTERVAL (3 * MR1750_KEYS_POLL_INTERVAL) + +#define MR1750_MAC0_OFFSET 0 +#define MR1750_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led mr1750_leds_gpio[] __initdata = { + { + .name = "mr1750:blue:power", + .gpio = MR1750_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr1750:blue:wan", + .gpio = MR1750_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "mr1750:blue:wlan24", + .gpio = MR1750_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "mr1750:blue:wlan58", + .gpio = MR1750_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "mr1750:green:status", + .gpio = MR1750_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "mr1750:red:status", + .gpio = MR1750_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr1750_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR1750_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init mr1750_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_eth0_pll_data.pll_1000 = 0xbe000101; + ath79_eth0_pll_data.pll_100 = 0x80000101; + ath79_eth0_pll_data.pll_10 = 0x80001313; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio), + mr1750_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr1750_gpio_keys), + mr1750_gpio_keys); + + ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1); + ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac); + ath79_register_pci(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(5); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr600.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr600.c new file mode 100644 index 0000000..701330c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr600.c @@ -0,0 +1,177 @@ +/* + * OpenMesh OM2P board support + * + * Copyright (C) 2012 Marek Lindner + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MR600_GPIO_LED_WLAN58 12 +#define MR600_GPIO_LED_WPS 13 +#define MR600_GPIO_LED_POWER 14 + +#define MR600V2_GPIO_LED_WLAN58_RED 12 +#define MR600V2_GPIO_LED_WPS 13 +#define MR600V2_GPIO_LED_POWER 14 +#define MR600V2_GPIO_LED_WLAN24_GREEN 18 +#define MR600V2_GPIO_LED_WLAN24_YELLOW 19 +#define MR600V2_GPIO_LED_WLAN24_RED 20 +#define MR600V2_GPIO_LED_WLAN58_GREEN 21 +#define MR600V2_GPIO_LED_WLAN58_YELLOW 22 + +#define MR600_GPIO_BTN_RESET 17 + +#define MR600_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR600_KEYS_DEBOUNCE_INTERVAL (3 * MR600_KEYS_POLL_INTERVAL) + +#define MR600_MAC_OFFSET 0 +#define MR600_WMAC_CALDATA_OFFSET 0x1000 +#define MR600_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led mr600_leds_gpio[] __initdata = { + { + .name = "mr600:orange:power", + .gpio = MR600_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr600:blue:wps", + .gpio = MR600_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "mr600:green:wlan58", + .gpio = MR600_GPIO_LED_WLAN58, + .active_low = 1, + }, +}; + +static struct gpio_led mr600v2_leds_gpio[] __initdata = { + { + .name = "mr600:blue:power", + .gpio = MR600V2_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr600:blue:wps", + .gpio = MR600V2_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "mr600:red:wlan24", + .gpio = MR600V2_GPIO_LED_WLAN24_RED, + .active_low = 1, + }, + { + .name = "mr600:yellow:wlan24", + .gpio = MR600V2_GPIO_LED_WLAN24_YELLOW, + .active_low = 1, + }, + { + .name = "mr600:green:wlan24", + .gpio = MR600V2_GPIO_LED_WLAN24_GREEN, + .active_low = 1, + }, + { + .name = "mr600:red:wlan58", + .gpio = MR600V2_GPIO_LED_WLAN58_RED, + .active_low = 1, + }, + { + .name = "mr600:yellow:wlan58", + .gpio = MR600V2_GPIO_LED_WLAN58_YELLOW, + .active_low = 1, + }, + { + .name = "mr600:green:wlan58", + .gpio = MR600V2_GPIO_LED_WLAN58_GREEN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr600_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR600_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR600_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init mr600_base_setup(unsigned num_leds, struct gpio_led *leds) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, num_leds, leds); + ath79_register_gpio_keys_polled(-1, MR600_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr600_gpio_keys), + mr600_gpio_keys); + + ath79_init_mac(mac, art + MR600_MAC_OFFSET, 1); + ath79_register_wmac(art + MR600_WMAC_CALDATA_OFFSET, mac); + + ath79_init_mac(mac, art + MR600_MAC_OFFSET, 8); + ap91_pci_init(art + MR600_PCIE_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR600_MAC_OFFSET, 0); + + /* GMAC0 is connected to an external PHY */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +static void __init mr600_setup(void) +{ + mr600_base_setup(ARRAY_SIZE(mr600_leds_gpio), mr600_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); +} + +MIPS_MACHINE(ATH79_MACH_MR600, "MR600", "OpenMesh MR600", mr600_setup); + +static void __init mr600v2_setup(void) +{ + mr600_base_setup(ARRAY_SIZE(mr600v2_leds_gpio), mr600v2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_MR600V2, "MR600v2", "OpenMesh MR600v2", mr600v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c new file mode 100644 index 0000000..9c3164d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c @@ -0,0 +1,140 @@ +/* + * MR900 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Marek Lindner + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define MR900_GPIO_LED_LAN 12 +#define MR900_GPIO_LED_WLAN_2G 13 +#define MR900_GPIO_LED_STATUS_GREEN 19 +#define MR900_GPIO_LED_STATUS_RED 21 +#define MR900_GPIO_LED_POWER 22 +#define MR900_GPIO_LED_WLAN_5G 23 + +#define MR900_GPIO_BTN_RESET 17 + +#define MR900_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR900_KEYS_DEBOUNCE_INTERVAL (3 * MR900_KEYS_POLL_INTERVAL) + +#define MR900_MAC0_OFFSET 0 +#define MR900_WMAC_CALDATA_OFFSET 0x1000 +#define MR900_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led mr900_leds_gpio[] __initdata = { + { + .name = "mr900:blue:power", + .gpio = MR900_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr900:blue:wan", + .gpio = MR900_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "mr900:blue:wlan24", + .gpio = MR900_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "mr900:blue:wlan58", + .gpio = MR900_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "mr900:green:status", + .gpio = MR900_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "mr900:red:status", + .gpio = MR900_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr900_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR900_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR900_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init mr900_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6], pcie_mac[6]; + struct ath9k_platform_data *pdata; + + ath79_eth0_pll_data.pll_1000 = 0xbe000101; + ath79_eth0_pll_data.pll_100 = 0x80000101; + ath79_eth0_pll_data.pll_10 = 0x80001313; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio), + mr900_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr900_gpio_keys), + mr900_gpio_keys); + + ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1); + ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac); + ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16); + ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac); + pdata = ap9x_pci_get_wmac_data(0); + if (!pdata) { + pr_err("mr900: unable to get address of wlan data\n"); + return; + } + pdata->use_eeprom = true; + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(5); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_MR900, "MR900", "OpenMesh MR900", mr900_setup); +MIPS_MACHINE(ATH79_MACH_MR900v2, "MR900v2", "OpenMesh MR900v2", mr900_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n600.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n600.c new file mode 100644 index 0000000..a87413d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n600.c @@ -0,0 +1,202 @@ +/* + * WD My Net N600 board support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define MYNET_N600_GPIO_LED_WIFI 0 +#define MYNET_N600_GPIO_LED_POWER 11 +#define MYNET_N600_GPIO_LED_INTERNET 12 +#define MYNET_N600_GPIO_LED_WPS 13 + +#define MYNET_N600_GPIO_LED_LAN1 4 +#define MYNET_N600_GPIO_LED_LAN2 3 +#define MYNET_N600_GPIO_LED_LAN3 2 +#define MYNET_N600_GPIO_LED_LAN4 1 + +#define MYNET_N600_GPIO_BTN_RESET 16 +#define MYNET_N600_GPIO_BTN_WPS 17 + +#define MYNET_N600_GPIO_EXTERNAL_LNA0 14 +#define MYNET_N600_GPIO_EXTERNAL_LNA1 15 + +#define MYNET_N600_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MYNET_N600_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N600_KEYS_POLL_INTERVAL) + +#define MYNET_N600_MAC0_OFFSET 0 +#define MYNET_N600_MAC1_OFFSET 6 +#define MYNET_N600_WMAC_CALDATA_OFFSET 0x1000 +#define MYNET_N600_PCIE_CALDATA_OFFSET 0x5000 + +#define MYNET_N600_NVRAM_ADDR 0x1f058010 +#define MYNET_N600_NVRAM_SIZE 0x7ff0 + +static struct gpio_led mynet_n600_leds_gpio[] __initdata = { + { + .name = "wd:blue:power", + .gpio = MYNET_N600_GPIO_LED_POWER, + .active_low = 0, + }, + { + .name = "wd:blue:wps", + .gpio = MYNET_N600_GPIO_LED_WPS, + .active_low = 0, + }, + { + .name = "wd:blue:wireless", + .gpio = MYNET_N600_GPIO_LED_WIFI, + .active_low = 0, + }, + { + .name = "wd:blue:internet", + .gpio = MYNET_N600_GPIO_LED_INTERNET, + .active_low = 0, + }, + { + .name = "wd:green:lan1", + .gpio = MYNET_N600_GPIO_LED_LAN1, + .active_low = 1, + }, + { + .name = "wd:green:lan2", + .gpio = MYNET_N600_GPIO_LED_LAN2, + .active_low = 1, + }, + { + .name = "wd:green:lan3", + .gpio = MYNET_N600_GPIO_LED_LAN3, + .active_low = 1, + }, + { + .name = "wd:green:lan4", + .gpio = MYNET_N600_GPIO_LED_LAN4, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mynet_n600_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MYNET_N600_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N600_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MYNET_N600_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N600_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void mynet_n600_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N600_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, MYNET_N600_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +#define MYNET_N600_WAN_PHY_MASK BIT(0) + +static void __init mynet_n600_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN1, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN2, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN3, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN4, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_INTERNET, + AR934X_GPIO_OUT_GPIO); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n600_leds_gpio), + mynet_n600_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MYNET_N600_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mynet_n600_gpio_keys), + mynet_n600_gpio_keys); + + /* + * Control signal for external LNAs 0 and 1 + * Taken from GPL bootloader source: + * board/ar7240/db12x/alpha_gpio.c + */ + ath79_wmac_set_ext_lna_gpio(0, MYNET_N600_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, MYNET_N600_GPIO_EXTERNAL_LNA1); + + mynet_n600_get_mac("wlan24mac=", tmpmac); + ath79_register_wmac(art + MYNET_N600_WMAC_CALDATA_OFFSET, tmpmac); + + mynet_n600_get_mac("wlan5mac=", tmpmac); + ap91_pci_init(art + MYNET_N600_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + mynet_n600_get_mac("lanmac=", ath79_eth1_data.mac_addr); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + mynet_n600_get_mac("wanmac=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = MYNET_N600_WAN_PHY_MASK; + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = MYNET_N600_WAN_PHY_MASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_MYNET_N600, "MYNET-N600", "WD My Net N600", + mynet_n600_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c new file mode 100644 index 0000000..9d69dc5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c @@ -0,0 +1,226 @@ +/* + * WD My Net N750 board support + * + * Copyright (C) 2013 Felix Kaechele + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + + +/* + * Taken from GPL bootloader source: + * board/ar7240/db12x/alpha_gpio.c + */ +#define MYNET_N750_GPIO_LED_WIFI 11 +#define MYNET_N750_GPIO_LED_INTERNET 12 +#define MYNET_N750_GPIO_LED_WPS 13 +#define MYNET_N750_GPIO_LED_POWER 14 + +#define MYNET_N750_GPIO_BTN_RESET 17 +#define MYNET_N750_GPIO_BTN_WPS 19 + +#define MYNET_N750_GPIO_EXTERNAL_LNA0 15 +#define MYNET_N750_GPIO_EXTERNAL_LNA1 18 + +#define MYNET_N750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MYNET_N750_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N750_KEYS_POLL_INTERVAL) + +#define MYNET_N750_WMAC_CALDATA_OFFSET 0x1000 +#define MYNET_N750_PCIE_CALDATA_OFFSET 0x5000 + +#define MYNET_N750_NVRAM_ADDR 0x1f058010 +#define MYNET_N750_NVRAM_SIZE 0x7ff0 + +static struct gpio_led mynet_n750_leds_gpio[] __initdata = { + { + .name = "wd:blue:power", + .gpio = MYNET_N750_GPIO_LED_POWER, + .active_low = 0, + }, + { + .name = "wd:blue:wps", + .gpio = MYNET_N750_GPIO_LED_WPS, + .active_low = 0, + }, + { + .name = "wd:blue:wireless", + .gpio = MYNET_N750_GPIO_LED_WIFI, + .active_low = 0, + }, + { + .name = "wd:blue:internet", + .gpio = MYNET_N750_GPIO_LED_INTERNET, + .active_low = 0, + }, +}; + +static struct gpio_keys_button mynet_n750_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N750_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N750_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info mynet_n750_leds_ar8327[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "wd:green:lan1"), + AR8327_LED_INFO(PHY1_0, HW, "wd:green:lan2"), + AR8327_LED_INFO(PHY2_0, HW, "wd:green:lan3"), + AR8327_LED_INFO(PHY3_0, HW, "wd:green:lan4"), + AR8327_LED_INFO(PHY4_0, HW, "wd:green:wan"), + AR8327_LED_INFO(PHY0_1, HW, "wd:yellow:lan1"), + AR8327_LED_INFO(PHY1_1, HW, "wd:yellow:lan2"), + AR8327_LED_INFO(PHY2_1, HW, "wd:yellow:lan3"), + AR8327_LED_INFO(PHY3_1, HW, "wd:yellow:lan4"), + AR8327_LED_INFO(PHY4_1, HW, "wd:yellow:wan"), +}; + +static struct ar8327_pad_cfg mynet_n750_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg mynet_n750_ar8327_led_cfg = { + .led_ctrl0 = 0xcc35cc35, + .led_ctrl1 = 0xca35ca35, + .led_ctrl2 = 0xc935c935, + .led_ctrl3 = 0x03ffff00, + .open_drain = false, +}; + +static struct ar8327_platform_data mynet_n750_ar8327_data = { + .pad0_cfg = &mynet_n750_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &mynet_n750_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(mynet_n750_leds_ar8327), + .leds = mynet_n750_leds_ar8327, +}; + +static struct mdio_board_info mynet_n750_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &mynet_n750_ar8327_data, + }, +}; + +static void mynet_n750_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N750_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, MYNET_N750_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +/* + * The bootloader on this board powers down all PHYs on the switch + * before booting the kernel. We bring all PHYs back up so that they are + * discoverable by the mdio bus scan and the switch is detected + * correctly. + */ +static void mynet_n750_mdio_fixup(struct mii_bus *bus) +{ + int i; + + for (i = 0; i < 5; i++) + bus->write(bus, i, MII_BMCR, + (BMCR_RESET | BMCR_ANENABLE | BMCR_SPEED1000)); + + mdelay(1000); +} + +static void __init mynet_n750_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio), + mynet_n750_leds_gpio); + ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mynet_n750_gpio_keys), + mynet_n750_gpio_keys); + /* + * Control signal for external LNAs 0 and 1 + * Taken from GPL bootloader source: + * board/ar7240/db12x/alpha_gpio.c + */ + ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1); + + mynet_n750_get_mac("wlan24mac=", tmpmac); + ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac); + + mynet_n750_get_mac("wlan5mac=", tmpmac); + ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(mynet_n750_mdio0_info, + ARRAY_SIZE(mynet_n750_mdio0_info)); + + ath79_mdio0_data.reset = mynet_n750_mdio_fixup; + ath79_register_mdio(0, 0x0); + + mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_MYNET_N750, "MYNET-N750", "WD My Net N750", + mynet_n750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c new file mode 100644 index 0000000..3d48ca8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c @@ -0,0 +1,208 @@ +/* + * WD My Net WI-FI Range Extender (Codename:Starfish db12x) board support + * + * Copyright (C) 2013 Christian Lamparter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define MYNET_REXT_GPIO_LED_POWER 11 +#define MYNET_REXT_GPIO_LED_ETHERNET 12 +#define MYNET_REXT_GPIO_LED_WIFI 19 + +#define MYNET_REXT_GPIO_LED_RF_QTY1 20 +#define MYNET_REXT_GPIO_LED_RF_QTY2 21 +#define MYNET_REXT_GPIO_LED_RF_QTY3 22 + +#define MYNET_REXT_GPIO_BTN_RESET 13 +#define MYNET_REXT_GPIO_BTN_WPS 15 +#define MYNET_REXT_GPIO_SW_RF 14 + +#define MYNET_REXT_GPIO_PHY_SWRST 16 /* disables Ethernet PHY */ +#define MYNET_REXT_GPIO_PHY_INT 17 +#define MYNET_REXT_GPIO_18 18 + +#define MYNET_REXT_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MYNET_REXT_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_REXT_KEYS_POLL_INTERVAL) + +#define MYNET_REXT_WMAC_CALDATA_OFFSET 0x1000 + +#define MYNET_REXT_NVRAM_ADDR 0x1f7e0010 +#define MYNET_REXT_NVRAM_SIZE 0xfff0 + +#define MYNET_REXT_ART_ADDR 0x1f7f0000 + +static const char *mynet_rext_part_probes[] = { + "cybertan", + NULL, +}; + +static struct flash_platform_data mynet_rext_flash_data = { + .type = "s25fl064k", + .part_probes = mynet_rext_part_probes, +}; + +static struct gpio_led mynet_rext_leds_gpio[] __initdata = { + { + .name = "wd:blue:power", + .gpio = MYNET_REXT_GPIO_LED_POWER, + .active_low = 0, + }, + { + .name = "wd:blue:wireless", + .gpio = MYNET_REXT_GPIO_LED_WIFI, + .active_low = 1, + }, + { + .name = "wd:blue:ethernet", + .gpio = MYNET_REXT_GPIO_LED_ETHERNET, + .active_low = 1, + }, + { + .name = "wd:blue:quality1", + .gpio = MYNET_REXT_GPIO_LED_RF_QTY1, + .active_low = 1, + }, + { + .name = "wd:blue:quality2", + .gpio = MYNET_REXT_GPIO_LED_RF_QTY2, + .active_low = 1, + }, + { + .name = "wd:blue:quality3", + .gpio = MYNET_REXT_GPIO_LED_RF_QTY3, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mynet_rext_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_REXT_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_REXT_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RF Band switch", + .type = EV_SW, + .code = BTN_1, + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_REXT_GPIO_SW_RF, + }, +}; + +static struct at803x_platform_data mynet_rext_at803x_data = { + .disable_smarteee = 0, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 0, + .fixup_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info mynet_rext_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 4, + .platform_data = &mynet_rext_at803x_data, + }, +}; + +static void mynet_rext_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_REXT_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, MYNET_REXT_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +static void __init mynet_rext_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(MYNET_REXT_ART_ADDR); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&mynet_rext_flash_data); + + /* GPIO configuration from drivers/char/GPIO8.c */ + + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_POWER, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_WIFI, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY1, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY2, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY3, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_ETHERNET, + AR934X_GPIO_OUT_GPIO); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_rext_leds_gpio), + mynet_rext_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MYNET_REXT_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mynet_rext_gpio_keys), + mynet_rext_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_RXD_DELAY | + AR934X_ETH_CFG_RDV_DELAY); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(mynet_rext_mdio0_info, + ARRAY_SIZE(mynet_rext_mdio0_info)); + + /* LAN */ + mynet_rext_get_mac("et0macaddr=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to an external PHY on Port 4 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_pll_data.pll_10 = 0x00001313; /* athrs_mac.c */ + ath79_eth0_pll_data.pll_1000 = 0x0e000000; /* athrs_mac.c */ + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_register_eth(0); + + /* WLAN */ + mynet_rext_get_mac("wl0_hwaddr=", tmpmac); + ap91_pci_init(art + MYNET_REXT_WMAC_CALDATA_OFFSET, tmpmac); +} + +MIPS_MACHINE(ATH79_MACH_MYNET_REXT, "MYNET-REXT", + "WD My Net Wi-Fi Range Extender", mynet_rext_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c new file mode 100644 index 0000000..c2460ce --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c @@ -0,0 +1,124 @@ +/* + * Planex MZK-W04NU board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MZK_W04NU_GPIO_LED_USB 0 +#define MZK_W04NU_GPIO_LED_STATUS 1 +#define MZK_W04NU_GPIO_LED_WPS 3 +#define MZK_W04NU_GPIO_LED_WLAN 6 +#define MZK_W04NU_GPIO_LED_AP 15 +#define MZK_W04NU_GPIO_LED_ROUTER 16 + +#define MZK_W04NU_GPIO_BTN_APROUTER 5 +#define MZK_W04NU_GPIO_BTN_WPS 12 +#define MZK_W04NU_GPIO_BTN_RESET 21 + +#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL) + +static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { + { + .name = "planex:green:status", + .gpio = MZK_W04NU_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "planex:blue:wps", + .gpio = MZK_W04NU_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "planex:green:wlan", + .gpio = MZK_W04NU_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "planex:green:usb", + .gpio = MZK_W04NU_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "planex:green:ap", + .gpio = MZK_W04NU_GPIO_LED_AP, + .active_low = 1, + }, { + .name = "planex:green:router", + .gpio = MZK_W04NU_GPIO_LED_ROUTER, + .active_low = 1, + } +}; + +static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "aprouter", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_APROUTER, + .active_low = 0, + } +}; + +#define MZK_W04NU_WAN_PHYMASK BIT(4) +#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) + +static void __init mzk_w04nu_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, MZK_W04NU_MDIO_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), + mzk_w04nu_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzk_w04nu_gpio_keys), + mzk_w04nu_gpio_keys); + ath79_register_usb(); + + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", + mzk_w04nu_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c new file mode 100644 index 0000000..8c40365 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c @@ -0,0 +1,115 @@ +/* + * Planex MZK-W300NH board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MZK_W300NH_GPIO_LED_STATUS 1 +#define MZK_W300NH_GPIO_LED_WPS 3 +#define MZK_W300NH_GPIO_LED_WLAN 6 +#define MZK_W300NH_GPIO_LED_AP_GREEN 15 +#define MZK_W300NH_GPIO_LED_AP_AMBER 16 + +#define MZK_W300NH_GPIO_BTN_APROUTER 5 +#define MZK_W300NH_GPIO_BTN_WPS 12 +#define MZK_W300NH_GPIO_BTN_RESET 21 + +#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL) + +static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { + { + .name = "planex:green:status", + .gpio = MZK_W300NH_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "planex:blue:wps", + .gpio = MZK_W300NH_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "planex:green:wlan", + .gpio = MZK_W300NH_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "planex:green:aprouter", + .gpio = MZK_W300NH_GPIO_LED_AP_GREEN, + }, { + .name = "planex:amber:aprouter", + .gpio = MZK_W300NH_GPIO_LED_AP_AMBER, + } +}; + +static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "aprouter", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_APROUTER, + .active_low = 0, + } +}; + +#define MZK_W300NH_WAN_PHYMASK BIT(4) +#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) + +static void __init mzk_w300nh_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, MZK_W300NH_MDIO_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), + mzk_w300nh_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzk_w300nh_gpio_keys), + mzk_w300nh_gpio_keys); + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", + mzk_w300nh_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c new file mode 100644 index 0000000..ca00777 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c @@ -0,0 +1,220 @@ +/* + * Zyxel NBG 460N/550N/550NH board support + * + * Copyright (C) 2010 Michael Kurz + * + * based on mach-tl-wr1043nd.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* LEDs */ +#define NBG460N_GPIO_LED_WPS 3 +#define NBG460N_GPIO_LED_WAN 6 +#define NBG460N_GPIO_LED_POWER 14 +#define NBG460N_GPIO_LED_WLAN 15 + +/* Buttons */ +#define NBG460N_GPIO_BTN_WPS 12 +#define NBG460N_GPIO_BTN_RESET 21 + +#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL) + +/* RTC chip PCF8563 I2C interface */ +#define NBG460N_GPIO_PCF8563_SDA 8 +#define NBG460N_GPIO_PCF8563_SCK 7 + +/* Switch configuration I2C interface */ +#define NBG460N_GPIO_RTL8366_SDA 16 +#define NBG460N_GPIO_RTL8366_SCK 18 + +static struct mtd_partition nbg460n_partitions[] = { + { + .name = "Bootbase", + .offset = 0, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "U-Boot Config", + .offset = 0x010000, + .size = 0x030000, + }, { + .name = "U-Boot", + .offset = 0x040000, + .size = 0x030000, + }, { + .name = "linux", + .offset = 0x070000, + .size = 0x0e0000, + }, { + .name = "rootfs", + .offset = 0x150000, + .size = 0x2a0000, + }, { + .name = "CalibData", + .offset = 0x3f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x070000, + .size = 0x380000, + } +}; + +static struct flash_platform_data nbg460n_flash_data = { + .parts = nbg460n_partitions, + .nr_parts = ARRAY_SIZE(nbg460n_partitions), +}; + +static struct gpio_led nbg460n_leds_gpio[] __initdata = { + { + .name = "nbg460n:green:power", + .gpio = NBG460N_GPIO_LED_POWER, + .active_low = 0, + .default_trigger = "default-on", + }, { + .name = "nbg460n:green:wps", + .gpio = NBG460N_GPIO_LED_WPS, + .active_low = 0, + }, { + .name = "nbg460n:green:wlan", + .gpio = NBG460N_GPIO_LED_WLAN, + .active_low = 0, + }, { + /* Not really for controlling the LED, + when set low the LED blinks uncontrollable */ + .name = "nbg460n:green:wan", + .gpio = NBG460N_GPIO_LED_WAN, + .active_low = 0, + } +}; + +static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG460N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG460N_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { + .sda_pin = NBG460N_GPIO_PCF8563_SDA, + .scl_pin = NBG460N_GPIO_PCF8563_SCK, + .udelay = 10, +}; + +static struct platform_device nbg460n_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .num_resources = 0, + .resource = NULL, + .dev = { + .platform_data = &nbg460n_i2c_device_platdata, + }, +}; + +static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static void nbg460n_i2c_init(void) +{ + /* The gpio interface */ + platform_device_register(&nbg460n_i2c_device); + /* I2C devices */ + i2c_register_board_info(0, nbg460n_i2c_devs, + ARRAY_SIZE(nbg460n_i2c_devs)); +} + + +static struct rtl8366_platform_data nbg460n_rtl8366s_data = { + .gpio_sda = NBG460N_GPIO_RTL8366_SDA, + .gpio_sck = NBG460N_GPIO_RTL8366_SCK, +}; + +static struct platform_device nbg460n_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &nbg460n_rtl8366s_data, + } +}; + +static void __init nbg460n_setup(void) +{ + /* end of bootloader sector contains mac address */ + u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); + /* last sector contains wlan calib data */ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + /* LAN Port */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + /* WAN Port */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + ath79_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + /* register the switch phy */ + platform_device_register(&nbg460n_rtl8366s_device); + + /* register flash */ + ath79_register_m25p80(&nbg460n_flash_data); + + ath79_register_wmac(eeprom, mac); + + /* register RTC chip */ + nbg460n_i2c_init(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), + nbg460n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nbg460n_gpio_keys), + nbg460n_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", + nbg460n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c new file mode 100644 index 0000000..69a73cc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c @@ -0,0 +1,276 @@ +/* + * ZyXEL NBG6716 board support + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * Copyright (c) 2013 Andre Valentin + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define NBG6716_GPIO_LED_INTERNET 18 +#define NBG6716_GPIO_LED_POWER 15 +#define NBG6716_GPIO_LED_USB1 4 +#define NBG6716_GPIO_LED_USB2 13 +#define NBG6716_GPIO_LED_WIFI2G 19 +#define NBG6716_GPIO_LED_WIFI5G 17 +#define NBG6716_GPIO_LED_WPS 21 + +#define NBG6716_GPIO_BTN_RESET 23 +#define NBG6716_GPIO_BTN_RFKILL 1 +#define NBG6716_GPIO_BTN_USB1 0 +#define NBG6716_GPIO_BTN_USB2 14 +#define NBG6716_GPIO_BTN_WPS 22 + +#define NBG6716_GPIO_USB_POWER 16 + +#define NBG6716_KEYS_POLL_INTERVAL 20 /* msecs */ +#define NBG6716_KEYS_DEBOUNCE_INTERVAL (3 * NBG6716_KEYS_POLL_INTERVAL) + +#define NBG6716_MAC0_OFFSET 0 +#define NBG6716_MAC1_OFFSET 6 +#define NBG6716_WMAC_CALDATA_OFFSET 0x1000 +#define NBG6716_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led nbg6716_leds_gpio[] __initdata = { + { + .name = "zyxel:white:internet", + .gpio = NBG6716_GPIO_LED_INTERNET, + .active_low = 1, + }, + { + .name = "zyxel:white:power", + .gpio = NBG6716_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "zyxel:white:usb1", + .gpio = NBG6716_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "zyxel:white:usb2", + .gpio = NBG6716_GPIO_LED_USB2, + .active_low = 1, + }, + { + .name = "zyxel:white:wifi2g", + .gpio = NBG6716_GPIO_LED_WIFI2G, + .active_low = 1, + }, + { + .name = "zyxel:white:wifi5g", + .gpio = NBG6716_GPIO_LED_WIFI5G, + .active_low = 1, + }, + { + .name = "zyxel:white:wps", + .gpio = NBG6716_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button nbg6716_gpio_keys[] __initdata = { + { + .desc = "RESET button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_RFKILL, + .active_low = 0, + }, + { + .desc = "USB1 eject button", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_USB1, + .active_low = 1, + }, + { + .desc = "USB2 eject button", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_USB2, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg nbg6716_ar8327_pad0_cfg; +static struct ar8327_pad_cfg nbg6716_ar8327_pad6_cfg; +static struct ar8327_led_cfg nbg6716_ar8327_led_cfg; + +static struct ar8327_platform_data nbg6716_ar8327_data = { + .pad0_cfg = &nbg6716_ar8327_pad0_cfg, + .pad6_cfg = &nbg6716_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &nbg6716_ar8327_led_cfg +}; + +static struct mdio_board_info nbg6716_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &nbg6716_ar8327_data, + }, +}; + +static void nbg6716_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(0x1f040000); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, 0x10000, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +static void __init nbg6716_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1f050000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg6716_leds_gpio), + nbg6716_leds_gpio); + ath79_register_gpio_keys_polled(-1, NBG6716_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nbg6716_gpio_keys), + nbg6716_gpio_keys); + + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); + ath79_register_nfc(); + + gpio_request_one(NBG6716_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); + + nbg6716_get_mac("ethaddr=", tmpmac); + + ath79_register_pci(); + + ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, tmpmac, 2); + ath79_init_mac(ath79_eth1_data.mac_addr, tmpmac, 3); + + mdiobus_register_board_info(nbg6716_mdio0_info, + ARRAY_SIZE(nbg6716_mdio0_info)); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); +} + +static void __init nbg6716_010_setup(void) +{ + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ + nbg6716_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; + nbg6716_ar8327_pad0_cfg.txclk_delay_en = true; + nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true; + nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + nbg6716_ar8327_pad0_cfg.mac06_exchange_en = true; + + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ + nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; + nbg6716_ar8327_pad6_cfg.rxclk_delay_en = true; + nbg6716_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + nbg6716_ar8327_led_cfg.open_drain = 0; + nbg6716_ar8327_led_cfg.led_ctrl0 = 0xffb7ffb7; + nbg6716_ar8327_led_cfg.led_ctrl1 = 0xffb7ffb7; + nbg6716_ar8327_led_cfg.led_ctrl2 = 0xffb7ffb7; + nbg6716_ar8327_led_cfg.led_ctrl3 = 0x03ffff00; + + nbg6716_common_setup(); +} + +MIPS_MACHINE(ATH79_MACH_NBG6716, "NBG6716", + "Zyxel NBG6716", + nbg6716_010_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c new file mode 100644 index 0000000..6b0bdc3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c @@ -0,0 +1,225 @@ +/* + * OpenMesh OM2P support + * + * Copyright (C) 2011 Marek Lindner + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OM2P_GPIO_LED_POWER 0 +#define OM2P_GPIO_LED_GREEN 13 +#define OM2P_GPIO_LED_RED 14 +#define OM2P_GPIO_LED_YELLOW 15 +#define OM2P_GPIO_LED_LAN 16 +#define OM2P_GPIO_LED_WAN 17 +#define OM2P_GPIO_BTN_RESET 1 + +#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL) + +#define OM2P_WAN_PHYMASK BIT(4) + +#define OM2P_LC_GPIO_LED_POWER 1 +#define OM2P_LC_GPIO_LED_GREEN 15 +#define OM2P_LC_GPIO_LED_RED 16 +#define OM2P_LC_GPIO_LED_YELLOW 0 +#define OM2P_LC_GPIO_LED_LAN 13 +#define OM2P_LC_GPIO_LED_WAN 17 +#define OM2P_LC_GPIO_BTN_RESET 12 + +static struct flash_platform_data om2p_flash_data = { + .type = "s25sl12800", + .name = "ar7240-nor0", +}; + +static struct gpio_led om2p_leds_gpio[] __initdata = { + { + .name = "om2p:blue:power", + .gpio = OM2P_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om2p:red:wifi", + .gpio = OM2P_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om2p:yellow:wifi", + .gpio = OM2P_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om2p:green:wifi", + .gpio = OM2P_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "om2p:blue:lan", + .gpio = OM2P_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "om2p:blue:wan", + .gpio = OM2P_GPIO_LED_WAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button om2p_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL, + .gpio = OM2P_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init om2p_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(&om2p_flash_data); + + ath79_register_mdio(0, ~OM2P_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_OM2P, "OM2P", "OpenMesh OM2P", om2p_setup); + + +static struct flash_platform_data om2p_lc_flash_data = { + .type = "s25sl12800", +}; + +static void __init om2p_lc_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000); + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + ath79_register_m25p80(&om2p_lc_flash_data); + + om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER; + om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED; + om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW; + om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN; + om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN; + om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN; + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + + om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET; + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(art, NULL); +} + +MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup); +MIPS_MACHINE(ATH79_MACH_OM2Pv2, "OM2Pv2", "OpenMesh OM2Pv2", om2p_lc_setup); + +static void __init om2p_hs_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000); + + /* make lan / wan leds software controllable */ + ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); + + /* enable reset button */ + ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO); + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + + om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN; + om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN; + + ath79_register_m25p80(&om2p_lc_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); + + ath79_register_wmac(art, NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup); +MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c new file mode 100644 index 0000000..49acd3b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c @@ -0,0 +1,218 @@ +/* + * OpenMesh OM5P support + * + * Copyright (C) 2013 Marek Lindner + * Copyright (C) 2014 Sven Eckelmann + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OM5P_GPIO_LED_POWER 13 +#define OM5P_GPIO_LED_GREEN 16 +#define OM5P_GPIO_LED_RED 19 +#define OM5P_GPIO_LED_YELLOW 17 +#define OM5P_GPIO_LED_LAN 14 +#define OM5P_GPIO_LED_WAN 15 +#define OM5P_GPIO_BTN_RESET 4 +#define OM5P_GPIO_I2C_SCL 20 +#define OM5P_GPIO_I2C_SDA 21 + +#define OM5P_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM5P_KEYS_DEBOUNCE_INTERVAL (3 * OM5P_KEYS_POLL_INTERVAL) + +#define OM5P_WMAC_CALDATA_OFFSET 0x1000 +#define OM5P_PCI_CALDATA_OFFSET 0x5000 + +static struct gpio_led om5p_leds_gpio[] __initdata = { + { + .name = "om5p:blue:power", + .gpio = OM5P_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om5p:red:wifi", + .gpio = OM5P_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om5p:yellow:wifi", + .gpio = OM5P_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om5p:green:wifi", + .gpio = OM5P_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "om5p:blue:lan", + .gpio = OM5P_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "om5p:blue:wan", + .gpio = OM5P_GPIO_LED_WAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button om5p_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OM5P_KEYS_DEBOUNCE_INTERVAL, + .gpio = OM5P_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct flash_platform_data om5p_flash_data = { + .type = "mx25l12805d", +}; + +static void __init om5p_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + /* make lan / wan leds software controllable */ + ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&om5p_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio), + om5p_leds_gpio); + ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om5p_gpio_keys), + om5p_gpio_keys); + + ath79_init_mac(mac, art, 2); + ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_OM5P, "OM5P", "OpenMesh OM5P", om5p_setup); + +static struct i2c_gpio_platform_data om5pan_i2c_device_platdata = { + .sda_pin = OM5P_GPIO_I2C_SDA, + .scl_pin = OM5P_GPIO_I2C_SCL, + .udelay = 10, + .sda_is_open_drain = 1, + .scl_is_open_drain = 1, +}; + +static struct platform_device om5pan_i2c_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &om5pan_i2c_device_platdata, + }, +}; + +static struct i2c_board_info om5pan_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("tmp423", 0x4c), + }, +}; + +static struct at803x_platform_data om5p_an_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info om5p_an_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 7, + .platform_data = &om5p_an_at803x_data, + }, +}; + +static void __init om5p_an_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + /* temperature sensor */ + platform_device_register(&om5pan_i2c_device); + i2c_register_board_info(0, om5pan_i2c_devs, + ARRAY_SIZE(om5pan_i2c_devs)); + + /* make lan / wan leds software controllable */ + ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&om5p_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio), + om5p_leds_gpio); + + ath79_init_mac(mac, art, 0x02); + ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + ath79_setup_ar934x_eth_rx_delay(2, 2); + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, 0x0); + + mdiobus_register_board_info(om5p_an_mdio0_info, + ARRAY_SIZE(om5p_an_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); + + /* GMAC0 is connected to the PHY7 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_mask = BIT(7); + ath79_eth0_pll_data.pll_1000 = 0x02000000; + ath79_eth0_pll_data.pll_100 = 0x00000101; + ath79_eth0_pll_data.pll_10 = 0x00001313; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(1); + + ath79_init_mac(mac, art, 0x10); + ap91_pci_init(art + OM5P_PCI_CALDATA_OFFSET, mac); +} + +MIPS_MACHINE(ATH79_MACH_OM5P_AN, "OM5P-AN", "OpenMesh OM5P AN", om5p_an_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-onion-omega.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-onion-omega.c new file mode 100644 index 0000000..c739840 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-onion-omega.c @@ -0,0 +1,84 @@ +/* + * Onion Omega board support + * + * Copyright (C) 2015 Boken Lin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OMEGA_GPIO_LED_SYSTEM 27 +#define OMEGA_GPIO_BTN_RESET 11 + +#define OMEGA_GPIO_USB_POWER 8 + +#define OMEGA_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OMEGA_KEYS_DEBOUNCE_INTERVAL (3 * OMEGA_KEYS_POLL_INTERVAL) + +static const char *omega_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data omega_flash_data = { + .part_probes = omega_part_probes, +}; + +static struct gpio_led omega_leds_gpio[] __initdata = { + { + .name = "onion:amber:system", + .gpio = OMEGA_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button omega_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OMEGA_KEYS_DEBOUNCE_INTERVAL, + .gpio = OMEGA_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init onion_omega_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&omega_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(omega_leds_gpio), + omega_leds_gpio); + ath79_register_gpio_keys_polled(-1, OMEGA_KEYS_POLL_INTERVAL, + ARRAY_SIZE(omega_gpio_keys), + omega_gpio_keys); + + gpio_request_one(OMEGA_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ONION_OMEGA, "ONION-OMEGA", "Onion Omega", onion_omega_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c new file mode 100644 index 0000000..3a350e9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c @@ -0,0 +1,83 @@ +/* + * Atheros PB42 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) + +#define PB42_GPIO_BTN_SW4 8 +#define PB42_GPIO_BTN_SW5 3 + +static struct gpio_keys_button pb42_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB42_GPIO_BTN_SW4, + .active_low = 1, + }, { + .desc = "sw5", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB42_GPIO_BTN_SW5, + .active_low = 1, + } +}; + +static const char *pb42_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data pb42_flash_data = { + .part_probes = pb42_part_probes, +}; + +#define PB42_WAN_PHYMASK BIT(20) +#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) +#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) + +static void __init pb42_init(void) +{ + ath79_register_m25p80(&pb42_flash_data); + + ath79_register_mdio(0, ~PB42_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb42_gpio_keys), + pb42_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c new file mode 100644 index 0000000..76715a5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c @@ -0,0 +1,70 @@ +/* + * Atheros PB92 board support + * + * Copyright (C) 2010 Felix Fietkau + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL) + +#define PB92_GPIO_BTN_SW4 8 +#define PB92_GPIO_BTN_SW5 3 + +static struct gpio_keys_button pb92_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB92_GPIO_BTN_SW4, + .active_low = 1, + }, { + .desc = "sw5", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB92_GPIO_BTN_SW5, + .active_low = 1, + } +}; + +static void __init pb92_init(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + ath79_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb92_gpio_keys), + pb92_gpio_keys); + + ath79_register_usb(); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_PB92, "PB92", "Atheros PB92", pb92_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-qihoo-c301.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-qihoo-c301.c new file mode 100644 index 0000000..a682f35 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-qihoo-c301.c @@ -0,0 +1,166 @@ +/* + * Qihoo 360 C301 board support + * + * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2014 Weijie Gao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define QIHOO_C301_GPIO_LED_STATUS_GREEN 0 +#define QIHOO_C301_GPIO_LED_STATUS_RED 11 + +#define QIHOO_C301_GPIO_LED_WAN 1 +#define QIHOO_C301_GPIO_LED_LAN1 2 +#define QIHOO_C301_GPIO_LED_LAN2 3 +#define QIHOO_C301_GPIO_ETH_LEN_EN 18 + +#define QIHOO_C301_GPIO_BTN_RESET 16 + +#define QIHOO_C301_GPIO_USB_POWER 19 + +#define QIHOO_C301_GPIO_SPI_CS1 12 + +#define QIHOO_C301_GPIO_EXTERNAL_LNA0 14 +#define QIHOO_C301_GPIO_EXTERNAL_LNA1 15 + +#define QIHOO_C301_KEYS_POLL_INTERVAL 20 /* msecs */ +#define QIHOO_C301_KEYS_DEBOUNCE_INTERVAL \ + (3 * QIHOO_C301_KEYS_POLL_INTERVAL) + +#define QIHOO_C301_WMAC_CALDATA_OFFSET 0x1000 + +#define QIHOO_C301_NVRAM_ADDR 0x1f058010 +#define QIHOO_C301_NVRAM_SIZE 0x7ff0 + +static struct gpio_led qihoo_c301_leds_gpio[] __initdata = { + { + .name = "qihoo:green:status", + .gpio = QIHOO_C301_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "qihoo:red:status", + .gpio = QIHOO_C301_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button qihoo_c301_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = QIHOO_C301_KEYS_DEBOUNCE_INTERVAL, + .gpio = QIHOO_C301_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct flash_platform_data flash __initdata = {NULL, NULL, 0}; + +static void qihoo_c301_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(QIHOO_C301_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, QIHOO_C301_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +static void __init qihoo_c301_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80_multi(&flash); + + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK2); + + ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1, + AR934X_GPIO_OUT_SPI_CS1); + + gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "Ethernet LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio), + qihoo_c301_leds_gpio); + + ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL, + ARRAY_SIZE(qihoo_c301_gpio_keys), + qihoo_c301_gpio_keys); + + ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1); + + qihoo_c301_get_mac("wlan24mac=", tmpmac); + ath79_register_wmac(art + QIHOO_C301_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_register_pci(); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + gpio_request_one(QIHOO_C301_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_QIHOO_C301, "QIHOO-C301", "Qihoo 360 C301", + qihoo_c301_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-r6100.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-r6100.c new file mode 100644 index 0000000..c1f0e2c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-r6100.c @@ -0,0 +1,146 @@ +/* + * NETGEAR R6100 board support + * + * Copyright (C) 2014 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define R6100_GPIO_LED_WLAN 0 +#define R6100_GPIO_LED_USB 11 +#define R6100_GPIO_LED_WAN_GREEN 13 +#define R6100_GPIO_LED_POWER_AMBER 14 +#define R6100_GPIO_LED_WAN_AMBER 15 +#define R6100_GPIO_LED_POWER_GREEN 17 + +#define R6100_GPIO_BTN_WIRELESS 1 +#define R6100_GPIO_BTN_WPS 3 +#define R6100_GPIO_BTN_RESET 12 + +#define R6100_GPIO_USB_POWER 16 + +#define R6100_KEYS_POLL_INTERVAL 20 /* msecs */ +#define R6100_KEYS_DEBOUNCE_INTERVAL (3 * R6100_KEYS_POLL_INTERVAL) + +static struct gpio_led r6100_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = R6100_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:power", + .gpio = R6100_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wan", + .gpio = R6100_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wan", + .gpio = R6100_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, + { + .name = "netgear:blue:usb", + .gpio = R6100_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "netgear:blue:wlan", + .gpio = R6100_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button r6100_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL, + .gpio = R6100_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL, + .gpio = R6100_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL, + .gpio = R6100_GPIO_BTN_WIRELESS, + .active_low = 0, + }, +}; + +static void __init r6100_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(r6100_leds_gpio), + r6100_leds_gpio); + ath79_register_gpio_keys_polled(-1, R6100_KEYS_POLL_INTERVAL, + ARRAY_SIZE(r6100_gpio_keys), + r6100_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + gpio_request_one(R6100_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); + ath79_register_nfc(); + + ath79_register_usb(); + + ath79_register_wmac_simple(); + + ap91_pci_init_simple(); +} + +MIPS_MACHINE(ATH79_MACH_R6100, "R6100", "NETGEAR R6100", + r6100_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c new file mode 100644 index 0000000..afd5608 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c @@ -0,0 +1,338 @@ +/* + * MikroTik RouterBOARD 2011 support + * + * Copyright (C) 2012 Stijn Tintel + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb2011: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "routerboot.h" + +#define RB2011_GPIO_NAND_NCE 14 +#define RB2011_GPIO_SFP_LOS 21 + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_MIN_SIZE 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x1000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +#define RB_ART_SIZE 0x10000 + +#define RB2011_FLAG_SFP BIT(0) +#define RB2011_FLAG_USB BIT(1) +#define RB2011_FLAG_WLAN BIT(2) + +static struct mtd_partition rb2011_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .size = RB_SOFT_CFG_SIZE, + } +}; + +static void __init rb2011_init_partitions(const struct rb_info *info) +{ + rb2011_spi_partitions[0].size = info->hard_cfg_offs; + rb2011_spi_partitions[1].offset = info->hard_cfg_offs; + rb2011_spi_partitions[3].offset = info->soft_cfg_offs; +} + +static struct mtd_partition rb2011_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data rb2011_spi_flash_data = { + .parts = rb2011_spi_partitions, + .nr_parts = ARRAY_SIZE(rb2011_spi_partitions), +}; + +static struct ar8327_pad_cfg rb2011_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL3, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_pad_cfg rb2011_ar8327_pad6_cfg; +static struct ar8327_sgmii_cfg rb2011_ar8327_sgmii_cfg; + +static struct ar8327_led_cfg rb2011_ar8327_led_cfg = { + .led_ctrl0 = 0xc731c731, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static const struct ar8327_led_info rb2011_ar8327_leds[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "rb:green:eth1"), + AR8327_LED_INFO(PHY1_0, HW, "rb:green:eth2"), + AR8327_LED_INFO(PHY2_0, HW, "rb:green:eth3"), + AR8327_LED_INFO(PHY3_0, HW, "rb:green:eth4"), + AR8327_LED_INFO(PHY4_0, HW, "rb:green:eth5"), + AR8327_LED_INFO(PHY0_1, SW, "rb:green:eth6"), + AR8327_LED_INFO(PHY1_1, SW, "rb:green:eth7"), + AR8327_LED_INFO(PHY2_1, SW, "rb:green:eth8"), + AR8327_LED_INFO(PHY3_1, SW, "rb:green:eth9"), + AR8327_LED_INFO(PHY4_1, SW, "rb:green:eth10"), + AR8327_LED_INFO(PHY4_2, SW, "rb:green:usr"), +}; + +static struct ar8327_platform_data rb2011_ar8327_data = { + .pad0_cfg = &rb2011_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &rb2011_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(rb2011_ar8327_leds), + .leds = rb2011_ar8327_leds, +}; + +static struct mdio_board_info rb2011_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb2011_ar8327_data, + }, +}; + +static void __init rb2011_wlan_init(void) +{ + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + + art_buf = rb_get_wlan_data(); + if (art_buf == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 11); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + + kfree(art_buf); +} + +static void rb2011_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB2011_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB2011_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb2011_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb2011_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb2011_nand_ecclayout; + } + + return 0; +} + +static void __init rb2011_nand_init(void) +{ + gpio_request_one(RB2011_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); + + ath79_nfc_set_scan_fixup(rb2011_nand_scan_fixup); + ath79_nfc_set_parts(rb2011_nand_partitions, + ARRAY_SIZE(rb2011_nand_partitions)); + ath79_nfc_set_select_chip(rb2011_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + +static int rb2011_get_port_link(unsigned port) +{ + if (port != 6) + return -EINVAL; + + /* The Loss of signal line is active low */ + return !gpio_get_value(RB2011_GPIO_SFP_LOS); +} + +static void __init rb2011_sfp_init(void) +{ + gpio_request_one(RB2011_GPIO_SFP_LOS, GPIOF_IN, "SFP LOS"); + + rb2011_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; + + rb2011_ar8327_data.pad6_cfg = &rb2011_ar8327_pad6_cfg; + + rb2011_ar8327_sgmii_cfg.sgmii_ctrl = 0xc70167d0; + rb2011_ar8327_sgmii_cfg.serdes_aen = true; + + rb2011_ar8327_data.sgmii_cfg = &rb2011_ar8327_sgmii_cfg; + + rb2011_ar8327_data.port6_cfg.force_link = 1; + rb2011_ar8327_data.port6_cfg.speed = AR8327_PORT_SPEED_1000; + rb2011_ar8327_data.port6_cfg.duplex = 1; + + rb2011_ar8327_data.get_port_link = rb2011_get_port_link; +} + +static int __init rb2011_setup(u32 flags) +{ + const struct rb_info *info; + char buf[64]; + + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); + if (!info) + return -ENODEV; + + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", + (info->board_name) ? info->board_name : ""); + mips_set_machine_name(buf); + + rb2011_init_partitions(info); + + ath79_register_m25p80(&rb2011_spi_flash_data); + rb2011_nand_init(); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb2011_mdio0_info, + ARRAY_SIZE(rb2011_mdio0_info)); + + /* GMAC0 is connected to an ar8327 switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); + + if (flags & RB2011_FLAG_SFP) + rb2011_sfp_init(); + + if (flags & RB2011_FLAG_WLAN) + rb2011_wlan_init(); + + if (flags & RB2011_FLAG_USB) + ath79_register_usb(); + + return 0; +} + +static void __init rb2011l_setup(void) +{ + rb2011_setup(0); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011L, "2011L", rb2011l_setup); + +static void __init rb2011us_setup(void) +{ + rb2011_setup(RB2011_FLAG_SFP | RB2011_FLAG_USB); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011US, "2011US", rb2011us_setup); + +static void __init rb2011r5_setup(void) +{ + rb2011_setup(RB2011_FLAG_SFP | RB2011_FLAG_USB | RB2011_FLAG_WLAN); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011R5, "2011r5", rb2011r5_setup); + +static void __init rb2011g_setup(void) +{ + rb2011_setup(RB2011_FLAG_SFP | + RB2011_FLAG_USB | + RB2011_FLAG_WLAN); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011G, "2011G", rb2011g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c new file mode 100644 index 0000000..1a61b45 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c @@ -0,0 +1,465 @@ +/* + * MikroTik RouterBOARD 4xx series support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define RB4XX_GPIO_USER_LED 4 +#define RB4XX_GPIO_RESET_SWITCH 7 + +#define RB4XX_GPIO_CPLD_BASE 32 +#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1) +#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2) +#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3) +#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4) +#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5) + +#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL) + +static struct gpio_led rb4xx_leds_gpio[] __initdata = { + { + .name = "rb4xx:yellow:user", + .gpio = RB4XX_GPIO_USER_LED, + .active_low = 0, + }, { + .name = "rb4xx:green:led1", + .gpio = RB4XX_GPIO_CPLD_LED1, + .active_low = 1, + }, { + .name = "rb4xx:green:led2", + .gpio = RB4XX_GPIO_CPLD_LED2, + .active_low = 1, + }, { + .name = "rb4xx:green:led3", + .gpio = RB4XX_GPIO_CPLD_LED3, + .active_low = 1, + }, { + .name = "rb4xx:green:led4", + .gpio = RB4XX_GPIO_CPLD_LED4, + .active_low = 1, + }, { + .name = "rb4xx:green:led5", + .gpio = RB4XX_GPIO_CPLD_LED5, + .active_low = 0, + }, +}; + +static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = { + { + .desc = "reset_switch", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL, + .gpio = RB4XX_GPIO_RESET_SWITCH, + .active_low = 1, + } +}; + +static struct platform_device rb4xx_nand_device = { + .name = "rb4xx-nand", + .id = -1, +}; + +static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = { + { + .slot = 17, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 18, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 18, + .pin = 2, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 2, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 20, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 20, + .pin = 2, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 21, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 22, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 22, + .pin = 2, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 23, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 23, + .pin = 2, + .irq = ATH79_PCI_IRQ(0), + } +}; + +static struct mtd_partition rb4xx_partitions[] = { + { + .name = "routerboot", + .offset = 0, + .size = 0x0b000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .offset = 0x0b000, + .size = 0x01000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = 0x0d000, + .size = 0x02000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .offset = 0x0f000, + .size = 0x01000, + } +}; + +static struct flash_platform_data rb4xx_flash_data = { + .type = "pm25lv512", + .parts = rb4xx_partitions, + .nr_parts = ARRAY_SIZE(rb4xx_partitions), +}; + +static struct rb4xx_cpld_platform_data rb4xx_cpld_data = { + .gpio_base = RB4XX_GPIO_CPLD_BASE, +}; + +static struct mmc_spi_platform_data rb4xx_mmc_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct spi_board_info rb4xx_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .platform_data = &rb4xx_flash_data, + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "spi-rb4xx-cpld", + .platform_data = &rb4xx_cpld_data, + } +}; + +static struct spi_board_info rb4xx_microsd_info[] = { + { + .bus_num = 0, + .chip_select = 2, + .max_speed_hz = 25000000, + .modalias = "mmc_spi", + .platform_data = &rb4xx_mmc_data, + } +}; + + +static struct resource rb4xx_spi_resources[] = { + { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rb4xx_spi_device = { + .name = "rb4xx-spi", + .id = -1, + .resource = rb4xx_spi_resources, + .num_resources = ARRAY_SIZE(rb4xx_spi_resources), +}; + +static void __init rb4xx_generic_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), + rb4xx_leds_gpio); + + ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rb4xx_gpio_keys), + rb4xx_gpio_keys); + + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); + platform_device_register(&rb4xx_spi_device); + platform_device_register(&rb4xx_nand_device); +} + +static void __init rb411_setup(void) +{ + rb4xx_generic_setup(); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, 0xfffffffc); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x00000003; + + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", + rb411_setup); + +static void __init rb411u_setup(void) +{ + rb411_setup(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", + rb411u_setup); + +#define RB433_LAN_PHYMASK BIT(0) +#define RB433_WAN_PHYMASK BIT(4) +#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK) + +static void __init rb433_setup(void) +{ + rb4xx_generic_setup(); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", + rb433_setup); + +static void __init rb433u_setup(void) +{ + rb433_setup(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", + rb433u_setup); + +static void __init rb435g_setup(void) +{ + rb4xx_generic_setup(); + + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G", + rb435g_setup); + +#define RB450_LAN_PHYMASK BIT(0) +#define RB450_WAN_PHYMASK BIT(4) +#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK) + +static void __init rb450_generic_setup(int gige) +{ + rb4xx_generic_setup(); + ath79_register_mdio(0, ~RB450_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = (gige) ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = (gige) ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); +} + +static void __init rb450_setup(void) +{ + rb450_generic_setup(0); +} + +MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450", + rb450_setup); + +static void __init rb450g_setup(void) +{ + rb450_generic_setup(1); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); +} + +MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", + rb450g_setup); + +static void __init rb493_setup(void) +{ + rb4xx_generic_setup(); + + ath79_register_mdio(0, 0x3fffff00); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x00000001; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", + rb493_setup); + +#define RB493G_GPIO_MDIO_MDC 7 +#define RB493G_GPIO_MDIO_DATA 8 + +#define RB493G_MDIO_PHYMASK BIT(0) + +static struct mdio_gpio_platform_data rb493g_mdio_data = { + .mdc = RB493G_GPIO_MDIO_MDC, + .mdio = RB493G_GPIO_MDIO_DATA, + + .phy_mask = ~RB493G_MDIO_PHYMASK, +}; + +static struct platform_device rb493g_mdio_device = { + .name = "mdio-gpio", + .id = -1, + .dev = { + .platform_data = &rb493g_mdio_data, + }, +}; + +static void __init rb493g_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), + rb4xx_leds_gpio); + + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + platform_device_register(&rb4xx_spi_device); + platform_device_register(&rb4xx_nand_device); + + ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev; + ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + platform_device_register(&rb493g_mdio_device); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G", + rb493g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c new file mode 100644 index 0000000..5656d3c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c @@ -0,0 +1,346 @@ +/* + * MikroTik RouterBOARD 750/750GL support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-usb.h" +#include "dev-eth.h" +#include "machtypes.h" +#include "routerboot.h" + +static struct rb750_led_data rb750_leds[] = { + { + .name = "rb750:green:act", + .mask = RB750_LED_ACT, + .active_low = 1, + }, { + .name = "rb750:green:port1", + .mask = RB750_LED_PORT5, + .active_low = 1, + }, { + .name = "rb750:green:port2", + .mask = RB750_LED_PORT4, + .active_low = 1, + }, { + .name = "rb750:green:port3", + .mask = RB750_LED_PORT3, + .active_low = 1, + }, { + .name = "rb750:green:port4", + .mask = RB750_LED_PORT2, + .active_low = 1, + }, { + .name = "rb750:green:port5", + .mask = RB750_LED_PORT1, + .active_low = 1, + } +}; + +static struct rb750_led_data rb750gr3_leds[] = { + { + .name = "rb750:green:act", + .mask = RB7XX_LED_ACT, + .active_low = 1, + }, +}; + +static struct rb750_led_platform_data rb750_leds_data; +static struct platform_device rb750_leds_device = { + .name = "leds-rb750", + .dev = { + .platform_data = &rb750_leds_data, + } +}; + +static struct rb7xx_nand_platform_data rb750_nand_data; +static struct platform_device rb750_nand_device = { + .name = "rb750-nand", + .id = -1, + .dev = { + .platform_data = &rb750_nand_data, + } +}; + +static void rb750_latch_change(u32 mask_clr, u32 mask_set) +{ + static DEFINE_SPINLOCK(lock); + static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; + static u32 latch_oe; + static u32 latch_clr; + unsigned long flags; + u32 t; + + spin_lock_irqsave(&lock, flags); + + if ((mask_clr & BIT(31)) != 0 && + (latch_set & RB750_LVC573_LE) == 0) { + goto unlock; + } + + latch_set = (latch_set | mask_set) & ~mask_clr; + latch_clr = (latch_clr | mask_clr) & ~mask_set; + + if (latch_oe == 0) + latch_oe = __raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_OE); + + if (likely(latch_set & RB750_LVC573_LE)) { + void __iomem *base = ath79_gpio_base; + + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= mask_clr | latch_oe | mask_set; + + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + __raw_writel(latch_clr, base + AR71XX_GPIO_REG_CLEAR); + __raw_writel(latch_set, base + AR71XX_GPIO_REG_SET); + } else if (mask_clr & RB750_LVC573_LE) { + void __iomem *base = ath79_gpio_base; + + latch_oe = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(RB750_LVC573_LE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + } + +unlock: + spin_unlock_irqrestore(&lock, flags); +} + +static void rb750_nand_enable_pins(void) +{ + rb750_latch_change(RB750_LVC573_LE, 0); + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_SPI_EN); +} + +static void rb750_nand_disable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, + AR724X_GPIO_FUNC_JTAG_DISABLE); + rb750_latch_change(0, RB750_LVC573_LE); +} + +static void __init rb750_setup(void) +{ + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + rb750_leds_data.num_leds = ARRAY_SIZE(rb750_leds); + rb750_leds_data.leds = rb750_leds; + rb750_leds_data.latch_change = rb750_latch_change; + platform_device_register(&rb750_leds_device); + + rb750_nand_data.nce_line = RB750_NAND_NCE; + rb750_nand_data.enable_pins = rb750_nand_enable_pins; + rb750_nand_data.disable_pins = rb750_nand_disable_pins; + rb750_nand_data.latch_change = rb750_latch_change; + platform_device_register(&rb750_nand_device); +} + +MIPS_MACHINE(ATH79_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", + rb750_setup); + +static struct ar8327_pad_cfg rb750gr3_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data rb750gr3_ar8327_data = { + .pad0_cfg = &rb750gr3_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info rb750g3_mdio_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb750gr3_ar8327_data, + }, +}; + +static void rb750gr3_nand_enable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_SPI_EN | + AR724X_GPIO_FUNC_SPI_CS_EN2); +} + +static void rb750gr3_nand_disable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN | + AR724X_GPIO_FUNC_SPI_CS_EN2, + AR724X_GPIO_FUNC_JTAG_DISABLE); +} + +static void rb750gr3_latch_change(u32 mask_clr, u32 mask_set) +{ + static DEFINE_SPINLOCK(lock); + static u32 latch_set = RB7XX_LED_ACT; + static u32 latch_clr; + void __iomem *base = ath79_gpio_base; + unsigned long flags; + u32 t; + + spin_lock_irqsave(&lock, flags); + + latch_set = (latch_set | mask_set) & ~mask_clr; + latch_clr = (latch_clr | mask_clr) & ~mask_set; + + mask_set = latch_set & (RB7XX_USB_POWERON | RB7XX_MONITOR); + mask_clr = latch_clr & (RB7XX_USB_POWERON | RB7XX_MONITOR); + + if ((latch_set ^ RB7XX_LED_ACT) & RB7XX_LED_ACT) { + /* enable output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= RB7XX_LED_ACT; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + + mask_clr |= RB7XX_LED_ACT; + } else { + /* disable output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t &= ~RB7XX_LED_ACT; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + } + + __raw_writel(mask_set, base + AR71XX_GPIO_REG_SET); + __raw_writel(mask_clr, base + AR71XX_GPIO_REG_CLEAR); + + spin_unlock_irqrestore(&lock, flags); +} + +static void __init rb750gr3_setup(void) +{ + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(rb750g3_mdio_info, + ARRAY_SIZE(rb750g3_mdio_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_pll_data.pll_1000 = 0x62000000; + + ath79_register_eth(0); + + rb750_leds_data.num_leds = ARRAY_SIZE(rb750gr3_leds); + rb750_leds_data.leds = rb750gr3_leds; + rb750_leds_data.latch_change = rb750gr3_latch_change; + platform_device_register(&rb750_leds_device); + + rb750_nand_data.nce_line = RB7XX_NAND_NCE; + rb750_nand_data.enable_pins = rb750gr3_nand_enable_pins; + rb750_nand_data.disable_pins = rb750gr3_nand_disable_pins; + rb750_nand_data.latch_change = rb750gr3_latch_change; + platform_device_register(&rb750_nand_device); +} + +MIPS_MACHINE(ATH79_MACH_RB_750G_R3, "750Gr3", "MikroTik RouterBOARD 750GL", + rb750gr3_setup); + +#define RB751_HARDCONFIG 0x1f00b000 +#define RB751_HARDCONFIG_SIZE 0x1000 + +static void __init rb751_wlan_setup(void) +{ + u8 *hardconfig = (u8 *) KSEG1ADDR(RB751_HARDCONFIG); + struct ath9k_platform_data *wmac_data; + u16 tag_len; + u8 *tag; + u16 mac_len; + u8 *mac; + int err; + + wmac_data = ap9x_pci_get_wmac_data(0); + if (!wmac_data) { + pr_err("rb75x: unable to get address of wlan data\n"); + return; + } + + ap9x_pci_setup_wmac_led_pin(0, 9); + + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE, + RB_ID_WLAN_DATA, &tag, &tag_len); + if (err) { + pr_err("rb75x: no calibration data found\n"); + return; + } + + err = rle_decode(tag, tag_len, (unsigned char *) wmac_data->eeprom_data, + sizeof(wmac_data->eeprom_data), NULL, NULL); + if (err) { + pr_err("rb75x: unable to decode wlan eeprom data\n"); + return; + } + + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE, + RB_ID_MAC_ADDRESS_PACK, &mac, &mac_len); + if (err) { + pr_err("rb75x: no mac address found\n"); + return; + } + + ap91_pci_init(NULL, mac); +} + +static void __init rb751_setup(void) +{ + rb750_setup(); + ath79_register_usb(); + rb751_wlan_setup(); +} + +MIPS_MACHINE(ATH79_MACH_RB_751, "751", "MikroTik RouterBOARD 751", + rb751_setup); + +static void __init rb751g_setup(void) +{ + rb750gr3_setup(); + ath79_register_usb(); + rb751_wlan_setup(); +} + +MIPS_MACHINE(ATH79_MACH_RB_751G, "751g", "MikroTik RouterBOARD 751G", + rb751g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c new file mode 100644 index 0000000..9ef5c44 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c @@ -0,0 +1,349 @@ +/* + * MikroTik RouterBOARD 91X support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb91x: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" +#include "routerboot.h" + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_MIN_SIZE 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x1000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +#define RB91X_FLAG_USB BIT(0) +#define RB91X_FLAG_PCIE BIT(1) + +#define RB91X_LATCH_GPIO_BASE AR934X_GPIO_COUNT +#define RB91X_LATCH_GPIO(_x) (RB91X_LATCH_GPIO_BASE + (_x)) + +#define RB91X_SSR_GPIO_BASE (RB91X_LATCH_GPIO_BASE + AR934X_GPIO_COUNT) +#define RB91X_SSR_GPIO(_x) (RB91X_SSR_GPIO_BASE + (_x)) + +#define RB91X_SSR_BIT_LED1 0 +#define RB91X_SSR_BIT_LED2 1 +#define RB91X_SSR_BIT_LED3 2 +#define RB91X_SSR_BIT_LED4 3 +#define RB91X_SSR_BIT_LED5 4 +#define RB91X_SSR_BIT_5 5 +#define RB91X_SSR_BIT_USB_POWER 6 +#define RB91X_SSR_BIT_PCIE_POWER 7 + +#define RB91X_GPIO_SSR_STROBE RB91X_LATCH_GPIO(0) +#define RB91X_GPIO_LED_POWER RB91X_LATCH_GPIO(1) +#define RB91X_GPIO_LED_USER RB91X_LATCH_GPIO(2) +#define RB91X_GPIO_NAND_READ RB91X_LATCH_GPIO(3) +#define RB91X_GPIO_NAND_RDY RB91X_LATCH_GPIO(4) +#define RB91X_GPIO_NLE RB91X_LATCH_GPIO(11) +#define RB91X_GPIO_NAND_NRW RB91X_LATCH_GPIO(12) +#define RB91X_GPIO_NAND_NCE RB91X_LATCH_GPIO(13) +#define RB91X_GPIO_NAND_CLE RB91X_LATCH_GPIO(14) +#define RB91X_GPIO_NAND_ALE RB91X_LATCH_GPIO(15) + +#define RB91X_GPIO_LED_1 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED1) +#define RB91X_GPIO_LED_2 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED2) +#define RB91X_GPIO_LED_3 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED3) +#define RB91X_GPIO_LED_4 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED4) +#define RB91X_GPIO_LED_5 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED5) +#define RB91X_GPIO_USB_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_USB_POWER) +#define RB91X_GPIO_PCIE_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_PCIE_POWER) + +struct rb_board_info { + const char *name; + u32 flags; +}; + +static struct mtd_partition rb711gr100_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .size = RB_SOFT_CFG_SIZE, + } +}; + +static struct flash_platform_data rb711gr100_spi_flash_data = { + .parts = rb711gr100_spi_partitions, + .nr_parts = ARRAY_SIZE(rb711gr100_spi_partitions), +}; + +static int rb711gr100_gpio_latch_gpios[AR934X_GPIO_COUNT] __initdata = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 +}; + +static struct gpio_latch_platform_data rb711gr100_gpio_latch_data __initdata = { + .base = RB91X_LATCH_GPIO_BASE, + .num_gpios = ARRAY_SIZE(rb711gr100_gpio_latch_gpios), + .gpios = rb711gr100_gpio_latch_gpios, + .le_gpio_index = 11, + .le_active_low = true, +}; + +static struct rb91x_nand_platform_data rb711gr100_nand_data __initdata = { + .gpio_nce = RB91X_GPIO_NAND_NCE, + .gpio_ale = RB91X_GPIO_NAND_ALE, + .gpio_cle = RB91X_GPIO_NAND_CLE, + .gpio_rdy = RB91X_GPIO_NAND_RDY, + .gpio_read = RB91X_GPIO_NAND_READ, + .gpio_nrw = RB91X_GPIO_NAND_NRW, + .gpio_nle = RB91X_GPIO_NLE, +}; + +static u8 rb711gr100_ssr_initdata[] __initdata = { + BIT(RB91X_SSR_BIT_PCIE_POWER) | + BIT(RB91X_SSR_BIT_USB_POWER) | + BIT(RB91X_SSR_BIT_5) +}; + +static struct gen_74x164_chip_platform_data rb711gr100_ssr_data = { + .base = RB91X_SSR_GPIO_BASE, + .num_registers = ARRAY_SIZE(rb711gr100_ssr_initdata), + .init_data = rb711gr100_ssr_initdata, +}; + +static struct ath79_spi_controller_data rb711gr100_spi0_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, + .is_flash = true, +}; + +static struct ath79_spi_controller_data rb711gr100_spi1_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_GPIO, + .cs_line = RB91X_GPIO_SSR_STROBE, +}; + +static struct spi_board_info rb711gr100_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .platform_data = &rb711gr100_spi_flash_data, + .controller_data = &rb711gr100_spi0_cdata + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 10000000, + .modalias = "74x164", + .platform_data = &rb711gr100_ssr_data, + .controller_data = &rb711gr100_spi1_cdata + } +}; + +static struct ath79_spi_platform_data rb711gr100_spi_data __initdata = { + .bus_num = 0, + .num_chipselect = 2, +}; + +static struct gpio_led rb711gr100_leds[] __initdata = { + { + .name = "rb:green:led1", + .gpio = RB91X_GPIO_LED_1, + .active_low = 0, + }, + { + .name = "rb:green:led2", + .gpio = RB91X_GPIO_LED_2, + .active_low = 0, + }, + { + .name = "rb:green:led3", + .gpio = RB91X_GPIO_LED_3, + .active_low = 0, + }, + { + .name = "rb:green:led4", + .gpio = RB91X_GPIO_LED_4, + .active_low = 0, + }, + { + .name = "rb:green:led5", + .gpio = RB91X_GPIO_LED_5, + .active_low = 0, + }, + { + .name = "rb:green:user", + .gpio = RB91X_GPIO_LED_USER, + .active_low = 0, + }, + { + .name = "rb:green:power", + .gpio = RB91X_GPIO_LED_POWER, + .active_low = 0, + }, +}; + +static struct at803x_platform_data rb91x_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info rb91x_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb91x_at803x_data, + }, +}; + +static void __init rb711gr100_init_partitions(const struct rb_info *info) +{ + rb711gr100_spi_partitions[0].size = info->hard_cfg_offs; + rb711gr100_spi_partitions[1].offset = info->hard_cfg_offs; + + rb711gr100_spi_partitions[3].offset = info->soft_cfg_offs; +} + +void __init rb711gr100_wlan_init(void) +{ + char *caldata; + u8 wlan_mac[ETH_ALEN]; + + caldata = rb_get_wlan_data(); + if (caldata == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 1); + ath79_register_wmac(caldata + 0x1000, wlan_mac); + + kfree(caldata); +} + +#define RB_BOARD_INFO(_name, _flags) \ + { \ + .name = (_name), \ + .flags = (_flags), \ + } + +static const struct rb_board_info rb711gr100_boards[] __initconst = { + RB_BOARD_INFO("911G-2HPnD", 0), + RB_BOARD_INFO("911G-5HPnD", 0), + RB_BOARD_INFO("912UAG-2HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE), + RB_BOARD_INFO("912UAG-5HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE), +}; + +static u32 rb711gr100_get_flags(const struct rb_info *info) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rb711gr100_boards); i++) { + const struct rb_board_info *bi; + + bi = &rb711gr100_boards[i]; + if (strcmp(info->board_name, bi->name) == 0) + return bi->flags; + } + + return 0; +} + +static void __init rb711gr100_setup(void) +{ + const struct rb_info *info; + char buf[64]; + u32 flags; + + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); + if (!info) + return; + + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", + (info->board_name) ? info->board_name : ""); + mips_set_machine_name(buf); + + rb711gr100_init_partitions(info); + ath79_register_spi(&rb711gr100_spi_data, rb711gr100_spi_info, + ARRAY_SIZE(rb711gr100_spi_info)); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_RXD_DELAY | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb91x_mdio0_info, + ARRAY_SIZE(rb91x_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_pll_data.pll_1000 = 0x02000000; + + ath79_register_eth(0); + + rb711gr100_wlan_init(); + + platform_device_register_data(NULL, "rb91x-nand", -1, + &rb711gr100_nand_data, + sizeof(rb711gr100_nand_data)); + + platform_device_register_data(NULL, "gpio-latch", -1, + &rb711gr100_gpio_latch_data, + sizeof(rb711gr100_gpio_latch_data)); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb711gr100_leds), + rb711gr100_leds); + + flags = rb711gr100_get_flags(info); + + if (flags & RB91X_FLAG_USB) + ath79_register_usb(); + + if (flags & RB91X_FLAG_PCIE) + ath79_register_pci(); + +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_711GR100, "711Gr100", rb711gr100_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c new file mode 100644 index 0000000..c88c522 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c @@ -0,0 +1,236 @@ +/* + * MikroTik RouterBOARD 91X support + * + * Copyright (C) 2015 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-spi.h" +#include "machtypes.h" +#include "pci.h" +#include "routerboot.h" + +#define RB922_GPIO_LED_USR 12 +#define RB922_GPIO_USB_POWER 13 +#define RB922_GPIO_FAN_CTRL 14 +#define RB922_GPIO_BTN_RESET 20 +#define RB922_GPIO_NAND_NCE 23 + +#define RB922_PHY_ADDR 4 + +#define RB922_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RB922_KEYS_DEBOUNCE_INTERVAL (3 * RB922_KEYS_POLL_INTERVAL) + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_MIN_SIZE 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x1000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +static struct mtd_partition rb922gs_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .size = RB_SOFT_CFG_SIZE, + } +}; + +static struct flash_platform_data rb922gs_spi_flash_data = { + .parts = rb922gs_spi_partitions, + .nr_parts = ARRAY_SIZE(rb922gs_spi_partitions), +}; + +static struct gpio_led rb922gs_leds[] __initdata = { + { + .name = "rb:green:user", + .gpio = RB922_GPIO_LED_USR, + .active_low = 1, + }, +}; + +static struct gpio_keys_button rb922gs_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RB922_KEYS_DEBOUNCE_INTERVAL, + .gpio = RB922_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct at803x_platform_data rb922gs_at803x_data = { + .disable_smarteee = 1, +}; + +static struct mdio_board_info rb922gs_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = RB922_PHY_ADDR, + .platform_data = &rb922gs_at803x_data, + }, +}; + +static void __init rb922gs_init_partitions(const struct rb_info *info) +{ + rb922gs_spi_partitions[0].size = info->hard_cfg_offs; + rb922gs_spi_partitions[1].offset = info->hard_cfg_offs; + rb922gs_spi_partitions[3].offset = info->soft_cfg_offs; +} + +static void rb922gs_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB922_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB922_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb922gs_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb922gs_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb922gs_nand_ecclayout; + } + + return 0; +} + +static struct mtd_partition rb922gs_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void __init rb922gs_nand_init(void) +{ + gpio_request_one(RB922_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); + + ath79_nfc_set_scan_fixup(rb922gs_nand_scan_fixup); + ath79_nfc_set_parts(rb922gs_nand_partitions, + ARRAY_SIZE(rb922gs_nand_partitions)); + ath79_nfc_set_select_chip(rb922gs_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + +static void __init rb922gs_setup(void) +{ + const struct rb_info *info; + char buf[64]; + + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); + if (!info) + return; + + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", + (info->board_name) ? info->board_name : ""); + mips_set_machine_name(buf); + + rb922gs_init_partitions(info); + ath79_register_m25p80(&rb922gs_spi_flash_data); + + rb922gs_nand_init(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb922gs_mdio0_info, + ARRAY_SIZE(rb922gs_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR); + ath79_eth0_pll_data.pll_10 = 0x81001313; + ath79_eth0_pll_data.pll_100 = 0x81000101; + ath79_eth0_pll_data.pll_1000 = 0x8f000000; + + ath79_register_eth(0); + + ath79_register_pci(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds); + ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rb922gs_gpio_keys), + rb922gs_gpio_keys); + + /* NOTE: + * This only supports the RB911G-5HPacD board for now. For other boards + * more devices must be registered based on the hardware options which + * can be found in the hardware configuration of RouterBOOT. + */ +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_922GS, "922gs", rb922gs_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c new file mode 100644 index 0000000..c2261ab --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c @@ -0,0 +1,258 @@ +/* + * MikroTik RouterBOARD 95X support + * + * Copyright (C) 2012 Stijn Tintel + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Kamil Trzcinski + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb95x: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "routerboot.h" +#include "dev-leds-gpio.h" + +#define RB95X_GPIO_NAND_NCE 14 + +static struct mtd_partition rb95x_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct gpio_led rb951ui_leds_gpio[] __initdata = { + { + .name = "rb:green:wlan", + .gpio = 11, + .active_low = 1, + }, { + .name = "rb:green:act", + .gpio = 3, + .active_low = 1, + }, { + .name = "rb:green:port1", + .gpio = 13, + .active_low = 1, + }, { + .name = "rb:green:port2", + .gpio = 12, + .active_low = 1, + }, { + .name = "rb:green:port3", + .gpio = 4, + .active_low = 1, + }, { + .name = "rb:green:port4", + .gpio = 21, + .active_low = 1, + }, { + .name = "rb:green:port5", + .gpio = 16, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg rb95x_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data rb95x_ar8327_data = { + .pad0_cfg = &rb95x_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info rb95x_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb95x_ar8327_data, + }, +}; + +void __init rb95x_wlan_init(void) +{ + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + + art_buf = rb_get_wlan_data(); + if (art_buf == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 11); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + + kfree(art_buf); +} + +static void rb95x_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB95X_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB95X_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb95x_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb95x_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb95x_nand_ecclayout; + } + + return 0; +} + +void __init rb95x_nand_init(void) +{ + gpio_request_one(RB95X_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); + + ath79_nfc_set_scan_fixup(rb95x_nand_scan_fixup); + ath79_nfc_set_parts(rb95x_nand_partitions, + ARRAY_SIZE(rb95x_nand_partitions)); + ath79_nfc_set_select_chip(rb95x_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + +static int __init rb95x_setup(void) +{ + const struct rb_info *info; + + info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000); + if (!info) + return -EINVAL; + + rb95x_nand_init(); + + return 0; +} + +static void __init rb951g_setup(void) +{ + if (rb95x_setup()) + return; + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb95x_mdio0_info, + ARRAY_SIZE(rb95x_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + rb95x_wlan_init(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_951G, "951G", "MikroTik RouterBOARD 951G-2HnD", + rb951g_setup); + +static void __init rb951ui_setup(void) +{ + if (rb95x_setup()) + return; + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + gpio_request_one(20, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "POE power"); + + rb95x_wlan_init(); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb951ui_leds_gpio), + rb951ui_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_RB_951U, "951HnD", "MikroTik RouterBOARD 951Ui-2HnD", + rb951ui_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c new file mode 100644 index 0000000..94e0b44 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c @@ -0,0 +1,238 @@ +/* + * MikroTik RouterBOARD SXT Lite support + * + * Copyright (C) 2012 Stijn Tintel + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Vyacheslav Adamanov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "sxtlite: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-wmac.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "routerboot.h" +#include + +#define SXTLITE_GPIO_NAND_NCE 14 +#define SXTLITE_GPIO_LED_USER 3 +#define SXTLITE_GPIO_LED_1 13 +#define SXTLITE_GPIO_LED_2 12 +#define SXTLITE_GPIO_LED_3 4 +#define SXTLITE_GPIO_LED_4 21 +#define SXTLITE_GPIO_LED_5 18 +#define SXTLITE_GPIO_LED_POWER 11 + +#define SXTLITE_GPIO_BUZZER 19 + +#define SXTLITE_GPIO_BTN_RESET 15 + +#define SXTLITE_KEYS_POLL_INTERVAL 20 +#define SXTLITE_KEYS_DEBOUNCE_INTERVAL (3 * SXTLITE_KEYS_POLL_INTERVAL) + +static struct mtd_partition rbsxtlite_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct gpio_led rbsxtlite_leds_gpio[] __initdata = { + { + .name = "rb:green:user", + .gpio = SXTLITE_GPIO_LED_USER, + .active_low = 1, + }, + { + .name = "rb:green:led1", + .gpio = SXTLITE_GPIO_LED_1, + .active_low = 1, + }, + { + .name = "rb:green:led2", + .gpio = SXTLITE_GPIO_LED_2, + .active_low = 1, + }, + { + .name = "rb:green:led3", + .gpio = SXTLITE_GPIO_LED_3, + .active_low = 1, + }, + { + .name = "rb:green:led4", + .gpio = SXTLITE_GPIO_LED_4, + .active_low = 1, + }, + { + .name = "rb:green:led5", + .gpio = SXTLITE_GPIO_LED_5, + .active_low = 1, + }, + { + .name = "rb:green:power", + .gpio = SXTLITE_GPIO_LED_POWER, + }, +}; + +static struct gpio_keys_button rbsxtlite_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = SXTLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = SXTLITE_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static int __init rbsxtlite_rbinfo_init(void) +{ + const struct rb_info *info; + + info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000); + if (!info) + return -EINVAL; + return 0; + +} + +void __init rbsxtlite_wlan_init(void) +{ + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + + art_buf = rb_get_wlan_data(); + if (art_buf == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 1); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + + kfree(art_buf); +} + +static void rbsxtlite_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(SXTLITE_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(SXTLITE_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rbsxtlite_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rbsxtlite_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rbsxtlite_nand_ecclayout; + } + + return 0; +} + +void __init rbsxtlite_gpio_init(void) +{ + gpio_request_one(SXTLITE_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); +} + +void __init rbsxtlite_nand_init(void) +{ + ath79_nfc_set_scan_fixup(rbsxtlite_nand_scan_fixup); + ath79_nfc_set_parts(rbsxtlite_nand_partitions, + ARRAY_SIZE(rbsxtlite_nand_partitions)); + ath79_nfc_set_select_chip(rbsxtlite_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + + +static void __init rbsxtlite_setup(void) +{ + if(rbsxtlite_rbinfo_init()) + return; + rbsxtlite_nand_init(); + rbsxtlite_wlan_init(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rbsxtlite_leds_gpio), + rbsxtlite_leds_gpio); + ath79_register_gpio_keys_polled(-1, SXTLITE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rbsxtlite_gpio_keys), + rbsxtlite_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* GMAC0 is left unused */ + + /* GMAC1 is connected to MAC0 on the internal switch */ + /* The ethernet port connects to PHY P0, which connects to MAC1 + on the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + +} + + +MIPS_MACHINE(ATH79_MACH_RB_SXTLITE2ND, "sxt2n", "Mikrotik RouterBOARD SXT Lite2", + rbsxtlite_setup); + +MIPS_MACHINE(ATH79_MACH_RB_SXTLITE5ND, "sxt5n", "Mikrotik RouterBOARD SXT Lite5", + rbsxtlite_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c new file mode 100644 index 0000000..bb7c247 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c @@ -0,0 +1,91 @@ +/* + * Redwave RW2458N support + * + * Copyright (C) 2011-2013 Cezary Jackiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define RW2458N_GPIO_LED_D3 1 +#define RW2458N_GPIO_LED_D4 0 +#define RW2458N_GPIO_LED_D5 11 +#define RW2458N_GPIO_LED_D6 7 +#define RW2458N_GPIO_BTN_RESET 12 + +#define RW2458N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RW2458N_KEYS_DEBOUNCE_INTERVAL (3 * RW2458N_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button rw2458n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RW2458N_KEYS_DEBOUNCE_INTERVAL, + .gpio = RW2458N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define RW2458N_WAN_PHYMASK BIT(4) + +static struct gpio_led rw2458n_leds_gpio[] __initdata = { + { + .name = "rw2458n:green:d3", + .gpio = RW2458N_GPIO_LED_D3, + .active_low = 1, + }, { + .name = "rw2458n:green:d4", + .gpio = RW2458N_GPIO_LED_D4, + .active_low = 1, + }, { + .name = "rw2458n:green:d5", + .gpio = RW2458N_GPIO_LED_D5, + .active_low = 1, + }, { + .name = "rw2458n:green:d6", + .gpio = RW2458N_GPIO_LED_D6, + .active_low = 1, + } +}; + +static void __init rw2458n_setup(void) +{ + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~RW2458N_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rw2458n_leds_gpio), + rw2458n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, RW2458N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rw2458n_gpio_keys), + rw2458n_gpio_keys); + ath79_register_usb(); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RW2458N, "RW2458N", "Redwave RW2458N", + rw2458n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-smart-300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-smart-300.c new file mode 100644 index 0000000..2520e96 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-smart-300.c @@ -0,0 +1,135 @@ +/* + * NC-LINK SMART-300 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define SMART_300_GPIO_LED_WLAN 13 +#define SMART_300_GPIO_LED_WAN 18 +#define SMART_300_GPIO_LED_LAN4 19 +#define SMART_300_GPIO_LED_LAN3 12 +#define SMART_300_GPIO_LED_LAN2 21 +#define SMART_300_GPIO_LED_LAN1 20 +#define SMART_300_GPIO_LED_SYSTEM 15 +#define SMART_300_GPIO_LED_POWER 14 + +#define SMART_300_GPIO_BTN_RESET 17 +#define SMART_300_GPIO_SW_RFKILL 16 + +#define SMART_300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define SMART_300_KEYS_DEBOUNCE_INTERVAL (3 * SMART_300_KEYS_POLL_INTERVAL) + +#define SMART_300_GPIO_MASK 0x007fffff + +static const char *smart_300_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data smart_300_flash_data = { + .part_probes = smart_300_part_probes, +}; + +static struct gpio_led smart_300_leds_gpio[] __initdata = { + { + .name = "nc-link:green:lan1", + .gpio = SMART_300_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "nc-link:green:lan2", + .gpio = SMART_300_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "nc-link:green:lan3", + .gpio = SMART_300_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "nc-link:green:lan4", + .gpio = SMART_300_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "nc-link:green:system", + .gpio = SMART_300_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "nc-link:green:wan", + .gpio = SMART_300_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "nc-link:green:wlan", + .gpio = SMART_300_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button smart_300_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = SMART_300_KEYS_DEBOUNCE_INTERVAL, + .gpio = SMART_300_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init smart_300_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(smart_300_leds_gpio), + smart_300_leds_gpio); + + ath79_register_gpio_keys_polled(1, SMART_300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(smart_300_gpio_keys), + smart_300_gpio_keys); + + ath79_register_m25p80(&smart_300_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); + + gpio_request(SMART_300_GPIO_LED_POWER, "power"); + gpio_direction_output(SMART_300_GPIO_LED_POWER, GPIOF_OUT_INIT_LOW); +} + +MIPS_MACHINE(ATH79_MACH_SMART_300, "SMART-300", "NC-LINK SMART-300", + smart_300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c new file mode 100644 index 0000000..855664e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c @@ -0,0 +1,111 @@ +/* + * TrendNET TEW-632BRP board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define TEW_632BRP_GPIO_LED_STATUS 1 +#define TEW_632BRP_GPIO_LED_WPS 3 +#define TEW_632BRP_GPIO_LED_WLAN 6 +#define TEW_632BRP_GPIO_BTN_WPS 12 +#define TEW_632BRP_GPIO_BTN_RESET 21 + +#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL) + +#define TEW_632BRP_CONFIG_ADDR 0x1f020000 +#define TEW_632BRP_CONFIG_SIZE 0x10000 + +static struct gpio_led tew_632brp_leds_gpio[] __initdata = { + { + .name = "tew-632brp:green:status", + .gpio = TEW_632BRP_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "tew-632brp:blue:wps", + .gpio = TEW_632BRP_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "tew-632brp:green:wlan", + .gpio = TEW_632BRP_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_632BRP_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_632BRP_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +#define TEW_632BRP_LAN_PHYMASK BIT(0) +#define TEW_632BRP_WAN_PHYMASK BIT(4) +#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ + TEW_632BRP_WAN_PHYMASK)) + +static void __init tew_632brp_setup(void) +{ + const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + u8 *wlan_mac = NULL; + + if (ath79_nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, + "lan_mac=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + wlan_mac = mac; + } + + ath79_register_mdio(0, TEW_632BRP_MDIO_MASK); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), + tew_632brp_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_632brp_gpio_keys), + tew_632brp_gpio_keys); + + ath79_register_wmac(eeprom, wlan_mac); +} + +MIPS_MACHINE(ATH79_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", + tew_632brp_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c new file mode 100644 index 0000000..80a5443 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c @@ -0,0 +1,198 @@ +/* + * TRENDnet TEW-673GRU board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TEW673GRU_GPIO_LCD_SCK 0 +#define TEW673GRU_GPIO_LCD_MOSI 1 +#define TEW673GRU_GPIO_LCD_MISO 2 +#define TEW673GRU_GPIO_LCD_CS 6 + +#define TEW673GRU_GPIO_LED_WPS 9 + +#define TEW673GRU_GPIO_BTN_RESET 3 +#define TEW673GRU_GPIO_BTN_WPS 8 + +#define TEW673GRU_GPIO_RTL8366_SDA 5 +#define TEW673GRU_GPIO_RTL8366_SCK 7 + +#define TEW673GRU_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW673GRU_KEYS_DEBOUNCE_INTERVAL (3 * TEW673GRU_KEYS_POLL_INTERVAL) + +#define TEW673GRU_CAL0_OFFSET 0x1000 +#define TEW673GRU_CAL1_OFFSET 0x5000 +#define TEW673GRU_MAC0_OFFSET 0xffa0 +#define TEW673GRU_MAC1_OFFSET 0xffb4 + +#define TEW673GRU_CAL_LOCATION_0 0x1f660000 +#define TEW673GRU_CAL_LOCATION_1 0x1f7f0000 + +static struct gpio_led tew673gru_leds_gpio[] __initdata = { + { + .name = "trendnet:blue:wps", + .gpio = TEW673GRU_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button tew673gru_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW673GRU_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW673GRU_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_initval tew673gru_rtl8366s_initvals[] = { + { .reg = 0x06, .val = 0x0108 }, +}; + +static struct rtl8366_platform_data tew673gru_rtl8366s_data = { + .gpio_sda = TEW673GRU_GPIO_RTL8366_SDA, + .gpio_sck = TEW673GRU_GPIO_RTL8366_SCK, + .num_initvals = ARRAY_SIZE(tew673gru_rtl8366s_initvals), + .initvals = tew673gru_rtl8366s_initvals, +}; + +static struct platform_device tew673gru_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tew673gru_rtl8366s_data, + } +}; + +static struct spi_board_info tew673gru_spi_info[] = { + { + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 400000, + .modalias = "spidev", + .mode = SPI_MODE_2, + .controller_data = (void *) TEW673GRU_GPIO_LCD_CS, + }, +}; + +static struct spi_gpio_platform_data tew673gru_spi_data = { + .sck = TEW673GRU_GPIO_LCD_SCK, + .miso = TEW673GRU_GPIO_LCD_MISO, + .mosi = TEW673GRU_GPIO_LCD_MOSI, + .num_chipselect = 1, +}; + +static struct platform_device tew673gru_spi_device = { + .name = "spi_gpio", + .id = 1, + .dev = { + .platform_data = &tew673gru_spi_data, + }, +}; + +static bool __init tew673gru_is_caldata_valid(u8 *p) +{ + u16 *magic0, *magic1; + + magic0 = (u16 *)(p + TEW673GRU_CAL0_OFFSET); + magic1 = (u16 *)(p + TEW673GRU_CAL1_OFFSET); + + return (*magic0 == 0xa55a && *magic1 == 0xa55a); +} + +static void __init tew673gru_wlan_init(void) +{ + u8 mac1[ETH_ALEN], mac2[ETH_ALEN]; + u8 *caldata; + + caldata = (u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_0); + if (!tew673gru_is_caldata_valid(caldata)) { + caldata = (u8 *)KSEG1ADDR(TEW673GRU_CAL_LOCATION_1); + if (!tew673gru_is_caldata_valid(caldata)) { + pr_err("no calibration data found\n"); + return; + } + } + + ath79_parse_ascii_mac(caldata + TEW673GRU_MAC0_OFFSET, mac1); + ath79_parse_ascii_mac(caldata + TEW673GRU_MAC1_OFFSET, mac2); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(caldata + TEW673GRU_CAL0_OFFSET, mac1, + caldata + TEW673GRU_CAL1_OFFSET, mac2); +} + +static void __init tew673gru_setup(void) +{ + tew673gru_wlan_init(); + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x11110000; + + ath79_eth1_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + ath79_eth1_pll_data.pll_1000 = 0x11110000; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew673gru_leds_gpio), + tew673gru_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TEW673GRU_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew673gru_gpio_keys), + tew673gru_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&tew673gru_rtl8366s_device); + + spi_register_board_info(tew673gru_spi_info, + ARRAY_SIZE(tew673gru_spi_info)); + platform_device_register(&tew673gru_spi_device); +} + +MIPS_MACHINE(ATH79_MACH_TEW_673GRU, "TEW-673GRU", "TRENDnet TEW-673GRU", + tew673gru_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c new file mode 100644 index 0000000..304b994 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c @@ -0,0 +1,153 @@ +/* + * TRENDnet TEW-712BR board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TEW_712BR_GPIO_BTN_WPS 11 +#define TEW_712BR_GPIO_BTN_RESET 12 + +#define TEW_712BR_GPIO_LED_LAN1 13 +#define TEW_712BR_GPIO_LED_LAN2 14 +#define TEW_712BR_GPIO_LED_LAN3 15 +#define TEW_712BR_GPIO_LED_LAN4 16 +#define TEW_712BR_GPIO_LED_POWER_GREEN 20 +#define TEW_712BR_GPIO_LED_POWER_ORANGE 27 +#define TEW_712BR_GPIO_LED_WAN_GREEN 17 +#define TEW_712BR_GPIO_LED_WAN_ORANGE 23 +#define TEW_712BR_GPIO_LED_WLAN 0 +#define TEW_712BR_GPIO_LED_WPS 26 + +#define TEW_712BR_GPIO_WAN_LED_ENABLE 1 + +#define TEW_712BR_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_712BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_712BR_KEYS_POLL_INTERVAL) + +#define TEW_712BR_ART_ADDRESS 0x1f010000 +#define TEW_712BR_CALDATA_OFFSET 0x1000 + +#define TEW_712BR_MAC_PART_ADDRESS 0x1f020000 +#define TEW_712BR_LAN_MAC_OFFSET 0x04 +#define TEW_712BR_WAN_MAC_OFFSET 0x16 + +static struct gpio_led tew_712br_leds_gpio[] __initdata = { + { + .name = "trendnet:green:lan1", + .gpio = TEW_712BR_GPIO_LED_LAN1, + .active_low = 0, + }, { + .name = "trendnet:green:lan2", + .gpio = TEW_712BR_GPIO_LED_LAN2, + .active_low = 0, + }, { + .name = "trendnet:green:lan3", + .gpio = TEW_712BR_GPIO_LED_LAN3, + .active_low = 0, + }, { + .name = "trendnet:green:lan4", + .gpio = TEW_712BR_GPIO_LED_LAN4, + .active_low = 0, + }, { + .name = "trendnet:blue:wps", + .gpio = TEW_712BR_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "trendnet:green:power", + .gpio = TEW_712BR_GPIO_LED_POWER_GREEN, + .active_low = 0, + }, { + .name = "trendnet:orange:power", + .gpio = TEW_712BR_GPIO_LED_POWER_ORANGE, + .active_low = 0, + }, { + .name = "trendnet:green:wan", + .gpio = TEW_712BR_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "trendnet:orange:wan", + .gpio = TEW_712BR_GPIO_LED_WAN_ORANGE, + .active_low = 0, + }, { + .name = "trendnet:green:wlan", + .gpio = TEW_712BR_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tew_712br_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_712BR_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_712BR_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init tew_712br_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TEW_712BR_ART_ADDRESS); + u8 *mac = (u8 *) KSEG1ADDR(TEW_712BR_MAC_PART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + gpio_request_one(TEW_712BR_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_712br_leds_gpio), + tew_712br_leds_gpio); + + ath79_register_gpio_keys_polled(1, TEW_712BR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_712br_gpio_keys), + tew_712br_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_parse_ascii_mac(mac + TEW_712BR_LAN_MAC_OFFSET, lan_mac); + ath79_parse_ascii_mac(mac + TEW_712BR_WAN_MAC_OFFSET, wan_mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + TEW_712BR_CALDATA_OFFSET, wan_mac); +} + +MIPS_MACHINE(ATH79_MACH_TEW_712BR, "TEW-712BR", + "TRENDnet TEW-712BR", tew_712br_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-732br.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-732br.c new file mode 100644 index 0000000..1f26f6f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-732br.c @@ -0,0 +1,127 @@ +/* + * TRENDnet TEW-732BR board support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TEW_732BR_GPIO_BTN_WPS 16 +#define TEW_732BR_GPIO_BTN_RESET 17 + +#define TEW_732BR_GPIO_LED_POWER_GREEN 4 +#define TEW_732BR_GPIO_LED_POWER_AMBER 14 +#define TEW_732BR_GPIO_LED_PLANET_GREEN 12 +#define TEW_732BR_GPIO_LED_PLANET_AMBER 22 + +#define TEW_732BR_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_732BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_732BR_KEYS_POLL_INTERVAL) + +#define TEW_732BR_ART_ADDRESS 0x1fff0000 +#define TEW_732BR_CALDATA_OFFSET 0x1000 +#define TEW_732BR_LAN_MAC_OFFSET 0xffa0 +#define TEW_732BR_WAN_MAC_OFFSET 0xffb4 + +static struct gpio_led tew_732br_leds_gpio[] __initdata = { + { + .name = "trendnet:green:power", + .gpio = TEW_732BR_GPIO_LED_POWER_GREEN, + .active_low = 0, + }, + { + .name = "trendnet:amber:power", + .gpio = TEW_732BR_GPIO_LED_POWER_AMBER, + .active_low = 0, + }, + { + .name = "trendnet:green:wan", + .gpio = TEW_732BR_GPIO_LED_PLANET_GREEN, + .active_low = 1, + }, + { + .name = "trendnet:amber:wan", + .gpio = TEW_732BR_GPIO_LED_PLANET_AMBER, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tew_732br_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_732BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_732BR_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_732BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_732BR_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void __init tew_732br_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TEW_732BR_ART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_732br_leds_gpio), + tew_732br_leds_gpio); + + ath79_register_gpio_keys_polled(1, TEW_732BR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_732br_gpio_keys), + tew_732br_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_parse_ascii_mac(art + TEW_732BR_LAN_MAC_OFFSET, lan_mac); + ath79_parse_ascii_mac(art + TEW_732BR_WAN_MAC_OFFSET, wan_mac); + + ath79_register_wmac(art + TEW_732BR_CALDATA_OFFSET, lan_mac); + + ath79_register_mdio(1, 0x0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + /* LAN: GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN: GMAC0 is connected to the PHY4 of the internal switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TEW_732BR, "TEW-732BR", "TRENDnet TEW-732BR", + tew_732br_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c new file mode 100644 index 0000000..74ccf63 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c @@ -0,0 +1,183 @@ +/* + * TP-LINK TL-MR11U/TL-MR3040 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR11U_GPIO_LED_3G 27 +#define TL_MR11U_GPIO_LED_WLAN 26 +#define TL_MR11U_GPIO_LED_LAN 17 + +#define TL_MR11U_GPIO_BTN_WPS 20 +#define TL_MR11U_GPIO_BTN_RESET 11 + +#define TL_MR11U_GPIO_USB_POWER 8 +#define TL_MR3040_GPIO_USB_POWER 18 + +#define TL_MR3040_V2_GPIO_BTN_SW1 19 +#define TL_MR3040_V2_GPIO_BTN_SW2 20 + +#define TL_MR11U_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR11U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR11U_KEYS_POLL_INTERVAL) + +static const char *tl_mr11u_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr11u_flash_data = { + .part_probes = tl_mr11u_part_probes, +}; + +static struct gpio_led tl_mr11u_leds_gpio[] __initdata = { + { + .name = "tp-link:green:3g", + .gpio = TL_MR11U_GPIO_LED_3G, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_MR11U_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "tp-link:green:lan", + .gpio = TL_MR11U_GPIO_LED_LAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_mr11u_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_WPS, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_mr3040_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_SW, + .code = BTN_0, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3040_V2_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_SW, + .code = BTN_1, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3040_V2_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init common_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable hardware control LAN1 and LAN2 LEDs, enabling GPIO14 and GPIO15 */ + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_mr11u_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio), + tl_mr11u_leds_gpio); + + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_mr11u_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr11u_gpio_keys), + tl_mr11u_gpio_keys); + gpio_request_one(TL_MR11U_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR11U, "TL-MR11U", "TP-LINK TL-MR11U", + tl_mr11u_setup); + +static void __init tl_mr3040_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + 1, tl_mr11u_gpio_keys); + gpio_request_one(TL_MR3040_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3040, "TL-MR3040", "TP-LINK TL-MR3040", + tl_mr3040_setup); + +static void __init tl_mr3040_v2_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3040_v2_gpio_keys), + tl_mr3040_v2_gpio_keys); + gpio_request_one(TL_MR3040_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3040_V2, "TL-MR3040-v2", "TP-LINK TL-MR3040 v2", + tl_mr3040_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr13u.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr13u.c new file mode 100644 index 0000000..84b6937 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr13u.c @@ -0,0 +1,107 @@ +/* + * TP-LINK TL-MR13U board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR13U_GPIO_LED_SYSTEM 27 + +#define TL_MR13U_GPIO_BTN_RESET 11 +#define TL_MR13U_GPIO_BTN_SW1 6 +#define TL_MR13U_GPIO_BTN_SW2 7 + +#define TL_MR13U_GPIO_USB_POWER 18 + +#define TL_MR13U_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR13U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR13U_KEYS_POLL_INTERVAL) + +static const char *tl_mr13u_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr13u_flash_data = { + .part_probes = tl_mr13u_part_probes, +}; + +static struct gpio_led tl_mr13u_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_MR13U_GPIO_LED_SYSTEM, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_mr13u_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR13U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR13U_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR13U_GPIO_BTN_SW2, + .active_low = 0, + }, +}; + +static void __init tl_mr13u_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_mr13u_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr13u_leds_gpio), + tl_mr13u_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_MR13U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr13u_gpio_keys), + tl_mr13u_gpio_keys); + + gpio_request_one(TL_MR13U_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR13U, "TL-MR13U", "TP-LINK TL-MR13U v1", + tl_mr13u_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c new file mode 100644 index 0000000..0a9dfbc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c @@ -0,0 +1,126 @@ +/* + * TP-LINK TL-MR3020 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR3020_GPIO_LED_3G 27 +#define TL_MR3020_GPIO_LED_WLAN 0 +#define TL_MR3020_GPIO_LED_LAN 17 +#define TL_MR3020_GPIO_LED_WPS 26 + +#define TL_MR3020_GPIO_BTN_WPS 11 +#define TL_MR3020_GPIO_BTN_SW1 18 +#define TL_MR3020_GPIO_BTN_SW2 20 + +#define TL_MR3020_GPIO_USB_POWER 8 + +#define TL_MR3020_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR3020_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3020_KEYS_POLL_INTERVAL) + +static const char *tl_mr3020_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr3020_flash_data = { + .part_probes = tl_mr3020_part_probes, +}; + +static struct gpio_led tl_mr3020_leds_gpio[] __initdata = { + { + .name = "tp-link:green:3g", + .gpio = TL_MR3020_GPIO_LED_3G, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_MR3020_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "tp-link:green:lan", + .gpio = TL_MR3020_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "tp-link:green:wps", + .gpio = TL_MR3020_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_mr3020_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init tl_mr3020_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_mr3020_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio), + tl_mr3020_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3020_gpio_keys), + tl_mr3020_gpio_keys); + + gpio_request_one(TL_MR3020_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3020, "TL-MR3020", "TP-LINK TL-MR3020", + tl_mr3020_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c new file mode 100644 index 0000000..5924ac5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c @@ -0,0 +1,147 @@ +/* + * TP-LINK TL-MR3220/3420 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TL_MR3X20_GPIO_LED_QSS 0 +#define TL_MR3X20_GPIO_LED_SYSTEM 1 +#define TL_MR3X20_GPIO_LED_3G 8 + +#define TL_MR3X20_GPIO_BTN_RESET 11 +#define TL_MR3X20_GPIO_BTN_QSS 12 + +#define TL_MR3X20_GPIO_USB_POWER 6 + +#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL) + +static const char *tl_mr3x20_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr3x20_flash_data = { + .part_probes = tl_mr3x20_part_probes, +}; + +static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_MR3X20_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_MR3X20_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:3g", + .gpio = TL_MR3X20_GPIO_LED_3G, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3X20_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3X20_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_ap99_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_mr3x20_flash_data); + + ath79_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3x20_gpio_keys), + tl_mr3x20_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + /* WAN port */ + ath79_register_eth(0); + + ap91_pci_init(ee, mac); +} + +static void __init tl_mr3x20_usb_setup(void) +{ + /* enable power for the USB port */ + gpio_request_one(TL_MR3X20_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); +} + +static void __init tl_mr3220_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 1); + tl_mr3x20_usb_setup(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220", + tl_mr3220_setup); + +static void __init tl_mr3420_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); + tl_mr3x20_usb_setup(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420", + tl_mr3420_setup); + +static void __init tl_wr841n_v7_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio) - 1, + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V7, "TL-WR841N-v7", + "TP-LINK TL-WR841N/ND v7", tl_wr841n_v7_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa701nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa701nd-v2.c new file mode 100644 index 0000000..aab92b3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa701nd-v2.c @@ -0,0 +1,116 @@ +/* + * TP-LINK TL-WA701ND v2 board support + * + * Copyright (C) 2015 Luigi Tarenga + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA701NDV2_GPIO_LED_WLAN 0 +#define TL_WA701NDV2_GPIO_LED_QSS 1 +#define TL_WA701NDV2_GPIO_LED_LAN 17 +#define TL_WA701NDV2_GPIO_LED_SYSTEM 27 + +#define TL_WA701NDV2_GPIO_BTN_RESET 11 +#define TL_WA701NDV2_GPIO_BTN_QSS 26 + +#define TL_WA701NDV2_GPIO_USB_POWER 8 + +#define TL_WA701NDV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA701NDV2_KEYS_POLL_INTERVAL) + +static const char *tl_wa701ndv2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa701ndv2_flash_data = { + .part_probes = tl_wa701ndv2_part_probes, +}; + +static struct gpio_led tl_wa701ndv2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:wlan", + .gpio = TL_WA701NDV2_GPIO_LED_WLAN, + .active_low = 0, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA701NDV2_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:lan", + .gpio = TL_WA701NDV2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA701NDV2_GPIO_LED_SYSTEM, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa701ndv2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA701NDV2_GPIO_BTN_RESET, + .active_low = 0, + } , { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA701NDV2_GPIO_BTN_QSS, + .active_low = 0, + } + +}; + +static void __init tl_wa701ndv2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa701ndv2_leds_gpio), + tl_wa701ndv2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA701NDV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa701ndv2_gpio_keys), + tl_wa701ndv2_gpio_keys); + + gpio_request_one(TL_WA701NDV2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&tl_wa701ndv2_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + /* ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); */ + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA701ND_V2, "TL-WA701ND-v2", + "TP-LINK TL-WA701ND v2", tl_wa701ndv2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa7210n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa7210n-v2.c new file mode 100644 index 0000000..276353a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa7210n-v2.c @@ -0,0 +1,125 @@ +/* + * TP-LINK TL-WA7210N v2.1 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2014 Nicolas Braud-Santoni + * Copyright (C) 2014 Alexander List + * Copyright (C) 2015 Hendrik Frenzel + * + * rebased on TL-WA7510Nv1 support, + * Copyright (C) 2012 Stefan Helmert + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#include "common.h" + +#define TL_WA7210N_V2_GPIO_BTN_RESET 11 +#define TL_WA7210N_V2_KEYS_POLL_INT 20 +#define TL_WA7210N_V2_KEYS_DEBOUNCE_INT (3 * TL_WA7210N_V2_KEYS_POLL_INT) + +#define TL_WA7210N_V2_GPIO_LED_LAN 17 +#define TL_WA7210N_V2_GPIO_LED_SIG1 0 +#define TL_WA7210N_V2_GPIO_LED_SIG2 1 +#define TL_WA7210N_V2_GPIO_LED_SIG3 27 +#define TL_WA7210N_V2_GPIO_LED_SIG4 26 + +#define TL_WA7210N_V2_GPIO_LNA_EN 28 + +static const char *tl_wa7210n_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct gpio_keys_button tl_wa7210n_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA7210N_V2_KEYS_DEBOUNCE_INT, + .gpio = TL_WA7210N_V2_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static struct gpio_led tl_wa7210n_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA7210N_V2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:signal1", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG1, + .active_low = 0, + }, { + .name = "tp-link:green:signal2", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG2, + .active_low = 0, + }, { + .name = "tp-link:green:signal3", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG3, + .active_low = 1, + }, { + .name = "tp-link:green:signal4", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG4, + .active_low = 1, + }, +}; + +static struct flash_platform_data tl_wa7210n_v2_flash_data = { + .part_probes = tl_wa7210n_v2_part_probes, +}; + +static void __init tl_wa7210n_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_gpio_keys_polled(-1, TL_WA7210N_V2_KEYS_POLL_INT, + ARRAY_SIZE(tl_wa7210n_v2_gpio_keys), + tl_wa7210n_v2_gpio_keys); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa7210n_v2_leds_gpio), + tl_wa7210n_v2_leds_gpio); + + ath79_gpio_function_enable(TL_WA7210N_V2_GPIO_LNA_EN); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_mdio(0, 0x0); + + ath79_register_wmac(ee, mac); + + ath79_register_m25p80(&tl_wa7210n_v2_flash_data); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA7210N_V2, "TL-WA7210N-v2", "TP-LINK TL-WA7210N v2", + tl_wa7210n_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa830re-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa830re-v2.c new file mode 100644 index 0000000..1c74fed --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa830re-v2.c @@ -0,0 +1,132 @@ +/* + * TP-LINK TL-WA830RE v2 board support + * + * Copyright (C) 2014 Fredrik Jonson + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA830REV2_GPIO_LED_WLAN 13 +#define TL_WA830REV2_GPIO_LED_QSS 15 +#define TL_WA830REV2_GPIO_LED_LAN 18 +#define TL_WA830REV2_GPIO_LED_SYSTEM 14 + +#define TL_WA830REV2_GPIO_BTN_RESET 17 +#define TL_WA830REV2_GPIO_SW_RFKILL 16 /* WPS for MR3420 v2 */ + +#define TL_WA830REV2_GPIO_USB_POWER 4 + +#define TL_WA830REV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA830REV2_KEYS_POLL_INTERVAL) + +static const char *tl_wa830re_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa830re_v2_flash_data = { + .part_probes = tl_wa830re_v2_part_probes, +}; + +static struct gpio_led tl_wa830re_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:qss", + .gpio = TL_WA830REV2_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA830REV2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:lan", + .gpio = TL_WA830REV2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA830REV2_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wa830re_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA830REV2_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA830REV2_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static void __init tl_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + /* config gpio4 as normal gpio function */ + ath79_gpio_output_select(TL_WA830REV2_GPIO_USB_POWER, + AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&tl_wa830re_v2_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wa830re_v2_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa830re_v2_leds_gpio) - 1, + tl_wa830re_v2_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WA830REV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa830re_v2_gpio_keys), + tl_wa830re_v2_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA830RE_V2, "TL-WA830RE-v2", "TP-LINK TL-WA830RE v2", + tl_wa830re_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c new file mode 100644 index 0000000..b4fb2a9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c @@ -0,0 +1,104 @@ +/* + * TP-LINK TL-WA901N/ND v2 board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Pieter Hollants + * Copyright (C) 2011 Jonathan Bennett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA901ND_V2_GPIO_LED_QSS 4 +#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2 +#define TL_WA901ND_V2_GPIO_LED_WLAN 9 + +#define TL_WA901ND_V2_GPIO_BTN_RESET 3 +#define TL_WA901ND_V2_GPIO_BTN_QSS 7 + +#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \ + (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL) + +static const char *tl_wa901nd_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa901nd_v2_flash_data = { + .part_probes = tl_wa901nd_v2_part_probes, +}; + +static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA901ND_V2_GPIO_LED_QSS, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA901ND_V2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_V2_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_V2_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wa901nd_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x00001000; + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC | + AR71XX_RESET_GE0_PHY; + ath79_register_eth(0); + + ath79_register_m25p80(&tl_wa901nd_v2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio), + tl_wa901nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa901nd_v2_gpio_keys), + tl_wa901nd_v2_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V2, "TL-WA901ND-v2", + "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c new file mode 100644 index 0000000..957b92c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c @@ -0,0 +1,127 @@ +/* + * TP-LINK TL-WA901N/ND v1, TL-WA7510N v1 board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Pieter Hollants + * Copyright (C) 2012 Stefan Helmert + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WA901ND_GPIO_LED_QSS 0 +#define TL_WA901ND_GPIO_LED_SYSTEM 1 +#define TL_WA901ND_GPIO_LED_LAN 13 + +#define TL_WA901ND_GPIO_BTN_RESET 11 +#define TL_WA901ND_GPIO_BTN_QSS 12 + +#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL) + +static const char *tl_wa901nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa901nd_flash_data = { + .part_probes = tl_wa901nd_part_probes, +}; + +static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA901ND_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA901ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA901ND_GPIO_LED_QSS, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init common_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + /* + * ath79_eth0 would be the WAN port, but is not connected. + * ath79_eth1 connects to the internal switch chip, however + * we have a single LAN port only. + */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + + ath79_register_m25p80(&tl_wa901nd_flash_data); +} + +static void __init tl_wa901nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio), + tl_wa901nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa901nd_gpio_keys), + tl_wa901nd_gpio_keys); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND", + tl_wa901nd_setup); + +static void __init tl_wa7510n_v1_setup(void) +{ + common_setup(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA7510N_V1, "TL-WA7510N", "TP-LINK TL-WA7510N v1", + tl_wa7510n_v1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wax50re.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wax50re.c new file mode 100644 index 0000000..965b1cd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wax50re.c @@ -0,0 +1,313 @@ +/* + * TP-LINK TL-WA750RE v1/TL-WA801ND v2/TL-WA850RE v1/TL-WA901ND v3 + * board support + * + * Copyright (C) 2013 Martijn Zilverschoon + * Copyright (C) 2013 Jiri Pirko + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WAX50RE_GPIO_LED_LAN 20 +#define TL_WAX50RE_GPIO_LED_WLAN 13 +#define TL_WAX50RE_GPIO_LED_RE 15 +#define TL_WAX50RE_GPIO_LED_SIGNAL1 0 +#define TL_WAX50RE_GPIO_LED_SIGNAL2 1 +#define TL_WAX50RE_GPIO_LED_SIGNAL3 2 +#define TL_WAX50RE_GPIO_LED_SIGNAL4 3 +#define TL_WAX50RE_GPIO_LED_SIGNAL5 4 + +#define TL_WA860RE_GPIO_LED_WLAN_ORANGE 0 +#define TL_WA860RE_GPIO_LED_WLAN_GREEN 2 +#define TL_WA860RE_GPIO_LED_POWER_ORANGE 12 +#define TL_WA860RE_GPIO_LED_POWER_GREEN 14 +#define TL_WA860RE_GPIO_LED_LAN 20 + +#define TL_WA801ND_V2_GPIO_LED_LAN 18 +#define TL_WA801ND_V2_GPIO_LED_SYSTEM 14 + +#define TL_WAX50RE_GPIO_BTN_RESET 17 +#define TL_WAX50RE_GPIO_BTN_WPS 16 + +#define TL_WA860RE_GPIO_BTN_RESET 17 +#define TL_WA860RE_GPIO_BTN_WPS 16 +#define TL_WA860RE_GPIO_BTN_ONOFF 11 + +#define TL_WAX50RE_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL (3 * TL_WAX50RE_KEYS_POLL_INTERVAL) + +static const char *tl_wax50re_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wax50re_flash_data = { + .part_probes = tl_wax50re_part_probes, +}; + +static struct gpio_led tl_wa750re_leds_gpio[] __initdata = { + { + .name = "tp-link:orange:lan", + .gpio = TL_WAX50RE_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:orange:wlan", + .gpio = TL_WAX50RE_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:orange:re", + .gpio = TL_WAX50RE_GPIO_LED_RE, + .active_low = 1, + }, { + .name = "tp-link:orange:signal1", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL1, + .active_low = 1, + }, { + .name = "tp-link:orange:signal2", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL2, + .active_low = 1, + }, { + .name = "tp-link:orange:signal3", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL3, + .active_low = 1, + }, { + .name = "tp-link:orange:signal4", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL4, + .active_low = 1, + }, { + .name = "tp-link:orange:signal5", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL5, + .active_low = 1, + }, +}; + +static struct gpio_led tl_wa850re_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:lan", + .gpio = TL_WAX50RE_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:blue:wlan", + .gpio = TL_WAX50RE_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:blue:re", + .gpio = TL_WAX50RE_GPIO_LED_RE, + .active_low = 1, + }, { + .name = "tp-link:blue:signal1", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL1, + .active_low = 1, + }, { + .name = "tp-link:blue:signal2", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL2, + .active_low = 1, + }, { + .name = "tp-link:blue:signal3", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL3, + .active_low = 1, + }, { + .name = "tp-link:blue:signal4", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL4, + .active_low = 1, + }, { + .name = "tp-link:blue:signal5", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL5, + .active_low = 1, + }, +}; + +static struct gpio_led tl_wa860re_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA860RE_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:power", + .gpio = TL_WA860RE_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "tp-link:orange:power", + .gpio = TL_WA860RE_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA860RE_GPIO_LED_WLAN_GREEN, + .active_low = 1, + }, { + .name = "tp-link:orange:wlan", + .gpio = TL_WA860RE_GPIO_LED_WLAN_ORANGE, + .active_low = 1, + }, +}; + + +static struct gpio_keys_button tl_wax50re_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WAX50RE_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WAX50RE_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wa860re_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA860RE_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA860RE_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "ONOFF", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA860RE_GPIO_BTN_ONOFF, + .active_low = 1, + }, +}; + +static struct gpio_led tl_wa801nd_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA801ND_V2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WAX50RE_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WAX50RE_GPIO_LED_RE, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA801ND_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static void __init tl_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wax50re_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wa750re_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa750re_leds_gpio), + tl_wa750re_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys), + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA750RE, "TL-WA750RE", "TP-LINK TL-WA750RE", + tl_wa750re_setup); + +static void __init tl_wa801nd_v2_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio), + tl_wa801nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys), + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA801ND_V2, "TL-WA801ND-v2", "TP-LINK TL-WA801ND v2", + tl_wa801nd_v2_setup); + +static void __init tl_wa850re_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa850re_leds_gpio), + tl_wa850re_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys), + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA850RE, "TL-WA850RE", "TP-LINK TL-WA850RE", + tl_wa850re_setup); + +static void __init tl_wa860re_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa860re_leds_gpio), + tl_wa860re_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa860re_gpio_keys), + tl_wa860re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA860RE, "TL-WA860RE", "TP-LINK TL-WA860RE", + tl_wa860re_setup); + +static void __init tl_wa901nd_v3_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio), + tl_wa801nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys) - 1, + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V3, "TL-WA901ND-v3", "TP-LINK TL-WA901ND v3", + tl_wa901nd_v3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3320-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3320-v2.c new file mode 100644 index 0000000..3e452f2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3320-v2.c @@ -0,0 +1,146 @@ +/* + * TP-LINK TL-WDR3320 v2 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2015 Weijie Gao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR3320_GPIO_LED_WLAN5G 12 +#define WDR3320_GPIO_LED_SYSTEM 14 +#define WDR3320_GPIO_LED_QSS 15 +#define WDR3320_GPIO_LED_WAN 4 +#define WDR3320_GPIO_LED_LAN1 18 +#define WDR3320_GPIO_LED_LAN2 20 +#define WDR3320_GPIO_LED_LAN3 21 +#define WDR3320_GPIO_LED_LAN4 22 + +#define WDR3320_GPIO_BTN_RESET 16 + +#define WDR3320_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR3320_KEYS_DEBOUNCE_INTERVAL (3 * WDR3320_KEYS_POLL_INTERVAL) + +#define WDR3320_WMAC_CALDATA_OFFSET 0x1000 +#define WDR3320_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr3320_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr3320_flash_data = { + .part_probes = wdr3320_part_probes, +}; + +static struct gpio_led wdr3320_leds_gpio[] __initdata = { + { + .name = "tp-link:green:qss", + .gpio = WDR3320_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:green:system", + .gpio = WDR3320_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan5g", + .gpio = WDR3320_GPIO_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr3320_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WDR3320_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR3320_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init wdr3320_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr3320_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3320_leds_gpio), + wdr3320_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR3320_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr3320_gpio_keys), + wdr3320_gpio_keys); + + ath79_init_mac(tmpmac, mac, 0); + ath79_register_wmac(art + WDR3320_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, -1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR3320_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK0); + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN3, + AR934X_GPIO_OUT_LED_LINK2); + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN4, + AR934X_GPIO_OUT_LED_LINK3); + ath79_gpio_output_select(WDR3320_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR3320_V2, "TL-WDR3320-v2", + "TP-LINK TL-WDR3320 v2", + wdr3320_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3500.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3500.c new file mode 100644 index 0000000..452c20b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3500.c @@ -0,0 +1,169 @@ +/* + * TP-LINK TL-WDR3500 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Gui Iribarren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR3500_GPIO_LED_USB 11 +#define WDR3500_GPIO_LED_WLAN2G 13 +#define WDR3500_GPIO_LED_SYSTEM 14 +#define WDR3500_GPIO_LED_QSS 15 +#define WDR3500_GPIO_LED_WAN 18 +#define WDR3500_GPIO_LED_LAN1 19 +#define WDR3500_GPIO_LED_LAN2 20 +#define WDR3500_GPIO_LED_LAN3 21 +#define WDR3500_GPIO_LED_LAN4 22 + +#define WDR3500_GPIO_BTN_WPS 16 +#define WDR3500_GPIO_BTN_RFKILL 17 + +#define WDR3500_GPIO_USB_POWER 12 + +#define WDR3500_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR3500_KEYS_DEBOUNCE_INTERVAL (3 * WDR3500_KEYS_POLL_INTERVAL) + +#define WDR3500_MAC0_OFFSET 0 +#define WDR3500_MAC1_OFFSET 6 +#define WDR3500_WMAC_CALDATA_OFFSET 0x1000 +#define WDR3500_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr3500_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr3500_flash_data = { + .part_probes = wdr3500_part_probes, +}; + +static struct gpio_led wdr3500_leds_gpio[] __initdata = { + { + .name = "tp-link:green:qss", + .gpio = WDR3500_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:green:system", + .gpio = WDR3500_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:usb", + .gpio = WDR3500_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan2g", + .gpio = WDR3500_GPIO_LED_WLAN2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr3500_gpio_keys[] __initdata = { + { + .desc = "QSS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WDR3500_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR3500_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = WDR3500_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR3500_GPIO_BTN_RFKILL, + }, +}; + + +static void __init wdr3500_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr3500_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3500_leds_gpio), + wdr3500_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR3500_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr3500_gpio_keys), + wdr3500_gpio_keys); + + ath79_init_mac(tmpmac, mac, 0); + ath79_register_wmac(art + WDR3500_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR3500_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + gpio_request_one(WDR3500_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK3); + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK2); + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN3, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN4, + AR934X_GPIO_OUT_LED_LINK0); + ath79_gpio_output_select(WDR3500_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR3500, "TL-WDR3500", + "TP-LINK TL-WDR3500", + wdr3500_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c new file mode 100644 index 0000000..3afc714 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c @@ -0,0 +1,206 @@ +/* + * TP-LINK TL-WDR4300 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR4300_GPIO_LED_USB1 11 +#define WDR4300_GPIO_LED_USB2 12 +#define WDR4300_GPIO_LED_WLAN2G 13 +#define WDR4300_GPIO_LED_SYSTEM 14 +#define WDR4300_GPIO_LED_QSS 15 + +#define WDR4300_GPIO_BTN_WPS 16 +#define WDR4300_GPIO_BTN_RFKILL 17 + +#define WDR4300_GPIO_EXTERNAL_LNA0 18 +#define WDR4300_GPIO_EXTERNAL_LNA1 19 + +#define WDR4300_GPIO_USB1_POWER 22 +#define WDR4300_GPIO_USB2_POWER 21 + +#define WDR4300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WDR4300_KEYS_POLL_INTERVAL) + +#define WDR4300_MAC0_OFFSET 0 +#define WDR4300_MAC1_OFFSET 6 +#define WDR4300_WMAC_CALDATA_OFFSET 0x1000 +#define WDR4300_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr4300_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr4300_flash_data = { + .part_probes = wdr4300_part_probes, +}; + +static struct gpio_led wdr4300_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:qss", + .gpio = WDR4300_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:blue:system", + .gpio = WDR4300_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:usb1", + .gpio = WDR4300_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "tp-link:green:usb2", + .gpio = WDR4300_GPIO_LED_USB2, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan2g", + .gpio = WDR4300_GPIO_LED_WLAN2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr4300_gpio_keys[] __initdata = { + { + .desc = "QSS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR4300_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR4300_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info wdr4300_leds_ar8327[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"), + AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"), + AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"), + AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"), + AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"), +}; + +static struct ar8327_pad_cfg wdr4300_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wdr4300_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data wdr4300_ar8327_data = { + .pad0_cfg = &wdr4300_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wdr4300_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(wdr4300_leds_ar8327), + .leds = wdr4300_leds_ar8327, +}; + +static struct mdio_board_info wdr4300_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wdr4300_ar8327_data, + }, +}; + +static void __init wdr4300_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr4300_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio), + wdr4300_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr4300_gpio_keys), + wdr4300_gpio_keys); + + ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 0); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(wdr4300_mdio0_info, + ARRAY_SIZE(wdr4300_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + gpio_request_one(WDR4300_GPIO_USB1_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB1 power"); + gpio_request_one(WDR4300_GPIO_USB2_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB2 power"); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR4300, "TL-WDR4300", + "TP-LINK TL-WDR3600/4300/4310", + wdr4300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr6500-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr6500-v2.c new file mode 100644 index 0000000..c2e75c2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr6500-v2.c @@ -0,0 +1,141 @@ +/* + * TP-LINK TL-WDR6500 v2 + * + * Copyright (C) 2015 Weijie Gao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WDR6500_V2_GPIO_LED_SYS 21 +#define TL_WDR6500_V2_GPIO_LED_WAN 18 +#define TL_WDR6500_V2_GPIO_LED_LAN1 17 +#define TL_WDR6500_V2_GPIO_LED_LAN2 16 +#define TL_WDR6500_V2_GPIO_LED_LAN3 15 +#define TL_WDR6500_V2_GPIO_LED_LAN4 14 + +#define TL_WDR6500_V2_GPIO_BTN_RESET 1 + +#define TL_WDR6500_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WDR6500_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WDR6500_V2_KEYS_POLL_INTERVAL) + +#define TL_WDR6500_V2_WMAC_CALDATA_OFFSET 0x1000 +#define TL_WDR6500_V2_PCIE_CALDATA_OFFSET 0x5000 + +static const char *tl_wdr6500_v2_part_probes[] = { + "tp-link-64k", + NULL, +}; + +static struct flash_platform_data tl_wdr6500_v2_flash_data = { + .part_probes = tl_wdr6500_v2_part_probes, +}; + +static struct gpio_led tl_wdr6500_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WDR6500_V2_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:white:system", + .gpio = TL_WDR6500_V2_GPIO_LED_SYS, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_wdr6500_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WDR6500_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WDR6500_V2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + + +static void __init tl_ap151_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f00fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&tl_wdr6500_v2_flash_data); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_data.speed = SPEED_1000; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(ee + TL_WDR6500_V2_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_register_pci(); + + ath79_register_usb(); +} + +static void __init tl_wdr6500_v2_setup(void) +{ + tl_ap151_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wdr6500_v2_leds_gpio), + tl_wdr6500_v2_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WDR6500_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wdr6500_v2_gpio_keys), + tl_wdr6500_v2_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR6500_V2, "TL-WDR6500-v2", "TP-LINK TL-WDR6500 v2", + tl_wdr6500_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c new file mode 100644 index 0000000..fa8c474 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c @@ -0,0 +1,138 @@ +/* + * TP-LINK TL-WR1041 v2 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * Copyright (C) 2011-2012 Anan Huang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1041NV2_GPIO_BTN_RESET 14 +#define TL_WR1041NV2_GPIO_LED_WPS 13 +#define TL_WR1041NV2_GPIO_LED_WLAN 11 + +#define TL_WR1041NV2_GPIO_LED_SYSTEM 12 + +#define TL_WR1041NV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1041NV2_KEYS_POLL_INTERVAL) + +#define TL_WR1041NV2_PCIE_CALDATA_OFFSET 0x5000 + +static const char *tl_wr1041nv2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr1041nv2_flash_data = { + .part_probes = tl_wr1041nv2_part_probes, +}; + +static struct gpio_led tl_wr1041nv2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR1041NV2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR1041NV2_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR1041NV2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr1041nv2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1041NV2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data db120_ar8327_data = { + .pad0_cfg = &db120_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info db120_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &db120_ar8327_data, + }, +}; + +static void __init tl_wr1041nv2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr1041nv2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1041nv2_leds_gpio), + tl_wr1041nv2_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR1041NV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1041nv2_gpio_keys), + tl_wr1041nv2_gpio_keys); + ath79_register_wmac(ee, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + mdiobus_register_board_info(db120_mdio0_info, + ARRAY_SIZE(db120_mdio0_info)); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1041N_V2, "TL-WR1041N-v2", + "TP-LINK TL-WR1041N v2", tl_wr1041nv2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c new file mode 100644 index 0000000..abdbde0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c @@ -0,0 +1,215 @@ +/* + * TP-LINK TL-WR1043ND v2 board support + * + * Copyright (c) 2013 Gabor Juhos + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1043_V2_GPIO_LED_WLAN 12 +#define TL_WR1043_V2_GPIO_LED_USB 15 +#define TL_WR1043_V2_GPIO_LED_WPS 18 +#define TL_WR1043_V2_GPIO_LED_SYSTEM 19 + +#define TL_WR1043_V2_GPIO_BTN_RESET 16 +#define TL_WR1043_V2_GPIO_BTN_RFKILL 17 + +#define TL_WR1043_V2_GPIO_USB_POWER 21 + +#define TL_WR1043_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043_V2_KEYS_POLL_INTERVAL) + +#define TL_WR1043_V2_WMAC_CALDATA_OFFSET 0x1000 + +static const char *wr1043nd_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wr1043nd_v2_flash_data = { + .part_probes = wr1043nd_v2_part_probes, +}; + +static struct gpio_led tl_wr1043_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:wps", + .gpio = TL_WR1043_V2_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "tp-link:green:system", + .gpio = TL_WR1043_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_WR1043_V2_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "tp-link:green:usb", + .gpio = TL_WR1043_V2_GPIO_LED_USB, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr1043_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043_V2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043_V2_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info tl_wr1043_leds_ar8327[] = { + AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:lan4"), + AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan3"), + AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"), + AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan1"), + AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:wan"), +}; + +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ +static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ +static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wr1043nd_v2_ar8327_led_cfg = { + .led_ctrl0 = 0xcc35cc35, + .led_ctrl1 = 0xca35ca35, + .led_ctrl2 = 0xc935c935, + .led_ctrl3 = 0x03ffff00, + .open_drain = true, +}; + +static struct ar8327_platform_data wr1043nd_v2_ar8327_data = { + .pad0_cfg = &wr1043nd_v2_ar8327_pad0_cfg, + .pad6_cfg = &wr1043nd_v2_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wr1043nd_v2_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(tl_wr1043_leds_ar8327), + .leds = tl_wr1043_leds_ar8327, +}; + +static struct mdio_board_info wr1043nd_v2_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wr1043nd_v2_ar8327_data, + }, +}; + +static void __init tl_wr1043nd_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(&wr1043nd_v2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio), + tl_wr1043_v2_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1043_v2_gpio_keys), + tl_wr1043_v2_gpio_keys); + + ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac); + + mdiobus_register_board_info(wr1043nd_v2_mdio0_info, + ARRAY_SIZE(wr1043nd_v2_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + ath79_register_usb(); + + gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND_V2, "TL-WR1043ND-v2", + "TP-LINK TL-WR1043ND v2", tl_wr1043nd_v2_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c new file mode 100644 index 0000000..61aeb52 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c @@ -0,0 +1,141 @@ +/* + * TP-LINK TL-WR1043N/ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1043ND_GPIO_LED_USB 1 +#define TL_WR1043ND_GPIO_LED_SYSTEM 2 +#define TL_WR1043ND_GPIO_LED_QSS 5 +#define TL_WR1043ND_GPIO_LED_WLAN 9 + +#define TL_WR1043ND_GPIO_BTN_RESET 3 +#define TL_WR1043ND_GPIO_BTN_QSS 7 + +#define TL_WR1043ND_GPIO_RTL8366_SDA 18 +#define TL_WR1043ND_GPIO_RTL8366_SCK 19 + +#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr1043nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr1043nd_flash_data = { + .part_probes = tl_wr1043nd_part_probes, +}; + +static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:usb", + .gpio = TL_WR1043ND_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR1043ND_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR1043ND_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void tl_wr1043nd_rtl8366rb_hw_reset(bool active) +{ + if (active) + ath79_device_reset_set(AR71XX_RESET_GE0_PHY); + else + ath79_device_reset_clear(AR71XX_RESET_GE0_PHY); +} + +static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = { + .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, + .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, + .hw_reset = tl_wr1043nd_rtl8366rb_hw_reset, +}; + +static struct platform_device tl_wr1043nd_rtl8366rb_device = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tl_wr1043nd_rtl8366rb_data, + } +}; + +static void __init tl_wr1043nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + tl_wr1043nd_rtl8366rb_hw_reset(true); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x1a000000; + + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_register_m25p80(&tl_wr1043nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), + tl_wr1043nd_leds_gpio); + + platform_device_register(&tl_wr1043nd_rtl8366rb_device); + + ath79_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1043nd_gpio_keys), + tl_wr1043nd_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", + tl_wr1043nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c new file mode 100644 index 0000000..8f6db5e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c @@ -0,0 +1,156 @@ +/* + * TP-LINK TL-WR2543N/ND board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TL_WR2543N_GPIO_LED_WPS 0 +#define TL_WR2543N_GPIO_LED_USB 8 + +/* The WLAN LEDs use GPIOs on the discrete AR9380 wmac */ +#define TL_WR2543N_GPIO_WMAC_LED_WLAN2G 0 +#define TL_WR2543N_GPIO_WMAC_LED_WLAN5G 1 + +#define TL_WR2543N_GPIO_BTN_RESET 11 +#define TL_WR2543N_GPIO_BTN_WPS 12 + +#define TL_WR2543N_GPIO_RTL8367_SDA 1 +#define TL_WR2543N_GPIO_RTL8367_SCK 6 + +#define TL_WR2543N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR2543N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR2543N_KEYS_POLL_INTERVAL) + +static const char *tl_wr2543n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr2543n_flash_data = { + .part_probes = tl_wr2543n_part_probes, +}; + +static struct gpio_led tl_wr2543n_leds_gpio[] __initdata = { + { + .name = "tp-link:green:usb", + .gpio = TL_WR2543N_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR2543N_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_led tl_wr2543n_wmac_leds_gpio[] = { + { + .name = "tp-link:green:wlan5g", + .gpio = TL_WR2543N_GPIO_WMAC_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr2543n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR2543N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR2543N_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8367_extif_config tl_wr2543n_rtl8367_extif0_cfg = { + .mode = RTL8367_EXTIF_MODE_RGMII, + .txdelay = 1, + .rxdelay = 0, + .ability = { + .force_mode = 1, + .txpause = 1, + .rxpause = 1, + .link = 1, + .duplex = 1, + .speed = RTL8367_PORT_SPEED_1000, + }, +}; + +static struct rtl8367_platform_data tl_wr2543n_rtl8367_data = { + .gpio_sda = TL_WR2543N_GPIO_RTL8367_SDA, + .gpio_sck = TL_WR2543N_GPIO_RTL8367_SCK, + .extif0_cfg = &tl_wr2543n_rtl8367_extif0_cfg, +}; + +static struct platform_device tl_wr2543n_rtl8367_device = { + .name = RTL8367_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tl_wr2543n_rtl8367_data, + } +}; + +static void __init tl_wr2543n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr2543n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr2543n_leds_gpio), + tl_wr2543n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR2543N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr2543n_gpio_keys), + tl_wr2543n_gpio_keys); + ath79_register_usb(); + + /* + * The ath9k driver uses this pin for its default led device, which is + * named ath9k-phy0, and reflects activity on either the 2 GHz or 5 GHz + * bands. This pin is connected to the WR2543's 2GHz WLAN LED. + */ + ap9x_pci_setup_wmac_led_pin(0, TL_WR2543N_GPIO_WMAC_LED_WLAN2G); + + /* + * We also have the driver set up an led device for the WR2543's + * separate 5 GHz WLAN LED in case the user wants it. + */ + ap9x_pci_setup_wmac_leds(0, tl_wr2543n_wmac_leds_gpio, + ARRAY_SIZE(tl_wr2543n_wmac_leds_gpio)); + ap91_pci_init(eeprom, mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_eth0_data.mii_bus_dev = &tl_wr2543n_rtl8367_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x1a000000; + + ath79_register_eth(0); + + platform_device_register(&tl_wr2543n_rtl8367_device); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR2543N, "TL-WR2543N", "TP-LINK TL-WR2543N/ND", + tl_wr2543n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c new file mode 100644 index 0000000..1d8d01c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c @@ -0,0 +1,118 @@ +/* + * TP-LINK TL-WR703N/TL-MR10U board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR703N_GPIO_LED_SYSTEM 27 +#define TL_WR703N_GPIO_BTN_RESET 11 + +#define TL_WR703N_GPIO_USB_POWER 8 + +#define TL_MR10U_GPIO_USB_POWER 18 + +#define TL_WR703N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR703N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR703N_KEYS_POLL_INTERVAL) + +static const char *tl_wr703n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr703n_flash_data = { + .part_probes = tl_wr703n_part_probes, +}; + +static struct gpio_led tl_wr703n_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_WR703N_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr703n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR703N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR703N_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init common_setup(unsigned usb_power_gpio, bool sec_ethernet) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_wr703n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio), + tl_wr703n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr703n_gpio_keys), + tl_wr703n_gpio_keys); + + gpio_request_one(usb_power_gpio, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + if (sec_ethernet) + { + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + ath79_register_eth(1); + } + + ath79_register_wmac(ee, mac); +} + +static void __init tl_mr10u_setup(void) +{ + common_setup(TL_MR10U_GPIO_USB_POWER, false); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR10U, "TL-MR10U", "TP-LINK TL-MR10U", + tl_mr10u_setup); + +static void __init tl_wr703n_setup(void) +{ + common_setup(TL_WR703N_GPIO_USB_POWER, false); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR703N, "TL-WR703N", "TP-LINK TL-WR703N v1", + tl_wr703n_setup); + +static void __init tl_wr710n_setup(void) +{ + common_setup(TL_WR703N_GPIO_USB_POWER, true); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR710N, "TL-WR710N", "TP-LINK TL-WR710N v1", + tl_wr710n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr720n-v3.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr720n-v3.c new file mode 100644 index 0000000..2bb3b44 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr720n-v3.c @@ -0,0 +1,108 @@ +/* + * TP-LINK TL-WR720N board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2013 yousong + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR720N_GPIO_LED_SYSTEM 27 +#define TL_WR720N_GPIO_BTN_RESET 11 +#define TL_WR720N_GPIO_BTN_SW1 18 +#define TL_WR720N_GPIO_BTN_SW2 20 + +#define TL_WR720N_GPIO_USB_POWER 8 + +#define TL_WR720N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR720N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR720N_KEYS_POLL_INTERVAL) + +static const char *tl_wr720n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr720n_flash_data = { + .part_probes = tl_wr720n_part_probes, +}; + +static struct gpio_led tl_wr720n_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_WR720N_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr720n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR720N_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR720N_GPIO_BTN_SW1, + .active_low = 0, + }, { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR720N_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init tl_wr720n_v3_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_wr720n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr720n_leds_gpio), + tl_wr720n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR720N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr720n_gpio_keys), + tl_wr720n_gpio_keys); + + gpio_request_one(TL_WR720N_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR720N_V3, "TL-WR720N-v3", "TP-LINK TL-WR720N v3/v4", + tl_wr720n_v3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c new file mode 100644 index 0000000..851b762 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c @@ -0,0 +1,187 @@ +/* + * TP-LINK TL-WR741ND v4/TL-MR3220 v2 board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR741NDV4_GPIO_BTN_RESET 11 +#define TL_WR741NDV4_GPIO_BTN_WPS 26 + +#define TL_WR741NDV4_GPIO_LED_WLAN 0 +#define TL_WR741NDV4_GPIO_LED_QSS 1 +#define TL_WR741NDV4_GPIO_LED_WAN 13 +#define TL_WR741NDV4_GPIO_LED_LAN1 14 +#define TL_WR741NDV4_GPIO_LED_LAN2 15 +#define TL_WR741NDV4_GPIO_LED_LAN3 16 +#define TL_WR741NDV4_GPIO_LED_LAN4 17 +#define TL_WR741NDV4_GPIO_LED_SYSTEM 27 + +#define TL_MR3220V2_GPIO_BTN_WPS 11 +#define TL_MR3220V2_GPIO_BTN_WIFI 24 + +#define TL_MR3220V2_GPIO_LED_3G 26 +#define TL_MR3220V2_GPIO_USB_POWER 8 + +#define TL_WR741NDV4_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741NDV4_KEYS_POLL_INTERVAL) + +static const char *tl_wr741ndv4_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr741ndv4_flash_data = { + .part_probes = tl_wr741ndv4_part_probes, +}; + +static struct gpio_led tl_wr741ndv4_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR741NDV4_GPIO_LED_LAN1, + .active_low = 0, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR741NDV4_GPIO_LED_LAN2, + .active_low = 0, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR741NDV4_GPIO_LED_LAN3, + .active_low = 0, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR741NDV4_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR741NDV4_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR741NDV4_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR741NDV4_GPIO_LED_WAN, + .active_low = 0, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR741NDV4_GPIO_LED_WLAN, + .active_low = 0, + }, { + /* the 3G LED is only present on the MR3220 v2 */ + .name = "tp-link:green:3g", + .gpio = TL_MR3220V2_GPIO_LED_3G, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_wr741ndv4_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741NDV4_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741NDV4_GPIO_BTN_WPS, + .active_low = 0, + } +}; + +static struct gpio_keys_button tl_mr3220v2_gpio_keys[] __initdata = { + { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3220V2_GPIO_BTN_WPS, + .active_low = 0, + }, { + .desc = "WIFI button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3220V2_GPIO_BTN_WIFI, + .active_low = 0, + } +}; + +static void __init tl_ap121_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(&tl_wr741ndv4_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wr741ndv4_setup(void) +{ + tl_ap121_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio) - 1, + tl_wr741ndv4_leds_gpio); + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr741ndv4_gpio_keys), + tl_wr741ndv4_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR741ND_V4, "TL-WR741ND-v4", + "TP-LINK TL-WR741ND v4", tl_wr741ndv4_setup); + +static void __init tl_mr3220v2_setup(void) +{ + tl_ap121_setup(); + + gpio_request_one(TL_MR3220V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio), + tl_wr741ndv4_leds_gpio); + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3220v2_gpio_keys), + tl_mr3220v2_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3220_V2, "TL-MR3220-v2", + "TP-LINK TL-MR3220 v2", tl_mr3220v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c new file mode 100644 index 0000000..5931654 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c @@ -0,0 +1,130 @@ +/* + * TP-LINK TL-WR741ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define TL_WR741ND_GPIO_LED_QSS 0 +#define TL_WR741ND_GPIO_LED_SYSTEM 1 +#define TL_WR741ND_GPIO_LED_LAN1 13 +#define TL_WR741ND_GPIO_LED_LAN2 14 +#define TL_WR741ND_GPIO_LED_LAN3 15 +#define TL_WR741ND_GPIO_LED_LAN4 16 +#define TL_WR741ND_GPIO_LED_WAN 17 + +#define TL_WR741ND_GPIO_BTN_RESET 11 +#define TL_WR741ND_GPIO_BTN_QSS 12 + +#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr741nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr741nd_flash_data = { + .part_probes = tl_wr741nd_part_probes, +}; + +static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR741ND_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR741ND_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR741ND_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR741ND_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR741ND_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR741ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR741ND_GPIO_LED_WAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wr741nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr741nd_flash_data); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), + tl_wr741nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr741nd_gpio_keys), + tl_wr741nd_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap91_pci_init(ee, mac); +} +MIPS_MACHINE(ATH79_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", + tl_wr741nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c new file mode 100644 index 0000000..73cfdd9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c @@ -0,0 +1,286 @@ +/* + * TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR841NV8_GPIO_LED_WLAN 13 +#define TL_WR841NV8_GPIO_LED_QSS 15 +#define TL_WR841NV8_GPIO_LED_WAN 18 +#define TL_WR841NV8_GPIO_LED_LAN1 19 +#define TL_WR841NV8_GPIO_LED_LAN2 20 +#define TL_WR841NV8_GPIO_LED_LAN3 21 +#define TL_WR841NV8_GPIO_LED_LAN4 12 +#define TL_WR841NV8_GPIO_LED_SYSTEM 14 + +#define TL_WR841NV8_GPIO_BTN_RESET 17 +#define TL_WR841NV8_GPIO_SW_RFKILL 16 /* WPS for MR3420 v2 */ + +#define TL_MR3420V2_GPIO_LED_3G 11 +#define TL_MR3420V2_GPIO_USB_POWER 4 + +#define TL_WR941NDV5_GPIO_LED_WLAN 13 +#define TL_WR941NDV5_GPIO_LED_QSS 15 +#define TL_WR941NDV5_GPIO_LED_WAN 18 +#define TL_WR941NDV5_GPIO_LED_LAN1 19 +#define TL_WR941NDV5_GPIO_LED_LAN2 20 +#define TL_WR941NDV5_GPIO_LED_LAN3 2 +#define TL_WR941NDV5_GPIO_LED_LAN4 3 +#define TL_WR941NDV5_GPIO_LED_SYSTEM 14 + +#define TL_WR841NV8_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV8_KEYS_POLL_INTERVAL) + +static const char *tl_wr841n_v8_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr841n_v8_flash_data = { + .part_probes = tl_wr841n_v8_part_probes, +}; + +static struct gpio_led tl_wr841n_v8_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR841NV8_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR841NV8_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR841NV8_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR841NV8_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841NV8_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR841NV8_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR841NV8_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR841NV8_GPIO_LED_WLAN, + .active_low = 1, + }, { + /* the 3G LED is only present on the MR3420 v2 */ + .name = "tp-link:green:3g", + .gpio = TL_MR3420V2_GPIO_LED_3G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr841n_v8_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static struct gpio_keys_button tl_mr3420v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static struct gpio_led tl_wr941nd_v5_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR941NDV5_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR941NDV5_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR941NDV5_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR941NDV5_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR941NDV5_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR941NDV5_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR941NDV5_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR941NDV5_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static void __init tl_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + /* config gpio4 as normal gpio function */ + ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER, + AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&tl_wr841n_v8_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wr841n_v8_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio) - 1, + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V8, "TL-WR841N-v8", "TP-LINK TL-WR841N/ND v8", + tl_wr841n_v8_setup); + + +static void __init tl_wr842n_v2_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio), + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); + + gpio_request_one(TL_MR3420V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR842N_V2, "TL-WR842N-v2", "TP-LINK TL-WR842N/ND v2", + tl_wr842n_v2_setup); + +static void __init tl_mr3420v2_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio), + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3420v2_gpio_keys), + tl_mr3420v2_gpio_keys); + + /* enable power for the USB port */ + gpio_request_one(TL_MR3420V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3420_V2, "TL-MR3420-v2", "TP-LINK TL-MR3420 v2", + tl_mr3420v2_setup); + + +static void __init tl_wr941nd_v5_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_v5_leds_gpio), + tl_wr941nd_v5_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR941ND_V5, "TL-WR941ND-v5", "TP-LINK TL-WR941N/ND v5", + tl_wr941nd_v5_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c new file mode 100644 index 0000000..3e5c2a2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c @@ -0,0 +1,144 @@ +/* + * TP-LINK TL-WR841N/ND v9 + * + * Copyright (C) 2014 Matthias Schiffer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR841NV9_GPIO_LED_WLAN 13 +#define TL_WR841NV9_GPIO_LED_QSS 3 +#define TL_WR841NV9_GPIO_LED_WAN 4 +#define TL_WR841NV9_GPIO_LED_LAN1 16 +#define TL_WR841NV9_GPIO_LED_LAN2 15 +#define TL_WR841NV9_GPIO_LED_LAN3 14 +#define TL_WR841NV9_GPIO_LED_LAN4 11 + +#define TL_WR841NV9_GPIO_BTN_RESET 12 +#define TL_WR841NV9_GPIO_BTN_WIFI 17 + +#define TL_WR841NV9_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV9_KEYS_POLL_INTERVAL) + +static const char *tl_wr841n_v9_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr841n_v9_flash_data = { + .part_probes = tl_wr841n_v9_part_probes, +}; + +static struct gpio_led tl_wr841n_v9_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR841NV9_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR841NV9_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR841NV9_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR841NV9_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841NV9_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR841NV9_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR841NV9_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr841n_v9_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV9_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WIFI button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV9_GPIO_BTN_WIFI, + .active_low = 1, + } +}; + + +static void __init tl_ap143_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&tl_wr841n_v9_flash_data); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + ath79_init_mac(tmpmac, mac, 0); + ath79_register_wmac(ee, tmpmac); +} + +static void __init tl_wr841n_v9_setup(void) +{ + tl_ap143_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v9_leds_gpio), + tl_wr841n_v9_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v9_gpio_keys), + tl_wr841n_v9_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9", + tl_wr841n_v9_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c new file mode 100644 index 0000000..11f853f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c @@ -0,0 +1,140 @@ +/* + * TP-LINK TL-WR841N/ND v1 board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 +#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 +#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 + +#define TL_WR841ND_V1_GPIO_BTN_RESET 3 +#define TL_WR841ND_V1_GPIO_BTN_QSS 7 + +#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \ + (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL) + +static struct mtd_partition tl_wr841n_v1_partitions[] = { + { + .name = "redboot", + .offset = 0, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x020000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x160000, + .size = 0x280000, + }, { + .name = "config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x020000, + .size = 0x3c0000, + } +}; + +static struct flash_platform_data tl_wr841n_v1_flash_data = { + .parts = tl_wr841n_v1_partitions, + .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), +}; + +static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:red:qss", + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, + } +}; + +static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { + .port_names[0] = "wan", + .port_names[1] = "lan1", + .port_names[2] = "lan2", + .port_names[3] = "lan3", + .port_names[4] = "lan4", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data tl_wr841n_v1_dsa_data = { + .nr_chips = 1, + .chip = &tl_wr841n_v1_dsa_chip, +}; + +static void __init tl_wr841n_v1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev, + &tl_wr841n_v1_dsa_data); + + ath79_register_m25p80(&tl_wr841n_v1_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), + tl_wr841n_v1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v1_gpio_keys), + tl_wr841n_v1_gpio_keys); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", + tl_wr841n_v1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c new file mode 100644 index 0000000..1ddeec7 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c @@ -0,0 +1,121 @@ +/* + * TP-LINK TL-WR941ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR941ND_GPIO_LED_SYSTEM 2 +#define TL_WR941ND_GPIO_LED_QSS_RED 4 +#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 +#define TL_WR941ND_GPIO_LED_WLAN 9 + +#define TL_WR941ND_GPIO_BTN_RESET 3 +#define TL_WR941ND_GPIO_BTN_QSS 7 + +#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr941nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr941nd_flash_data = { + .part_probes = tl_wr941nd_part_probes, +}; + +static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR941ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:red:qss", + .gpio = TL_WR941ND_GPIO_LED_QSS_RED, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR941ND_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR941ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR941ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static struct dsa_chip_data tl_wr941nd_dsa_chip = { + .port_names[0] = "wan", + .port_names[1] = "lan1", + .port_names[2] = "lan2", + .port_names[3] = "lan3", + .port_names[4] = "lan4", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data tl_wr941nd_dsa_data = { + .nr_chips = 1, + .chip = &tl_wr941nd_dsa_chip, +}; + +static void __init tl_wr941nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev, + &tl_wr941nd_dsa_data); + + ath79_register_m25p80(&tl_wr941nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), + tl_wr941nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr941nd_gpio_keys), + tl_wr941nd_gpio_keys); + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", + tl_wr941nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tube2h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tube2h.c new file mode 100644 index 0000000..19b32e2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tube2h.c @@ -0,0 +1,118 @@ +/* + * ALFA NETWORK Tube2H board support + * + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TUBE2H_GPIO_LED_SIGNAL4 0 +#define TUBE2H_GPIO_LED_SIGNAL3 1 +#define TUBE2H_GPIO_LED_SIGNAL2 13 +#define TUBE2H_GPIO_LED_LAN 17 +#define TUBE2H_GPIO_LED_SIGNAL1 27 +#define TUBE2H_GPIO_EXT_LNA 28 + +#define TUBE2H_GPIO_BTN_RESET 12 + +#define TUBE2H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TUBE2H_KEYS_DEBOUNCE_INTERVAL (3 * TUBE2H_KEYS_POLL_INTERVAL) + +#define TUBE2H_ART_ADDRESS 0x1f7f0000 +#define TUBE2H_LAN_MAC_OFFSET 0x06 +#define TUBE2H_CALDATA_OFFSET 0x1000 + +static struct gpio_led tube2h_leds_gpio[] __initdata = { + { + .name = "alfa:blue:lan", + .gpio = TUBE2H_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "alfa:red:signal1", + .gpio = TUBE2H_GPIO_LED_SIGNAL1, + .active_low = 1, + }, + { + .name = "alfa:orange:signal2", + .gpio = TUBE2H_GPIO_LED_SIGNAL2, + .active_low = 0, + }, + { + .name = "alfa:green:signal3", + .gpio = TUBE2H_GPIO_LED_SIGNAL3, + .active_low = 0, + }, + { + .name = "alfa:green:signal4", + .gpio = TUBE2H_GPIO_LED_SIGNAL4, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tube2h_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TUBE2H_KEYS_DEBOUNCE_INTERVAL, + .gpio = TUBE2H_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init tube2h_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TUBE2H_ART_ADDRESS); + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_JTAG_DISABLE | + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + /* Ensure that GPIO26 and GPIO27 are controllable by software */ + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + gpio_request_one(TUBE2H_GPIO_EXT_LNA, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "external LNA0"); + + ath79_register_wmac(art + TUBE2H_CALDATA_OFFSET, NULL); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tube2h_leds_gpio), + tube2h_leds_gpio); + ath79_register_gpio_keys_polled(-1, TUBE2H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tube2h_gpio_keys), + tube2h_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + TUBE2H_LAN_MAC_OFFSET, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TUBE2H, "TUBE2H", "ALFA NETWORK Tube2H", + tube2h_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c new file mode 100644 index 0000000..e49ac23 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c @@ -0,0 +1,205 @@ +/* + * Ubiquiti RouterStation support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008 Ubiquiti + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define UBNT_RS_GPIO_LED_RF 2 +#define UBNT_RS_GPIO_SW4 8 + +#define UBNT_LS_SR71_GPIO_LED_D25 0 +#define UBNT_LS_SR71_GPIO_LED_D26 1 +#define UBNT_LS_SR71_GPIO_LED_D24 2 +#define UBNT_LS_SR71_GPIO_LED_D23 4 +#define UBNT_LS_SR71_GPIO_LED_D22 5 +#define UBNT_LS_SR71_GPIO_LED_D27 6 +#define UBNT_LS_SR71_GPIO_LED_D28 7 + +#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */ +#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL) + +static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { + { + .name = "ubnt:green:rf", + .gpio = UBNT_RS_GPIO_LED_RF, + .active_low = 0, + } +}; + +static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { + { + .name = "ubnt:green:d22", + .gpio = UBNT_LS_SR71_GPIO_LED_D22, + .active_low = 0, + }, { + .name = "ubnt:green:d23", + .gpio = UBNT_LS_SR71_GPIO_LED_D23, + .active_low = 0, + }, { + .name = "ubnt:green:d24", + .gpio = UBNT_LS_SR71_GPIO_LED_D24, + .active_low = 0, + }, { + .name = "ubnt:red:d25", + .gpio = UBNT_LS_SR71_GPIO_LED_D25, + .active_low = 0, + }, { + .name = "ubnt:red:d26", + .gpio = UBNT_LS_SR71_GPIO_LED_D26, + .active_low = 0, + }, { + .name = "ubnt:green:d27", + .gpio = UBNT_LS_SR71_GPIO_LED_D27, + .active_low = 0, + }, { + .name = "ubnt:green:d28", + .gpio = UBNT_LS_SR71_GPIO_LED_D28, + .active_low = 0, + } +}; + +static struct gpio_keys_button ubnt_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, + .gpio = UBNT_RS_GPIO_SW4, + .active_low = 1, + } +}; + +static const char *ubnt_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data ubnt_flash_data = { + .part_probes = ubnt_part_probes, +}; + +static void __init ubnt_generic_setup(void) +{ + ath79_register_m25p80(&ubnt_flash_data); + + ath79_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_gpio_keys), + ubnt_gpio_keys); + ath79_register_pci(); +} + +#define UBNT_RS_WAN_PHYMASK BIT(20) +#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) + +static void __init ubnt_rs_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; + + /* + * There is Secondary MAC address duplicate problem with some + * UBNT HW batches. Do not increase Secondary MAC address by 1 + * but do workaround with 'Locally Administrated' bit. + */ + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), + ubnt_rs_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", + ubnt_rs_setup); + +#define UBNT_RSPRO_WAN_PHYMASK BIT(4) +#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +static void __init ubnt_rspro_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~(UBNT_RSPRO_WAN_PHYMASK | + UBNT_RSPRO_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; + + /* + * There is Secondary MAC address duplicate problem with some + * UBNT HW batches. Do not increase Secondary MAC address by 1 + * but do workaround with 'Locally Administrated' bit. + */ + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), + ubnt_rs_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", + ubnt_rspro_setup); + +static void __init ubnt_lsx_setup(void) +{ + ubnt_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); + +#define UBNT_LSSR71_PHY_MASK BIT(1) + +static void __init ubnt_lssr71_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~UBNT_LSSR71_PHY_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; + + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), + ubnt_ls_sr71_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", + ubnt_lssr71_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-weio.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-weio.c new file mode 100644 index 0000000..3973ada --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-weio.c @@ -0,0 +1,140 @@ +/** + * WEIO Web Of Things Platform + * + * Copyright (C) 2013 Drasko DRASKOVIC and Uros PETREVSKI + * + * ## ## ######## #### ####### + * ## ## ## ## ## ## ## + * ## ## ## ## ## ## ## + * ## ## ## ###### ## ## ## + * ## ## ## ## ## ## ## + * ## ## ## ## ## ## ## + * ### ### ######## #### ####### + * + * Web Of Things Platform + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Authors : + * Drasko DRASKOVIC + * Uros PETREVSKI + */ + +#include +#include +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WEIO_GPIO_LED_STA 1 +#define WEIO_GPIO_LED_AP 16 + +#define WEIO_GPIO_BTN_AP 20 +#define WEIO_GPIO_BTN_RESET 23 + +#define WEIO_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WEIO_KEYS_DEBOUNCE_INTERVAL (3 * WEIO_KEYS_POLL_INTERVAL) + +#define WEIO_MAC0_OFFSET 0x0000 +#define WEIO_MAC1_OFFSET 0x0006 +#define WEIO_CALDATA_OFFSET 0x1000 +#define WEIO_WMAC_MAC_OFFSET 0x1002 + +static struct gpio_led weio_leds_gpio[] __initdata = { + { + .name = "weio:green:sta", + .gpio = WEIO_GPIO_LED_STA, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "weio:green:ap", + .gpio = WEIO_GPIO_LED_AP, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static struct gpio_keys_button weio_gpio_keys[] __initdata = { + { + .desc = "ap button", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = WEIO_KEYS_DEBOUNCE_INTERVAL, + .gpio = WEIO_GPIO_BTN_AP, + .active_low = 1, + }, + { + .desc = "soft-reset button", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = WEIO_KEYS_DEBOUNCE_INTERVAL, + .gpio = WEIO_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data weio_i2c_gpio_data = { + .sda_pin = 18, + .scl_pin = 19, +}; + +static struct platform_device weio_i2c_gpio = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &weio_i2c_gpio_data, + }, +}; + +static void __init weio_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art + WEIO_CALDATA_OFFSET, art + WEIO_WMAC_MAC_OFFSET); +} + +static void __init weio_setup(void) +{ + weio_common_setup(); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + platform_device_register(&weio_i2c_gpio); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(weio_leds_gpio), + weio_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WEIO_KEYS_POLL_INTERVAL, + ARRAY_SIZE(weio_gpio_keys), + weio_gpio_keys); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_WEIO, "WEIO", "WeIO board", weio_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c new file mode 100644 index 0000000..48f49ad --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c @@ -0,0 +1,155 @@ +/* + * Buffalo WHR-HP-G300N board support + * + * based on ... + * + * TP-LINK TL-WR741ND board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WHRHPG300N_GPIO_LED_SECURITY 0 +#define WHRHPG300N_GPIO_LED_DIAG 1 +#define WHRHPG300N_GPIO_LED_ROUTER 6 + +#define WHRHPG300N_GPIO_BTN_ROUTER_ON 7 +#define WHRHPG300N_GPIO_BTN_ROUTER_AUTO 8 +#define WHRHPG300N_GPIO_BTN_RESET 11 +#define WHRHPG300N_GPIO_BTN_AOSS 12 +#define WHRHPG300N_GPIO_LED_LAN1 13 +#define WHRHPG300N_GPIO_LED_LAN2 14 +#define WHRHPG300N_GPIO_LED_LAN3 15 +#define WHRHPG300N_GPIO_LED_LAN4 16 +#define WHRHPG300N_GPIO_LED_WAN 17 + +#define WHRHPG300N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WHRHPG300N_KEYS_DEBOUNCE_INTERVAL (3 * WHRHPG300N_KEYS_POLL_INTERVAL) + +#define WHRHPG300N_MAC_OFFSET 0x20c + +static struct gpio_led whrhpg300n_leds_gpio[] __initdata = { + { + .name = "buffalo:orange:security", + .gpio = WHRHPG300N_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "buffalo:red:diag", + .gpio = WHRHPG300N_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "buffalo:green:router", + .gpio = WHRHPG300N_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "buffalo:green:wan", + .gpio = WHRHPG300N_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "buffalo:green:lan1", + .gpio = WHRHPG300N_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "buffalo:green:lan2", + .gpio = WHRHPG300N_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "buffalo:green:lan3", + .gpio = WHRHPG300N_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "buffalo:green:lan4", + .gpio = WHRHPG300N_GPIO_LED_LAN4, + .active_low = 1, + } +}; + +static struct gpio_keys_button whrhpg300n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHRHPG300N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "aoss/wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .gpio = WHRHPG300N_GPIO_BTN_AOSS, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_2, + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_ON, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_3, + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_AUTO, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + } +}; + +static void __init whrhpg300n_setup(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac = (u8 *) KSEG1ADDR(ee + WHRHPG300N_MAC_OFFSET); + + ath79_register_m25p80(NULL); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(whrhpg300n_leds_gpio), + whrhpg300n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WHRHPG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(whrhpg300n_gpio_keys), + whrhpg300n_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + /* WAN port */ + ath79_register_eth(0); + + ap9x_pci_setup_wmac_led_pin(0, 1); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_WHR_HP_G300N, "WHR-HP-G300N", "Buffalo WHR-HP-G300N", + whrhpg300n_setup); + +MIPS_MACHINE(ATH79_MACH_WHR_G301N, "WHR-G301N", "Buffalo WHR-G301N", + whrhpg300n_setup); + +MIPS_MACHINE(ATH79_MACH_WHR_HP_GN, "WHR-HP-GN", "Buffalo WHR-HP-GN", + whrhpg300n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c new file mode 100644 index 0000000..11006fd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c @@ -0,0 +1,114 @@ +/* + * Buffalo WLAE-AG300N board support + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WLAEAG300N_MAC_OFFSET 0x20c +#define WLAEAG300N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WLAEAG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLAEAG300N_KEYS_POLL_INTERVAL) + + +static struct gpio_led wlaeag300n_leds_gpio[] __initdata = { + /* + * Note: Writing 1 into GPIO 13 will power down the device. + */ + { + .name = "buffalo:green:wireless", + .gpio = 14, + .active_low = 1, + }, { + .name = "buffalo:red:wireless", + .gpio = 15, + .active_low = 1, + }, { + .name = "buffalo:green:status", + .gpio = 16, + .active_low = 1, + }, { + .name = "buffalo:red:status", + .gpio = 17, + .active_low = 1, + } +}; + + +static struct gpio_keys_button wlaeag300n_gpio_keys[] __initdata = { + { + .desc = "function", + .type = EV_KEY, + .code = KEY_MODE, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 0, + .active_low = 1, + }, { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "power", + .type = EV_KEY, + .code = KEY_POWER, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 1, + } +}; + +static void __init wlaeag300n_setup(void) +{ + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac1 = eeprom1 + WLAEAG300N_MAC_OFFSET; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 1); + + ath79_register_mdio(0, ~(BIT(0) | BIT(4))); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlaeag300n_leds_gpio), + wlaeag300n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WLAEAG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wlaeag300n_gpio_keys), + wlaeag300n_gpio_keys); + + ath79_register_m25p80(NULL); + + ap91_pci_init(eeprom1, mac1); +} + +MIPS_MACHINE(ATH79_MACH_WLAE_AG300N, "WLAE-AG300N", + "Buffalo WLAE-AG300N", wlaeag300n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c new file mode 100644 index 0000000..6a90c6e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c @@ -0,0 +1,206 @@ +/* + * Sitecom X8 AC1750 WLR-8100 board support + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WLR8100_GPIO_LED_USB 4 +#define WLR8100_GPIO_LED_WLAN_5G 12 +#define WLR8100_GPIO_LED_WLAN_2G 13 +#define WLR8100_GPIO_LED_STATUS_RED 14 +#define WLR8100_GPIO_LED_WPS_RED 15 +#define WLR8100_GPIO_LED_STATUS_AMBER 19 +#define WLR8100_GPIO_LED_WPS_GREEN 20 + +#define WLR8100_GPIO_BTN_WPS 16 +#define WLR8100_GPIO_BTN_RFKILL 21 + +#define WLR8100_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WLR8100_KEYS_DEBOUNCE_INTERVAL (3 * WLR8100_KEYS_POLL_INTERVAL) + +#define WLR8100_MAC0_OFFSET 0 +#define WLR8100_MAC1_OFFSET 6 +#define WLR8100_WMAC_CALDATA_OFFSET 0x1000 +#define WLR8100_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led wlr8100_leds_gpio[] __initdata = { + { + .name = "wlr8100:amber:status", + .gpio = WLR8100_GPIO_LED_STATUS_AMBER, + .active_low = 1, + }, + { + .name = "wlr8100:red:status", + .gpio = WLR8100_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { + .name = "wlr8100:green:wps", + .gpio = WLR8100_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { + .name = "wlr8100:red:wps", + .gpio = WLR8100_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { + .name = "wlr8100:red:wlan-2g", + .gpio = WLR8100_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "wlr8100:red:usb", + .gpio = WLR8100_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button wlr8100_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLR8100_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLR8100_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wlr8100_ar8327_pad0_cfg; +static struct ar8327_pad_cfg wlr8100_ar8327_pad6_cfg; + +static struct ar8327_platform_data wlr8100_ar8327_data = { + .pad0_cfg = &wlr8100_ar8327_pad0_cfg, + .pad6_cfg = &wlr8100_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info wlr8100_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wlr8100_ar8327_data, + }, +}; + +static void __init wlr8100_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlr8100_leds_gpio), + wlr8100_leds_gpio); + ath79_register_gpio_keys_polled(-1, WLR8100_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wlr8100_gpio_keys), + wlr8100_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WLR8100_MAC0_OFFSET, 0); + + mdiobus_register_board_info(wlr8100_mdio0_info, + ARRAY_SIZE(wlr8100_mdio0_info)); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); + + /* GMAC1 is connected tot eh SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); +} + +static void __init wlr8100_010_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ + wlr8100_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; + wlr8100_ar8327_pad0_cfg.txclk_delay_en = true; + wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true; + wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true; + + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ + wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; + wlr8100_ar8327_pad6_cfg.rxclk_delay_en = true; + wlr8100_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + wlr8100_common_setup(); + ap91_pci_init(art + WLR8100_PCIE_CALDATA_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WLR8100, "WLR8100", + "Sitecom WLR-8100", + wlr8100_010_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndap360.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndap360.c new file mode 100644 index 0000000..e70d88b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndap360.c @@ -0,0 +1,105 @@ +/* + * Netgear WNDAP360 board support (proper leds / button support missing) + * + * Based on AP96 + * Copyright (C) 2013 Jacek Kikiewicz + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WNDAP360_GPIO_LED_POWER_ORANGE 0 +#define WNDAP360_GPIO_LED_POWER_GREEN 2 + +/* Reset button - next to the power connector */ +#define WNDAP360_GPIO_BTN_RESET 8 + +#define WNDAP360_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDAP360_KEYS_DEBOUNCE_INTERVAL (3 * WNDAP360_KEYS_POLL_INTERVAL) + +#define WNDAP360_WMAC0_MAC_OFFSET 0x120c +#define WNDAP360_WMAC1_MAC_OFFSET 0x520c +#define WNDAP360_CALDATA0_OFFSET 0x1000 +#define WNDAP360_CALDATA1_OFFSET 0x5000 + +/* + * WNDAP360 this still uses leds definitions from AP96 + * + */ +static struct gpio_led wndap360_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNDAP360_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "netgear:orange:power", + .gpio = WNDAP360_GPIO_LED_POWER_ORANGE, + .active_low = 1, + } +}; + +static struct gpio_keys_button wndap360_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDAP360_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDAP360_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define WNDAP360_LAN_PHYMASK 0x0f + +static void __init wndap360_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, ~(WNDAP360_LAN_PHYMASK)); + + /* Reusing wifi MAC with offset of 1 as eth0 MAC */ + ath79_init_mac(ath79_eth0_data.mac_addr, + art + WNDAP360_WMAC0_MAC_OFFSET, 1); + ath79_eth0_pll_data.pll_1000 = 0x11110000; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = WNDAP360_LAN_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndap360_leds_gpio), + wndap360_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNDAP360_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndap360_gpio_keys), + wndap360_gpio_keys); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(art + WNDAP360_CALDATA0_OFFSET, + art + WNDAP360_WMAC0_MAC_OFFSET, + art + WNDAP360_CALDATA1_OFFSET, + art + WNDAP360_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_WNDAP360, "WNDAP360", "Netgear WNDAP360", wndap360_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c new file mode 100644 index 0000000..1315bab --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c @@ -0,0 +1,172 @@ +/* + * Netgear WNDR3700 board support + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WNDR3700_GPIO_LED_WPS_ORANGE 0 +#define WNDR3700_GPIO_LED_POWER_ORANGE 1 +#define WNDR3700_GPIO_LED_POWER_GREEN 2 +#define WNDR3700_GPIO_LED_WPS_GREEN 4 +#define WNDR3700_GPIO_LED_WAN_GREEN 6 + +#define WNDR3700_GPIO_BTN_WPS 3 +#define WNDR3700_GPIO_BTN_RESET 8 +#define WNDR3700_GPIO_BTN_WIFI 11 + +#define WNDR3700_GPIO_RTL8366_SDA 5 +#define WNDR3700_GPIO_RTL8366_SCK 7 + +#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL) + +#define WNDR3700_ETH0_MAC_OFFSET 0 +#define WNDR3700_ETH1_MAC_OFFSET 0x6 + +#define WNDR3700_WMAC0_MAC_OFFSET 0 +#define WNDR3700_WMAC1_MAC_OFFSET 0xc +#define WNDR3700_CALDATA0_OFFSET 0x1000 +#define WNDR3700_CALDATA1_OFFSET 0x5000 + +static struct gpio_led wndr3700_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNDR3700_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "netgear:orange:power", + .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "netgear:green:wps", + .gpio = WNDR3700_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, { + .name = "netgear:orange:wps", + .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, + .active_low = 1, + }, { + .name = "netgear:green:wan", + .gpio = WNDR3700_GPIO_LED_WAN_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_WIFI, + .active_low = 1, + } +}; + +static struct rtl8366_platform_data wndr3700_rtl8366s_data = { + .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, + .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, +}; + +static struct platform_device wndr3700_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wndr3700_rtl8366s_data, + } +}; + +static void __init wndr3700_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* + * The eth0 and wmac0 interfaces share the same MAC address which + * can lead to problems if operated unbridged. Set the locally + * administered bit on the eth0 MAC to make it unique. + */ + ath79_init_local_mac(ath79_eth0_data.mac_addr, + art + WNDR3700_ETH0_MAC_OFFSET); + ath79_eth0_pll_data.pll_1000 = 0x11110000; + ath79_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + WNDR3700_ETH1_MAC_OFFSET, 0); + ath79_eth1_pll_data.pll_1000 = 0x11110000; + ath79_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), + wndr3700_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndr3700_gpio_keys), + wndr3700_gpio_keys); + + platform_device_register(&wndr3700_rtl8366s_device); + platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */ + ap9x_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6)); + + /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */ + ap9x_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6)); + + ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, + art + WNDR3700_WMAC0_MAC_OFFSET, + art + WNDR3700_CALDATA1_OFFSET, + art + WNDR3700_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_WNDR3700, "WNDR3700", + "NETGEAR WNDR3700/WNDR3800/WNDRMAC", + wndr3700_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr4300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr4300.c new file mode 100644 index 0000000..2884c6c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr4300.c @@ -0,0 +1,210 @@ +/* + * NETGEAR WNDR3700v4/WNDR4300 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2014 Ralph Perlich + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* AR9344 GPIOs */ +#define WNDR4300_GPIO_LED_POWER_GREEN 0 +#define WNDR4300_GPIO_LED_POWER_AMBER 2 +#define WNDR4300_GPIO_LED_USB 13 +#define WNDR4300_GPIO_LED_WAN_GREEN 1 +#define WNDR4300_GPIO_LED_WAN_AMBER 3 +#define WNDR4300_GPIO_LED_WLAN2G 11 +#define WNDR4300_GPIO_LED_WLAN5G 14 +#define WNDR4300_GPIO_LED_WPS_GREEN 16 +#define WNDR4300_GPIO_LED_WPS_AMBER 17 + +#define WNDR4300_GPIO_BTN_RESET 21 +#define WNDR4300_GPIO_BTN_WIRELESS 15 +#define WNDR4300_GPIO_BTN_WPS 12 + +/* AR9580 GPIOs */ +#define WNDR4300_GPIO_USB_5V 0 + +#define WNDR4300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WNDR4300_KEYS_POLL_INTERVAL) + +static struct gpio_led wndr4300_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNDR4300_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:power", + .gpio = WNDR4300_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wan", + .gpio = WNDR4300_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wan", + .gpio = WNDR4300_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:usb", + .gpio = WNDR4300_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "netgear:green:wps", + .gpio = WNDR4300_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wps", + .gpio = WNDR4300_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wlan2g", + .gpio = WNDR4300_GPIO_LED_WLAN2G, + .active_low = 1, + }, + { + .name = "netgear:blue:wlan5g", + .gpio = WNDR4300_GPIO_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wndr4300_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR4300_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR4300_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Wireless button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR4300_GPIO_BTN_WIRELESS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wndr4300_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wndr4300_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data wndr4300_ar8327_data = { + .pad0_cfg = &wndr4300_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wndr4300_ar8327_led_cfg, +}; + +static struct mdio_board_info wndr4300_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wndr4300_ar8327_data, + }, +}; + +static void __init wndr4300_setup(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(wndr4300_leds_gpio); i++) + ath79_gpio_output_select(wndr4300_leds_gpio[i].gpio, + AR934X_GPIO_OUT_GPIO); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio), + wndr4300_leds_gpio); + ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndr4300_gpio_keys), + wndr4300_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(wndr4300_mdio0_info, + ARRAY_SIZE(wndr4300_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); + ath79_register_nfc(); + ath79_register_usb(); + + ath79_register_wmac_simple(); + + /* enable power for the USB port */ + ap9x_pci_setup_wmac_gpio(0, BIT(WNDR4300_GPIO_USB_5V), + BIT(WNDR4300_GPIO_USB_5V)); + + ap91_pci_init_simple(); +} + +MIPS_MACHINE(ATH79_MACH_WNDR3700_V4, "WNDR3700_V4", "NETGEAR WNDR3700v4", + wndr4300_setup); +MIPS_MACHINE(ATH79_MACH_WNDR4300, "WNDR4300", "NETGEAR WNDR4300", + wndr4300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v3.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v3.c new file mode 100644 index 0000000..2e14782 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v3.c @@ -0,0 +1,140 @@ +/* + * NETGEAR WNR2000v3/WNR612v2/WNR1000v2 board support + * + * Copytight (C) 2013 Mathieu Olivari + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Andy Boyett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WNR2000V3_GPIO_LED_WAN_GREEN 0 +#define WNR2000V3_GPIO_LED_LAN1_AMBER 1 +#define WNR2000V3_GPIO_LED_LAN4_AMBER 12 +#define WNR2000V3_GPIO_LED_PWR_GREEN 14 +#define WNR2000V3_GPIO_BTN_WPS 11 + +#define WNR612V2_GPIO_LED_PWR_GREEN 11 + +#define WNR1000V2_GPIO_LED_PWR_AMBER 1 +#define WNR1000V2_GPIO_LED_PWR_GREEN 11 + +#define WNR2000V3_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000V3_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000V3_KEYS_POLL_INTERVAL) + +#define WNR2000V3_MAC0_OFFSET 0 +#define WNR2000V3_MAC1_OFFSET 6 +#define WNR2000V3_PCIE_CALDATA_OFFSET 0x1000 + +static struct gpio_led wnr2000v3_leds_gpio[] __initdata = { + { + .name = "wnr2000v3:green:power", + .gpio = WNR2000V3_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "wnr2000v3:green:wan", + .gpio = WNR2000V3_GPIO_LED_WAN_GREEN, + .active_low = 1, + } +}; + +static struct gpio_led wnr612v2_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR612V2_GPIO_LED_PWR_GREEN, + .active_low = 1, + } +}; + +static struct gpio_led wnr1000v2_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR1000V2_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "netgear:amber:power", + .gpio = WNR1000V2_GPIO_LED_PWR_AMBER, + .active_low = 1, + } +}; + +static struct gpio_keys_button wnr2000v3_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000V3_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V3_GPIO_BTN_WPS, + } +}; + +static void __init wnr_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V3_MAC0_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V3_MAC1_OFFSET, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + ap91_pci_init(art + WNR2000V3_PCIE_CALDATA_OFFSET, NULL); +} + +static void __init wnr2000v3_setup(void) +{ + wnr_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v3_leds_gpio), + wnr2000v3_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000V3_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000v3_gpio_keys), + wnr2000v3_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000_V3, "WNR2000V3", "NETGEAR WNR2000 V3", wnr2000v3_setup); + +static void __init wnr612v2_setup(void) +{ + wnr_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr612v2_leds_gpio), + wnr612v2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_WNR612_V2, "WNR612V2", "NETGEAR WNR612 V2", wnr612v2_setup); + +static void __init wnr1000v2_setup(void) +{ + wnr_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr1000v2_leds_gpio), + wnr1000v2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_WNR1000_V2, "WNR1000V2", "NETGEAR WNR1000 V2", wnr1000v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c new file mode 100644 index 0000000..c5159a3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c @@ -0,0 +1,214 @@ +/* + * NETGEAR WNR2000v4 board support + * + * Copyright (C) 2015 Michael Bazzinotti + * Copyright (C) 2014 Michaël Burtin + * Copyright (C) 2013 Mathieu Olivari + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Andy Boyett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* AR9341 GPIOs */ +#define WNR2000V4_GPIO_LED_PWR_GREEN 0 +#define WNR2000V4_GPIO_LED_PWR_AMBER 1 +#define WNR2000V4_GPIO_LED_WPS 2 +#define WNR2000V4_GPIO_LED_WLAN 12 +#define WNR2000V4_GPIO_LED_LAN1_GREEN 13 +#define WNR2000V4_GPIO_LED_LAN2_GREEN 14 +#define WNR2000V4_GPIO_LED_LAN3_GREEN 15 +#define WNR2000V4_GPIO_LED_LAN4_GREEN 16 +#define WNR2000V4_GPIO_LED_LAN1_AMBER 18 +#define WNR2000V4_GPIO_LED_LAN2_AMBER 19 +#define WNR2000V4_GPIO_LED_LAN3_AMBER 20 +#define WNR2000V4_GPIO_LED_LAN4_AMBER 21 +#define WNR2000V4_GPIO_LED_WAN_GREEN 17 +#define WNR2000V4_GPIO_LED_WAN_AMBER 22 +/* Buttons */ +#define WNR2000V4_GPIO_BTN_WPS 3 +#define WNR2000V4_GPIO_BTN_RESET 4 +#define WNR2000V4_GPIO_BTN_WLAN 11 +#define WNR2000V4_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000V4_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000V4_KEYS_POLL_INTERVAL) + + +/* ART offsets */ +#define WNR2000V4_MAC0_OFFSET 0 /* WAN/WLAN0 MAC */ +#define WNR2000V4_MAC1_OFFSET 6 /* Eth-switch0 MAC */ + +static struct gpio_led wnr2000v4_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR2000V4_GPIO_LED_PWR_GREEN, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "netgear:amber:status", + .gpio = WNR2000V4_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wan", + .gpio = WNR2000V4_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wan", + .gpio = WNR2000V4_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, + { + .name = "netgear:blue:wlan", + .gpio = WNR2000V4_GPIO_LED_WLAN, + .active_low = 1, + }, + /* LAN LEDS */ + { + .name = "netgear:green:lan1", + .gpio = WNR2000V4_GPIO_LED_LAN1_GREEN, + .active_low = 1, + }, + { + .name = "netgear:green:lan2", + .gpio = WNR2000V4_GPIO_LED_LAN2_GREEN, + .active_low = 1, + }, + { + .name = "netgear:green:lan3", + .gpio = WNR2000V4_GPIO_LED_LAN3_GREEN, + .active_low = 1, + }, + { + .name = "netgear:green:lan4", + .gpio = WNR2000V4_GPIO_LED_LAN4_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:lan1", + .gpio = WNR2000V4_GPIO_LED_LAN1_AMBER, + .active_low = 1, + }, + { + .name = "netgear:amber:lan2", + .gpio = WNR2000V4_GPIO_LED_LAN2_AMBER, + .active_low = 1, + }, + { + .name = "netgear:amber:lan3", + .gpio = WNR2000V4_GPIO_LED_LAN3_AMBER, + .active_low = 1, + }, + { + .name = "netgear:amber:lan4", + .gpio = WNR2000V4_GPIO_LED_LAN4_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wps", + .gpio = WNR2000V4_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wnr2000v4_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V4_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V4_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WLAN button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V4_GPIO_BTN_WLAN, + .active_low = 1, + }, +}; + +static void __init wnr_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(1, 0x0); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch, GE0 */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch, GE1 */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, art); +} + +static void __init wnr2000v4_setup(void) +{ + int i; + + wnr_common_setup(); + + /* Ensure no LED has an internal MUX signal, otherwise + control of LED could be lost... This is especially important + for most green LEDS (Eth,WAN).. who arrive in this function with + MUX signals set. */ + for (i = 0; i < ARRAY_SIZE(wnr2000v4_leds_gpio); i++) + ath79_gpio_output_select(wnr2000v4_leds_gpio[i].gpio, + AR934X_GPIO_OUT_GPIO); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v4_leds_gpio), + wnr2000v4_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000V4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000v4_gpio_keys), + wnr2000v4_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000_V4, "WNR2000V4", "NETGEAR WNR2000 V4", wnr2000v4_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c new file mode 100644 index 0000000..b4da7ec --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c @@ -0,0 +1,145 @@ +/* + * NETGEAR WNR2000 board support + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Andy Boyett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WNR2000_GPIO_LED_PWR_GREEN 14 +#define WNR2000_GPIO_LED_PWR_AMBER 7 +#define WNR2000_GPIO_LED_WPS 4 +#define WNR2000_GPIO_LED_WLAN 6 +#define WNR2000_GPIO_BTN_RESET 21 +#define WNR2000_GPIO_BTN_WPS 8 + +#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL) + +static struct mtd_partition wnr2000_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x040000, + .size = 0x010000, + }, { + .name = "rootfs", + .offset = 0x050000, + .size = 0x240000, + }, { + .name = "user-config", + .offset = 0x290000, + .size = 0x010000, + }, { + .name = "uImage", + .offset = 0x2a0000, + .size = 0x120000, + }, { + .name = "language_table", + .offset = 0x3c0000, + .size = 0x020000, + }, { + .name = "rootfs_checksum", + .offset = 0x3e0000, + .size = 0x010000, + }, { + .name = "art", + .offset = 0x3f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wnr2000_flash_data = { + .parts = wnr2000_partitions, + .nr_parts = ARRAY_SIZE(wnr2000_partitions), +}; + +static struct gpio_led wnr2000_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR2000_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "netgear:amber:power", + .gpio = WNR2000_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:wps", + .gpio = WNR2000_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "netgear:blue:wlan", + .gpio = WNR2000_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000_GPIO_BTN_WPS, + } +}; + +static void __init wnr2000_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wnr2000_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), + wnr2000_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000_gpio_keys), + wnr2000_gpio_keys); + + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2200.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2200.c new file mode 100644 index 0000000..bf7f9ee --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2200.c @@ -0,0 +1,137 @@ +/* + * NETGEAR WNR2200 board support + * + * Copyright (C) 2013 Aidan Kissane + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WNR2200_GPIO_LED_LAN2_AMBER 0 +#define WNR2200_GPIO_LED_LAN4_AMBER 1 +#define WNR2200_GPIO_LED_WPS 5 +#define WNR2200_GPIO_LED_WAN_GREEN 7 +#define WNR2200_GPIO_LED_USB 8 +#define WNR2200_GPIO_LED_LAN3_AMBER 11 +#define WNR2200_GPIO_LED_WAN_AMBER 12 +#define WNR2200_GPIO_LED_LAN1_GREEN 13 +#define WNR2200_GPIO_LED_LAN2_GREEN 14 +#define WNR2200_GPIO_LED_LAN3_GREEN 15 +#define WNR2200_GPIO_LED_LAN4_GREEN 16 +#define WNR2200_GPIO_LED_PWR_AMBER 21 +#define WNR2200_GPIO_LED_PWR_GREEN 22 + +#define WNR2200_GPIO_USB_POWER 24 + +#define WNR2200_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2200_KEYS_DEBOUNCE_INTERVAL (3 * WNR2200_KEYS_POLL_INTERVAL) + +#define WNR2200_MAC0_OFFSET 0 +#define WNR2200_MAC1_OFFSET 6 +#define WNR2200_PCIE_CALDATA_OFFSET 0x1000 + +static struct gpio_led wnr2200_leds_gpio[] __initdata = { + { + .name = "netgear:amber:lan2", + .gpio = WNR2200_GPIO_LED_LAN2_AMBER, + .active_low = 1, + }, { + .name = "netgear:amber:lan4", + .gpio = WNR2200_GPIO_LED_LAN4_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:wps", + .gpio = WNR2200_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "netgear:green:wan", + .gpio = WNR2200_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:usb", + .gpio = WNR2200_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "netgear:amber:lan3", + .gpio = WNR2200_GPIO_LED_LAN3_AMBER, + .active_low = 1, + }, { + .name = "netgear:amber:wan", + .gpio = WNR2200_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:lan1", + .gpio = WNR2200_GPIO_LED_LAN1_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:lan2", + .gpio = WNR2200_GPIO_LED_LAN2_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:lan3", + .gpio = WNR2200_GPIO_LED_LAN3_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:lan4", + .gpio = WNR2200_GPIO_LED_LAN4_GREEN, + .active_low = 1, + }, { + .name = "netgear:amber:power", + .gpio = WNR2200_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:power", + .gpio = WNR2200_GPIO_LED_PWR_GREEN, + .active_low = 1, + } +}; + +static void __init wnr2200_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2200_MAC0_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2200_MAC1_OFFSET, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + ap91_pci_init(art + WNR2200_PCIE_CALDATA_OFFSET, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2200_leds_gpio), + wnr2200_leds_gpio); + + /* enable power for the USB port */ + gpio_request_one(WNR2200_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_WNR2200, "WNR2200", "NETGEAR WNR2200", wnr2200_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c new file mode 100644 index 0000000..dc4aee0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c @@ -0,0 +1,109 @@ +/* + * Compex WP543/WPJ543 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define WP543_GPIO_SW6 2 +#define WP543_GPIO_LED_1 3 +#define WP543_GPIO_LED_2 4 +#define WP543_GPIO_LED_WLAN 5 +#define WP543_GPIO_LED_CONN 6 +#define WP543_GPIO_LED_DIAG 7 +#define WP543_GPIO_SW4 8 + +#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL) + +static struct gpio_led wp543_leds_gpio[] __initdata = { + { + .name = "wp543:green:led1", + .gpio = WP543_GPIO_LED_1, + .active_low = 1, + }, { + .name = "wp543:green:led2", + .gpio = WP543_GPIO_LED_2, + .active_low = 1, + }, { + .name = "wp543:green:wlan", + .gpio = WP543_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "wp543:green:conn", + .gpio = WP543_GPIO_LED_CONN, + .active_low = 1, + }, { + .name = "wp543:green:diag", + .gpio = WP543_GPIO_LED_DIAG, + .active_low = 1, + } +}; + +static struct gpio_keys_button wp543_gpio_keys[] __initdata = { + { + .desc = "sw6", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, + .gpio = WP543_GPIO_SW6, + .active_low = 1, + }, { + .desc = "sw4", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, + .gpio = WP543_GPIO_SW4, + .active_low = 1, + } +}; + +static const char *wp543_part_probes[] = { + "MyLoader", + NULL, +}; + +static struct flash_platform_data wp543_flash_data = { + .part_probes = wp543_part_probes, +}; + +static void __init wp543_setup(void) +{ + ath79_register_m25p80(&wp543_flash_data); + + ath79_register_mdio(0, 0xfffffff0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x0f; + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC | + AR71XX_RESET_GE0_PHY; + ath79_register_eth(0); + + ath79_register_usb(); + ath79_register_pci(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), + wp543_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wp543_gpio_keys), + wp543_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WP543, "WP543", "Compex WP543", wp543_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c new file mode 100644 index 0000000..9452484 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c @@ -0,0 +1,97 @@ +/* + * Compex WPE72 board support + * + * Copyright (C) 2012 Johnathan Boyce + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define WPE72_GPIO_RESET 12 +#define WPE72_GPIO_LED_DIAG 13 +#define WPE72_GPIO_LED_1 14 +#define WPE72_GPIO_LED_2 15 +#define WPE72_GPIO_LED_3 16 +#define WPE72_GPIO_LED_4 17 + +#define WPE72_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPE72_KEYS_DEBOUNCE_INTERVAL (3 * WPE72_KEYS_POLL_INTERVAL) + +static struct gpio_led wpe72_leds_gpio[] __initdata = { + { + .name = "wpe72:green:led1", + .gpio = WPE72_GPIO_LED_1, + .active_low = 1, + }, { + .name = "wpe72:green:led2", + .gpio = WPE72_GPIO_LED_2, + .active_low = 1, + }, { + .name = "wpe72:green:led3", + .gpio = WPE72_GPIO_LED_3, + .active_low = 1, + }, { + .name = "wpe72:green:led4", + .gpio = WPE72_GPIO_LED_4, + .active_low = 1, + }, { + .name = "wpe72:green:diag", + .gpio = WPE72_GPIO_LED_DIAG, + .active_low = 1, + } +}; + +static struct gpio_keys_button wpe72_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPE72_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPE72_GPIO_RESET, + .active_low = 1, + } +}; + +static const char *wpe72_part_probes[] = { + "MyLoader", + NULL, +}; + +static struct flash_platform_data wpe72_flash_data = { + .part_probes = wpe72_part_probes, +}; + +static void __init wpe72_setup(void) +{ + ath79_register_m25p80(&wpe72_flash_data); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_pci(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpe72_leds_gpio), + wpe72_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WPE72_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpe72_gpio_keys), + wpe72_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WPE72, "WPE72", "Compex WPE72", wpe72_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c new file mode 100644 index 0000000..3ca94dc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c @@ -0,0 +1,175 @@ +/* + * Compex WPJ344 board support + * + * Copyright (c) 2011 Qualcomm Atheros + * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-usb.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WPJ344_GPIO_LED_SIG1 15 +#define WPJ344_GPIO_LED_SIG2 20 +#define WPJ344_GPIO_LED_SIG3 21 +#define WPJ344_GPIO_LED_SIG4 22 +#define WPJ344_GPIO_LED_STATUS 14 + +#define WPJ344_GPIO_BTN_RESET 12 + +#define WPJ344_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPJ344_KEYS_DEBOUNCE_INTERVAL (3 * WPJ344_KEYS_POLL_INTERVAL) + +#define WPJ344_MAC0_OFFSET 0 +#define WPJ344_MAC1_OFFSET 6 +#define WPJ344_WMAC_CALDATA_OFFSET 0x1000 +#define WPJ344_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led wpj344_leds_gpio[] __initdata = { + { + .name = "wpj344:green:status", + .gpio = WPJ344_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "wpj344:red:sig1", + .gpio = WPJ344_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "wpj344:yellow:sig2", + .gpio = WPJ344_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "wpj344:green:sig3", + .gpio = WPJ344_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "wpj344:green:sig4", + .gpio = WPJ344_GPIO_LED_SIG4, + .active_low = 1, + } +}; + +static struct gpio_keys_button wpj344_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPJ344_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPJ344_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wpj344_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wpj344_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data wpj344_ar8327_data = { + .pad0_cfg = &wpj344_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wpj344_ar8327_led_cfg, +}; + +static struct mdio_board_info wpj344_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wpj344_ar8327_data, + }, +}; + +static void __init wpj344_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio), + wpj344_leds_gpio); + ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpj344_gpio_keys), + wpj344_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + + mdiobus_register_board_info(wpj344_mdio0_info, + ARRAY_SIZE(wpj344_mdio0_info)); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_WPJ344, "WPJ344", "Compex WPJ344", wpj344_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c new file mode 100644 index 0000000..8a238da --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c @@ -0,0 +1,143 @@ +/* + * Compex WPJ531 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "pci.h" +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WPJ531_GPIO_LED_SIG1 14 +#define WPJ531_GPIO_LED_SIG2 15 +#define WPJ531_GPIO_LED_SIG3 22 +#define WPJ531_GPIO_LED_SIG4 23 +#define WPJ531_GPIO_BUZZER 4 + +#define WPJ531_GPIO_BTN_RESET 17 + +#define WPJ531_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPJ531_KEYS_DEBOUNCE_INTERVAL (3 * WPJ531_KEYS_POLL_INTERVAL) + +#define WPJ531_MAC0_OFFSET 0x10 +#define WPJ531_MAC1_OFFSET 0x18 +#define WPJ531_WMAC_CALDATA_OFFSET 0x1000 +#define WPJ531_PCIE_CALDATA_OFFSET 0x5000 + +#define WPJ531_ART_SIZE 0x8000 + +static struct gpio_led wpj531_leds_gpio[] __initdata = { + { + .name = "wpj531:red:sig1", + .gpio = WPJ531_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "wpj531:yellow:sig2", + .gpio = WPJ531_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "wpj531:green:sig3", + .gpio = WPJ531_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "wpj531:green:sig4", + .gpio = WPJ531_GPIO_LED_SIG4, + .active_low = 1, + }, + { + .name = "wpj531:buzzer", + .gpio = WPJ531_GPIO_BUZZER, + .active_low = 0, + } +}; + +static struct gpio_keys_button wpj531_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPJ531_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPJ531_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000); + + ath79_register_m25p80(NULL); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* LAN */ + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ531_MAC0_OFFSET, 0); + ath79_register_eth(0); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ531_MAC1_OFFSET, 0); + ath79_register_eth(1); + + ath79_register_wmac(art + WPJ531_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + ath79_register_usb(); +} + +static void __init wpj531_setup(void) +{ + common_setup(); + + ath79_register_leds_gpio(-1, + ARRAY_SIZE(wpj531_leds_gpio), + wpj531_leds_gpio); + + ath79_register_gpio_keys_polled(-1, + WPJ531_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpj531_gpio_keys), + wpj531_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WPJ531, "WPJ531", "Compex WPJ531", wpj531_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c new file mode 100644 index 0000000..c7b120d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c @@ -0,0 +1,177 @@ +/* + * Compex WPJ558 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-usb.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WPJ558_GPIO_LED_SIG1 14 +#define WPJ558_GPIO_LED_SIG2 15 +#define WPJ558_GPIO_LED_SIG3 22 +#define WPJ558_GPIO_LED_SIG4 23 +#define WPJ558_GPIO_BUZZER 4 + +#define WPJ558_GPIO_BTN_RESET 17 + +#define WPJ558_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPJ558_KEYS_DEBOUNCE_INTERVAL (3 * WPJ558_KEYS_POLL_INTERVAL) + +#define WPJ558_MAC_OFFSET 0x1002 +#define WPJ558_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led wpj558_leds_gpio[] __initdata = { + { + .name = "wpj558:red:sig1", + .gpio = WPJ558_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "wpj558:yellow:sig2", + .gpio = WPJ558_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "wpj558:green:sig3", + .gpio = WPJ558_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "wpj558:green:sig4", + .gpio = WPJ558_GPIO_LED_SIG4, + .active_low = 1, + }, + { + .name = "wpj558:buzzer", + .gpio = WPJ558_GPIO_BUZZER, + .active_low = 0, + } +}; + +static struct gpio_keys_button wpj558_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPJ558_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPJ558_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wpj558_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_pad_cfg wpj558_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data wpj558_ar8327_data = { + .pad0_cfg = &wpj558_ar8327_pad0_cfg, + .pad6_cfg = &wpj558_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info wpj558_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wpj558_ar8327_data, + }, +}; + +static void __init wpj558_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj558_leds_gpio), + wpj558_leds_gpio); + ath79_register_gpio_keys_polled(-1, WPJ558_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpj558_gpio_keys), + wpj558_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + WPJ558_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + + mdiobus_register_board_info(wpj558_mdio0_info, + ARRAY_SIZE(wpj558_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_register_eth(0); + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_WPJ558, "WPJ558", "Compex WPJ558", wpj558_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c new file mode 100644 index 0000000..ede3c21 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c @@ -0,0 +1,126 @@ +/* + * Linksys WRT160NL board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "nvram.h" +#include "machtypes.h" + +#define WRT160NL_GPIO_LED_POWER 14 +#define WRT160NL_GPIO_LED_WPS_AMBER 9 +#define WRT160NL_GPIO_LED_WPS_BLUE 8 +#define WRT160NL_GPIO_LED_WLAN 6 + +#define WRT160NL_GPIO_BTN_WPS 7 +#define WRT160NL_GPIO_BTN_RESET 21 + +#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL) + +#define WRT160NL_NVRAM_ADDR 0x1f7e0000 +#define WRT160NL_NVRAM_SIZE 0x10000 + +static const char *wrt160nl_part_probes[] = { + "cybertan", + NULL, +}; + +static struct flash_platform_data wrt160nl_flash_data = { + .part_probes = wrt160nl_part_probes, +}; + +static struct gpio_led wrt160nl_leds_gpio[] __initdata = { + { + .name = "wrt160nl:blue:power", + .gpio = WRT160NL_GPIO_LED_POWER, + .active_low = 1, + .default_trigger = "default-on", + }, { + .name = "wrt160nl:amber:wps", + .gpio = WRT160NL_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, { + .name = "wrt160nl:blue:wps", + .gpio = WRT160NL_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, { + .name = "wrt160nl:blue:wlan", + .gpio = WRT160NL_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRT160NL_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRT160NL_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init wrt160nl_setup(void) +{ + const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, + "lan_hwaddr=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + } + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = 0x01; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wrt160nl_flash_data); + + ath79_register_usb(); + + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, + "wl0_hwaddr=", mac) == 0) + ath79_register_wmac(eeprom, mac); + else + ath79_register_wmac(eeprom, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), + wrt160nl_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrt160nl_gpio_keys), + wrt160nl_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", + wrt160nl_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c new file mode 100644 index 0000000..6c4c1cb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c @@ -0,0 +1,161 @@ +/* + * Linksys WRT400N board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2009 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WRT400N_GPIO_LED_POWER 1 +#define WRT400N_GPIO_LED_WPS_BLUE 4 +#define WRT400N_GPIO_LED_WPS_AMBER 5 +#define WRT400N_GPIO_LED_WLAN 6 + +#define WRT400N_GPIO_BTN_RESET 8 +#define WRT400N_GPIO_BTN_WLSEC 3 + +#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) + +#define WRT400N_MAC_ADDR_OFFSET 0x120c +#define WRT400N_CALDATA0_OFFSET 0x1000 +#define WRT400N_CALDATA1_OFFSET 0x5000 + +static struct mtd_partition wrt400n_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = 0x030000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "env", + .offset = 0x030000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "linux", + .offset = 0x040000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x180000, + .size = 0x630000, + }, { + .name = "nvram", + .offset = 0x7b0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "factory", + .offset = 0x7c0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "language", + .offset = 0x7d0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "caldata", + .offset = 0x7f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x040000, + .size = 0x770000, + } +}; + +static struct flash_platform_data wrt400n_flash_data = { + .parts = wrt400n_partitions, + .nr_parts = ARRAY_SIZE(wrt400n_partitions), +}; + +static struct gpio_led wrt400n_leds_gpio[] __initdata = { + { + .name = "wrt400n:blue:wps", + .gpio = WRT400N_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, { + .name = "wrt400n:amber:wps", + .gpio = WRT400N_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, { + .name = "wrt400n:blue:wlan", + .gpio = WRT400N_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "wrt400n:blue:power", + .gpio = WRT400N_GPIO_LED_POWER, + .active_low = 0, + .default_trigger = "default-on", + } +}; + +static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, + .gpio = WRT400N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wlsec", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, + .gpio = WRT400N_GPIO_BTN_WLSEC, + .active_low = 1, + } +}; + +static void __init wrt400n_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wrt400n_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), + wrt400n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrt400n_gpio_keys), + wrt400n_gpio_keys); + + ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, + art + WRT400N_CALDATA1_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c new file mode 100644 index 0000000..428876f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c @@ -0,0 +1,221 @@ +/* + * Buffalo WZR-450HP2 board support + * + * Copyright (c) 2013 Gabor Juhos + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WZR_450HP2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZR_450HP2_KEYS_DEBOUNCE_INTERVAL (3 * WZR_450HP2_KEYS_POLL_INTERVAL) + +#define WZR_450HP2_WMAC_CALDATA_OFFSET 0x1000 + +static struct mtd_partition wzrhpg450h_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + }, { + .name = "ART", + .offset = 0x0ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0050000, + .size = 0x0f90000, + }, { + .name = "user_property", + .offset = 0x0fe0000, + .size = 0x0010000, + } +}; + +static struct flash_platform_data wzr_450hp2_flash_data = { + .parts = wzrhpg450h_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions), +}; + +static struct gpio_led wzr_450hp2_leds_gpio[] __initdata = { + { + .name = "buffalo:green:wps", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:green:system", + .gpio = 20, + .active_low = 1, + }, + { + .name = "buffalo:green:wlan", + .gpio = 18, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzr_450hp2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 17, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 21, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info wzr_450hp2_leds_ar8327[] = { + AR8327_LED_INFO(PHY0_0, HW, "buffalo:green:lan1"), + AR8327_LED_INFO(PHY1_0, HW, "buffalo:green:lan2"), + AR8327_LED_INFO(PHY2_0, HW, "buffalo:green:lan3"), + AR8327_LED_INFO(PHY3_0, HW, "buffalo:green:lan4"), + AR8327_LED_INFO(PHY4_0, HW, "buffalo:green:wan"), +}; + +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ +static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ +static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wzr_450hp2_ar8327_led_cfg = { + .led_ctrl0 = 0xcc35cc35, + .led_ctrl1 = 0xca35ca35, + .led_ctrl2 = 0xc935c935, + .led_ctrl3 = 0x03ffff00, + .open_drain = true, +}; + +static struct ar8327_platform_data wzr_450hp2_ar8327_data = { + .pad0_cfg = &wzr_450hp2_ar8327_pad0_cfg, + .pad6_cfg = &wzr_450hp2_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wzr_450hp2_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(wzr_450hp2_leds_ar8327), + .leds = wzr_450hp2_leds_ar8327, +}; + +static struct mdio_board_info wzr_450hp2_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wzr_450hp2_ar8327_data, + }, +}; + +static void __init wzr_450hp2_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac_wan = art; + u8 *mac_lan = mac_wan + ETH_ALEN; + + ath79_register_m25p80(&wzr_450hp2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzr_450hp2_leds_gpio), + wzr_450hp2_leds_gpio); + ath79_register_gpio_keys_polled(-1, WZR_450HP2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzr_450hp2_gpio_keys), + wzr_450hp2_gpio_keys); + + ath79_register_wmac(art + WZR_450HP2_WMAC_CALDATA_OFFSET, mac_lan); + + mdiobus_register_board_info(wzr_450hp2_mdio0_info, + ARRAY_SIZE(wzr_450hp2_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac_wan, 0); + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac_lan, 0); + ath79_register_eth(1); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_WZR_450HP2, "WZR-450HP2", + "Buffalo WZR-450HP2", wzr_450hp2_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c new file mode 100644 index 0000000..edd48f2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c @@ -0,0 +1,205 @@ +/* + * Buffalo WZR-HP-AG300H board support + * + * Copyright (C) 2011 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPAG300H_MAC_OFFSET 0x20c +#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpag300h_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f90000, + }, { + .name = "user_property", + .offset = 0x1ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wzrhpag300h_flash_data = { + .parts = wzrhpag300h_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpag300h_flash_partitions), +}; + +static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 1, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpag300h_wmac0_leds_gpio[] = { + { + .name = "buffalo:amber:band2g", + .gpio = 1, + .active_low = 1, + }, + { + .name = "buffalo:green:usb", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:green:band2g", + .gpio = 5, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpag300h_wmac1_leds_gpio[] = { + { + .name = "buffalo:green:band5g", + .gpio = 1, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine", + .gpio = 4, + .active_low = 1, + }, + { + .name = "buffalo:amber:band5g", + .gpio = 5, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 3, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 5, + .active_low = 1, + }, { + .desc = "router_auto", + .type = EV_SW, + .code = BTN_6, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 6, + .active_low = 1, + }, { + .desc = "router_off", + .type = EV_SW, + .code = BTN_5, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 1, + }, { + .desc = "movie_engine", + .type = EV_SW, + .code = BTN_7, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 1, + } +}; + +static void __init wzrhpag300h_setup(void) +{ + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000); + u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000); + u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET; + u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1); + + ath79_register_mdio(0, ~(BIT(0) | BIT(4))); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio), + wzrhpag300h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpag300h_gpio_keys), + wzrhpag300h_gpio_keys); + + ath79_register_m25p80_multi(&wzrhpag300h_flash_data); + + ap94_pci_init(eeprom1, mac1, eeprom2, mac2); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio, + ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio)); + ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio, + ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio)); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_AG300H, "WZR-HP-AG300H", + "Buffalo WZR-HP-AG300H/WZR-600DHP", wzrhpag300h_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c new file mode 100644 index 0000000..0a3eba9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c @@ -0,0 +1,279 @@ +/* + * Buffalo WZR-HP-G300NH board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WZRHPG300NH_GPIO_LED_USB 0 +#define WZRHPG300NH_GPIO_LED_DIAG 1 +#define WZRHPG300NH_GPIO_LED_WIRELESS 6 +#define WZRHPG300NH_GPIO_LED_SECURITY 17 +#define WZRHPG300NH_GPIO_LED_ROUTER 18 + +#define WZRHPG300NH_GPIO_RTL8366_SDA 19 +#define WZRHPG300NH_GPIO_RTL8366_SCK 20 + +#define WZRHPG300NH_GPIO_74HC153_S0 9 +#define WZRHPG300NH_GPIO_74HC153_S1 11 +#define WZRHPG300NH_GPIO_74HC153_1Y 12 +#define WZRHPG300NH_GPIO_74HC153_2Y 14 + +#define WZRHPG300NH_GPIO_EXP_BASE 32 +#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) +#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) +#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) +#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) +#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) +#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) +#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) + +#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL) + +#define WZRHPG300NH_MAC_OFFSET 0x20c + +static struct mtd_partition wzrhpg300nh_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f60000, + }, { + .name = "user_property", + .offset = 0x1fc0000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x1fe0000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data wzrhpg300nh_flash_data = { + .width = 2, + .parts = wzrhpg300nh_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), +}; + +#define WZRHPG300NH_FLASH_BASE 0x1e000000 +#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) + +static struct resource wzrhpg300nh_flash_resources[] = { + [0] = { + .start = WZRHPG300NH_FLASH_BASE, + .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device wzrhpg300nh_flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = wzrhpg300nh_flash_resources, + .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), + .dev = { + .platform_data = &wzrhpg300nh_flash_data, + } +}; + +static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { + { + .name = "buffalo:orange:security", + .gpio = WZRHPG300NH_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "buffalo:green:wireless", + .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, + .active_low = 1, + }, { + .name = "buffalo:green:router", + .gpio = WZRHPG300NH_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "buffalo:red:diag", + .gpio = WZRHPG300NH_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "buffalo:blue:usb", + .gpio = WZRHPG300NH_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_AOSS, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_USB, + .active_low = 1, + }, { + .desc = "qos_on", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, + .active_low = 0, + }, { + .desc = "qos_off", + .type = EV_KEY, + .code = BTN_4, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, + .active_low = 0, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, + .active_low = 0, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, + .active_low = 0, + } +}; + +static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { + .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, + .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, + .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, + .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, + .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, +}; + +static struct platform_device wzrhpg300nh_74hc153_device = { + .name = NXP_74HC153_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_74hc153_data, + } +}; + +static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = { + .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, + .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, +}; + +static struct platform_device wzrhpg300nh_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_rtl8366_data, + } +}; + +static struct platform_device wzrhpg300nh_rtl8366rb_device = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_rtl8366_data, + } +}; + +static void __init wzrhpg300nh_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET; + bool hasrtl8366rb = false; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB) + hasrtl8366rb = true; + + if (hasrtl8366rb) { + ath79_eth0_pll_data.pll_1000 = 0x1f000000; + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; + ath79_eth1_pll_data.pll_1000 = 0x100; + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; + } else { + ath79_eth0_pll_data.pll_1000 = 0x1e000100; + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; + ath79_eth1_pll_data.pll_1000 = 0x1e000100; + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; + } + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_wmac(eeprom, NULL); + + platform_device_register(&wzrhpg300nh_74hc153_device); + platform_device_register(&wzrhpg300nh_flash_device); + + if (hasrtl8366rb) + platform_device_register(&wzrhpg300nh_rtl8366rb_device); + else + platform_device_register(&wzrhpg300nh_rtl8366s_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), + wzrhpg300nh_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg300nh_gpio_keys), + wzrhpg300nh_gpio_keys); + +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", + "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c new file mode 100644 index 0000000..733d996 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c @@ -0,0 +1,170 @@ +/* + * Buffalo WZR-HP-G300NH2 board support + * + * Copyright (C) 2011 Felix Fietkau + * Copyright (C) 2011 Mark Deneen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPG300NH2_MAC_OFFSET 0x20c +#define WZRHPG300NH2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH2_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpg300nh2_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f90000, + }, { + .name = "user_property", + .offset = 0x1ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wzrhpg300nh2_flash_data = { + .parts = wzrhpg300nh2_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg300nh2_flash_partitions), +}; + +static struct gpio_led wzrhpg300nh2_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 16, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpg300nh2_wmac_leds_gpio[] = { + { + .name = "buffalo:blue:usb", + .gpio = 4, + .active_low = 1, + }, + { + .name = "buffalo:orange:security", + .gpio = 6, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 7, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine_on", + .gpio = 8, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine_off", + .gpio = 9, + .active_low = 1, + }, +}; + +/* The AOSS button is wmac gpio 12 */ +static struct gpio_keys_button wzrhpg300nh2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 1, + }, { + .desc = "qos", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 0, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 0, + }, +}; + +static void __init wzrhpg300nh2_setup(void) +{ + + u8 *eeprom = (u8 *) KSEG1ADDR(0x1f051000); + u8 *mac0 = eeprom + WZRHPG300NH2_MAC_OFFSET; + /* There is an eth1 but it is not connected to the switch */ + + ath79_register_m25p80_multi(&wzrhpg300nh2_flash_data); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_register_mdio(0, ~(BIT(0))); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + /* gpio13 is usb power. Turn it on. */ + gpio_request_one(13, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh2_leds_gpio), + wzrhpg300nh2_leds_gpio); + ath79_register_gpio_keys_polled(-1, WZRHPG300NH2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg300nh2_gpio_keys), + wzrhpg300nh2_gpio_keys); + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_leds(0, wzrhpg300nh2_wmac_leds_gpio, + ARRAY_SIZE(wzrhpg300nh2_wmac_leds_gpio)); + + ap91_pci_init(eeprom, mac0); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH2, "WZR-HP-G300NH2", + "Buffalo WZR-HP-G300NH2", wzrhpg300nh2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c new file mode 100644 index 0000000..a559d73 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c @@ -0,0 +1,165 @@ +/* + * Buffalo WZR-HP-G450G board support + * + * Copyright (C) 2011 Felix Fietkau + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPG450H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG450H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG450H_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpg450h_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + }, { + .name = "ART", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f80000, + }, { + .name = "user_property", + .offset = 0x1fe0000, + .size = 0x0020000, + } +}; + +static struct flash_platform_data wzrhpg450h_flash_data = { + .parts = wzrhpg450h_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions), +}; + +static struct gpio_led wzrhpg450h_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 14, + .active_low = 1, + }, + { + .name = "buffalo:orange:security", + .gpio = 13, + .active_low = 1, + }, +}; + + +static struct gpio_led wzrhpg450h_wmac_leds_gpio[] = { + { + .name = "buffalo:blue:movie_engine", + .gpio = 13, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 14, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzrhpg450h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 6, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 1, + }, { + .desc = "movie_engine", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 0, + }, { + .desc = "router_off", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 0, + } +}; + + +static void __init wzrhpg450h_init(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1f051000); + u8 *mac = (u8 *) ee + 2; + + ath79_register_m25p80_multi(&wzrhpg450h_flash_data); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg450h_leds_gpio), + wzrhpg450h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPG450H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg450h_gpio_keys), + wzrhpg450h_gpio_keys); + + ath79_register_eth(0); + + gpio_request_one(16, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ap91_pci_init(ee, NULL); + ap9x_pci_get_wmac_data(0)->tx_gain_buffalo = true; + ap9x_pci_get_wmac_data(1)->tx_gain_buffalo = true; + ap9x_pci_setup_wmac_led_pin(0, 15); + ap9x_pci_setup_wmac_leds(0, wzrhpg450h_wmac_leds_gpio, + ARRAY_SIZE(wzrhpg450h_wmac_leds_gpio)); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G450H, "WZR-HP-G450H", "Buffalo WZR-HP-G450H", + wzrhpg450h_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c new file mode 100644 index 0000000..bc79ab9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c @@ -0,0 +1,154 @@ +/* + * Zcomax ZCN-1523H-2-8/5-16 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" + +#define ZCN_1523H_GPIO_BTN_RESET 0 +#define ZCN_1523H_GPIO_LED_INIT 11 +#define ZCN_1523H_GPIO_LED_LAN1 17 + +#define ZCN_1523H_2_GPIO_LED_WEAK 13 +#define ZCN_1523H_2_GPIO_LED_MEDIUM 14 +#define ZCN_1523H_2_GPIO_LED_STRONG 15 + +#define ZCN_1523H_5_GPIO_LAN2_POWER 1 +#define ZCN_1523H_5_GPIO_LED_LAN2 13 +#define ZCN_1523H_5_GPIO_LED_WEAK 14 +#define ZCN_1523H_5_GPIO_LED_MEDIUM 15 +#define ZCN_1523H_5_GPIO_LED_STRONG 16 + +#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL, + .gpio = ZCN_1523H_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:amber:init", + .gpio = ZCN_1523H_GPIO_LED_INIT, + .active_low = 1, + }, { + .name = "zcn-1523h:green:lan1", + .gpio = ZCN_1523H_GPIO_LED_LAN1, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:red:weak", + .gpio = ZCN_1523H_2_GPIO_LED_WEAK, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:medium", + .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM, + .active_low = 1, + }, { + .name = "zcn-1523h:green:strong", + .gpio = ZCN_1523H_2_GPIO_LED_STRONG, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:red:weak", + .gpio = ZCN_1523H_5_GPIO_LED_WEAK, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:medium", + .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM, + .active_low = 1, + }, { + .name = "zcn-1523h:green:strong", + .gpio = ZCN_1523H_5_GPIO_LED_STRONG, + .active_low = 1, + }, { + .name = "zcn-1523h:green:lan2", + .gpio = ZCN_1523H_5_GPIO_LED_LAN2, + .active_low = 1, + } +}; + +static void __init zcn_1523h_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio), + zcn_1523h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(zcn_1523h_gpio_keys), + zcn_1523h_gpio_keys); + + ap91_pci_init(ee, mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN1 port */ + ath79_register_eth(0); +} + +static void __init zcn_1523h_2_setup(void) +{ + zcn_1523h_generic_setup(); + ap9x_pci_setup_wmac_gpio(0, BIT(9), 0); + + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio), + zcn_1523h_2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2", + zcn_1523h_2_setup); + +static void __init zcn_1523h_5_setup(void) +{ + zcn_1523h_generic_setup(); + ap9x_pci_setup_wmac_gpio(0, BIT(8), 0); + + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio), + zcn_1523h_5_leds_gpio); + + /* LAN2 port */ + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5", + zcn_1523h_5_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/nvram.c b/target/linux/ar71xx/files/arch/mips/ath79/nvram.c new file mode 100644 index 0000000..e55af5a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/nvram.c @@ -0,0 +1,80 @@ +/* + * Atheros AR71xx minimal nvram support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "nvram.h" + +char *ath79_nvram_find_var(const char *name, const char *buf, unsigned buf_len) +{ + unsigned len = strlen(name); + char *cur, *last; + + if (buf_len == 0 || len == 0) + return NULL; + + if (buf_len < len) + return NULL; + + if (len == 1) + return memchr(buf, (int) *name, buf_len); + + last = (char *) buf + buf_len - len; + for (cur = (char *) buf; cur <= last; cur++) + if (cur[0] == name[0] && memcmp(cur, name, len) == 0) + return cur + len; + + return NULL; +} + +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, + const char *name, char *mac) +{ + char *buf; + char *mac_str; + int ret; + int t; + + buf = vmalloc(nvram_len); + if (!buf) + return -ENOMEM; + + memcpy(buf, nvram, nvram_len); + buf[nvram_len - 1] = '\0'; + + mac_str = ath79_nvram_find_var(name, buf, nvram_len); + if (!mac_str) { + ret = -EINVAL; + goto free; + } + + if (strlen(mac_str) == 19 && mac_str[0] == '"' && mac_str[18] == '"') { + mac_str[18] = 0; + mac_str++; + } + + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != 6) { + ret = -EINVAL; + goto free; + } + + ret = 0; + +free: + vfree(buf); + return ret; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/nvram.h b/target/linux/ar71xx/files/arch/mips/ath79/nvram.h new file mode 100644 index 0000000..75151d4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/nvram.h @@ -0,0 +1,19 @@ +/* + * Atheros AR71xx minimal nvram support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_NVRAM_H +#define _ATH79_NVRAM_H + +char *ath79_nvram_find_var(const char *name, const char *buf, + unsigned buf_len); +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, + const char *name, char *mac); + +#endif /* _ATH79_NVRAM_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c new file mode 100644 index 0000000..2202351 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c @@ -0,0 +1,126 @@ +/* + * Atheros AP94 reference board PCI initialization + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +struct ath9k_fixup { + u16 *cal_data; + unsigned slot; +}; + +static int ath9k_num_fixups; +static struct ath9k_fixup ath9k_fixups[2]; + +static void ath9k_pci_fixup(struct pci_dev *dev) +{ + void __iomem *mem; + u16 *cal_data = NULL; + u16 cmd; + u32 bar0; + u32 val; + unsigned i; + + for (i = 0; i < ath9k_num_fixups; i++) { + if (ath9k_fixups[i].cal_data == NULL) + continue; + + if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) + continue; + + cal_data = ath9k_fixups[i].cal_data; + break; + } + + if (cal_data == NULL) + return; + + if (*cal_data != 0xa55a) { + pr_err("pci %s: invalid calibration data\n", pci_name(dev)); + return; + } + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + + mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + + switch (ath79_soc) { + case ATH79_SOC_AR7161: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + AR71XX_PCI_MEM_BASE); + break; + case ATH79_SOC_AR7240: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR7242: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); + break; + case ATH79_SOC_AR9344: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); + break; + + default: + BUG(); + } + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); + + /* set pointer to first reg address */ + cal_data += 3; + while (*cal_data != 0xffff) { + u32 reg; + reg = *cal_data++; + val = *cal_data++; + val |= (*cal_data++) << 16; + + __raw_writel(val, mem + reg); + udelay(100); + } + + pci_read_config_dword(dev, PCI_VENDOR_ID, &val); + dev->vendor = val & 0xffff; + dev->device = (val >> 16) & 0xffff; + + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); + dev->revision = val & 0xff; + dev->class = val >> 8; /* upper 3 bytes */ + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + + iounmap(mem); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + +void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) +{ + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; + ath9k_fixups[ath9k_num_fixups].cal_data = cal_data; + ath9k_num_fixups++; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h new file mode 100644 index 0000000..5794941 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h @@ -0,0 +1,6 @@ +#ifndef _PCI_ATH9K_FIXUP +#define _PCI_ATH9K_FIXUP + +void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init; + +#endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c new file mode 100644 index 0000000..76776e1 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c @@ -0,0 +1,358 @@ +/* + * RouterBoot helper routines + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "routerboot.h" + +#define RB_BLOCK_SIZE 0x1000 +#define RB_ART_SIZE 0x10000 +#define RB_MAGIC_ERD 0x00455244 /* extended radio data */ + +static struct rb_info rb_info; + +static u32 get_u32(void *buf) +{ + u8 *p = buf; + + return ((u32) p[3] + ((u32) p[2] << 8) + ((u32) p[1] << 16) + + ((u32) p[0] << 24)); +} + +static u16 get_u16(void *buf) +{ + u8 *p = buf; + + return (u16) p[1] + ((u16) p[0] << 8); +} + +__init int +routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard) +{ + u32 magic_ref = hard ? RB_MAGIC_HARD : RB_MAGIC_SOFT; + u32 magic; + u32 cur = *offset; + + while (cur < buflen) { + magic = get_u32(buf + cur); + if (magic == magic_ref) { + *offset = cur; + return 0; + } + + cur += 0x1000; + } + + return -ENOENT; +} + +__init int +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len) +{ + uint32_t magic; + bool align = false; + int ret; + + if (buflen < 4) + return -EINVAL; + + magic = get_u32(buf); + switch (magic) { + case RB_MAGIC_ERD: + align = true; + /* fall trough */ + case RB_MAGIC_HARD: + /* skip magic value */ + buf += 4; + buflen -= 4; + break; + + case RB_MAGIC_SOFT: + if (buflen < 8) + return -EINVAL; + + /* skip magic and CRC value */ + buf += 8; + buflen -= 8; + + break; + + default: + return -EINVAL; + } + + ret = -ENOENT; + while (buflen > 2) { + u16 id; + u16 len; + + len = get_u16(buf); + buf += 2; + buflen -= 2; + + if (buflen < 2) + break; + + id = get_u16(buf); + buf += 2; + buflen -= 2; + + if (id == RB_ID_TERMINATOR) + break; + + if (buflen < len) + break; + + if (id == tag_id) { + if (tag_len) + *tag_len = len; + if (tag_data) + *tag_data = buf; + ret = 0; + break; + } + + if (align) + len = (len + 3) / 4; + + buf += len; + buflen -= len; + } + + return ret; +} + +static inline int +rb_find_hard_cfg_tag(u16 tag_id, u8 **tag_data, u16 *tag_len) +{ + if (!rb_info.hard_cfg_data || + !rb_info.hard_cfg_size) + return -ENOENT; + + return routerboot_find_tag(rb_info.hard_cfg_data, + rb_info.hard_cfg_size, + tag_id, tag_data, tag_len); +} + +__init const char * +rb_get_board_name(void) +{ + u16 tag_len; + u8 *tag; + int err; + + err = rb_find_hard_cfg_tag(RB_ID_BOARD_NAME, &tag, &tag_len); + if (err) + return NULL; + + return tag; +} + +__init u32 +rb_get_hw_options(void) +{ + u16 tag_len; + u8 *tag; + int err; + + err = rb_find_hard_cfg_tag(RB_ID_HW_OPTIONS, &tag, &tag_len); + if (err) + return 0; + + return get_u32(tag); +} + +static void * __init +__rb_get_wlan_data(u16 id) +{ + u16 tag_len; + u8 *tag; + void *buf; + int err; + u32 magic; + size_t src_done; + size_t dst_done; + + err = rb_find_hard_cfg_tag(RB_ID_WLAN_DATA, &tag, &tag_len); + if (err) { + pr_err("no calibration data found\n"); + goto err; + } + + buf = kmalloc(RB_ART_SIZE, GFP_KERNEL); + if (buf == NULL) { + pr_err("no memory for calibration data\n"); + goto err; + } + + magic = get_u32(tag); + if (magic == RB_MAGIC_ERD) { + u8 *erd_data; + u16 erd_len; + + if (id == 0) + goto err_free; + + err = routerboot_find_tag(tag, tag_len, id, + &erd_data, &erd_len); + if (err) { + pr_err("no ERD data found for id %u\n", id); + goto err_free; + } + + dst_done = RB_ART_SIZE; + err = lzo1x_decompress_safe(erd_data, erd_len, buf, &dst_done); + if (err) { + pr_err("unable to decompress calibration data %d\n", + err); + goto err_free; + } + } else { + if (id != 0) + goto err_free; + + err = rle_decode((char *) tag, tag_len, buf, RB_ART_SIZE, + &src_done, &dst_done); + if (err) { + pr_err("unable to decode calibration data\n"); + goto err_free; + } + } + + return buf; + +err_free: + kfree(buf); +err: + return NULL; +} + +__init void * +rb_get_wlan_data(void) +{ + return __rb_get_wlan_data(0); +} + +__init void * +rb_get_ext_wlan_data(u16 id) +{ + return __rb_get_wlan_data(id); +} + +__init const struct rb_info * +rb_init_info(void *data, unsigned int size) +{ + unsigned int offset; + + if (size == 0 || (size % RB_BLOCK_SIZE) != 0) + return NULL; + + for (offset = 0; offset < size; offset += RB_BLOCK_SIZE) { + u32 magic; + + magic = get_u32(data + offset); + switch (magic) { + case RB_MAGIC_HARD: + rb_info.hard_cfg_offs = offset; + break; + + case RB_MAGIC_SOFT: + rb_info.soft_cfg_offs = offset; + break; + } + } + + if (!rb_info.hard_cfg_offs) { + pr_err("could not find a valid RouterBOOT hard config\n"); + return NULL; + } + + if (!rb_info.soft_cfg_offs) { + pr_err("could not find a valid RouterBOOT soft config\n"); + return NULL; + } + + rb_info.hard_cfg_size = RB_BLOCK_SIZE; + rb_info.hard_cfg_data = kmemdup(data + rb_info.hard_cfg_offs, + RB_BLOCK_SIZE, GFP_KERNEL); + if (!rb_info.hard_cfg_data) + return NULL; + + rb_info.board_name = rb_get_board_name(); + rb_info.hw_options = rb_get_hw_options(); + + return &rb_info; +} + +static char *rb_ext_wlan_data; + +static ssize_t +rb_ext_wlan_data_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t off, size_t count) +{ + if (off + count > attr->size) + return -EFBIG; + + memcpy(buf, &rb_ext_wlan_data[off], count); + + return count; +} + +static const struct bin_attribute rb_ext_wlan_data_attr = { + .attr = { + .name = "ext_wlan_data", + .mode = S_IRUSR | S_IWUSR, + }, + .read = rb_ext_wlan_data_read, + .size = RB_ART_SIZE, +}; + +static int __init rb_sysfs_init(void) +{ + struct kobject *rb_kobj; + int ret; + + rb_ext_wlan_data = rb_get_ext_wlan_data(1); + if (rb_ext_wlan_data == NULL) + return -ENOENT; + + rb_kobj = kobject_create_and_add("routerboot", firmware_kobj); + if (rb_kobj == NULL) { + ret = -ENOMEM; + pr_err("unable to create sysfs entry\n"); + goto err_free_wlan_data; + } + + ret = sysfs_create_bin_file(rb_kobj, &rb_ext_wlan_data_attr); + if (ret) { + pr_err("unable to create sysfs file, %d\n", ret); + goto err_put_kobj; + } + + return 0; + +err_put_kobj: + kobject_put(rb_kobj); +err_free_wlan_data: + kfree(rb_ext_wlan_data); + return ret; +} + +late_initcall(rb_sysfs_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h new file mode 100644 index 0000000..c1d7fb9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h @@ -0,0 +1,63 @@ +/* + * RouterBoot definitions + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_ROUTERBOOT_H_ +#define _ATH79_ROUTERBOOT_H_ + +struct rb_info { + unsigned int hard_cfg_offs; + unsigned int hard_cfg_size; + void *hard_cfg_data; + unsigned int soft_cfg_offs; + + const char *board_name; + u32 hw_options; +}; + +#ifdef CONFIG_ATH79_ROUTERBOOT +const struct rb_info *rb_init_info(void *data, unsigned int size); +void *rb_get_wlan_data(void); +void *rb_get_ext_wlan_data(u16 id); + +int routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len); +int routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard); +#else +static inline const struct rb_info * +rb_init_info(void *data, unsigned int size) +{ + return NULL; +} + +static inline void *rb_get_wlan_data(void) +{ + return NULL; +} + +static inline void *rb_get_wlan_data(u16 id) +{ + return NULL; +} + +static inline int +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len) +{ + return -ENOENT; +} + +static inline int +routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard) +{ + return -ENOENT; +} +#endif + +#endif /* _ATH79_ROUTERBOOT_H_ */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h b/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h new file mode 100644 index 0000000..8a99d56 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h @@ -0,0 +1,34 @@ +/* + * Compex's MyLoader specific definitions + * + * Copyright (C) 2006-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ASM_MIPS_FW_MYLOADER_H +#define _ASM_MIPS_FW_MYLOADER_H + +#include + +struct myloader_info { + uint32_t vid; + uint32_t did; + uint32_t svid; + uint32_t sdid; + uint8_t macs[MYLO_ETHADDR_COUNT][6]; +}; + +#ifdef CONFIG_MYLOADER +extern struct myloader_info *myloader_get_info(void) __init; +#else +static inline struct myloader_info *myloader_get_info(void) +{ + return NULL; +} +#endif /* CONFIG_MYLOADER */ + +#endif /* _ASM_MIPS_FW_MYLOADER_H */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h new file mode 100644 index 0000000..d46dc4e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h @@ -0,0 +1,65 @@ +/* + * Atheros AR71xx SoC specific platform data definitions + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_PLATFORM_H +#define __ASM_MACH_ATH79_PLATFORM_H + +#include +#include +#include +#include + +struct ag71xx_switch_platform_data { + u8 phy4_mii_en:1; + u8 phy_poll_mask; +}; + +struct ag71xx_platform_data { + phy_interface_t phy_if_mode; + u32 phy_mask; + int speed; + int duplex; + u32 reset_bit; + u8 mac_addr[ETH_ALEN]; + struct device *mii_bus_dev; + + u8 has_gbit:1; + u8 is_ar91xx:1; + u8 is_ar7240:1; + u8 is_ar724x:1; + u8 has_ar8216:1; + + struct ag71xx_switch_platform_data *switch_data; + + void (*ddr_flush)(void); + void (*set_speed)(int speed); + + u32 fifo_cfg1; + u32 fifo_cfg2; + u32 fifo_cfg3; + + unsigned int max_frame_len; + unsigned int desc_pktlen_mask; +}; + +struct ag71xx_mdio_platform_data { + u32 phy_mask; + u8 builtin_switch:1; + u8 is_ar7240:1; + u8 is_ar9330:1; + u8 is_ar934x:1; + unsigned long mdio_clock; + unsigned long ref_clock; + + void (*reset)(struct mii_bus *bus); +}; + +#endif /* __ASM_MACH_ATH79_PLATFORM_H */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h new file mode 100644 index 0000000..50d5a20 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h @@ -0,0 +1,84 @@ +/* + * MikroTik RouterBOARD 750 definitions + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef _MACH_RB750_H +#define _MACH_RB750_H + +#include + +#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ +#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ +#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ +#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ +#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ +#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ +#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ +#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ +#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ +#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ +#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ +#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ +#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ +#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ +#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ + +#define RB750_GPIO_BTN_RESET 1 +#define RB750_GPIO_SPI_CS0 2 +#define RB750_GPIO_LED_ACT 12 +#define RB750_GPIO_LED_PORT1 13 +#define RB750_GPIO_LED_PORT2 14 +#define RB750_GPIO_LED_PORT3 15 +#define RB750_GPIO_LED_PORT4 16 +#define RB750_GPIO_LED_PORT5 17 + +#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) +#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) +#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) +#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) +#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) +#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) +#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) + +#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) + +#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ + RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) + +#define RB7XX_GPIO_NAND_NCE 0 +#define RB7XX_GPIO_MON 9 +#define RB7XX_GPIO_LED_ACT 11 +#define RB7XX_GPIO_USB_POWERON 13 + +#define RB7XX_NAND_NCE BIT(RB7XX_GPIO_NAND_NCE) +#define RB7XX_LED_ACT BIT(RB7XX_GPIO_LED_ACT) +#define RB7XX_MONITOR BIT(RB7XX_GPIO_MON) +#define RB7XX_USB_POWERON BIT(RB7XX_GPIO_USB_POWERON) + +struct rb750_led_data { + char *name; + char *default_trigger; + u32 mask; + int active_low; +}; + +struct rb750_led_platform_data { + int num_leds; + struct rb750_led_data *leds; + void (*latch_change)(u32 clear, u32 set); +}; + +struct rb7xx_nand_platform_data { + u32 nce_line; + + void (*enable_pins)(void); + void (*disable_pins)(void); + void (*latch_change)(u32, u32); +}; + +#endif /* _MACH_RB750_H */ \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h new file mode 100644 index 0000000..5b17e94 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h @@ -0,0 +1,48 @@ +/* + * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define CPLD_GPIO_nLED1 0 +#define CPLD_GPIO_nLED2 1 +#define CPLD_GPIO_nLED3 2 +#define CPLD_GPIO_nLED4 3 +#define CPLD_GPIO_FAN 4 +#define CPLD_GPIO_ALE 5 +#define CPLD_GPIO_CLE 6 +#define CPLD_GPIO_nCE 7 +#define CPLD_GPIO_nLED5 8 + +#define CPLD_NUM_GPIOS 9 + +#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) +#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) +#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) +#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) +#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) +#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) +#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) +#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) +#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) + +struct rb4xx_cpld_platform_data { + unsigned gpio_base; +}; + +extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); +extern int rb4xx_cpld_read(unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_read_from(unsigned addr, + unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); diff --git a/target/linux/ar71xx/files/drivers/gpio/gpio-latch.c b/target/linux/ar71xx/files/drivers/gpio/gpio-latch.c new file mode 100644 index 0000000..d911f6a --- /dev/null +++ b/target/linux/ar71xx/files/drivers/gpio/gpio-latch.c @@ -0,0 +1,220 @@ +/* + * GPIO latch driver + * + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct gpio_latch_chip { + struct gpio_chip gc; + + struct mutex mutex; + struct mutex latch_mutex; + bool latch_enabled; + int le_gpio; + bool le_active_low; + int *gpios; +}; + +static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc) +{ + return container_of(gc, struct gpio_latch_chip, gc); +} + +static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable) +{ + mutex_lock(&glc->mutex); + + if (enable) + glc->latch_enabled = true; + + if (glc->latch_enabled) + mutex_lock(&glc->latch_mutex); +} + +static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable) +{ + if (glc->latch_enabled) + mutex_unlock(&glc->latch_mutex); + + if (disable) + glc->latch_enabled = true; + + mutex_unlock(&glc->mutex); +} + +static int +gpio_latch_get(struct gpio_chip *gc, unsigned offset) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + int ret; + + gpio_latch_lock(glc, false); + ret = gpio_get_value(glc->gpios[offset]); + gpio_latch_unlock(glc, false); + + return ret; +} + +static void +gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + bool enable_latch = false; + bool disable_latch = false; + int gpio; + + gpio = glc->gpios[offset]; + + if (gpio == glc->le_gpio) { + enable_latch = value ^ glc->le_active_low; + disable_latch = !enable_latch; + } + + gpio_latch_lock(glc, enable_latch); + gpio_set_value(gpio, value); + gpio_latch_unlock(glc, disable_latch); +} + +static int +gpio_latch_direction_input(struct gpio_chip *gc, unsigned offset) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + int ret; + + gpio_latch_lock(glc, false); + ret = gpio_direction_input(glc->gpios[offset]); + gpio_latch_unlock(glc, false); + + return ret; +} + +static int +gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + bool enable_latch = false; + bool disable_latch = false; + int gpio; + int ret; + + gpio = glc->gpios[offset]; + + if (gpio == glc->le_gpio) { + enable_latch = value ^ glc->le_active_low; + disable_latch = !enable_latch; + } + + gpio_latch_lock(glc, enable_latch); + ret = gpio_direction_output(gpio, value); + gpio_latch_unlock(glc, disable_latch); + + return ret; +} + +static int gpio_latch_probe(struct platform_device *pdev) +{ + struct gpio_latch_chip *glc; + struct gpio_latch_platform_data *pdata; + struct gpio_chip *gc; + int size; + int ret; + int i; + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) + return -EINVAL; + + if (pdata->le_gpio_index >= pdata->num_gpios || + !pdata->num_gpios || + !pdata->gpios) + return -EINVAL; + + for (i = 0; i < pdata->num_gpios; i++) { + int gpio = pdata->gpios[i]; + + ret = devm_gpio_request(&pdev->dev, gpio, + GPIO_LATCH_DRIVER_NAME); + if (ret) + return ret; + } + + glc = devm_kzalloc(&pdev->dev, sizeof(*glc), GFP_KERNEL); + if (!glc) + return -ENOMEM; + + mutex_init(&glc->mutex); + mutex_init(&glc->latch_mutex); + + size = pdata->num_gpios * sizeof(glc->gpios[0]); + glc->gpios = devm_kzalloc(&pdev->dev, size , GFP_KERNEL); + if (!glc->gpios) + return -ENOMEM; + + memcpy(glc->gpios, pdata->gpios, size); + + glc->le_gpio = glc->gpios[pdata->le_gpio_index]; + glc->le_active_low = pdata->le_active_low; + + gc = &glc->gc; + + gc->label = GPIO_LATCH_DRIVER_NAME; + gc->base = pdata->base; + gc->can_sleep = true; + gc->ngpio = pdata->num_gpios; + gc->get = gpio_latch_get; + gc->set = gpio_latch_set; + gc->direction_input = gpio_latch_direction_input, + gc->direction_output = gpio_latch_direction_output; + + platform_set_drvdata(pdev, glc); + + ret = gpiochip_add(&glc->gc); + if (ret) + return ret; + + return 0; +} + +static int gpio_latch_remove(struct platform_device *pdev) +{ + struct gpio_latch_chip *glc = platform_get_drvdata(pdev); + + gpiochip_remove(&glc->gc); + return 0; +} + + +static struct platform_driver gpio_latch_driver = { + .probe = gpio_latch_probe, + .remove = gpio_latch_remove, + .driver = { + .name = GPIO_LATCH_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init gpio_latch_init(void) +{ + return platform_driver_register(&gpio_latch_driver); +} + +postcore_initcall(gpio_latch_init); + +MODULE_DESCRIPTION("GPIO latch driver"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c new file mode 100644 index 0000000..8c01efe --- /dev/null +++ b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c @@ -0,0 +1,251 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer GPIO driver + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NXP_74HC153_NUM_GPIOS 8 +#define NXP_74HC153_S0_MASK 0x1 +#define NXP_74HC153_S1_MASK 0x2 +#define NXP_74HC153_BANK_MASK 0x4 + +struct nxp_74hc153_chip { + struct device *parent; + struct gpio_chip gpio_chip; + struct mutex lock; +}; + +static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) +{ + return container_of(gc, struct nxp_74hc153_chip, gpio_chip); +} + +static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) +{ + return 0; +} + +static int nxp_74hc153_direction_output(struct gpio_chip *gc, + unsigned offset, int val) +{ + return -EINVAL; +} + +static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) +{ + struct nxp_74hc153_chip *nxp; + struct nxp_74hc153_platform_data *pdata; + unsigned s0; + unsigned s1; + unsigned pin; + int ret; + + nxp = gpio_to_nxp(gc); + pdata = nxp->parent->platform_data; + + s0 = !!(offset & NXP_74HC153_S0_MASK); + s1 = !!(offset & NXP_74HC153_S1_MASK); + pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y + : pdata->gpio_pin_1y; + + mutex_lock(&nxp->lock); + gpio_set_value(pdata->gpio_pin_s0, s0); + gpio_set_value(pdata->gpio_pin_s1, s1); + ret = gpio_get_value(pin); + mutex_unlock(&nxp->lock); + + return ret; +} + +static void nxp_74hc153_set_value(struct gpio_chip *gc, + unsigned offset, int val) +{ + /* not supported */ +} + +static int nxp_74hc153_probe(struct platform_device *pdev) +{ + struct nxp_74hc153_platform_data *pdata; + struct nxp_74hc153_chip *nxp; + struct gpio_chip *gc; + int err; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { + dev_dbg(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); + if (nxp == NULL) { + dev_err(&pdev->dev, "no memory for private data\n"); + return -ENOMEM; + } + + err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_s0, err); + goto err_free_nxp; + } + + err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_s1, err); + goto err_free_s0; + } + + err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_1y, err); + goto err_free_s1; + } + + err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_2y, err); + goto err_free_1y; + } + + err = gpio_direction_output(pdata->gpio_pin_s0, 0); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_s0, err); + goto err_free_2y; + } + + err = gpio_direction_output(pdata->gpio_pin_s1, 0); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_s1, err); + goto err_free_2y; + } + + err = gpio_direction_input(pdata->gpio_pin_1y); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_1y, err); + goto err_free_2y; + } + + err = gpio_direction_input(pdata->gpio_pin_2y); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_2y, err); + goto err_free_2y; + } + + nxp->parent = &pdev->dev; + mutex_init(&nxp->lock); + + gc = &nxp->gpio_chip; + + gc->direction_input = nxp_74hc153_direction_input; + gc->direction_output = nxp_74hc153_direction_output; + gc->get = nxp_74hc153_get_value; + gc->set = nxp_74hc153_set_value; + gc->can_sleep = 1; + + gc->base = pdata->gpio_base; + gc->ngpio = NXP_74HC153_NUM_GPIOS; + gc->label = dev_name(nxp->parent); + gc->dev = nxp->parent; + gc->owner = THIS_MODULE; + + err = gpiochip_add(&nxp->gpio_chip); + if (err) { + dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); + goto err_free_2y; + } + + platform_set_drvdata(pdev, nxp); + return 0; + +err_free_2y: + gpio_free(pdata->gpio_pin_2y); +err_free_1y: + gpio_free(pdata->gpio_pin_1y); +err_free_s1: + gpio_free(pdata->gpio_pin_s1); +err_free_s0: + gpio_free(pdata->gpio_pin_s0); +err_free_nxp: + kfree(nxp); + return err; +} + +static int nxp_74hc153_remove(struct platform_device *pdev) +{ + struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); + struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; + + if (nxp) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + int err; + + err = gpiochip_remove(&nxp->gpio_chip); + if (err) { + dev_err(&pdev->dev, + "unable to remove gpio chip, err=%d\n", + err); + return err; + } +#else + gpiochip_remove(&nxp->gpio_chip); +#endif + gpio_free(pdata->gpio_pin_2y); + gpio_free(pdata->gpio_pin_1y); + gpio_free(pdata->gpio_pin_s1); + gpio_free(pdata->gpio_pin_s0); + + kfree(nxp); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver nxp_74hc153_driver = { + .probe = nxp_74hc153_probe, + .remove = nxp_74hc153_remove, + .driver = { + .name = NXP_74HC153_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init nxp_74hc153_init(void) +{ + return platform_driver_register(&nxp_74hc153_driver); +} +subsys_initcall(nxp_74hc153_init); + +static void __exit nxp_74hc153_exit(void) +{ + platform_driver_unregister(&nxp_74hc153_driver); +} +module_exit(nxp_74hc153_exit); + +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/leds/leds-rb750.c b/target/linux/ar71xx/files/drivers/leds/leds-rb750.c new file mode 100644 index 0000000..79e98b4 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/leds/leds-rb750.c @@ -0,0 +1,144 @@ +/* + * LED driver for the RouterBOARD 750 + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "leds-rb750" + +struct rb750_led_dev { + struct led_classdev cdev; + u32 mask; + int active_low; + void (*latch_change)(u32 clear, u32 set); +}; + +struct rb750_led_drvdata { + struct rb750_led_dev *led_devs; + int num_leds; +}; + +static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) +{ + return (struct rb750_led_dev *)container_of(led_cdev, + struct rb750_led_dev, cdev); +} + +static void rb750_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct rb750_led_dev *rbled = to_rbled(led_cdev); + int level; + + level = (value == LED_OFF) ? 0 : 1; + level ^= rbled->active_low; + + if (level) + rbled->latch_change(0, rbled->mask); + else + rbled->latch_change(rbled->mask, 0); +} + +static int rb750_led_probe(struct platform_device *pdev) +{ + struct rb750_led_platform_data *pdata; + struct rb750_led_drvdata *drvdata; + int ret = 0; + int i; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + + sizeof(struct rb750_led_dev) * pdata->num_leds, + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->num_leds = pdata->num_leds; + drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; + + for (i = 0; i < drvdata->num_leds; i++) { + struct rb750_led_dev *rbled = &drvdata->led_devs[i]; + struct rb750_led_data *led_data = &pdata->leds[i]; + + rbled->cdev.name = led_data->name; + rbled->cdev.default_trigger = led_data->default_trigger; + rbled->cdev.brightness_set = rb750_led_brightness_set; + rbled->cdev.brightness = LED_OFF; + + rbled->mask = led_data->mask; + rbled->active_low = !!led_data->active_low; + rbled->latch_change = pdata->latch_change; + + ret = led_classdev_register(&pdev->dev, &rbled->cdev); + if (ret) + goto err; + } + + platform_set_drvdata(pdev, drvdata); + return 0; + +err: + for (i = i - 1; i >= 0; i--) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return ret; +} + +static int rb750_led_remove(struct platform_device *pdev) +{ + struct rb750_led_drvdata *drvdata; + int i; + + drvdata = platform_get_drvdata(pdev); + for (i = 0; i < drvdata->num_leds; i++) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return 0; +} + +static struct platform_driver rb750_led_driver = { + .probe = rb750_led_probe, + .remove = rb750_led_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:leds-rb750"); + +static int __init rb750_led_init(void) +{ + return platform_driver_register(&rb750_led_driver); +} + +static void __exit rb750_led_exit(void) +{ + platform_driver_unregister(&rb750_led_driver); +} + +module_init(rb750_led_init); +module_exit(rb750_led_exit); + +MODULE_DESCRIPTION(DRV_NAME); +MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c b/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c new file mode 100644 index 0000000..6425b05 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c @@ -0,0 +1,76 @@ +/* + * USB LED driver for the NETGEAR WNDR3700 + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "wndr3700-led-usb" + +static void wndr3700_usb_led_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + if (brightness) + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); + else + ath79_device_reset_set(AR71XX_RESET_GE1_PHY); +} + +static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) +{ + return ath79_device_reset_get(AR71XX_RESET_GE1_PHY) ? LED_OFF : LED_FULL; +} + +static struct led_classdev wndr3700_usb_led = { + .name = "netgear:green:usb", + .brightness_set = wndr3700_usb_led_set, + .brightness_get = wndr3700_usb_led_get, +}; + +static int wndr3700_usb_led_probe(struct platform_device *pdev) +{ + return led_classdev_register(&pdev->dev, &wndr3700_usb_led); +} + +static int wndr3700_usb_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&wndr3700_usb_led); + return 0; +} + +static struct platform_driver wndr3700_usb_led_driver = { + .probe = wndr3700_usb_led_probe, + .remove = wndr3700_usb_led_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init wndr3700_usb_led_init(void) +{ + return platform_driver_register(&wndr3700_usb_led_driver); +} + +static void __exit wndr3700_usb_led_exit(void) +{ + platform_driver_unregister(&wndr3700_usb_led_driver); +} + +module_init(wndr3700_usb_led_init); +module_exit(wndr3700_usb_led_exit); + +MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c b/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c new file mode 100644 index 0000000..7c6dad8 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2009 Christian Daniel + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * TRX flash partition table. + * Based on ar7 map by Felix Fietkau + * + */ + +#include +#include +#include +#include + +#include +#include + +struct cybertan_header { + char magic[4]; + u8 res1[4]; + char fw_date[3]; + char fw_ver[3]; + char id[4]; + char hw_ver; + char unused; + u8 flags[2]; + u8 res2[10]; +}; + +#define TRX_PARTS 6 +#define TRX_MAGIC 0x30524448 +#define TRX_MAX_OFFSET 3 + +struct trx_header { + uint32_t magic; /* "HDR0" */ + uint32_t len; /* Length of file including header */ + uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ + uint32_t flag_version; /* 0:15 flags, 16:31 version */ + uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ +}; + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +struct uimage_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data» Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +}; + +struct firmware_header { + struct cybertan_header cybertan; + struct trx_header trx; + struct uimage_header uimage; +} __packed; + +#define UBOOT_LEN 0x40000 +#define ART_LEN 0x10000 +#define NVRAM_LEN 0x10000 + +static int cybertan_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct firmware_header *header; + struct trx_header *theader; + struct uimage_header *uheader; + struct mtd_partition *trx_parts; + size_t retlen; + unsigned int kernel_len; + unsigned int uboot_len; + unsigned int nvram_len; + unsigned int art_len; + int ret; + + uboot_len = max_t(unsigned int, master->erasesize, UBOOT_LEN); + nvram_len = max_t(unsigned int, master->erasesize, NVRAM_LEN); + art_len = max_t(unsigned int, master->erasesize, ART_LEN); + + trx_parts = kzalloc(TRX_PARTS * sizeof(struct mtd_partition), + GFP_KERNEL); + if (!trx_parts) { + ret = -ENOMEM; + goto out; + } + + header = vmalloc(sizeof(*header)); + if (!header) { + return -ENOMEM; + goto free_parts; + } + + ret = mtd_read(master, uboot_len, sizeof(*header), + &retlen, (void *) header); + if (ret) + goto free_hdr; + + if (retlen != sizeof(*header)) { + ret = -EIO; + goto free_hdr; + } + + theader = &header->trx; + if (le32_to_cpu(theader->magic) != TRX_MAGIC) { + printk(KERN_NOTICE "%s: no TRX header found\n", master->name); + goto free_hdr; + } + + uheader = &header->uimage; + if (uheader->ih_magic != IH_MAGIC) { + printk(KERN_NOTICE "%s: no uImage found\n", master->name); + goto free_hdr; + } + + kernel_len = le32_to_cpu(theader->offsets[1]) + + sizeof(struct cybertan_header); + + trx_parts[0].name = "u-boot"; + trx_parts[0].offset = 0; + trx_parts[0].size = uboot_len; + trx_parts[0].mask_flags = MTD_WRITEABLE; + + trx_parts[1].name = "kernel"; + trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; + trx_parts[1].size = kernel_len; + trx_parts[1].mask_flags = 0; + + trx_parts[2].name = "rootfs"; + trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; + trx_parts[2].size = master->size - uboot_len - nvram_len - art_len - + trx_parts[1].size; + trx_parts[2].mask_flags = 0; + + trx_parts[3].name = "nvram"; + trx_parts[3].offset = master->size - nvram_len - art_len; + trx_parts[3].size = nvram_len; + trx_parts[3].mask_flags = MTD_WRITEABLE; + + trx_parts[4].name = "art"; + trx_parts[4].offset = master->size - art_len; + trx_parts[4].size = art_len; + trx_parts[4].mask_flags = MTD_WRITEABLE; + + trx_parts[5].name = "firmware"; + trx_parts[5].offset = uboot_len; + trx_parts[5].size = master->size - uboot_len - nvram_len - art_len; + trx_parts[5].mask_flags = 0; + + vfree(header); + + *pparts = trx_parts; + return TRX_PARTS; + +free_hdr: + vfree(header); +free_parts: + kfree(trx_parts); +out: + return ret; +} + +static struct mtd_part_parser cybertan_parser = { + .owner = THIS_MODULE, + .parse_fn = cybertan_parse_partitions, + .name = "cybertan", +}; + +static int __init cybertan_parser_init(void) +{ + register_mtd_parser(&cybertan_parser); + + return 0; +} + +module_init(cybertan_parser_init); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Christian Daniel "); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c new file mode 100644 index 0000000..90ba03a --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c @@ -0,0 +1,1508 @@ +/* + * Driver for the built-in NAND controller of the Atheros AR934x SoCs + * + * Copyright (C) 2011-2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define AR934X_NFC_REG_CMD 0x00 +#define AR934X_NFC_REG_CTRL 0x04 +#define AR934X_NFC_REG_STATUS 0x08 +#define AR934X_NFC_REG_INT_MASK 0x0c +#define AR934X_NFC_REG_INT_STATUS 0x10 +#define AR934X_NFC_REG_ECC_CTRL 0x14 +#define AR934X_NFC_REG_ECC_OFFSET 0x18 +#define AR934X_NFC_REG_ADDR0_0 0x1c +#define AR934X_NFC_REG_ADDR0_1 0x24 +#define AR934X_NFC_REG_ADDR1_0 0x20 +#define AR934X_NFC_REG_ADDR1_1 0x28 +#define AR934X_NFC_REG_SPARE_SIZE 0x30 +#define AR934X_NFC_REG_PROTECT 0x38 +#define AR934X_NFC_REG_LOOKUP_EN 0x40 +#define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4) +#define AR934X_NFC_REG_DMA_ADDR 0x64 +#define AR934X_NFC_REG_DMA_COUNT 0x68 +#define AR934X_NFC_REG_DMA_CTRL 0x6c +#define AR934X_NFC_REG_MEM_CTRL 0x80 +#define AR934X_NFC_REG_DATA_SIZE 0x84 +#define AR934X_NFC_REG_READ_STATUS 0x88 +#define AR934X_NFC_REG_TIME_SEQ 0x8c +#define AR934X_NFC_REG_TIMINGS_ASYN 0x90 +#define AR934X_NFC_REG_TIMINGS_SYN 0x94 +#define AR934X_NFC_REG_FIFO_DATA 0x98 +#define AR934X_NFC_REG_TIME_MODE 0x9c +#define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0 +#define AR934X_NFC_REG_FIFO_INIT 0xb0 +#define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4 + +#define AR934X_NFC_CMD_CMD_SEQ_S 0 +#define AR934X_NFC_CMD_CMD_SEQ_M 0x3f +#define AR934X_NFC_CMD_SEQ_1C 0x00 +#define AR934X_NFC_CMD_SEQ_ERASE 0x0e +#define AR934X_NFC_CMD_SEQ_12 0x0c +#define AR934X_NFC_CMD_SEQ_1C1AXR 0x21 +#define AR934X_NFC_CMD_SEQ_S 0x24 +#define AR934X_NFC_CMD_SEQ_1C3AXR 0x27 +#define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a +#define AR934X_NFC_CMD_SEQ_18 0x32 +#define AR934X_NFC_CMD_INPUT_SEL_SIU 0 +#define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6) +#define AR934X_NFC_CMD_ADDR_SEL_0 0 +#define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7) +#define AR934X_NFC_CMD_CMD0_S 8 +#define AR934X_NFC_CMD_CMD0_M 0xff +#define AR934X_NFC_CMD_CMD1_S 16 +#define AR934X_NFC_CMD_CMD1_M 0xff +#define AR934X_NFC_CMD_CMD2_S 24 +#define AR934X_NFC_CMD_CMD2_M 0xff + +#define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7 +#define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0 +#define AR934X_NFC_CTRL_SPARE_EN BIT(3) +#define AR934X_NFC_CTRL_INT_EN BIT(4) +#define AR934X_NFC_CTRL_ECC_EN BIT(5) +#define AR934X_NFC_CTRL_BLOCK_SIZE_S 6 +#define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3 +#define AR934X_NFC_CTRL_BLOCK_SIZE_32 0 +#define AR934X_NFC_CTRL_BLOCK_SIZE_64 1 +#define AR934X_NFC_CTRL_BLOCK_SIZE_128 2 +#define AR934X_NFC_CTRL_BLOCK_SIZE_256 3 +#define AR934X_NFC_CTRL_PAGE_SIZE_S 8 +#define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7 +#define AR934X_NFC_CTRL_PAGE_SIZE_256 0 +#define AR934X_NFC_CTRL_PAGE_SIZE_512 1 +#define AR934X_NFC_CTRL_PAGE_SIZE_1024 2 +#define AR934X_NFC_CTRL_PAGE_SIZE_2048 3 +#define AR934X_NFC_CTRL_PAGE_SIZE_4096 4 +#define AR934X_NFC_CTRL_PAGE_SIZE_8192 5 +#define AR934X_NFC_CTRL_PAGE_SIZE_16384 6 +#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11) +#define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0 +#define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12) +#define AR934X_NFC_CTRL_LOOKUP_EN BIT(13) +#define AR934X_NFC_CTRL_PROT_EN BIT(14) +#define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0 +#define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15) +#define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16) +#define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17) +#define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7 +#define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18 +#define AR934X_NFC_CTRL_SMALL_PAGE BIT(21) + +#define AR934X_NFC_DMA_CTRL_DMA_START BIT(7) +#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0 +#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6) +#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5) +#define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5 +#define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1) +#define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0) + +#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x)) +#define AR934X_NFC_INT_CMD_END BIT(1) + +#define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8 +#define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f +#define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7 +#define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2) +#define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1) +#define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0) + +#define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff + +/* default timing values */ +#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff +#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22 +#define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf + +#define AR934X_NFC_ID_BUF_SIZE 8 +#define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */ +#define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */ +#define AR934X_NFC_DONE_TIMEOUT 1000 +#define AR934X_NFC_DMA_RETRIES 20 + +#define AR934X_NFC_USE_IRQ true +#define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0) + +#define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043 + +#undef AR934X_NFC_DEBUG_DATA +#undef AR934X_NFC_DEBUG + +struct ar934x_nfc; + +static inline __attribute__ ((format (printf, 2, 3))) +void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...) +{ +} + +#ifdef AR934X_NFC_DEBUG +#define nfc_dbg(_nfc, fmt, ...) \ + dev_info((_nfc)->parent, fmt, ##__VA_ARGS__) +#else +#define nfc_dbg(_nfc, fmt, ...) \ + _nfc_dbg((_nfc), fmt, ##__VA_ARGS__) +#endif /* AR934X_NFC_DEBUG */ + +#ifdef AR934X_NFC_DEBUG_DATA +static void +nfc_debug_data(const char *label, void *data, int len) +{ + print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1, + data, len, 0); +} +#else +static inline void +nfc_debug_data(const char *label, void *data, int len) {} +#endif /* AR934X_NFC_DEBUG_DATA */ + +struct ar934x_nfc { + struct mtd_info mtd; + struct nand_chip nand_chip; + struct device *parent; + void __iomem *base; + void (*select_chip)(int chip_no); + bool swap_dma; + int irq; + wait_queue_head_t irq_waitq; + + bool spurious_irq_expected; + u32 irq_status; + + u32 ctrl_reg; + u32 ecc_ctrl_reg; + u32 ecc_offset_reg; + u32 ecc_thres; + u32 ecc_oob_pos; + + bool small_page; + unsigned int addr_count0; + unsigned int addr_count1; + + u8 *buf; + dma_addr_t buf_dma; + unsigned int buf_size; + int buf_index; + + bool read_id; + + int erase1_page_addr; + + int rndout_page_addr; + int rndout_read_cmd; + + int seqin_page_addr; + int seqin_column; + int seqin_read_cmd; +}; + +static void ar934x_nfc_restart(struct ar934x_nfc *nfc); + +static inline bool +is_all_ff(u8 *buf, int len) +{ + while (len--) + if (buf[len] != 0xff) + return false; + + return true; +} + +static inline void +ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val) +{ + __raw_writel(val, nfc->base + reg); +} + +static inline u32 +ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg) +{ + return __raw_readl(nfc->base + reg); +} + +static inline struct ar934x_nfc_platform_data * +ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc) +{ + return nfc->parent->platform_data; +} + +static inline struct +ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd) +{ + return container_of(mtd, struct ar934x_nfc, mtd); +} + +static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc) +{ + return AR934X_NFC_USE_IRQ; +} + +static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg) +{ + wmb(); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD); +} + +static bool +__ar934x_nfc_dev_ready(struct ar934x_nfc *nfc) +{ + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS); + return (status & 0xff) == 0xff; +} + +static inline bool +__ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc) +{ + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL); + return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0; +} + +static int +ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc) +{ + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT); + do { + if (__ar934x_nfc_dev_ready(nfc)) + return 0; + } while time_before(jiffies, timeout); + + nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n", + ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS), + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS)); + return -ETIMEDOUT; +} + +static int +ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc) +{ + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT); + do { + if (__ar934x_nfc_is_dma_ready(nfc)) + return 0; + } while time_before(jiffies, timeout); + + nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n", + ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL)); + return -ETIMEDOUT; +} + +static int +ar934x_nfc_wait_irq(struct ar934x_nfc *nfc) +{ + long timeout; + int ret; + + timeout = wait_event_timeout(nfc->irq_waitq, + (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0, + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT)); + + ret = 0; + if (!timeout) { + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + nfc_dbg(nfc, + "timeout waiting for interrupt, status:%08x\n", + nfc->irq_status); + ret = -ETIMEDOUT; + } + + nfc->irq_status = 0; + return ret; +} + +static int +ar934x_nfc_wait_done(struct ar934x_nfc *nfc) +{ + int ret; + + if (ar934x_nfc_use_irq(nfc)) + ret = ar934x_nfc_wait_irq(nfc); + else + ret = ar934x_nfc_wait_dev_ready(nfc); + + if (ret) + return ret; + + return ar934x_nfc_wait_dma_ready(nfc); +} + +static int +ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size) +{ + nfc->buf = dma_alloc_coherent(nfc->parent, size, + &nfc->buf_dma, GFP_KERNEL); + if (nfc->buf == NULL) { + dev_err(nfc->parent, "no memory for DMA buffer\n"); + return -ENOMEM; + } + + nfc->buf_size = size; + nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size); + + return 0; +} + +static void +ar934x_nfc_free_buf(struct ar934x_nfc *nfc) +{ + dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma); +} + +static void +ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr, + u32 *addr0, u32 *addr1) +{ + u32 a0, a1; + + a0 = 0; + a1 = 0; + + if (column == -1) { + /* ERASE1 */ + a0 = (page_addr & 0xffff) << 16; + a1 = (page_addr >> 16) & 0xf; + } else if (page_addr != -1) { + /* SEQIN, READ0, etc.. */ + + /* TODO: handle 16bit bus width */ + if (nfc->small_page) { + a0 = column & 0xff; + a0 |= (page_addr & 0xff) << 8; + a0 |= ((page_addr >> 8) & 0xff) << 16; + a0 |= ((page_addr >> 16) & 0xff) << 24; + } else { + a0 = column & 0x0FFF; + a0 |= (page_addr & 0xffff) << 16; + + if (nfc->addr_count0 > 4) + a1 = (page_addr >> 16) & 0xf; + } + } + + *addr0 = a0; + *addr1 = a1; +} + +static void +ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command) +{ + u32 cmd_reg; + + cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 | + AR934X_NFC_CMD_SEQ_1C; + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); +} + +static int +ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr, + int len, u32 cmd_reg, u32 ctrl_reg, bool write) +{ + u32 addr0, addr1; + u32 dma_ctrl; + int dir; + int err; + int retries = 0; + + WARN_ON(len & 3); + + if (WARN_ON(len > nfc->buf_size)) + dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size); + + if (write) { + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE; + dir = DMA_TO_DEVICE; + } else { + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ; + dir = DMA_FROM_DEVICE; + } + + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1); + + dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START | + (AR934X_NFC_DMA_CTRL_DMA_BURST_3 << + AR934X_NFC_DMA_CTRL_DMA_BURST_S); + + cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0; + ctrl_reg |= AR934X_NFC_CTRL_INT_EN; + + nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n", + (write) ? "write" : "read", + addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg); + +retry: + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg); + + if (ar934x_nfc_use_irq(nfc)) { + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK); + } + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + err = ar934x_nfc_wait_done(nfc); + if (err) { + dev_dbg(nfc->parent, "%s operation stuck at page %d\n", + (write) ? "write" : "read", page_addr); + + ar934x_nfc_restart(nfc); + if (retries++ < AR934X_NFC_DMA_RETRIES) + goto retry; + + dev_err(nfc->parent, "%s operation failed on page %d\n", + (write) ? "write" : "read", page_addr); + } + + return err; +} + +static int +ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command) +{ + u32 cmd_reg; + int err; + + nfc_dbg(nfc, "readid, cmd:%02x\n", command); + + cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR; + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, + cmd_reg, nfc->ctrl_reg, false); + + nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE); + + return err; +} + +static int +ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr, int len) +{ + u32 cmd_reg; + int err; + + nfc_dbg(nfc, "read, column=%d page=%d len=%d\n", + column, page_addr, len); + + cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + if (nfc->small_page) { + cmd_reg |= AR934X_NFC_CMD_SEQ_18; + } else { + cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR; + } + + err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len, + cmd_reg, nfc->ctrl_reg, false); + + nfc_debug_data("[data] ", nfc->buf, len); + + return err; +} + +static void +ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr) +{ + u32 addr0, addr1; + u32 ctrl_reg; + u32 cmd_reg; + + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1); + + ctrl_reg = nfc->ctrl_reg; + if (nfc->small_page) { + /* override number of address cycles for the erase command */ + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M << + AR934X_NFC_CTRL_ADDR_CYCLE0_S); + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M << + AR934X_NFC_CTRL_ADDR_CYCLE1_S); + ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE); + ctrl_reg |= (nfc->addr_count0 + 1) << + AR934X_NFC_CTRL_ADDR_CYCLE0_S; + } + + cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE; + + nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n", + page_addr, addr0, addr1, cmd_reg, ctrl_reg); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); +} + +static int +ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr, int len) +{ + u32 cmd_reg; + + nfc_dbg(nfc, "write, column=%d page=%d len=%d\n", + column, page_addr, len); + + nfc_debug_data("[data] ", nfc->buf, len); + + cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_12; + + return ar934x_nfc_do_rw_command(nfc, column, page_addr, len, + cmd_reg, nfc->ctrl_reg, true); +} + +static void +ar934x_nfc_read_status(struct ar934x_nfc *nfc) +{ + u32 cmd_reg; + u32 status; + + cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_S; + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS); + + nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n", + cmd_reg, (status & 0xff)); + + if (nfc->swap_dma) + nfc->buf[0 ^ 3] = status; + else + nfc->buf[0] = status; +} + +static void +ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, + int page_addr) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + struct nand_chip *nand = mtd->priv; + + nfc->read_id = false; + if (command != NAND_CMD_PAGEPROG) + nfc->buf_index = 0; + + switch (command) { + case NAND_CMD_RESET: + ar934x_nfc_send_cmd(nfc, command); + break; + + case NAND_CMD_READID: + nfc->read_id = true; + ar934x_nfc_send_readid(nfc, command); + break; + + case NAND_CMD_READ0: + case NAND_CMD_READ1: + if (nfc->small_page) { + ar934x_nfc_send_read(nfc, command, column, page_addr, + mtd->writesize + mtd->oobsize); + } else { + ar934x_nfc_send_read(nfc, command, 0, page_addr, + mtd->writesize + mtd->oobsize); + nfc->buf_index = column; + nfc->rndout_page_addr = page_addr; + nfc->rndout_read_cmd = command; + } + break; + + case NAND_CMD_READOOB: + if (nfc->small_page) + ar934x_nfc_send_read(nfc, NAND_CMD_READOOB, + column, page_addr, + mtd->oobsize); + else + ar934x_nfc_send_read(nfc, NAND_CMD_READ0, + mtd->writesize, page_addr, + mtd->oobsize); + break; + + case NAND_CMD_RNDOUT: + if (WARN_ON(nfc->small_page)) + break; + + /* emulate subpage read */ + ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0, + nfc->rndout_page_addr, + mtd->writesize + mtd->oobsize); + nfc->buf_index = column; + break; + + case NAND_CMD_ERASE1: + nfc->erase1_page_addr = page_addr; + break; + + case NAND_CMD_ERASE2: + ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr); + break; + + case NAND_CMD_STATUS: + ar934x_nfc_read_status(nfc); + break; + + case NAND_CMD_SEQIN: + if (nfc->small_page) { + /* output read command */ + if (column >= mtd->writesize) { + column -= mtd->writesize; + nfc->seqin_read_cmd = NAND_CMD_READOOB; + } else if (column < 256) { + nfc->seqin_read_cmd = NAND_CMD_READ0; + } else { + column -= 256; + nfc->seqin_read_cmd = NAND_CMD_READ1; + } + } else { + nfc->seqin_read_cmd = NAND_CMD_READ0; + } + nfc->seqin_column = column; + nfc->seqin_page_addr = page_addr; + break; + + case NAND_CMD_PAGEPROG: + if (nand->ecc.mode == NAND_ECC_HW) { + /* the data is already written */ + break; + } + + if (nfc->small_page) + ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd); + + ar934x_nfc_send_write(nfc, command, nfc->seqin_column, + nfc->seqin_page_addr, + nfc->buf_index); + break; + + default: + dev_err(nfc->parent, + "unsupported command: %x, column:%d page_addr=%d\n", + command, column, page_addr); + break; + } +} + +static int +ar934x_nfc_dev_ready(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + return __ar934x_nfc_dev_ready(nfc); +} + +static void +ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + if (nfc->select_chip) + nfc->select_chip(chip_no); +} + +static u8 +ar934x_nfc_read_byte(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + u8 data; + + WARN_ON(nfc->buf_index >= nfc->buf_size); + + if (nfc->swap_dma || nfc->read_id) + data = nfc->buf[nfc->buf_index ^ 3]; + else + data = nfc->buf[nfc->buf_index]; + + nfc->buf_index++; + + return data; +} + +static void +ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int i; + + WARN_ON(nfc->buf_index + len > nfc->buf_size); + + if (nfc->swap_dma) { + for (i = 0; i < len; i++) { + nfc->buf[nfc->buf_index ^ 3] = buf[i]; + nfc->buf_index++; + } + } else { + for (i = 0; i < len; i++) { + nfc->buf[nfc->buf_index] = buf[i]; + nfc->buf_index++; + } + } +} + +static void +ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int buf_index; + int i; + + WARN_ON(nfc->buf_index + len > nfc->buf_size); + + buf_index = nfc->buf_index; + + if (nfc->swap_dma || nfc->read_id) { + for (i = 0; i < len; i++) { + buf[i] = nfc->buf[buf_index ^ 3]; + buf_index++; + } + } else { + for (i = 0; i < len; i++) { + buf[i] = nfc->buf[buf_index]; + buf_index++; + } + } + + nfc->buf_index = buf_index; +} + +static inline void +ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc) +{ + nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN; + nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN; +} + +static inline void +ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc) +{ + nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN; + nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN; +} + +static int +ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int err; + + nfc_dbg(nfc, "read_oob: page:%d\n", page); + + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page, + mtd->oobsize); + if (err) + return err; + + memcpy(chip->oob_poi, nfc->buf, mtd->oobsize); + + return 0; +} + +static int +ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + nfc_dbg(nfc, "write_oob: page:%d\n", page); + + memcpy(nfc->buf, chip->oob_poi, mtd->oobsize); + + return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize, + page, mtd->oobsize); +} + +static int +ar934x_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int len; + int err; + + nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required); + + len = mtd->writesize; + if (oob_required) + len += mtd->oobsize; + + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len); + if (err) + return err; + + memcpy(buf, nfc->buf, mtd->writesize); + + if (oob_required) + memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize); + + return 0; +} + +static int +ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + u32 ecc_ctrl; + int max_bitflips = 0; + bool ecc_failed; + bool ecc_corrected; + int err; + + nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required); + + ar934x_nfc_enable_hwecc(nfc); + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, + mtd->writesize); + ar934x_nfc_disable_hwecc(nfc); + + if (err) + return err; + + /* TODO: optimize to avoid memcpy */ + memcpy(buf, nfc->buf, mtd->writesize); + + /* read the ECC status */ + ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL); + ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT; + ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT; + + if (oob_required || ecc_failed) { + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, + page, mtd->oobsize); + if (err) + return err; + + if (oob_required) + memcpy(chip->oob_poi, nfc->buf, mtd->oobsize); + } + + if (ecc_failed) { + /* + * The hardware ECC engine reports uncorrectable errors + * on empty pages. Check the ECC bytes and the data. If + * both contains 0xff bytes only, dont report a failure. + * + * TODO: prebuild a buffer with 0xff bytes and use memcmp + * for better performance? + */ + if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) || + !is_all_ff(buf, mtd->writesize)) + mtd->ecc_stats.failed++; + } else if (ecc_corrected) { + /* + * The hardware does not report the exact count of the + * corrected bitflips, use assumptions based on the + * threshold. + */ + if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) { + /* + * The number of corrected bitflips exceeds the + * threshold. Assume the maximum. + */ + max_bitflips = chip->ecc.strength * chip->ecc.steps; + } else { + max_bitflips = nfc->ecc_thres * chip->ecc.steps; + } + + mtd->ecc_stats.corrected += max_bitflips; + } + + return max_bitflips; +} + +static int +ar934x_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int page; + int len; + + page = nfc->seqin_page_addr; + + nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required); + + memcpy(nfc->buf, buf, mtd->writesize); + len = mtd->writesize; + + if (oob_required) { + memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize); + len += mtd->oobsize; + } + + return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len); +} + +static int +ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int page; + int err; + + page = nfc->seqin_page_addr; + + nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required); + + /* write OOB first */ + if (oob_required && + !is_all_ff(chip->oob_poi, mtd->oobsize)) { + err = ar934x_nfc_write_oob(mtd, chip, page); + if (err) + return err; + } + + /* TODO: optimize to avoid memcopy */ + memcpy(nfc->buf, buf, mtd->writesize); + + ar934x_nfc_enable_hwecc(nfc); + err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, + mtd->writesize); + ar934x_nfc_disable_hwecc(nfc); + + return err; +} + +static void +ar934x_nfc_hw_init(struct ar934x_nfc *nfc) +{ + struct ar934x_nfc_platform_data *pdata; + + pdata = ar934x_nfc_get_platform_data(nfc); + if (pdata->hw_reset) { + pdata->hw_reset(true); + pdata->hw_reset(false); + } + + /* + * setup timings + * TODO: make it configurable via platform data + */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ, + AR934X_NFC_TIME_SEQ_DEFAULT); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN, + AR934X_NFC_TIMINGS_ASYN_DEFAULT); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN, + AR934X_NFC_TIMINGS_SYN_DEFAULT); + + /* disable WP on all chips, and select chip 0 */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0); + + /* initialize Control register */ + nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN; + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + if (nfc->small_page) { + /* Setup generic sequence register for small page reads. */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL, + AR934X_NFC_GENSEQ_SMALL_PAGE_READ); + } +} + +static void +ar934x_nfc_restart(struct ar934x_nfc *nfc) +{ + u32 ctrl_reg; + + if (nfc->select_chip) + nfc->select_chip(-1); + + ctrl_reg = nfc->ctrl_reg; + ar934x_nfc_hw_init(nfc); + nfc->ctrl_reg = ctrl_reg; + + if (nfc->select_chip) + nfc->select_chip(0); + + ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET); +} + +static irqreturn_t +ar934x_nfc_irq_handler(int irq, void *data) +{ + struct ar934x_nfc *nfc = data; + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK); + if (status) { + nfc_dbg(nfc, "got IRQ, status:%08x\n", status); + + nfc->irq_status = status; + nfc->spurious_irq_expected = true; + wake_up(&nfc->irq_waitq); + } else { + if (nfc->spurious_irq_expected) { + nfc->spurious_irq_expected = false; + } else { + dev_warn(nfc->parent, "spurious interrupt\n"); + } + } + + return IRQ_HANDLED; +} + +static int +ar934x_nfc_init_tail(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + struct nand_chip *chip = &nfc->nand_chip; + u32 ctrl; + u32 t; + int err; + + switch (mtd->oobsize) { + case 16: + case 64: + case 128: + ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize); + break; + + default: + dev_err(nfc->parent, "unsupported OOB size: %d bytes\n", + mtd->oobsize); + return -ENXIO; + } + + ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN; + + switch (mtd->erasesize / mtd->writesize) { + case 32: + t = AR934X_NFC_CTRL_BLOCK_SIZE_32; + break; + + case 64: + t = AR934X_NFC_CTRL_BLOCK_SIZE_64; + break; + + case 128: + t = AR934X_NFC_CTRL_BLOCK_SIZE_128; + break; + + case 256: + t = AR934X_NFC_CTRL_BLOCK_SIZE_256; + break; + + default: + dev_err(nfc->parent, "unsupported block size: %u\n", + mtd->erasesize / mtd->writesize); + return -ENXIO; + } + + ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S; + + switch (mtd->writesize) { + case 256: + nfc->small_page = 1; + t = AR934X_NFC_CTRL_PAGE_SIZE_256; + break; + + case 512: + nfc->small_page = 1; + t = AR934X_NFC_CTRL_PAGE_SIZE_512; + break; + + case 1024: + t = AR934X_NFC_CTRL_PAGE_SIZE_1024; + break; + + case 2048: + t = AR934X_NFC_CTRL_PAGE_SIZE_2048; + break; + + case 4096: + t = AR934X_NFC_CTRL_PAGE_SIZE_4096; + break; + + case 8192: + t = AR934X_NFC_CTRL_PAGE_SIZE_8192; + break; + + case 16384: + t = AR934X_NFC_CTRL_PAGE_SIZE_16384; + break; + + default: + dev_err(nfc->parent, "unsupported write size: %d bytes\n", + mtd->writesize); + return -ENXIO; + } + + ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S; + + if (nfc->small_page) { + ctrl |= AR934X_NFC_CTRL_SMALL_PAGE; + + if (chip->chipsize > (32 << 20)) { + nfc->addr_count0 = 4; + nfc->addr_count1 = 3; + } else if (chip->chipsize > (2 << 16)) { + nfc->addr_count0 = 3; + nfc->addr_count1 = 2; + } else { + nfc->addr_count0 = 2; + nfc->addr_count1 = 1; + } + } else { + if (chip->chipsize > (128 << 20)) { + nfc->addr_count0 = 5; + nfc->addr_count1 = 3; + } else if (chip->chipsize > (8 << 16)) { + nfc->addr_count0 = 4; + nfc->addr_count1 = 2; + } else { + nfc->addr_count0 = 3; + nfc->addr_count1 = 1; + } + } + + ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S; + ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S; + + nfc->ctrl_reg = ctrl; + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_free_buf(nfc); + err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize); + + return err; +} + +static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = { + .eccbytes = 28, + .eccpos = { + 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, 47, + }, + .oobfree = { + { + .offset = 4, + .length = 16, + }, + { + .offset = 48, + .length = 16, + }, + }, +}; + +static int +ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc) +{ + struct nand_chip *nand = &nfc->nand_chip; + u32 ecc_cap; + u32 ecc_thres; + + if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC)) { + dev_err(nfc->parent, "hardware ECC support is disabled\n"); + return -EINVAL; + } + + switch (nfc->mtd.writesize) { + case 2048: + /* + * Writing a subpage separately is not supported, because + * the controller only does ECC on full-page accesses. + */ + nand->options = NAND_NO_SUBPAGE_WRITE; + + nand->ecc.size = 512; + nand->ecc.bytes = 7; + nand->ecc.strength = 4; + nand->ecc.layout = &ar934x_nfc_oob_64_hwecc; + break; + + default: + dev_err(nfc->parent, + "hardware ECC is not available for %d byte pages\n", + nfc->mtd.writesize); + return -EINVAL; + } + + BUG_ON(!nand->ecc.layout); + + switch (nand->ecc.strength) { + case 4: + ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4; + ecc_thres = 4; + break; + + default: + dev_err(nfc->parent, "unsupported ECC strength %u\n", + nand->ecc.strength); + return -EINVAL; + } + + nfc->ecc_thres = ecc_thres; + nfc->ecc_oob_pos = nand->ecc.layout->eccpos[0]; + + nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S; + nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S; + + nfc->ecc_offset_reg = nfc->mtd.writesize + nfc->ecc_oob_pos; + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.read_page = ar934x_nfc_read_page; + nand->ecc.read_page_raw = ar934x_nfc_read_page_raw; + nand->ecc.write_page = ar934x_nfc_write_page; + nand->ecc.write_page_raw = ar934x_nfc_write_page_raw; + nand->ecc.read_oob = ar934x_nfc_read_oob; + nand->ecc.write_oob = ar934x_nfc_write_oob; + + return 0; +} + +static int +ar934x_nfc_probe(struct platform_device *pdev) +{ + static const char *part_probes[] = { "cmdlinepart", NULL, }; + struct ar934x_nfc_platform_data *pdata; + struct ar934x_nfc *nfc; + struct resource *res; + struct mtd_info *mtd; + struct nand_chip *nand; + struct mtd_part_parser_data ppdata; + int ret; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { + dev_err(&pdev->dev, "no platform data defined\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get I/O memory\n"); + return -EINVAL; + } + + nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL); + if (!nfc) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + return -ENOMEM; + } + + nfc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(nfc->base)) { + dev_err(&pdev->dev, "failed to remap I/O memory\n"); + return PTR_ERR(nfc->base); + } + + nfc->irq = platform_get_irq(pdev, 0); + if (nfc->irq < 0) { + dev_err(&pdev->dev, "no IRQ resource specified\n"); + return -EINVAL; + } + + init_waitqueue_head(&nfc->irq_waitq); + ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, 0, + dev_name(&pdev->dev), nfc); + if (ret) { + dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret); + return ret; + } + + nfc->parent = &pdev->dev; + nfc->select_chip = pdata->select_chip; + nfc->swap_dma = pdata->swap_dma; + + nand = &nfc->nand_chip; + mtd = &nfc->mtd; + + mtd->priv = nand; + mtd->owner = THIS_MODULE; + if (pdata->name) + mtd->name = pdata->name; + else + mtd->name = dev_name(&pdev->dev); + + nand->chip_delay = 25; + + nand->dev_ready = ar934x_nfc_dev_ready; + nand->cmdfunc = ar934x_nfc_cmdfunc; + nand->read_byte = ar934x_nfc_read_byte; + nand->write_buf = ar934x_nfc_write_buf; + nand->read_buf = ar934x_nfc_read_buf; + nand->select_chip = ar934x_nfc_select_chip; + + ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE); + if (ret) + goto err_free_irq; + + platform_set_drvdata(pdev, nfc); + + ar934x_nfc_hw_init(nfc); + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret); + goto err_free_buf; + } + + ret = ar934x_nfc_init_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "init tail failed, err:%d\n", ret); + goto err_free_buf; + } + + if (pdata->scan_fixup) { + ret = pdata->scan_fixup(mtd); + if (ret) + goto err_free_buf; + } + + switch (pdata->ecc_mode) { + case AR934X_NFC_ECC_SOFT: + nand->ecc.mode = NAND_ECC_SOFT; + break; + + case AR934X_NFC_ECC_SOFT_BCH: + nand->ecc.mode = NAND_ECC_SOFT_BCH; + break; + + case AR934X_NFC_ECC_HW: + ret = ar934x_nfc_setup_hwecc(nfc); + if (ret) + goto err_free_buf; + + break; + + default: + dev_err(nfc->parent, "unknown ECC mode %d\n", pdata->ecc_mode); + return -EINVAL; + } + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret); + goto err_free_buf; + } + + memset(&ppdata, '\0', sizeof(ppdata)); + ret = mtd_device_parse_register(mtd, part_probes, &ppdata, + pdata->parts, pdata->nr_parts); + if (ret) { + dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret); + goto err_free_buf; + } + + return 0; + +err_free_buf: + ar934x_nfc_free_buf(nfc); +err_free_irq: + free_irq(nfc->irq, nfc); + return ret; +} + +static int +ar934x_nfc_remove(struct platform_device *pdev) +{ + struct ar934x_nfc *nfc; + + nfc = platform_get_drvdata(pdev); + if (nfc) { + nand_release(&nfc->mtd); + ar934x_nfc_free_buf(nfc); + free_irq(nfc->irq, nfc); + } + + return 0; +} + +static struct platform_driver ar934x_nfc_driver = { + .probe = ar934x_nfc_probe, + .remove = ar934x_nfc_remove, + .driver = { + .name = AR934X_NFC_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ar934x_nfc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver"); +MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c new file mode 100644 index 0000000..5b9841b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c @@ -0,0 +1,305 @@ +/* + * NAND flash driver for the MikroTik RouterBoard 4xx series + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was based on the driver for Linux 2.6.22 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "rb4xx-nand" +#define DRV_VERSION "0.2.0" +#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" + +#define RB4XX_NAND_GPIO_READY 5 +#define RB4XX_NAND_GPIO_ALE 37 +#define RB4XX_NAND_GPIO_CLE 38 +#define RB4XX_NAND_GPIO_NCE 39 + +struct rb4xx_nand_info { + struct nand_chip chip; + struct mtd_info mtd; +}; + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb4xx_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb4xx_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static int rb4xx_nand_dev_ready(struct mtd_info *mtd) +{ + return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY); +} + +static void rb4xx_nand_write_cmd(unsigned char cmd) +{ + unsigned char data = cmd; + int err; + + err = rb4xx_cpld_write(&data, 1); + if (err) + pr_err("rb4xx_nand: write cmd failed, err=%d\n", err); +} + +static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE, + (ctrl & NAND_CLE) ? 1 : 0); + gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE, + (ctrl & NAND_ALE) ? 1 : 0); + gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE, + (ctrl & NAND_NCE) ? 0 : 1); + } + + if (cmd != NAND_CMD_NONE) + rb4xx_nand_write_cmd(cmd); +} + +static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd) +{ + unsigned char data = 0; + int err; + + err = rb4xx_cpld_read(&data, NULL, 1); + if (err) { + pr_err("rb4xx_nand: read data failed, err=%d\n", err); + data = 0xff; + } + + return data; +} + +static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf, + int len) +{ + int err; + + err = rb4xx_cpld_write(buf, len); + if (err) + pr_err("rb4xx_nand: write buf failed, err=%d\n", err); +} + +static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, + int len) +{ + int err; + + err = rb4xx_cpld_read(buf, NULL, len); + if (err) + pr_err("rb4xx_nand: read buf failed, err=%d\n", err); +} + +static int rb4xx_nand_probe(struct platform_device *pdev) +{ + struct rb4xx_nand_info *info; + int ret; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + + ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_READY); + goto err; + } + + ret = gpio_direction_input(RB4XX_NAND_GPIO_READY); + if (ret) { + dev_err(&pdev->dev, "unable to set input mode on gpio %d\n", + RB4XX_NAND_GPIO_READY); + goto err_free_gpio_ready; + } + + ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_ready; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_ale; + } + + ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_CLE); + goto err_free_gpio_ale; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_CLE); + goto err_free_gpio_cle; + } + + ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_NCE); + goto err_free_gpio_cle; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_nce; + } + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n"); + ret = -ENOMEM; + goto err_free_gpio_nce; + } + + info->chip.priv = &info; + info->mtd.priv = &info->chip; + info->mtd.owner = THIS_MODULE; + + info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; + info->chip.dev_ready = rb4xx_nand_dev_ready; + info->chip.read_byte = rb4xx_nand_read_byte; + info->chip.write_buf = rb4xx_nand_write_buf; + info->chip.read_buf = rb4xx_nand_read_buf; + + info->chip.chip_delay = 25; + info->chip.ecc.mode = NAND_ECC_SOFT; + + platform_set_drvdata(pdev, info); + + ret = nand_scan_ident(&info->mtd, 1, NULL); + if (ret) { + ret = -ENXIO; + goto err_free_info; + } + + if (info->mtd.writesize == 512) + info->chip.ecc.layout = &rb4xx_nand_ecclayout; + + ret = nand_scan_tail(&info->mtd); + if (ret) { + return -ENXIO; + goto err_set_drvdata; + } + + mtd_device_register(&info->mtd, rb4xx_nand_partitions, + ARRAY_SIZE(rb4xx_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&info->mtd); +err_set_drvdata: + platform_set_drvdata(pdev, NULL); +err_free_info: + kfree(info); +err_free_gpio_nce: + gpio_free(RB4XX_NAND_GPIO_NCE); +err_free_gpio_cle: + gpio_free(RB4XX_NAND_GPIO_CLE); +err_free_gpio_ale: + gpio_free(RB4XX_NAND_GPIO_ALE); +err_free_gpio_ready: + gpio_free(RB4XX_NAND_GPIO_READY); +err: + return ret; +} + +static int rb4xx_nand_remove(struct platform_device *pdev) +{ + struct rb4xx_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); + kfree(info); + gpio_free(RB4XX_NAND_GPIO_NCE); + gpio_free(RB4XX_NAND_GPIO_CLE); + gpio_free(RB4XX_NAND_GPIO_ALE); + gpio_free(RB4XX_NAND_GPIO_READY); + + return 0; +} + +static struct platform_driver rb4xx_nand_driver = { + .probe = rb4xx_nand_probe, + .remove = rb4xx_nand_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb4xx_nand_init(void) +{ + return platform_driver_register(&rb4xx_nand_driver); +} + +static void __exit rb4xx_nand_exit(void) +{ + platform_driver_unregister(&rb4xx_nand_driver); +} + +module_init(rb4xx_nand_init); +module_exit(rb4xx_nand_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_AUTHOR("Imre Kaloz "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c new file mode 100644 index 0000000..a20409b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c @@ -0,0 +1,354 @@ +/* + * NAND flash driver for the MikroTik RouterBOARD 750 + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRV_NAME "rb750-nand" +#define DRV_VERSION "0.1.0" +#define DRV_DESC "NAND flash driver for the RouterBOARD 750" + +#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) +#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) +#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) +#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) +#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) +#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) + +#define RB750_NAND_DATA_SHIFT 1 +#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) +#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) +#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ + RB750_NAND_NRE | RB750_NAND_NWE) + +struct rb750_nand_info { + struct nand_chip chip; + struct mtd_info mtd; + struct rb7xx_nand_platform_data *pdata; +}; + +static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) +{ + return container_of(mtd, struct rb750_nand_info, mtd); +} + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb750_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb750_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void rb750_nand_write(const u8 *buf, unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 out; + u32 t; + unsigned i; + + /* set data lines to output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); + + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); + out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); + for (i = 0; i != len; i++) { + u32 data; + + data = buf[i]; + data <<= RB750_NAND_DATA_SHIFT; + data |= out; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + + __raw_writel(data | RB750_NAND_NWE, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + /* set data lines to input mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OE); +} + +static void rb750_nand_read(u8 *read_buf, unsigned len) +{ + void __iomem *base = ath79_gpio_base; + unsigned i; + + for (i = 0; i < len; i++) { + u8 data; + + /* activate RE line */ + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + + /* read input lines */ + data = __raw_readl(base + AR71XX_GPIO_REG_IN) >> + RB750_NAND_DATA_SHIFT; + + /* deactivate RE line */ + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_SET); + + read_buf[i] = data; + } +} + +static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct rb750_nand_info *rbinfo = mtd_to_rbinfo(mtd); + void __iomem *base = ath79_gpio_base; + u32 t; + + if (chip >= 0) { + rbinfo->pdata->enable_pins(); + + /* set input mode for data lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_INPUT_BITS, + base + AR71XX_GPIO_REG_OE); + + /* deactivate RE and WE lines */ + __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, + base + AR71XX_GPIO_REG_SET); + /* flush write */ + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); + + /* activate CE line */ + __raw_writel(rbinfo->pdata->nce_line, + base + AR71XX_GPIO_REG_CLEAR); + } else { + /* deactivate CE line */ + __raw_writel(rbinfo->pdata->nce_line, + base + AR71XX_GPIO_REG_SET); + /* flush write */ + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); + + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY, + base + AR71XX_GPIO_REG_OE); + + rbinfo->pdata->disable_pins(); + } +} + +static int rb750_nand_dev_ready(struct mtd_info *mtd) +{ + void __iomem *base = ath79_gpio_base; + + return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY); +} + +static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *base = ath79_gpio_base; + u32 t; + + t = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); + t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; + t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; + + __raw_writel(t, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + if (cmd != NAND_CMD_NONE) { + u8 t = cmd; + rb750_nand_write(&t, 1); + } +} + +static u8 rb750_nand_read_byte(struct mtd_info *mtd) +{ + u8 data = 0; + rb750_nand_read(&data, 1); + return data; +} + +static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + rb750_nand_read(buf, len); +} + +static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + rb750_nand_write(buf, len); +} + +static void __init rb750_nand_gpio_init(struct rb750_nand_info *info) +{ + void __iomem *base = ath79_gpio_base; + u32 out; + u32 t; + + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* setup output levels */ + __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, + base + AR71XX_GPIO_REG_SET); + + __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, + base + AR71XX_GPIO_REG_CLEAR); + + /* setup input lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~(RB750_NAND_INPUT_BITS), base + AR71XX_GPIO_REG_OE); + + /* setup output lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= RB750_NAND_OUTPUT_BITS; + t |= info->pdata->nce_line; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + + info->pdata->latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); +} + +static int rb750_nand_probe(struct platform_device *pdev) +{ + struct rb750_nand_info *info; + struct rb7xx_nand_platform_data *pdata; + int ret; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->chip.priv = &info; + info->mtd.priv = &info->chip; + info->mtd.owner = THIS_MODULE; + + info->chip.select_chip = rb750_nand_select_chip; + info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; + info->chip.dev_ready = rb750_nand_dev_ready; + info->chip.read_byte = rb750_nand_read_byte; + info->chip.write_buf = rb750_nand_write_buf; + info->chip.read_buf = rb750_nand_read_buf; + + info->chip.chip_delay = 25; + info->chip.ecc.mode = NAND_ECC_SOFT; + + info->pdata = pdata; + + platform_set_drvdata(pdev, info); + + rb750_nand_gpio_init(info); + + ret = nand_scan_ident(&info->mtd, 1, NULL); + if (ret) { + ret = -ENXIO; + goto err_free_info; + } + + if (info->mtd.writesize == 512) + info->chip.ecc.layout = &rb750_nand_ecclayout; + + ret = nand_scan_tail(&info->mtd); + if (ret) { + return -ENXIO; + goto err_set_drvdata; + } + + ret = mtd_device_register(&info->mtd, rb750_nand_partitions, + ARRAY_SIZE(rb750_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&info->mtd); +err_set_drvdata: + platform_set_drvdata(pdev, NULL); +err_free_info: + kfree(info); + return ret; +} + +static int rb750_nand_remove(struct platform_device *pdev) +{ + struct rb750_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); + kfree(info); + + return 0; +} + +static struct platform_driver rb750_nand_driver = { + .probe = rb750_nand_probe, + .remove = rb750_nand_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb750_nand_init(void) +{ + return platform_driver_register(&rb750_nand_driver); +} + +static void __exit rb750_nand_exit(void) +{ + platform_driver_unregister(&rb750_nand_driver); +} + +module_init(rb750_nand_init); +module_exit(rb750_nand_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c new file mode 100644 index 0000000..f0aa3c3 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c @@ -0,0 +1,377 @@ +/* + * NAND flash driver for the MikroTik RouterBOARD 91x series + * + * Copyright (C) 2013-2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_DESC "NAND flash driver for the RouterBOARD 91x series" + +#define RB91X_NAND_NRWE BIT(12) + +#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\ + BIT(13) | BIT(14) | BIT(15)) + +#define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY) +#define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE) + +#define RB91X_NAND_LOW_DATA_MASK 0x1f +#define RB91X_NAND_HIGH_DATA_MASK 0xe0 +#define RB91X_NAND_HIGH_DATA_SHIFT 8 + +struct rb91x_nand_info { + struct nand_chip chip; + struct mtd_info mtd; + struct device *dev; + + int gpio_nce; + int gpio_ale; + int gpio_cle; + int gpio_rdy; + int gpio_read; + int gpio_nrw; + int gpio_nle; +}; + +static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) +{ + return container_of(mtd, struct rb91x_nand_info, mtd); +} + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb91x_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb91x_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void rb91x_nand_write(struct rb91x_nand_info *rbni, + const u8 *buf, + unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 oe_reg; + u32 out_reg; + u32 out; + unsigned i; + + /* enable the latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 0); + + oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); + out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* set data lines to output mode */ + __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE), + base + AR71XX_GPIO_REG_OE); + + out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE); + for (i = 0; i != len; i++) { + u32 data; + + data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) << + RB91X_NAND_HIGH_DATA_SHIFT; + data |= buf[i] & RB91X_NAND_LOW_DATA_MASK; + data |= out; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + + /* deactivate WE line */ + data |= RB91X_NAND_NRWE; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + /* restore registers */ + __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); + __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* disable the latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 1); +} + +static void rb91x_nand_read(struct rb91x_nand_info *rbni, + u8 *read_buf, + unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 oe_reg; + u32 out_reg; + unsigned i; + + /* enable read mode */ + gpio_set_value_cansleep(rbni->gpio_read, 1); + + /* enable latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 0); + + /* save registers */ + oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); + out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* set data lines to input mode */ + __raw_writel(oe_reg | RB91X_NAND_DATA_BITS, + base + AR71XX_GPIO_REG_OE); + + for (i = 0; i < len; i++) { + u32 in; + u8 data; + + /* activate RE line */ + __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + + /* read input lines */ + in = __raw_readl(base + AR71XX_GPIO_REG_IN); + + /* deactivate RE line */ + __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET); + + data = (in & RB91X_NAND_LOW_DATA_MASK); + data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) & + RB91X_NAND_HIGH_DATA_MASK; + + read_buf[i] = data; + } + + /* restore registers */ + __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); + __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* disable latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 1); + + /* disable read mode */ + gpio_set_value_cansleep(rbni->gpio_read, 0); +} + +static int rb91x_nand_dev_ready(struct mtd_info *mtd) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + return gpio_get_value_cansleep(rbni->gpio_rdy); +} + +static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + if (ctrl & NAND_CTRL_CHANGE) { + gpio_set_value_cansleep(rbni->gpio_cle, + (ctrl & NAND_CLE) ? 1 : 0); + gpio_set_value_cansleep(rbni->gpio_ale, + (ctrl & NAND_ALE) ? 1 : 0); + gpio_set_value_cansleep(rbni->gpio_nce, + (ctrl & NAND_NCE) ? 0 : 1); + } + + if (cmd != NAND_CMD_NONE) { + u8 t = cmd; + + rb91x_nand_write(rbni, &t, 1); + } +} + +static u8 rb91x_nand_read_byte(struct mtd_info *mtd) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + u8 data = 0xff; + + rb91x_nand_read(rbni, &data, 1); + + return data; +} + +static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + rb91x_nand_read(rbni, buf, len); +} + +static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + rb91x_nand_write(rbni, buf, len); +} + +static int rb91x_nand_gpio_init(struct rb91x_nand_info *info) +{ + int ret; + + /* + * Ensure that the LATCH is disabled before initializing + * control lines. + */ + ret = devm_gpio_request_one(info->dev, info->gpio_nle, + GPIOF_OUT_INIT_HIGH, "LATCH enable"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_nce, + GPIOF_OUT_INIT_HIGH, "NAND nCE"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_nrw, + GPIOF_OUT_INIT_HIGH, "NAND nRW"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_cle, + GPIOF_OUT_INIT_LOW, "NAND CLE"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_ale, + GPIOF_OUT_INIT_LOW, "NAND ALE"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_read, + GPIOF_OUT_INIT_LOW, "NAND READ"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_rdy, + GPIOF_IN, "NAND RDY"); + return ret; +} + +static int rb91x_nand_probe(struct platform_device *pdev) +{ + struct rb91x_nand_info *rbni; + struct rb91x_nand_platform_data *pdata; + int ret; + + pr_info(DRV_DESC "\n"); + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) + return -EINVAL; + + rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL); + if (!rbni) + return -ENOMEM; + + rbni->dev = &pdev->dev; + rbni->gpio_nce = pdata->gpio_nce; + rbni->gpio_ale = pdata->gpio_ale; + rbni->gpio_cle = pdata->gpio_cle; + rbni->gpio_read = pdata->gpio_read; + rbni->gpio_nrw = pdata->gpio_nrw; + rbni->gpio_rdy = pdata->gpio_rdy; + rbni->gpio_nle = pdata->gpio_nle; + + rbni->chip.priv = &rbni; + rbni->mtd.priv = &rbni->chip; + rbni->mtd.owner = THIS_MODULE; + + rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl; + rbni->chip.dev_ready = rb91x_nand_dev_ready; + rbni->chip.read_byte = rb91x_nand_read_byte; + rbni->chip.write_buf = rb91x_nand_write_buf; + rbni->chip.read_buf = rb91x_nand_read_buf; + + rbni->chip.chip_delay = 25; + rbni->chip.ecc.mode = NAND_ECC_SOFT; + + platform_set_drvdata(pdev, rbni); + + ret = rb91x_nand_gpio_init(rbni); + if (ret) + return ret; + + ret = nand_scan_ident(&rbni->mtd, 1, NULL); + if (ret) + return ret; + + if (rbni->mtd.writesize == 512) + rbni->chip.ecc.layout = &rb91x_nand_ecclayout; + + ret = nand_scan_tail(&rbni->mtd); + if (ret) + return ret; + + ret = mtd_device_register(&rbni->mtd, rb91x_nand_partitions, + ARRAY_SIZE(rb91x_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&rbni->mtd); + return ret; +} + +static int rb91x_nand_remove(struct platform_device *pdev) +{ + struct rb91x_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + + return 0; +} + +static struct platform_driver rb91x_nand_driver = { + .probe = rb91x_nand_probe, + .remove = rb91x_nand_remove, + .driver = { + .name = RB91X_NAND_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(rb91x_nand_driver); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c new file mode 100644 index 0000000..ac1efa1 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define TPLINK_NUM_PARTS 5 +#define TPLINK_HEADER_V1 0x01000000 +#define TPLINK_HEADER_V2 0x02000000 +#define MD5SUM_LEN 16 + +#define TPLINK_ART_LEN 0x10000 +#define TPLINK_KERNEL_OFFS 0x20000 +#define TPLINK_64K_KERNEL_OFFS 0x10000 + +struct tplink_fw_header { + uint32_t version; /* header version */ + char vendor_name[24]; + char fw_version[36]; + uint32_t hw_id; /* hardware id */ + uint32_t hw_rev; /* hardware revision */ + uint32_t unk1; + uint8_t md5sum1[MD5SUM_LEN]; + uint32_t unk2; + uint8_t md5sum2[MD5SUM_LEN]; + uint32_t unk3; + uint32_t kernel_la; /* kernel load address */ + uint32_t kernel_ep; /* kernel entry point */ + uint32_t fw_length; /* total length of the firmware */ + uint32_t kernel_ofs; /* kernel data offset */ + uint32_t kernel_len; /* kernel data length */ + uint32_t rootfs_ofs; /* rootfs data offset */ + uint32_t rootfs_len; /* rootfs data length */ + uint32_t boot_ofs; /* bootloader data offset */ + uint32_t boot_len; /* bootloader data length */ + uint8_t pad[360]; +} __attribute__ ((packed)); + +static struct tplink_fw_header * +tplink_read_header(struct mtd_info *mtd, size_t offset) +{ + struct tplink_fw_header *header; + size_t header_len; + size_t retlen; + int ret; + u32 t; + + header = vmalloc(sizeof(*header)); + if (!header) + goto err; + + header_len = sizeof(struct tplink_fw_header); + ret = mtd_read(mtd, offset, header_len, &retlen, + (unsigned char *) header); + if (ret) + goto err_free_header; + + if (retlen != header_len) + goto err_free_header; + + /* sanity checks */ + t = be32_to_cpu(header->version); + if ((t != TPLINK_HEADER_V1) && (t != TPLINK_HEADER_V2)) + goto err_free_header; + + t = be32_to_cpu(header->kernel_ofs); + if (t != header_len) + goto err_free_header; + + return header; + +err_free_header: + vfree(header); +err: + return NULL; +} + +static int tplink_check_rootfs_magic(struct mtd_info *mtd, size_t offset) +{ + u32 magic; + size_t retlen; + int ret; + + ret = mtd_read(mtd, offset, sizeof(magic), &retlen, + (unsigned char *) &magic); + if (ret) + return ret; + + if (retlen != sizeof(magic)) + return -EIO; + + if (le32_to_cpu(magic) != SQUASHFS_MAGIC && + magic != 0x19852003) + return -EINVAL; + + return 0; +} + +static int tplink_parse_partitions_offset(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data, + size_t offset) +{ + struct mtd_partition *parts; + struct tplink_fw_header *header; + int nr_parts; + size_t art_offset; + size_t rootfs_offset; + size_t squashfs_offset; + int ret; + + nr_parts = TPLINK_NUM_PARTS; + parts = kzalloc(nr_parts * sizeof(struct mtd_partition), GFP_KERNEL); + if (!parts) { + ret = -ENOMEM; + goto err; + } + + header = tplink_read_header(master, offset); + if (!header) { + pr_notice("%s: no TP-Link header found\n", master->name); + ret = -ENODEV; + goto err_free_parts; + } + + squashfs_offset = offset + sizeof(struct tplink_fw_header) + + be32_to_cpu(header->kernel_len); + + ret = tplink_check_rootfs_magic(master, squashfs_offset); + if (ret == 0) + rootfs_offset = squashfs_offset; + else + rootfs_offset = offset + be32_to_cpu(header->rootfs_ofs); + + art_offset = master->size - TPLINK_ART_LEN; + + parts[0].name = "u-boot"; + parts[0].offset = 0; + parts[0].size = offset; + parts[0].mask_flags = MTD_WRITEABLE; + + parts[1].name = "kernel"; + parts[1].offset = offset; + parts[1].size = rootfs_offset - offset; + + parts[2].name = "rootfs"; + parts[2].offset = rootfs_offset; + parts[2].size = art_offset - rootfs_offset; + + parts[3].name = "art"; + parts[3].offset = art_offset; + parts[3].size = TPLINK_ART_LEN; + parts[3].mask_flags = MTD_WRITEABLE; + + parts[4].name = "firmware"; + parts[4].offset = offset; + parts[4].size = art_offset - offset; + + vfree(header); + + *pparts = parts; + return nr_parts; + +err_free_parts: + kfree(parts); +err: + *pparts = NULL; + return ret; +} + +static int tplink_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return tplink_parse_partitions_offset(master, pparts, data, + TPLINK_KERNEL_OFFS); +} + +static int tplink_parse_64k_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return tplink_parse_partitions_offset(master, pparts, data, + TPLINK_64K_KERNEL_OFFS); +} + +static struct mtd_part_parser tplink_parser = { + .owner = THIS_MODULE, + .parse_fn = tplink_parse_partitions, + .name = "tp-link", +}; + +static struct mtd_part_parser tplink_64k_parser = { + .owner = THIS_MODULE, + .parse_fn = tplink_parse_64k_partitions, + .name = "tp-link-64k", +}; + +static int __init tplink_parser_init(void) +{ + register_mtd_parser(&tplink_parser); + register_mtd_parser(&tplink_64k_parser); + + return 0; +} + +module_init(tplink_parser_init); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); diff --git a/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c new file mode 100644 index 0000000..b9e9af3 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c @@ -0,0 +1,311 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips + * Copyright (c) 2009 Gabor Juhos + * + * This driver was base on: net/dsa/mv88e6060.c + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips + * Copyright (c) 2008-2009 Marvell Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#define REG_BASE 0x10 +#define REG_PHY(p) (REG_BASE + (p)) +#define REG_PORT(p) (REG_BASE + 8 + (p)) +#define REG_GLOBAL (REG_BASE + 0x0f) +#define NUM_PORTS 7 + +static int reg_read(struct dsa_switch *ds, int addr, int reg) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + return mdiobus_read(ds->master_mii_bus, addr, reg); +#else + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); + return mdiobus_read(bus, addr, reg); +#endif +} + +#define REG_READ(addr, reg) \ + ({ \ + int __ret; \ + \ + __ret = reg_read(ds, addr, reg); \ + if (__ret < 0) \ + return __ret; \ + __ret; \ + }) + + +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + return mdiobus_write(ds->master_mii_bus, addr, reg, val); +#else + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); + return mdiobus_write(bus, addr, reg, val); +#endif +} + +#define REG_WRITE(addr, reg, val) \ + ({ \ + int __ret; \ + \ + __ret = reg_write(ds, addr, reg, val); \ + if (__ret < 0) \ + return __ret; \ + }) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) +{ +#else +static char *mv88e6063_probe(struct device *host_dev, int sw_addr) +{ + struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); +#endif + int ret; + + ret = mdiobus_read(bus, REG_PORT(0), 0x03); + if (ret >= 0) { + ret &= 0xfff0; + if (ret == 0x1530) + return "Marvell 88E6063"; + } + + return NULL; +} + +static int mv88e6063_switch_reset(struct dsa_switch *ds) +{ + int i; + int ret; + + /* + * Set all ports to the disabled state. + */ + for (i = 0; i < NUM_PORTS; i++) { + ret = REG_READ(REG_PORT(i), 0x04); + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); + } + + /* + * Wait for transmit queues to drain. + */ + msleep(2); + + /* + * Reset the switch. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); + + /* + * Wait up to one second for reset to complete. + */ + for (i = 0; i < 1000; i++) { + ret = REG_READ(REG_GLOBAL, 0x00); + if ((ret & 0x8000) == 0x0000) + break; + + msleep(1); + } + if (i == 1000) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6063_setup_global(struct dsa_switch *ds) +{ + /* + * Disable discarding of frames with excessive collisions, + * set the maximum frame size to 1536 bytes, and mask all + * interrupt sources. + */ + REG_WRITE(REG_GLOBAL, 0x04, 0x0800); + + /* + * Enable automatic address learning, set the address + * database size to 1024 entries, and set the default aging + * time to 5 minutes. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); + + return 0; +} + +static int mv88e6063_setup_port(struct dsa_switch *ds, int p) +{ + int addr = REG_PORT(p); + + /* + * Do not force flow control, disable Ingress and Egress + * Header tagging, disable VLAN tunneling, and set the port + * state to Forwarding. Additionally, if this is the CPU + * port, enable Ingress and Egress Trailer tagging mode. + */ + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); + + /* + * Port based VLAN map: give each port its own address + * database, allow the CPU port to talk to each of the 'real' + * ports, and allow each of the 'real' ports to only talk to + * the CPU port. + */ + REG_WRITE(addr, 0x06, + ((p & 0xf) << 12) | + (dsa_is_cpu_port(ds, p) ? + ds->phys_port_mask : + (1 << ds->dst->cpu_port))); + + /* + * Port Association Vector: when learning source addresses + * of packets, add the address to the address database using + * a port bitmap that has only the bit for this port set and + * the other bits clear. + */ + REG_WRITE(addr, 0x0b, 1 << p); + + return 0; +} + +static int mv88e6063_setup(struct dsa_switch *ds) +{ + int i; + int ret; + + ret = mv88e6063_switch_reset(ds); + if (ret < 0) + return ret; + + /* @@@ initialise atu */ + + ret = mv88e6063_setup_global(ds); + if (ret < 0) + return ret; + + for (i = 0; i < NUM_PORTS; i++) { + ret = mv88e6063_setup_port(ds, i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) +{ + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); + + return 0; +} + +static int mv88e6063_port_to_phy_addr(int port) +{ + if (port >= 0 && port <= NUM_PORTS) + return REG_PHY(port); + return -1; +} + +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_read(ds, addr, regnum); +} + +static int +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_write(ds, addr, regnum, val); +} + +static void mv88e6063_poll_link(struct dsa_switch *ds) +{ + int i; + + for (i = 0; i < DSA_MAX_PORTS; i++) { + struct net_device *dev; + int uninitialized_var(port_status); + int link; + int speed; + int duplex; + int fc; + + dev = ds->ports[i]; + if (dev == NULL) + continue; + + link = 0; + if (dev->flags & IFF_UP) { + port_status = reg_read(ds, REG_PORT(i), 0x00); + if (port_status < 0) + continue; + + link = !!(port_status & 0x1000); + } + + if (!link) { + if (netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + continue; + } + + speed = (port_status & 0x0100) ? 100 : 10; + duplex = (port_status & 0x0200) ? 1 : 0; + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; + + if (!netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " + "flow control %sabled\n", dev->name, + speed, duplex ? "full" : "half", + fc ? "en" : "dis"); + netif_carrier_on(dev); + } + } +} + +static struct dsa_switch_driver mv88e6063_switch_driver = { + .tag_protocol = htons(ETH_P_TRAILER), + .probe = mv88e6063_probe, + .setup = mv88e6063_setup, + .set_addr = mv88e6063_set_addr, + .phy_read = mv88e6063_phy_read, + .phy_write = mv88e6063_phy_write, + .poll_link = mv88e6063_poll_link, +}; + +static int __init mv88e6063_init(void) +{ + register_switch_driver(&mv88e6063_switch_driver); + return 0; +} +module_init(mv88e6063_init); + +static void __exit mv88e6063_cleanup(void) +{ + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig new file mode 100644 index 0000000..42d544f --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig @@ -0,0 +1,33 @@ +config AG71XX + tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support" + depends on ATH79 + select PHYLIB + help + If you wish to compile a kernel for AR7XXX/91XXX and enable + ethernet support, then you should always answer Y to this. + +if AG71XX + +config AG71XX_DEBUG + bool "Atheros AR71xx built-in ethernet driver debugging" + default n + help + Atheros AR71xx built-in ethernet driver debugging messages. + +config AG71XX_DEBUG_FS + bool "Atheros AR71xx built-in ethernet driver debugfs support" + depends on DEBUG_FS + default n + help + Say Y, if you need access to various statistics provided by + the ag71xx driver. + +config AG71XX_AR8216_SUPPORT + bool "special support for the Atheros AR8216 switch" + default n + default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU + help + Say 'y' here if you want to enable special support for the + Atheros AR8216 switch found on some boards. + +endif diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile new file mode 100644 index 0000000..b3ec408 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the Atheros AR71xx built-in ethernet macs +# + +ag71xx-y += ag71xx_main.o +ag71xx-y += ag71xx_ethtool.o +ag71xx-y += ag71xx_phy.o +ag71xx-y += ag71xx_mdio.o +ag71xx-y += ag71xx_ar7240.o + +ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o +ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o + +obj-$(CONFIG_AG71XX) += ag71xx.o + diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h new file mode 100644 index 0000000..b18c20b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h @@ -0,0 +1,485 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __AG71XX_H +#define __AG71XX_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define AG71XX_DRV_NAME "ag71xx" +#define AG71XX_DRV_VERSION "0.5.35" + +#define AG71XX_NAPI_WEIGHT 64 +#define AG71XX_OOM_REFILL (1 + HZ/10) + +#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) +#define AG71XX_INT_TX (AG71XX_INT_TX_PS) +#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) + +#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) +#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) + +#define AG71XX_TX_MTU_LEN 1540 + +#define AG71XX_TX_RING_SPLIT 512 +#define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ + AG71XX_TX_RING_SPLIT) +#define AG71XX_TX_RING_SIZE_DEFAULT 48 +#define AG71XX_RX_RING_SIZE_DEFAULT 128 + +#define AG71XX_TX_RING_SIZE_MAX 48 +#define AG71XX_RX_RING_SIZE_MAX 128 + +#ifdef CONFIG_AG71XX_DEBUG +#define DBG(fmt, args...) pr_debug(fmt, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#define ag71xx_assert(_cond) \ +do { \ + if (_cond) \ + break; \ + printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ + BUG(); \ +} while (0) + +struct ag71xx_desc { + u32 data; + u32 ctrl; +#define DESC_EMPTY BIT(31) +#define DESC_MORE BIT(24) +#define DESC_PKTLEN_M 0xfff + u32 next; + u32 pad; +} __attribute__((aligned(4))); + +struct ag71xx_buf { + union { + struct sk_buff *skb; + void *rx_buf; + }; + union { + dma_addr_t dma_addr; + unsigned long timestamp; + }; + unsigned int len; +}; + +struct ag71xx_ring { + struct ag71xx_buf *buf; + u8 *descs_cpu; + dma_addr_t descs_dma; + u16 desc_split; + u16 desc_size; + unsigned int curr; + unsigned int dirty; + unsigned int size; +}; + +struct ag71xx_mdio { + struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + void __iomem *mdio_base; + struct ag71xx_mdio_platform_data *pdata; +}; + +struct ag71xx_int_stats { + unsigned long rx_pr; + unsigned long rx_be; + unsigned long rx_of; + unsigned long tx_ps; + unsigned long tx_be; + unsigned long tx_ur; + unsigned long total; +}; + +struct ag71xx_napi_stats { + unsigned long napi_calls; + unsigned long rx_count; + unsigned long rx_packets; + unsigned long rx_packets_max; + unsigned long tx_count; + unsigned long tx_packets; + unsigned long tx_packets_max; + + unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; + unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; +}; + +struct ag71xx_debug { + struct dentry *debugfs_dir; + + struct ag71xx_int_stats int_stats; + struct ag71xx_napi_stats napi_stats; +}; + +struct ag71xx { + void __iomem *mac_base; + + spinlock_t lock; + struct platform_device *pdev; + struct net_device *dev; + struct napi_struct napi; + u32 msg_enable; + + struct ag71xx_desc *stop_desc; + dma_addr_t stop_desc_dma; + + struct ag71xx_ring rx_ring; + struct ag71xx_ring tx_ring; + + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + void *phy_priv; + + unsigned int link; + unsigned int speed; + int duplex; + + unsigned int max_frame_len; + unsigned int desc_pktlen_mask; + unsigned int rx_buf_size; + + struct work_struct restart_work; + struct delayed_work link_work; + struct timer_list oom_timer; + +#ifdef CONFIG_AG71XX_DEBUG_FS + struct ag71xx_debug debug; +#endif +}; + +extern struct ethtool_ops ag71xx_ethtool_ops; +void ag71xx_link_adjust(struct ag71xx *ag); + +int ag71xx_mdio_driver_init(void) __init; +void ag71xx_mdio_driver_exit(void); + +int ag71xx_phy_connect(struct ag71xx *ag); +void ag71xx_phy_disconnect(struct ag71xx *ag); +void ag71xx_phy_start(struct ag71xx *ag); +void ag71xx_phy_stop(struct ag71xx *ag); + +static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) +{ + return ag->pdev->dev.platform_data; +} + +static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) +{ + return (desc->ctrl & DESC_EMPTY) != 0; +} + +static inline struct ag71xx_desc * +ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) +{ + return (struct ag71xx_desc *) &ring->descs_cpu[idx * ring->desc_size]; +} + +/* Register offsets */ +#define AG71XX_REG_MAC_CFG1 0x0000 +#define AG71XX_REG_MAC_CFG2 0x0004 +#define AG71XX_REG_MAC_IPG 0x0008 +#define AG71XX_REG_MAC_HDX 0x000c +#define AG71XX_REG_MAC_MFL 0x0010 +#define AG71XX_REG_MII_CFG 0x0020 +#define AG71XX_REG_MII_CMD 0x0024 +#define AG71XX_REG_MII_ADDR 0x0028 +#define AG71XX_REG_MII_CTRL 0x002c +#define AG71XX_REG_MII_STATUS 0x0030 +#define AG71XX_REG_MII_IND 0x0034 +#define AG71XX_REG_MAC_IFCTL 0x0038 +#define AG71XX_REG_MAC_ADDR1 0x0040 +#define AG71XX_REG_MAC_ADDR2 0x0044 +#define AG71XX_REG_FIFO_CFG0 0x0048 +#define AG71XX_REG_FIFO_CFG1 0x004c +#define AG71XX_REG_FIFO_CFG2 0x0050 +#define AG71XX_REG_FIFO_CFG3 0x0054 +#define AG71XX_REG_FIFO_CFG4 0x0058 +#define AG71XX_REG_FIFO_CFG5 0x005c +#define AG71XX_REG_FIFO_RAM0 0x0060 +#define AG71XX_REG_FIFO_RAM1 0x0064 +#define AG71XX_REG_FIFO_RAM2 0x0068 +#define AG71XX_REG_FIFO_RAM3 0x006c +#define AG71XX_REG_FIFO_RAM4 0x0070 +#define AG71XX_REG_FIFO_RAM5 0x0074 +#define AG71XX_REG_FIFO_RAM6 0x0078 +#define AG71XX_REG_FIFO_RAM7 0x007c + +#define AG71XX_REG_TX_CTRL 0x0180 +#define AG71XX_REG_TX_DESC 0x0184 +#define AG71XX_REG_TX_STATUS 0x0188 +#define AG71XX_REG_RX_CTRL 0x018c +#define AG71XX_REG_RX_DESC 0x0190 +#define AG71XX_REG_RX_STATUS 0x0194 +#define AG71XX_REG_INT_ENABLE 0x0198 +#define AG71XX_REG_INT_STATUS 0x019c + +#define AG71XX_REG_FIFO_DEPTH 0x01a8 +#define AG71XX_REG_RX_SM 0x01b0 +#define AG71XX_REG_TX_SM 0x01b4 + +#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ +#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ +#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ +#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ +#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ +#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ +#define MAC_CFG1_LB BIT(8) /* Loopback mode */ +#define MAC_CFG1_SR BIT(31) /* Soft Reset */ + +#define MAC_CFG2_FDX BIT(0) +#define MAC_CFG2_CRC_EN BIT(1) +#define MAC_CFG2_PAD_CRC_EN BIT(2) +#define MAC_CFG2_LEN_CHECK BIT(4) +#define MAC_CFG2_HUGE_FRAME_EN BIT(5) +#define MAC_CFG2_IF_1000 BIT(9) +#define MAC_CFG2_IF_10_100 BIT(8) + +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ + | FIFO_CFG0_TXS | FIFO_CFG0_TXF) + +#define FIFO_CFG0_ENABLE_SHIFT 8 + +#define FIFO_CFG4_DE BIT(0) /* Drop Event */ +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG4_FC BIT(2) /* False Carrier */ +#define FIFO_CFG4_CE BIT(3) /* Code Error */ +#define FIFO_CFG4_CR BIT(4) /* CRC error */ +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ +#define FIFO_CFG4_LO BIT(6) /* Length out of range */ +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ +#define FIFO_CFG4_DR BIT(10) /* Dribble */ +#define FIFO_CFG4_LE BIT(11) /* Long Event */ +#define FIFO_CFG4_CF BIT(12) /* Control Frame */ +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ + +#define FIFO_CFG5_DE BIT(0) /* Drop Event */ +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG5_FC BIT(2) /* False Carrier */ +#define FIFO_CFG5_CE BIT(3) /* Code Error */ +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ +#define FIFO_CFG5_DR BIT(9) /* Dribble */ +#define FIFO_CFG5_CF BIT(10) /* Control Frame */ +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ +#define FIFO_CFG5_LE BIT(14) /* Long Event */ +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ +#define FIFO_CFG5_16 BIT(16) /* unknown */ +#define FIFO_CFG5_17 BIT(17) /* unknown */ +#define FIFO_CFG5_SF BIT(18) /* Short Frame */ +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ + +#define AG71XX_INT_TX_PS BIT(0) +#define AG71XX_INT_TX_UR BIT(1) +#define AG71XX_INT_TX_BE BIT(3) +#define AG71XX_INT_RX_PR BIT(4) +#define AG71XX_INT_RX_OF BIT(6) +#define AG71XX_INT_RX_BE BIT(7) + +#define MAC_IFCTL_SPEED BIT(16) + +#define MII_CFG_CLK_DIV_4 0 +#define MII_CFG_CLK_DIV_6 2 +#define MII_CFG_CLK_DIV_8 3 +#define MII_CFG_CLK_DIV_10 4 +#define MII_CFG_CLK_DIV_14 5 +#define MII_CFG_CLK_DIV_20 6 +#define MII_CFG_CLK_DIV_28 7 +#define MII_CFG_CLK_DIV_34 8 +#define MII_CFG_CLK_DIV_42 9 +#define MII_CFG_CLK_DIV_50 10 +#define MII_CFG_CLK_DIV_58 11 +#define MII_CFG_CLK_DIV_66 12 +#define MII_CFG_CLK_DIV_74 13 +#define MII_CFG_CLK_DIV_82 14 +#define MII_CFG_CLK_DIV_98 15 +#define MII_CFG_RESET BIT(31) + +#define MII_CMD_WRITE 0x0 +#define MII_CMD_READ 0x1 +#define MII_ADDR_SHIFT 8 +#define MII_IND_BUSY BIT(0) +#define MII_IND_INVALID BIT(2) + +#define TX_CTRL_TXE BIT(0) /* Tx Enable */ + +#define TX_STATUS_PS BIT(0) /* Packet Sent */ +#define TX_STATUS_UR BIT(1) /* Tx Underrun */ +#define TX_STATUS_BE BIT(3) /* Bus Error */ + +#define RX_CTRL_RXE BIT(0) /* Rx Enable */ + +#define RX_STATUS_PR BIT(0) /* Packet Received */ +#define RX_STATUS_OF BIT(2) /* Rx Overflow */ +#define RX_STATUS_BE BIT(3) /* Bus Error */ + +static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) +{ + switch (reg) { + case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: + case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM: + case AG71XX_REG_MII_CFG: + break; + + default: + BUG(); + } +} + +static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) +{ + ag71xx_check_reg_offset(ag, reg); + + __raw_writel(value, ag->mac_base + reg); + /* flush write */ + (void) __raw_readl(ag->mac_base + reg); +} + +static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) +{ + ag71xx_check_reg_offset(ag, reg); + + return __raw_readl(ag->mac_base + reg); +} + +static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) +{ + void __iomem *r; + + ag71xx_check_reg_offset(ag, reg); + + r = ag->mac_base + reg; + __raw_writel(__raw_readl(r) | mask, r); + /* flush write */ + (void)__raw_readl(r); +} + +static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) +{ + void __iomem *r; + + ag71xx_check_reg_offset(ag, reg); + + r = ag->mac_base + reg; + __raw_writel(__raw_readl(r) & ~mask, r); + /* flush write */ + (void) __raw_readl(r); +} + +static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) +{ + ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); +} + +static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) +{ + ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); +} + +#ifdef CONFIG_AG71XX_AR8216_SUPPORT +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, + int pktlen); +static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ + return ag71xx_get_pdata(ag)->has_ar8216; +} +#else +static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, + struct sk_buff *skb) +{ +} + +static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, + struct sk_buff *skb, + int pktlen) +{ + return 0; +} +static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ + return 0; +} +#endif + +#ifdef CONFIG_AG71XX_DEBUG_FS +int ag71xx_debugfs_root_init(void); +void ag71xx_debugfs_root_exit(void); +int ag71xx_debugfs_init(struct ag71xx *ag); +void ag71xx_debugfs_exit(struct ag71xx *ag); +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); +#else +static inline int ag71xx_debugfs_root_init(void) { return 0; } +static inline void ag71xx_debugfs_root_exit(void) {} +static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } +static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} +static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, + u32 status) {} +static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, + int rx, int tx) {} +#endif /* CONFIG_AG71XX_DEBUG_FS */ + +void ag71xx_ar7240_start(struct ag71xx *ag); +void ag71xx_ar7240_stop(struct ag71xx *ag); +int ag71xx_ar7240_init(struct ag71xx *ag); +void ag71xx_ar7240_cleanup(struct ag71xx *ag); + +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg); +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val); + +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr); +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr, u16 reg_val); + +#endif /* _AG71XX_H */ diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c new file mode 100644 index 0000000..8dfff3b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c @@ -0,0 +1,1229 @@ +/* + * Driver for the built-in ethernet switch of the Atheros AR7240 SoC + * Copyright (c) 2010 Gabor Juhos + * Copyright (c) 2010 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ag71xx.h" + +#define BITM(_count) (BIT(_count) - 1) +#define BITS(_shift, _count) (BITM(_count) << _shift) + +#define AR7240_REG_MASK_CTRL 0x00 +#define AR7240_MASK_CTRL_REVISION_M BITM(8) +#define AR7240_MASK_CTRL_VERSION_M BITM(8) +#define AR7240_MASK_CTRL_VERSION_S 8 +#define AR7240_MASK_CTRL_VERSION_AR7240 0x01 +#define AR7240_MASK_CTRL_VERSION_AR934X 0x02 +#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) + +#define AR7240_REG_MAC_ADDR0 0x20 +#define AR7240_REG_MAC_ADDR1 0x24 + +#define AR7240_REG_FLOOD_MASK 0x2c +#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) + +#define AR7240_REG_GLOBAL_CTRL 0x30 +#define AR7240_GLOBAL_CTRL_MTU_M BITM(11) +#define AR9340_GLOBAL_CTRL_MTU_M BITM(14) + +#define AR7240_REG_VTU 0x0040 +#define AR7240_VTU_OP BITM(3) +#define AR7240_VTU_OP_NOOP 0x0 +#define AR7240_VTU_OP_FLUSH 0x1 +#define AR7240_VTU_OP_LOAD 0x2 +#define AR7240_VTU_OP_PURGE 0x3 +#define AR7240_VTU_OP_REMOVE_PORT 0x4 +#define AR7240_VTU_ACTIVE BIT(3) +#define AR7240_VTU_FULL BIT(4) +#define AR7240_VTU_PORT BITS(8, 4) +#define AR7240_VTU_PORT_S 8 +#define AR7240_VTU_VID BITS(16, 12) +#define AR7240_VTU_VID_S 16 +#define AR7240_VTU_PRIO BITS(28, 3) +#define AR7240_VTU_PRIO_S 28 +#define AR7240_VTU_PRIO_EN BIT(31) + +#define AR7240_REG_VTU_DATA 0x0044 +#define AR7240_VTUDATA_MEMBER BITS(0, 10) +#define AR7240_VTUDATA_VALID BIT(11) + +#define AR7240_REG_ATU 0x50 +#define AR7240_ATU_FLUSH_ALL 0x1 + +#define AR7240_REG_AT_CTRL 0x5c +#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR7240_AT_CTRL_AGE_EN BIT(17) +#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18) +#define AR7240_AT_CTRL_RESERVED BIT(19) +#define AR7240_AT_CTRL_ARP_EN BIT(20) + +#define AR7240_REG_TAG_PRIORITY 0x70 + +#define AR7240_REG_SERVICE_TAG 0x74 +#define AR7240_SERVICE_TAG_M BITM(16) + +#define AR7240_REG_CPU_PORT 0x78 +#define AR7240_MIRROR_PORT_S 4 +#define AR7240_CPU_PORT_EN BIT(8) + +#define AR7240_REG_MIB_FUNCTION0 0x80 +#define AR7240_MIB_TIMER_M BITM(16) +#define AR7240_MIB_AT_HALF_EN BIT(16) +#define AR7240_MIB_BUSY BIT(17) +#define AR7240_MIB_FUNC_S 24 +#define AR7240_MIB_FUNC_M BITM(3) +#define AR7240_MIB_FUNC_NO_OP 0x0 +#define AR7240_MIB_FUNC_FLUSH 0x1 +#define AR7240_MIB_FUNC_CAPTURE 0x3 + +#define AR7240_REG_MDIO_CTRL 0x98 +#define AR7240_MDIO_CTRL_DATA_M BITM(16) +#define AR7240_MDIO_CTRL_REG_ADDR_S 16 +#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 +#define AR7240_MDIO_CTRL_CMD_WRITE 0 +#define AR7240_MDIO_CTRL_CMD_READ BIT(27) +#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) +#define AR7240_MDIO_CTRL_BUSY BIT(31) + +#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) +#define AR7240_PORT_STATUS_SPEED_S 0 +#define AR7240_PORT_STATUS_SPEED_M BITM(2) +#define AR7240_PORT_STATUS_SPEED_10 0 +#define AR7240_PORT_STATUS_SPEED_100 1 +#define AR7240_PORT_STATUS_SPEED_1000 2 +#define AR7240_PORT_STATUS_TXMAC BIT(2) +#define AR7240_PORT_STATUS_RXMAC BIT(3) +#define AR7240_PORT_STATUS_TXFLOW BIT(4) +#define AR7240_PORT_STATUS_RXFLOW BIT(5) +#define AR7240_PORT_STATUS_DUPLEX BIT(6) +#define AR7240_PORT_STATUS_LINK_UP BIT(8) +#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) +#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) + +#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) +#define AR7240_PORT_CTRL_STATE_M BITM(3) +#define AR7240_PORT_CTRL_STATE_DISABLED 0 +#define AR7240_PORT_CTRL_STATE_BLOCK 1 +#define AR7240_PORT_CTRL_STATE_LISTEN 2 +#define AR7240_PORT_CTRL_STATE_LEARN 3 +#define AR7240_PORT_CTRL_STATE_FORWARD 4 +#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) +#define AR7240_PORT_CTRL_VLAN_MODE_S 8 +#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 +#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 +#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 +#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 +#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) +#define AR7240_PORT_CTRL_HEADER BIT(11) +#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) +#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) +#define AR7240_PORT_CTRL_LEARN BIT(14) +#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) +#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) +#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) + +#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) + +#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 +#define AR7240_PORT_VLAN_DEST_PORTS_S 16 +#define AR7240_PORT_VLAN_MODE_S 30 +#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0 +#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1 +#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2 +#define AR7240_PORT_VLAN_MODE_SECURE 3 + + +#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) + +#define AR7240_STATS_RXBROAD 0x00 +#define AR7240_STATS_RXPAUSE 0x04 +#define AR7240_STATS_RXMULTI 0x08 +#define AR7240_STATS_RXFCSERR 0x0c +#define AR7240_STATS_RXALIGNERR 0x10 +#define AR7240_STATS_RXRUNT 0x14 +#define AR7240_STATS_RXFRAGMENT 0x18 +#define AR7240_STATS_RX64BYTE 0x1c +#define AR7240_STATS_RX128BYTE 0x20 +#define AR7240_STATS_RX256BYTE 0x24 +#define AR7240_STATS_RX512BYTE 0x28 +#define AR7240_STATS_RX1024BYTE 0x2c +#define AR7240_STATS_RX1518BYTE 0x30 +#define AR7240_STATS_RXMAXBYTE 0x34 +#define AR7240_STATS_RXTOOLONG 0x38 +#define AR7240_STATS_RXGOODBYTE 0x3c +#define AR7240_STATS_RXBADBYTE 0x44 +#define AR7240_STATS_RXOVERFLOW 0x4c +#define AR7240_STATS_FILTERED 0x50 +#define AR7240_STATS_TXBROAD 0x54 +#define AR7240_STATS_TXPAUSE 0x58 +#define AR7240_STATS_TXMULTI 0x5c +#define AR7240_STATS_TXUNDERRUN 0x60 +#define AR7240_STATS_TX64BYTE 0x64 +#define AR7240_STATS_TX128BYTE 0x68 +#define AR7240_STATS_TX256BYTE 0x6c +#define AR7240_STATS_TX512BYTE 0x70 +#define AR7240_STATS_TX1024BYTE 0x74 +#define AR7240_STATS_TX1518BYTE 0x78 +#define AR7240_STATS_TXMAXBYTE 0x7c +#define AR7240_STATS_TXOVERSIZE 0x80 +#define AR7240_STATS_TXBYTE 0x84 +#define AR7240_STATS_TXCOLLISION 0x8c +#define AR7240_STATS_TXABORTCOL 0x90 +#define AR7240_STATS_TXMULTICOL 0x94 +#define AR7240_STATS_TXSINGLECOL 0x98 +#define AR7240_STATS_TXEXCDEFER 0x9c +#define AR7240_STATS_TXDEFER 0xa0 +#define AR7240_STATS_TXLATECOL 0xa4 + +#define AR7240_PORT_CPU 0 +#define AR7240_NUM_PORTS 6 +#define AR7240_NUM_PHYS 5 + +#define AR7240_PHY_ID1 0x004d +#define AR7240_PHY_ID2 0xd041 + +#define AR934X_PHY_ID1 0x004d +#define AR934X_PHY_ID2 0xd042 + +#define AR7240_MAX_VLANS 16 + +#define AR934X_REG_OPER_MODE0 0x04 +#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6) +#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10) + +#define AR934X_REG_OPER_MODE1 0x08 +#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28) + +#define AR934X_REG_FLOOD_MASK 0x2c +#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p)) +#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p)) + +#define AR934X_REG_QM_CTRL 0x3c +#define AR934X_QM_CTRL_ARP_EN BIT(15) + +#define AR934X_REG_AT_CTRL 0x5c +#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR934X_AT_CTRL_AGE_EN BIT(17) +#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18) + +#define AR934X_MIB_ENABLE BIT(30) + +#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) +#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 +#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12) +#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13) +#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14) +#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15) +#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 +#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28) +#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 + +#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) +#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 +#define AR934X_PORT_VLAN2_8021Q_MODE_S 30 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 +#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 +#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 + +#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev) + +struct ar7240sw_port_stat { + unsigned long rx_broadcast; + unsigned long rx_pause; + unsigned long rx_multicast; + unsigned long rx_fcs_error; + unsigned long rx_align_error; + unsigned long rx_runt; + unsigned long rx_fragments; + unsigned long rx_64byte; + unsigned long rx_128byte; + unsigned long rx_256byte; + unsigned long rx_512byte; + unsigned long rx_1024byte; + unsigned long rx_1518byte; + unsigned long rx_maxbyte; + unsigned long rx_toolong; + unsigned long rx_good_byte; + unsigned long rx_bad_byte; + unsigned long rx_overflow; + unsigned long filtered; + + unsigned long tx_broadcast; + unsigned long tx_pause; + unsigned long tx_multicast; + unsigned long tx_underrun; + unsigned long tx_64byte; + unsigned long tx_128byte; + unsigned long tx_256byte; + unsigned long tx_512byte; + unsigned long tx_1024byte; + unsigned long tx_1518byte; + unsigned long tx_maxbyte; + unsigned long tx_oversize; + unsigned long tx_byte; + unsigned long tx_collision; + unsigned long tx_abortcol; + unsigned long tx_multicol; + unsigned long tx_singlecol; + unsigned long tx_excdefer; + unsigned long tx_defer; + unsigned long tx_xlatecol; +}; + +struct ar7240sw { + struct mii_bus *mii_bus; + struct ag71xx_switch_platform_data *swdata; + struct switch_dev swdev; + int num_ports; + u8 ver; + bool vlan; + u16 vlan_id[AR7240_MAX_VLANS]; + u8 vlan_table[AR7240_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[AR7240_NUM_PORTS]; + char buf[80]; + + rwlock_t stats_lock; + struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS]; +}; + +struct ar7240sw_hw_stat { + char string[ETH_GSTRING_LEN]; + int sizeof_stat; + int reg; +}; + +static DEFINE_MUTEX(reg_mutex); + +static inline int sw_is_ar7240(struct ar7240sw *as) +{ + return as->ver == AR7240_MASK_CTRL_VERSION_AR7240; +} + +static inline int sw_is_ar934x(struct ar7240sw *as) +{ + return as->ver == AR7240_MASK_CTRL_VERSION_AR934X; +} + +static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port) +{ + return BIT(port); +} + +static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as) +{ + return BIT(as->swdev.ports) - 1; +} + +static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port) +{ + return ar7240sw_port_mask_all(as) & ~BIT(port); +} + +static inline u16 mk_phy_addr(u32 reg) +{ + return 0x17 & ((reg >> 4) | 0x10); +} + +static inline u16 mk_phy_reg(u32 reg) +{ + return (reg << 1) & 0x1e; +} + +static inline u16 mk_high_addr(u32 reg) +{ + return (reg >> 7) & 0x1ff; +} + +static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg) +{ + unsigned long flags; + u16 phy_addr; + u16 phy_reg; + u32 hi, lo; + + reg = (reg & 0xfffffffc) >> 2; + phy_addr = mk_phy_addr(reg); + phy_reg = mk_phy_reg(reg); + + local_irq_save(flags); + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); + lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg); + hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1); + local_irq_restore(flags); + + return (hi << 16) | lo; +} + +static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val) +{ + unsigned long flags; + u16 phy_addr; + u16 phy_reg; + + reg = (reg & 0xfffffffc) >> 2; + phy_addr = mk_phy_addr(reg); + phy_reg = mk_phy_reg(reg); + + local_irq_save(flags); + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16)); + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff)); + local_irq_restore(flags); +} + +static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr) +{ + u32 ret; + + mutex_lock(®_mutex); + ret = __ar7240sw_reg_read(mii, reg_addr); + mutex_unlock(®_mutex); + + return ret; +} + +static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val) +{ + mutex_lock(®_mutex); + __ar7240sw_reg_write(mii, reg_addr, reg_val); + mutex_unlock(®_mutex); +} + +static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val) +{ + u32 t; + + mutex_lock(®_mutex); + t = __ar7240sw_reg_read(mii, reg); + t &= ~mask; + t |= val; + __ar7240sw_reg_write(mii, reg, t); + mutex_unlock(®_mutex); + + return t; +} + +static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val) +{ + u32 t; + + mutex_lock(®_mutex); + t = __ar7240sw_reg_read(mii, reg); + t |= val; + __ar7240sw_reg_write(mii, reg, t); + mutex_unlock(®_mutex); +} + +static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int i; + + for (i = 0; i < timeout; i++) { + u32 t; + + t = __ar7240sw_reg_read(mii, reg); + if ((t & mask) == val) + return 0; + + usleep_range(1000, 2000); + } + + return -ETIMEDOUT; +} + +static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int ret; + + mutex_lock(®_mutex); + ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout); + mutex_unlock(®_mutex); + return ret; +} + +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr) +{ + u32 t, val = 0xffff; + int err; + + if (phy_addr >= AR7240_NUM_PHYS) + return 0xffff; + + mutex_lock(®_mutex); + t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | + (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | + AR7240_MDIO_CTRL_MASTER_EN | + AR7240_MDIO_CTRL_BUSY | + AR7240_MDIO_CTRL_CMD_READ; + + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); + err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, + AR7240_MDIO_CTRL_BUSY, 0, 5); + if (!err) + val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL); + mutex_unlock(®_mutex); + + return val & AR7240_MDIO_CTRL_DATA_M; +} + +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr, u16 reg_val) +{ + u32 t; + int ret; + + if (phy_addr >= AR7240_NUM_PHYS) + return -EINVAL; + + mutex_lock(®_mutex); + t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | + (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | + AR7240_MDIO_CTRL_MASTER_EN | + AR7240_MDIO_CTRL_BUSY | + AR7240_MDIO_CTRL_CMD_WRITE | + reg_val; + + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); + ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, + AR7240_MDIO_CTRL_BUSY, 0, 5); + mutex_unlock(®_mutex); + + return ret; +} + +static int ar7240sw_capture_stats(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + int port; + int ret; + + write_lock(&as->stats_lock); + + /* Capture the hardware statistics for all ports */ + ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0, + (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S), + (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); + + /* Wait for the capturing to complete. */ + ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0, + AR7240_MIB_BUSY, 0, 10); + + if (ret) + goto unlock; + + for (port = 0; port < AR7240_NUM_PORTS; port++) { + unsigned int base; + struct ar7240sw_port_stat *stats; + + base = AR7240_REG_STATS_BASE(port); + stats = &as->port_stats[port]; + +#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r) + + stats->rx_good_byte += READ_STAT(RXGOODBYTE); + stats->tx_byte += READ_STAT(TXBYTE); + +#undef READ_STAT + } + + ret = 0; + +unlock: + write_unlock(&as->stats_lock); + return ret; +} + +static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) +{ + ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port), + AR7240_PORT_CTRL_STATE_DISABLED); +} + +static void ar7240sw_setup(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + + /* Enable CPU port, and disable mirror port */ + ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT, + AR7240_CPU_PORT_EN | + (15 << AR7240_MIRROR_PORT_S)); + + /* Setup TAG priority mapping */ + ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); + + if (sw_is_ar934x(as)) { + /* Enable aging, MAC replacing */ + ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL, + 0x2b /* 5 min age time */ | + AR934X_AT_CTRL_AGE_EN | + AR934X_AT_CTRL_LEARN_CHANGE); + /* Enable ARP frame acknowledge */ + ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL, + AR934X_QM_CTRL_ARP_EN); + /* Enable Broadcast/Multicast frames transmitted to the CPU */ + ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK, + AR934X_FLOOD_MASK_BC_DP(0) | + AR934X_FLOOD_MASK_MC_DP(0)); + + /* setup MTU */ + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, + AR9340_GLOBAL_CTRL_MTU_M, + AR9340_GLOBAL_CTRL_MTU_M); + + /* Enable MIB counters */ + ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0, + AR934X_MIB_ENABLE); + + } else { + /* Enable ARP frame acknowledge, aging, MAC replacing */ + ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, + AR7240_AT_CTRL_RESERVED | + 0x2b /* 5 min age time */ | + AR7240_AT_CTRL_AGE_EN | + AR7240_AT_CTRL_ARP_EN | + AR7240_AT_CTRL_LEARN_CHANGE); + /* Enable Broadcast frames transmitted to the CPU */ + ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, + AR7240_FLOOD_MASK_BROAD_TO_CPU); + + /* setup MTU */ + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, + AR7240_GLOBAL_CTRL_MTU_M, + AR7240_GLOBAL_CTRL_MTU_M); + } + + /* setup Service TAG */ + ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0); +} + +/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */ +static int +ar7240sw_phy_poll_reset(struct mii_bus *bus) +{ + const unsigned int sleep_msecs = 20; + int ret, elapsed, i; + + for (elapsed = sleep_msecs; elapsed <= 600; + elapsed += sleep_msecs) { + msleep(sleep_msecs); + for (i = 0; i < AR7240_NUM_PHYS; i++) { + ret = ar7240sw_phy_read(bus, i, MII_BMCR); + if (ret < 0) + return ret; + if (ret & BMCR_RESET) + break; + if (i == AR7240_NUM_PHYS - 1) { + usleep_range(1000, 2000); + return 0; + } + } + } + return -ETIMEDOUT; +} + +static int ar7240sw_reset(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + int ret; + int i; + + /* Set all ports to disabled state. */ + for (i = 0; i < AR7240_NUM_PORTS; i++) + ar7240sw_disable_port(as, i); + + /* Wait for transmit queues to drain. */ + usleep_range(2000, 3000); + + /* Reset the switch. */ + ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, + AR7240_MASK_CTRL_SOFT_RESET); + + ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, + AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); + + /* setup PHYs */ + for (i = 0; i < AR7240_NUM_PHYS; i++) { + ar7240sw_phy_write(mii, i, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + ar7240sw_phy_write(mii, i, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); + } + ret = ar7240sw_phy_poll_reset(mii); + if (ret) + return ret; + + ar7240sw_setup(as); + return ret; +} + +static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask) +{ + struct mii_bus *mii = as->mii_bus; + u32 ctrl; + u32 vid, mode; + + ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN | + AR7240_PORT_CTRL_SINGLE_VLAN; + + if (port == AR7240_PORT_CPU) { + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), + AR7240_PORT_STATUS_SPEED_1000 | + AR7240_PORT_STATUS_TXFLOW | + AR7240_PORT_STATUS_RXFLOW | + AR7240_PORT_STATUS_TXMAC | + AR7240_PORT_STATUS_RXMAC | + AR7240_PORT_STATUS_DUPLEX); + } else { + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), + AR7240_PORT_STATUS_LINK_AUTO); + } + + /* Set the default VID for this port */ + if (as->vlan) { + vid = as->vlan_id[as->pvid[port]]; + mode = AR7240_PORT_VLAN_MODE_SECURE; + } else { + vid = port; + mode = AR7240_PORT_VLAN_MODE_PORT_ONLY; + } + + if (as->vlan) { + if (as->vlan_tagged & BIT(port)) + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD << + AR7240_PORT_CTRL_VLAN_MODE_S; + else + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP << + AR7240_PORT_CTRL_VLAN_MODE_S; + } else { + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP << + AR7240_PORT_CTRL_VLAN_MODE_S; + } + + if (!portmask) { + if (port == AR7240_PORT_CPU) + portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU); + else + portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU); + } + + /* allow the port to talk to all other ports, but exclude its + * own ID to prevent frames from being reflected back to the + * port that they came from */ + portmask &= ar7240sw_port_mask_but(as, port); + + ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl); + if (sw_is_ar934x(as)) { + u32 vlan1, vlan2; + + vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S); + vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) | + (mode << AR934X_PORT_VLAN2_8021Q_MODE_S); + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1); + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2); + } else { + u32 vlan; + + vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) | + (portmask << AR7240_PORT_VLAN_DEST_PORTS_S); + + ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan); + } +} + +static int ar7240_set_addr(struct ar7240sw *as, u8 *addr) +{ + struct mii_bus *mii = as->mii_bus; + u32 t; + + t = (addr[4] << 8) | addr[5]; + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t); + + t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t); + + return 0; +} + +static int +ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + as->vlan_id[val->port_vlan] = val->value.i; + return 0; +} + +static int +ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + val->value.i = as->vlan_id[val->port_vlan]; + return 0; +} + +static int +ar7240_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + + /* make sure no invalid PVIDs get set */ + + if (vlan >= dev->vlans) + return -EINVAL; + + as->pvid[port] = vlan; + return 0; +} + +static int +ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + *vlan = as->pvid[port]; + return 0; +} + +static int +ar7240_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 ports = as->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < as->swdev.ports; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (as->vlan_tagged & (1 << i)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int +ar7240_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 *vt = &as->vlan_table[val->port_vlan]; + int i, j; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) + as->vlan_tagged |= (1 << p->id); + else { + as->vlan_tagged &= ~(1 << p->id); + as->pvid[p->id] = val->port_vlan; + + /* make sure that an untagged port does not + * appear in other vlans */ + for (j = 0; j < AR7240_MAX_VLANS; j++) { + if (j == val->port_vlan) + continue; + as->vlan_table[j] &= ~(1 << p->id); + } + } + + *vt |= 1 << p->id; + } + return 0; +} + +static int +ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + as->vlan = !!val->value.i; + return 0; +} + +static int +ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + val->value.i = as->vlan; + return 0; +} + +static void +ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val) +{ + struct mii_bus *mii = as->mii_bus; + + if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5)) + return; + + if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) { + val &= AR7240_VTUDATA_MEMBER; + val |= AR7240_VTUDATA_VALID; + ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val); + } + op |= AR7240_VTU_ACTIVE; + ar7240sw_reg_write(mii, AR7240_REG_VTU, op); +} + +static int +ar7240_hw_apply(struct switch_dev *dev) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 portmask[AR7240_NUM_PORTS]; + int i, j; + + /* flush all vlan translation unit entries */ + ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0); + + memset(portmask, 0, sizeof(portmask)); + if (as->vlan) { + /* calculate the port destination masks and load vlans + * into the vlan translation unit */ + for (j = 0; j < AR7240_MAX_VLANS; j++) { + u8 vp = as->vlan_table[j]; + + if (!vp) + continue; + + for (i = 0; i < as->swdev.ports; i++) { + u8 mask = (1 << i); + if (vp & mask) + portmask[i] |= vp & ~mask; + } + + ar7240_vtu_op(as, + AR7240_VTU_OP_LOAD | + (as->vlan_id[j] << AR7240_VTU_VID_S), + as->vlan_table[j]); + } + } else { + /* vlan disabled: + * isolate all ports, but connect them to the cpu port */ + for (i = 0; i < as->swdev.ports; i++) { + if (i == AR7240_PORT_CPU) + continue; + + portmask[i] = 1 << AR7240_PORT_CPU; + portmask[AR7240_PORT_CPU] |= (1 << i); + } + } + + /* update the port destination mask registers and tag settings */ + for (i = 0; i < as->swdev.ports; i++) + ar7240sw_setup_port(as, i, portmask[i]); + + return 0; +} + +static int +ar7240_reset_switch(struct switch_dev *dev) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + ar7240sw_reset(as); + return 0; +} + +static int +ar7240_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + struct mii_bus *mii = as->mii_bus; + u32 status; + + if (port > AR7240_NUM_PORTS) + return -EINVAL; + + status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port)); + link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO); + if (link->aneg) { + link->link = !!(status & AR7240_PORT_STATUS_LINK_UP); + if (!link->link) + return 0; + } else { + link->link = true; + } + + link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX); + link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW); + link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW); + switch (status & AR7240_PORT_STATUS_SPEED_M) { + case AR7240_PORT_STATUS_SPEED_10: + link->speed = SWITCH_PORT_SPEED_10; + break; + case AR7240_PORT_STATUS_SPEED_100: + link->speed = SWITCH_PORT_SPEED_100; + break; + case AR7240_PORT_STATUS_SPEED_1000: + link->speed = SWITCH_PORT_SPEED_1000; + break; + } + + return 0; +} + +static int +ar7240_get_port_stats(struct switch_dev *dev, int port, + struct switch_port_stats *stats) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + + if (port > AR7240_NUM_PORTS) + return -EINVAL; + + ar7240sw_capture_stats(as); + + read_lock(&as->stats_lock); + stats->rx_bytes = as->port_stats[port].rx_good_byte; + stats->tx_bytes = as->port_stats[port].tx_byte; + read_unlock(&as->stats_lock); + + return 0; +} + +static struct switch_attr ar7240_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = ar7240_set_vlan, + .get = ar7240_get_vlan, + .max = 1 + }, +}; + +static struct switch_attr ar7240_port[] = { +}; + +static struct switch_attr ar7240_vlan[] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID", + .set = ar7240_set_vid, + .get = ar7240_get_vid, + .max = 4094, + }, +}; + +static const struct switch_dev_ops ar7240_ops = { + .attr_global = { + .attr = ar7240_globals, + .n_attr = ARRAY_SIZE(ar7240_globals), + }, + .attr_port = { + .attr = ar7240_port, + .n_attr = ARRAY_SIZE(ar7240_port), + }, + .attr_vlan = { + .attr = ar7240_vlan, + .n_attr = ARRAY_SIZE(ar7240_vlan), + }, + .get_port_pvid = ar7240_get_pvid, + .set_port_pvid = ar7240_set_pvid, + .get_vlan_ports = ar7240_get_ports, + .set_vlan_ports = ar7240_set_ports, + .apply_config = ar7240_hw_apply, + .reset_switch = ar7240_reset_switch, + .get_port_link = ar7240_get_port_link, + .get_port_stats = ar7240_get_port_stats, +}; + +static struct ar7240sw *ar7240_probe(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct mii_bus *mii = ag->mii_bus; + struct ar7240sw *as; + struct switch_dev *swdev; + u32 ctrl; + u16 phy_id1; + u16 phy_id2; + int i; + + phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1); + phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2); + if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) && + (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) { + pr_err("%s: unknown phy id '%04x:%04x'\n", + dev_name(&mii->dev), phy_id1, phy_id2); + return NULL; + } + + as = kzalloc(sizeof(*as), GFP_KERNEL); + if (!as) + return NULL; + + as->mii_bus = mii; + as->swdata = pdata->switch_data; + + swdev = &as->swdev; + + ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL); + as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & + AR7240_MASK_CTRL_VERSION_M; + + if (sw_is_ar7240(as)) { + swdev->name = "AR7240/AR9330 built-in switch"; + swdev->ports = AR7240_NUM_PORTS - 1; + } else if (sw_is_ar934x(as)) { + swdev->name = "AR934X built-in switch"; + + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, + AR934X_OPER_MODE0_MAC_GMII_EN); + } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, + AR934X_OPER_MODE0_PHY_MII_EN); + } else { + pr_err("%s: invalid PHY interface mode\n", + dev_name(&mii->dev)); + goto err_free; + } + + if (as->swdata->phy4_mii_en) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1, + AR934X_REG_OPER_MODE1_PHY4_MII_EN); + swdev->ports = AR7240_NUM_PORTS - 1; + } else { + swdev->ports = AR7240_NUM_PORTS; + } + } else { + pr_err("%s: unsupported chip, ctrl=%08x\n", + dev_name(&mii->dev), ctrl); + goto err_free; + } + + swdev->cpu_port = AR7240_PORT_CPU; + swdev->vlans = AR7240_MAX_VLANS; + swdev->ops = &ar7240_ops; + + if (register_switch(&as->swdev, ag->dev) < 0) + goto err_free; + + pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name); + + /* initialize defaults */ + for (i = 0; i < AR7240_MAX_VLANS; i++) + as->vlan_id[i] = i; + + as->vlan_table[0] = ar7240sw_port_mask_all(as); + + return as; + +err_free: + kfree(as); + return NULL; +} + +static void link_function(struct work_struct *work) { + struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work); + struct ar7240sw *as = ag->phy_priv; + unsigned long flags; + u8 mask; + int i; + int status = 0; + + mask = ~as->swdata->phy_poll_mask; + for (i = 0; i < AR7240_NUM_PHYS; i++) { + int link; + + if (!(mask & BIT(i))) + continue; + + link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR); + if (link & BMSR_LSTATUS) { + status = 1; + break; + } + } + + spin_lock_irqsave(&ag->lock, flags); + if (status != ag->link) { + ag->link = status; + ag71xx_link_adjust(ag); + } + spin_unlock_irqrestore(&ag->lock, flags); + + schedule_delayed_work(&ag->link_work, HZ / 2); +} + +void ag71xx_ar7240_start(struct ag71xx *ag) +{ + struct ar7240sw *as = ag->phy_priv; + + ar7240sw_reset(as); + + ag->speed = SPEED_1000; + ag->duplex = 1; + + ar7240_set_addr(as, ag->dev->dev_addr); + ar7240_hw_apply(&as->swdev); + + schedule_delayed_work(&ag->link_work, HZ / 10); +} + +void ag71xx_ar7240_stop(struct ag71xx *ag) +{ + cancel_delayed_work_sync(&ag->link_work); +} + +int ag71xx_ar7240_init(struct ag71xx *ag) +{ + struct ar7240sw *as; + + as = ar7240_probe(ag); + if (!as) + return -ENODEV; + + ag->phy_priv = as; + ar7240sw_reset(as); + + rwlock_init(&as->stats_lock); + INIT_DELAYED_WORK(&ag->link_work, link_function); + + return 0; +} + +void ag71xx_ar7240_cleanup(struct ag71xx *ag) +{ + struct ar7240sw *as = ag->phy_priv; + + if (!as) + return; + + unregister_switch(&as->swdev); + kfree(as); + ag->phy_priv = NULL; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c new file mode 100644 index 0000000..7ec43b7 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c @@ -0,0 +1,44 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * Special support for the Atheros ar8216 switch chip + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AR8216_PACKET_TYPE_MASK 0xf +#define AR8216_PACKET_TYPE_NORMAL 0 + +#define AR8216_HEADER_LEN 2 + +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) +{ + skb_push(skb, AR8216_HEADER_LEN); + skb->data[0] = 0x10; + skb->data[1] = 0x80; +} + +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, + int pktlen) +{ + u8 type; + + type = skb->data[1] & AR8216_PACKET_TYPE_MASK; + switch (type) { + case AR8216_PACKET_TYPE_NORMAL: + break; + + default: + return -EINVAL; + } + + skb_pull(skb, AR8216_HEADER_LEN); + return 0; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c new file mode 100644 index 0000000..c480121 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c @@ -0,0 +1,285 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "ag71xx.h" + +static struct dentry *ag71xx_debugfs_root; + +static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) +{ + if (status) + ag->debug.int_stats.total++; + if (status & AG71XX_INT_TX_PS) + ag->debug.int_stats.tx_ps++; + if (status & AG71XX_INT_TX_UR) + ag->debug.int_stats.tx_ur++; + if (status & AG71XX_INT_TX_BE) + ag->debug.int_stats.tx_be++; + if (status & AG71XX_INT_RX_PR) + ag->debug.int_stats.rx_pr++; + if (status & AG71XX_INT_RX_OF) + ag->debug.int_stats.rx_of++; + if (status & AG71XX_INT_RX_BE) + ag->debug.int_stats.rx_be++; +} + +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ +#define PR_INT_STAT(_label, _field) \ + len += snprintf(buf + len, sizeof(buf) - len, \ + "%20s: %10lu\n", _label, ag->debug.int_stats._field); + + struct ag71xx *ag = file->private_data; + char buf[256]; + unsigned int len = 0; + + PR_INT_STAT("TX Packet Sent", tx_ps); + PR_INT_STAT("TX Underrun", tx_ur); + PR_INT_STAT("TX Bus Error", tx_be); + PR_INT_STAT("RX Packet Received", rx_pr); + PR_INT_STAT("RX Overflow", rx_of); + PR_INT_STAT("RX Bus Error", rx_be); + len += snprintf(buf + len, sizeof(buf) - len, "\n"); + PR_INT_STAT("Total", total); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +#undef PR_INT_STAT +} + +static const struct file_operations ag71xx_fops_int_stats = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_int_stats, + .owner = THIS_MODULE +}; + +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) +{ + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + + if (rx) { + stats->rx_count++; + stats->rx_packets += rx; + if (rx <= AG71XX_NAPI_WEIGHT) + stats->rx[rx]++; + if (rx > stats->rx_packets_max) + stats->rx_packets_max = rx; + } + + if (tx) { + stats->tx_count++; + stats->tx_packets += tx; + if (tx <= AG71XX_NAPI_WEIGHT) + stats->tx[tx]++; + if (tx > stats->tx_packets_max) + stats->tx_packets_max = tx; + } +} + +static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + char *buf; + unsigned int buflen; + unsigned int len = 0; + unsigned long rx_avg = 0; + unsigned long tx_avg = 0; + int ret; + int i; + + buflen = 2048; + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + if (stats->rx_count) + rx_avg = stats->rx_packets / stats->rx_count; + + if (stats->tx_count) + tx_avg = stats->tx_packets / stats->tx_count; + + len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n", + "len", "rx", "tx"); + + for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) + len += snprintf(buf + len, buflen - len, + "%3d: %10lu %10lu\n", + i, stats->rx[i], stats->tx[i]); + + len += snprintf(buf + len, buflen - len, "\n"); + + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "sum", stats->rx_count, stats->tx_count); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "avg", rx_avg, tx_avg); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "max", stats->rx_packets_max, stats->tx_packets_max); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "pkt", stats->rx_packets, stats->tx_packets); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return ret; +} + +static const struct file_operations ag71xx_fops_napi_stats = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_napi_stats, + .owner = THIS_MODULE +}; + +#define DESC_PRINT_LEN 64 + +static ssize_t read_file_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos, + struct ag71xx *ag, + struct ag71xx_ring *ring, + unsigned desc_reg) +{ + char *buf; + unsigned int buflen; + unsigned int len = 0; + unsigned long flags; + ssize_t ret; + int curr; + int dirty; + u32 desc_hw; + int i; + + buflen = (ring->size * DESC_PRINT_LEN); + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len += snprintf(buf + len, buflen - len, + "Idx ... %-8s %-8s %-8s %-8s . %-10s\n", + "desc", "next", "data", "ctrl", "timestamp"); + + spin_lock_irqsave(&ag->lock, flags); + + curr = (ring->curr % ring->size); + dirty = (ring->dirty % ring->size); + desc_hw = ag71xx_rr(ag, desc_reg); + for (i = 0; i < ring->size; i++) { + struct ag71xx_buf *ab = &ring->buf[i]; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size; + + len += snprintf(buf + len, buflen - len, + "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n", + i, + (i == curr) ? 'C' : ' ', + (i == dirty) ? 'D' : ' ', + (desc_hw == desc_dma) ? 'H' : ' ', + desc_dma, + desc->next, + desc->data, + desc->ctrl, + (desc->ctrl & DESC_EMPTY) ? 'E' : '*', + ab->timestamp); + } + + spin_unlock_irqrestore(&ag->lock, flags); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return ret; +} + +static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + + return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring, + AG71XX_REG_TX_DESC); +} + +static const struct file_operations ag71xx_fops_tx_ring = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_tx_ring, + .owner = THIS_MODULE +}; + +static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + + return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring, + AG71XX_REG_RX_DESC); +} + +static const struct file_operations ag71xx_fops_rx_ring = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_rx_ring, + .owner = THIS_MODULE +}; + +void ag71xx_debugfs_exit(struct ag71xx *ag) +{ + debugfs_remove_recursive(ag->debug.debugfs_dir); +} + +int ag71xx_debugfs_init(struct ag71xx *ag) +{ + struct device *dev = &ag->pdev->dev; + + ag->debug.debugfs_dir = debugfs_create_dir(dev_name(dev), + ag71xx_debugfs_root); + if (!ag->debug.debugfs_dir) { + dev_err(dev, "unable to create debugfs directory\n"); + return -ENOENT; + } + + debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_int_stats); + debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_napi_stats); + debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_tx_ring); + debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_rx_ring); + + return 0; +} + +int ag71xx_debugfs_root_init(void) +{ + if (ag71xx_debugfs_root) + return -EBUSY; + + ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); + if (!ag71xx_debugfs_root) + return -ENOENT; + + return 0; +} + +void ag71xx_debugfs_root_exit(void) +{ + debugfs_remove(ag71xx_debugfs_root); + ag71xx_debugfs_root = NULL; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c new file mode 100644 index 0000000..cad9f2f --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c @@ -0,0 +1,130 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +static int ag71xx_ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_gset(phydev, cmd); +} + +static int ag71xx_ethtool_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_sset(phydev, cmd); +} + +static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct ag71xx *ag = netdev_priv(dev); + + strcpy(info->driver, ag->pdev->dev.driver->name); + strcpy(info->version, AG71XX_DRV_VERSION); + strcpy(info->bus_info, dev_name(&ag->pdev->dev)); +} + +static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + + return ag->msg_enable; +} + +static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) +{ + struct ag71xx *ag = netdev_priv(dev); + + ag->msg_enable = msg_level; +} + +static void ag71xx_ethtool_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *er) +{ + struct ag71xx *ag = netdev_priv(dev); + + er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX; + er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX; + er->rx_mini_max_pending = 0; + er->rx_jumbo_max_pending = 0; + + er->tx_pending = ag->tx_ring.size; + er->rx_pending = ag->rx_ring.size; + er->rx_mini_pending = 0; + er->rx_jumbo_pending = 0; + + if (ag->tx_ring.desc_split) + er->tx_pending /= AG71XX_TX_RING_DS_PER_PKT; +} + +static int ag71xx_ethtool_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *er) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned tx_size; + unsigned rx_size; + int err; + + if (er->rx_mini_pending != 0|| + er->rx_jumbo_pending != 0 || + er->rx_pending == 0 || + er->tx_pending == 0) + return -EINVAL; + + tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ? + er->tx_pending : AG71XX_TX_RING_SIZE_MAX; + + rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ? + er->rx_pending : AG71XX_RX_RING_SIZE_MAX; + + if (netif_running(dev)) { + err = dev->netdev_ops->ndo_stop(dev); + if (err) + return err; + } + + if (ag->tx_ring.desc_split) + tx_size *= AG71XX_TX_RING_DS_PER_PKT; + + ag->tx_ring.size = tx_size; + ag->rx_ring.size = rx_size; + + if (netif_running(dev)) + err = dev->netdev_ops->ndo_open(dev); + + return err; +} + +struct ethtool_ops ag71xx_ethtool_ops = { + .set_settings = ag71xx_ethtool_set_settings, + .get_settings = ag71xx_ethtool_get_settings, + .get_drvinfo = ag71xx_ethtool_get_drvinfo, + .get_msglevel = ag71xx_ethtool_get_msglevel, + .set_msglevel = ag71xx_ethtool_set_msglevel, + .get_ringparam = ag71xx_ethtool_get_ringparam, + .set_ringparam = ag71xx_ethtool_set_ringparam, + .get_link = ethtool_op_get_link, +}; diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c new file mode 100644 index 0000000..c7671d9 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -0,0 +1,1406 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AG71XX_DEFAULT_MSG_ENABLE \ + (NETIF_MSG_DRV \ + | NETIF_MSG_PROBE \ + | NETIF_MSG_LINK \ + | NETIF_MSG_TIMER \ + | NETIF_MSG_IFDOWN \ + | NETIF_MSG_IFUP \ + | NETIF_MSG_RX_ERR \ + | NETIF_MSG_TX_ERR) + +static int ag71xx_msg_level = -1; + +module_param_named(msg_level, ag71xx_msg_level, int, 0); +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); + +#define ETH_SWITCH_HEADER_LEN 2 + +static inline unsigned int ag71xx_max_frame_len(unsigned int mtu) +{ + return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; +} + +static void ag71xx_dump_dma_regs(struct ag71xx *ag) +{ + DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_TX_CTRL), + ag71xx_rr(ag, AG71XX_REG_TX_DESC), + ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); + + DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_RX_CTRL), + ag71xx_rr(ag, AG71XX_REG_RX_DESC), + ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); +} + +static void ag71xx_dump_regs(struct ag71xx *ag) +{ + DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), + ag71xx_rr(ag, AG71XX_REG_MAC_IPG), + ag71xx_rr(ag, AG71XX_REG_MAC_HDX), + ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); + DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); + DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); +} + +static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) +{ + DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", + ag->dev->name, label, intr, + (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", + (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", + (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", + (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", + (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", + (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); +} + +static void ag71xx_ring_free(struct ag71xx_ring *ring) +{ + kfree(ring->buf); + + if (ring->descs_cpu) + dma_free_coherent(NULL, ring->size * ring->desc_size, + ring->descs_cpu, ring->descs_dma); +} + +static int ag71xx_ring_alloc(struct ag71xx_ring *ring) +{ + int err; + + ring->desc_size = sizeof(struct ag71xx_desc); + if (ring->desc_size % cache_line_size()) { + DBG("ag71xx: ring %p, desc size %u rounded to %u\n", + ring, ring->desc_size, + roundup(ring->desc_size, cache_line_size())); + ring->desc_size = roundup(ring->desc_size, cache_line_size()); + } + + ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size, + &ring->descs_dma, GFP_ATOMIC); + if (!ring->descs_cpu) { + err = -ENOMEM; + goto err; + } + + + ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL); + if (!ring->buf) { + err = -ENOMEM; + goto err; + } + + return 0; + +err: + return err; +} + +static void ag71xx_ring_tx_clean(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + struct net_device *dev = ag->dev; + u32 bytes_compl = 0, pkts_compl = 0; + + while (ring->curr != ring->dirty) { + struct ag71xx_desc *desc; + u32 i = ring->dirty % ring->size; + + desc = ag71xx_ring_desc(ring, i); + if (!ag71xx_desc_empty(desc)) { + desc->ctrl = 0; + dev->stats.tx_errors++; + } + + if (ring->buf[i].skb) { + bytes_compl += ring->buf[i].len; + pkts_compl++; + dev_kfree_skb_any(ring->buf[i].skb); + } + ring->buf[i].skb = NULL; + ring->dirty++; + } + + /* flush descriptors */ + wmb(); + + netdev_completed_queue(dev, pkts_compl, bytes_compl); +} + +static void ag71xx_ring_tx_init(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + int i; + + for (i = 0; i < ring->size; i++) { + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + + desc->next = (u32) (ring->descs_dma + + ring->desc_size * ((i + 1) % ring->size)); + + desc->ctrl = DESC_EMPTY; + ring->buf[i].skb = NULL; + } + + /* flush descriptors */ + wmb(); + + ring->curr = 0; + ring->dirty = 0; + netdev_reset_queue(ag->dev); +} + +static void ag71xx_ring_rx_clean(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + int i; + + if (!ring->buf) + return; + + for (i = 0; i < ring->size; i++) + if (ring->buf[i].rx_buf) { + dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, + ag->rx_buf_size, DMA_FROM_DEVICE); + kfree(ring->buf[i].rx_buf); + } +} + +static int ag71xx_buffer_offset(struct ag71xx *ag) +{ + int offset = NET_SKB_PAD; + + /* + * On AR71xx/AR91xx packets must be 4-byte aligned. + * + * When using builtin AR8216 support, hardware adds a 2-byte header, + * so we don't need any extra alignment in that case. + */ + if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag)) + return offset; + + return offset + NET_IP_ALIGN; +} + +static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, + int offset) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); + void *data; + + data = kmalloc(ag->rx_buf_size + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), + GFP_ATOMIC); + if (!data) + return false; + + buf->rx_buf = data; + buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size, + DMA_FROM_DEVICE); + desc->data = (u32) buf->dma_addr + offset; + return true; +} + +static int ag71xx_ring_rx_init(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + unsigned int i; + int ret; + int offset = ag71xx_buffer_offset(ag); + + ret = 0; + for (i = 0; i < ring->size; i++) { + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + + desc->next = (u32) (ring->descs_dma + + ring->desc_size * ((i + 1) % ring->size)); + + DBG("ag71xx: RX desc at %p, next is %08x\n", + desc, desc->next); + } + + for (i = 0; i < ring->size; i++) { + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + + if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) { + ret = -ENOMEM; + break; + } + + desc->ctrl = DESC_EMPTY; + } + + /* flush descriptors */ + wmb(); + + ring->curr = 0; + ring->dirty = 0; + + return ret; +} + +static int ag71xx_ring_rx_refill(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + unsigned int count; + int offset = ag71xx_buffer_offset(ag); + + count = 0; + for (; ring->curr - ring->dirty > 0; ring->dirty++) { + struct ag71xx_desc *desc; + unsigned int i; + + i = ring->dirty % ring->size; + desc = ag71xx_ring_desc(ring, i); + + if (!ring->buf[i].rx_buf && + !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) + break; + + desc->ctrl = DESC_EMPTY; + count++; + } + + /* flush descriptors */ + wmb(); + + DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); + + return count; +} + +static int ag71xx_rings_init(struct ag71xx *ag) +{ + int ret; + + ret = ag71xx_ring_alloc(&ag->tx_ring); + if (ret) + return ret; + + ag71xx_ring_tx_init(ag); + + ret = ag71xx_ring_alloc(&ag->rx_ring); + if (ret) + return ret; + + ret = ag71xx_ring_rx_init(ag); + return ret; +} + +static void ag71xx_rings_cleanup(struct ag71xx *ag) +{ + ag71xx_ring_rx_clean(ag); + ag71xx_ring_free(&ag->rx_ring); + + ag71xx_ring_tx_clean(ag); + netdev_reset_queue(ag->dev); + ag71xx_ring_free(&ag->tx_ring); +} + +static unsigned char *ag71xx_speed_str(struct ag71xx *ag) +{ + switch (ag->speed) { + case SPEED_1000: + return "1000"; + case SPEED_100: + return "100"; + case SPEED_10: + return "10"; + } + + return "?"; +} + +static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) +{ + u32 t; + + t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) + | (((u32) mac[3]) << 8) | ((u32) mac[2]); + + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); + + t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); +} + +static void ag71xx_dma_reset(struct ag71xx *ag) +{ + u32 val; + int i; + + ag71xx_dump_dma_regs(ag); + + /* stop RX and TX */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); + + /* + * give the hardware some time to really stop all rx/tx activity + * clearing the descriptors too early causes random memory corruption + */ + mdelay(1); + + /* clear descriptor addresses */ + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); + + /* clear pending RX/TX interrupts */ + for (i = 0; i < 256; i++) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + } + + /* clear pending errors */ + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); + + val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); + if (val) + pr_alert("%s: unable to clear DMA Rx status: %08x\n", + ag->dev->name, val); + + val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + + /* mask out reserved bits */ + val &= ~0xff000000; + + if (val) + pr_alert("%s: unable to clear DMA Tx status: %08x\n", + ag->dev->name, val); + + ag71xx_dump_dma_regs(ag); +} + +#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ + MAC_CFG1_SRX | MAC_CFG1_STX) + +#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) + +#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ + FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ + FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ + FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ + FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ + FIFO_CFG4_VT) + +#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ + FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ + FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ + FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ + FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ + FIFO_CFG5_17 | FIFO_CFG5_SF) + +static void ag71xx_hw_stop(struct ag71xx *ag) +{ + /* disable all interrupts and stop the rx/tx engine */ + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); +} + +static void ag71xx_hw_setup(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + /* setup MAC configuration registers */ + ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); + + ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, + MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); + + /* setup max frame length to zero */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); + + /* setup FIFO configuration registers */ + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); + if (pdata->is_ar724x) { + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); + } else { + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); + } + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); +} + +static void ag71xx_hw_init(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 reset_mask = pdata->reset_bit; + + ag71xx_hw_stop(ag); + + if (pdata->is_ar724x) { + u32 reset_phy = reset_mask; + + reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY; + reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY); + + ath79_device_reset_set(reset_phy); + msleep(50); + ath79_device_reset_clear(reset_phy); + msleep(200); + } + + ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); + udelay(20); + + ath79_device_reset_set(reset_mask); + msleep(100); + ath79_device_reset_clear(reset_mask); + msleep(200); + + ag71xx_hw_setup(ag); + + ag71xx_dma_reset(ag); +} + +static void ag71xx_fast_reset(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct net_device *dev = ag->dev; + u32 reset_mask = pdata->reset_bit; + u32 rx_ds, tx_ds; + u32 mii_reg; + + reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC; + + mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); + rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); + tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC); + + ath79_device_reset_set(reset_mask); + udelay(10); + ath79_device_reset_clear(reset_mask); + udelay(10); + + ag71xx_dma_reset(ag); + ag71xx_hw_setup(ag); + + /* setup max frame length */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, + ag71xx_max_frame_len(ag->dev->mtu)); + + ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); + ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds); + ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); + + ag71xx_hw_set_macaddr(ag, dev->dev_addr); +} + +static void ag71xx_hw_start(struct ag71xx *ag) +{ + /* start RX engine */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + + /* enable interrupts */ + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); +} + +void ag71xx_link_adjust(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 cfg2; + u32 ifctl; + u32 fifo5; + u32 fifo3; + + if (!ag->link) { + ag71xx_hw_stop(ag); + netif_carrier_off(ag->dev); + if (netif_msg_link(ag)) + pr_info("%s: link down\n", ag->dev->name); + return; + } + + if (pdata->is_ar724x) + ag71xx_fast_reset(ag); + + cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); + cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); + cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; + + ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); + ifctl &= ~(MAC_IFCTL_SPEED); + + fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); + fifo5 &= ~FIFO_CFG5_BM; + + switch (ag->speed) { + case SPEED_1000: + cfg2 |= MAC_CFG2_IF_1000; + fifo5 |= FIFO_CFG5_BM; + break; + case SPEED_100: + cfg2 |= MAC_CFG2_IF_10_100; + ifctl |= MAC_IFCTL_SPEED; + break; + case SPEED_10: + cfg2 |= MAC_CFG2_IF_10_100; + break; + default: + BUG(); + return; + } + + if (pdata->is_ar91xx) + fifo3 = 0x00780fff; + else if (pdata->is_ar724x) + fifo3 = pdata->fifo_cfg3; + else + fifo3 = 0x008001ff; + + if (ag->tx_ring.desc_split) { + fifo3 &= 0xffff; + fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; + } + + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3); + + if (pdata->set_speed) + pdata->set_speed(ag->speed); + + ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); + ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); + ag71xx_hw_start(ag); + + netif_carrier_on(ag->dev); + if (netif_msg_link(ag)) + pr_info("%s: link up (%sMbps/%s duplex)\n", + ag->dev->name, + ag71xx_speed_str(ag), + (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); + + DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + + DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); + + DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL)); +} + +static int ag71xx_open(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned int max_frame_len; + int ret; + + max_frame_len = ag71xx_max_frame_len(dev->mtu); + ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN; + + /* setup max frame length */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); + + ret = ag71xx_rings_init(ag); + if (ret) + goto err; + + napi_enable(&ag->napi); + + netif_carrier_off(dev); + ag71xx_phy_start(ag); + + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); + + ag71xx_hw_set_macaddr(ag, dev->dev_addr); + + netif_start_queue(dev); + + return 0; + +err: + ag71xx_rings_cleanup(ag); + return ret; +} + +static int ag71xx_stop(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned long flags; + + netif_carrier_off(dev); + ag71xx_phy_stop(ag); + + spin_lock_irqsave(&ag->lock, flags); + + netif_stop_queue(dev); + + ag71xx_hw_stop(ag); + ag71xx_dma_reset(ag); + + napi_disable(&ag->napi); + del_timer_sync(&ag->oom_timer); + + spin_unlock_irqrestore(&ag->lock, flags); + + ag71xx_rings_cleanup(ag); + + return 0; +} + +static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) +{ + int i; + struct ag71xx_desc *desc; + int ndesc = 0; + int split = ring->desc_split; + + if (!split) + split = len; + + while (len > 0) { + unsigned int cur_len = len; + + i = (ring->curr + ndesc) % ring->size; + desc = ag71xx_ring_desc(ring, i); + + if (!ag71xx_desc_empty(desc)) + return -1; + + if (cur_len > split) { + cur_len = split; + + /* + * TX will hang if DMA transfers <= 4 bytes, + * make sure next segment is more than 4 bytes long. + */ + if (len <= split + 4) + cur_len -= 4; + } + + desc->data = addr; + addr += cur_len; + len -= cur_len; + + if (len > 0) + cur_len |= DESC_MORE; + + /* prevent early tx attempt of this descriptor */ + if (!ndesc) + cur_len |= DESC_EMPTY; + + desc->ctrl = cur_len; + ndesc++; + } + + return ndesc; +} + +static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + struct ag71xx_ring *ring = &ag->tx_ring; + struct ag71xx_desc *desc; + dma_addr_t dma_addr; + int i, n, ring_min; + + if (ag71xx_has_ar8216(ag)) + ag71xx_add_ar8216_header(ag, skb); + + if (skb->len <= 4) { + DBG("%s: packet len is too small\n", ag->dev->name); + goto err_drop; + } + + dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + i = ring->curr % ring->size; + desc = ag71xx_ring_desc(ring, i); + + /* setup descriptor fields */ + n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask); + if (n < 0) + goto err_drop_unmap; + + i = (ring->curr + n - 1) % ring->size; + ring->buf[i].len = skb->len; + ring->buf[i].skb = skb; + ring->buf[i].timestamp = jiffies; + + netdev_sent_queue(dev, skb->len); + + desc->ctrl &= ~DESC_EMPTY; + ring->curr += n; + + /* flush descriptor */ + wmb(); + + ring_min = 2; + if (ring->desc_split) + ring_min *= AG71XX_TX_RING_DS_PER_PKT; + + if (ring->curr - ring->dirty >= ring->size - ring_min) { + DBG("%s: tx queue full\n", dev->name); + netif_stop_queue(dev); + } + + DBG("%s: packet injected into TX queue\n", ag->dev->name); + + /* enable TX engine */ + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); + + return NETDEV_TX_OK; + +err_drop_unmap: + dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE); + +err_drop: + dev->stats.tx_dropped++; + + dev_kfree_skb(skb); + return NETDEV_TX_OK; +} + +static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + int ret; + + switch (cmd) { + case SIOCETHTOOL: + if (ag->phy_dev == NULL) + break; + + spin_lock_irq(&ag->lock); + ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); + spin_unlock_irq(&ag->lock); + return ret; + + case SIOCSIFHWADDR: + if (copy_from_user + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGIFHWADDR: + if (copy_to_user + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGMIIPHY: + case SIOCGMIIREG: + case SIOCSMIIREG: + if (ag->phy_dev == NULL) + break; + + return phy_mii_ioctl(ag->phy_dev, ifr, cmd); + + default: + break; + } + + return -EOPNOTSUPP; +} + +static void ag71xx_oom_timer_handler(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct ag71xx *ag = netdev_priv(dev); + + napi_schedule(&ag->napi); +} + +static void ag71xx_tx_timeout(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + + if (netif_msg_tx_err(ag)) + pr_info("%s: tx timeout\n", ag->dev->name); + + schedule_work(&ag->restart_work); +} + +static void ag71xx_restart_work_func(struct work_struct *work) +{ + struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); + + if (ag71xx_get_pdata(ag)->is_ar724x) { + ag->link = 0; + ag71xx_link_adjust(ag); + return; + } + + ag71xx_stop(ag->dev); + ag71xx_open(ag->dev); +} + +static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp) +{ + u32 rx_sm, tx_sm, rx_fd; + + if (likely(time_before(jiffies, timestamp + HZ/10))) + return false; + + if (!netif_carrier_ok(ag->dev)) + return false; + + rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); + if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) + return true; + + tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); + rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); + if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && + ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) + return true; + + return false; +} + +static int ag71xx_tx_packets(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + int sent = 0; + int bytes_compl = 0; + int n = 0; + + DBG("%s: processing TX ring\n", ag->dev->name); + + while (ring->dirty + n != ring->curr) { + unsigned int i = (ring->dirty + n) % ring->size; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + struct sk_buff *skb = ring->buf[i].skb; + + if (!ag71xx_desc_empty(desc)) { + if (pdata->is_ar7240 && + ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) + schedule_work(&ag->restart_work); + break; + } + + n++; + if (!skb) + continue; + + dev_kfree_skb_any(skb); + ring->buf[i].skb = NULL; + + bytes_compl += ring->buf[i].len; + + sent++; + ring->dirty += n; + + while (n > 0) { + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + n--; + } + } + + DBG("%s: %d packets sent out\n", ag->dev->name, sent); + + ag->dev->stats.tx_bytes += bytes_compl; + ag->dev->stats.tx_packets += sent; + + if (!sent) + return 0; + + netdev_completed_queue(ag->dev, sent, bytes_compl); + if ((ring->curr - ring->dirty) < (ring->size * 3) / 4) + netif_wake_queue(ag->dev); + + return sent; +} + +static int ag71xx_rx_packets(struct ag71xx *ag, int limit) +{ + struct net_device *dev = ag->dev; + struct ag71xx_ring *ring = &ag->rx_ring; + int offset = ag71xx_buffer_offset(ag); + unsigned int pktlen_mask = ag->desc_pktlen_mask; + int done = 0; + + DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", + dev->name, limit, ring->curr, ring->dirty); + + while (done < limit) { + unsigned int i = ring->curr % ring->size; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + struct sk_buff *skb; + int pktlen; + int err = 0; + + if (ag71xx_desc_empty(desc)) + break; + + if ((ring->dirty + ring->size) == ring->curr) { + ag71xx_assert(0); + break; + } + + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + + pktlen = desc->ctrl & pktlen_mask; + pktlen -= ETH_FCS_LEN; + + dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, + ag->rx_buf_size, DMA_FROM_DEVICE); + + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + + skb = build_skb(ring->buf[i].rx_buf, 0); + if (!skb) { + kfree(ring->buf[i].rx_buf); + goto next; + } + + skb_reserve(skb, offset); + skb_put(skb, pktlen); + + if (ag71xx_has_ar8216(ag)) + err = ag71xx_remove_ar8216_header(ag, skb, pktlen); + + if (err) { + dev->stats.rx_dropped++; + kfree_skb(skb); + } else { + skb->dev = dev; + skb->ip_summed = CHECKSUM_NONE; + skb->protocol = eth_type_trans(skb, dev); + netif_receive_skb(skb); + } + +next: + ring->buf[i].rx_buf = NULL; + done++; + + ring->curr++; + } + + ag71xx_ring_rx_refill(ag); + + DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", + dev->name, ring->curr, ring->dirty, done); + + return done; +} + +static int ag71xx_poll(struct napi_struct *napi, int limit) +{ + struct ag71xx *ag = container_of(napi, struct ag71xx, napi); + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct net_device *dev = ag->dev; + struct ag71xx_ring *rx_ring; + unsigned long flags; + u32 status; + int tx_done; + int rx_done; + + pdata->ddr_flush(); + tx_done = ag71xx_tx_packets(ag); + + DBG("%s: processing RX ring\n", dev->name); + rx_done = ag71xx_rx_packets(ag, limit); + + ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); + + rx_ring = &ag->rx_ring; + if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL) + goto oom; + + status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); + if (unlikely(status & RX_STATUS_OF)) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); + dev->stats.rx_fifo_errors++; + + /* restart RX */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + } + + if (rx_done < limit) { + if (status & RX_STATUS_PR) + goto more; + + status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + if (status & TX_STATUS_PS) + goto more; + + DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", + dev->name, rx_done, tx_done, limit); + + napi_complete(napi); + + /* enable interrupts */ + spin_lock_irqsave(&ag->lock, flags); + ag71xx_int_enable(ag, AG71XX_INT_POLL); + spin_unlock_irqrestore(&ag->lock, flags); + return rx_done; + } + +more: + DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", + dev->name, rx_done, tx_done, limit); + return limit; + +oom: + if (netif_msg_rx_err(ag)) + pr_info("%s: out of memory\n", dev->name); + + mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); + napi_complete(napi); + return 0; +} + +static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct ag71xx *ag = netdev_priv(dev); + u32 status; + + status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); + ag71xx_dump_intr(ag, "raw", status); + + if (unlikely(!status)) + return IRQ_NONE; + + if (unlikely(status & AG71XX_INT_ERR)) { + if (status & AG71XX_INT_TX_BE) { + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); + dev_err(&dev->dev, "TX BUS error\n"); + } + if (status & AG71XX_INT_RX_BE) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); + dev_err(&dev->dev, "RX BUS error\n"); + } + } + + if (likely(status & AG71XX_INT_POLL)) { + ag71xx_int_disable(ag, AG71XX_INT_POLL); + DBG("%s: enable polling mode\n", dev->name); + napi_schedule(&ag->napi); + } + + ag71xx_debugfs_update_int_stats(ag, status); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +/* + * Polling 'interrupt' - used by things like netconsole to send skbs + * without having to re-enable interrupts. It's not called while + * the interrupt routine is executing. + */ +static void ag71xx_netpoll(struct net_device *dev) +{ + disable_irq(dev->irq); + ag71xx_interrupt(dev->irq, dev); + enable_irq(dev->irq); +} +#endif + +static int ag71xx_change_mtu(struct net_device *dev, int new_mtu) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned int max_frame_len; + + max_frame_len = ag71xx_max_frame_len(new_mtu); + if (new_mtu < 68 || max_frame_len > ag->max_frame_len) + return -EINVAL; + + if (netif_running(dev)) + return -EBUSY; + + dev->mtu = new_mtu; + return 0; +} + +static const struct net_device_ops ag71xx_netdev_ops = { + .ndo_open = ag71xx_open, + .ndo_stop = ag71xx_stop, + .ndo_start_xmit = ag71xx_hard_start_xmit, + .ndo_do_ioctl = ag71xx_do_ioctl, + .ndo_tx_timeout = ag71xx_tx_timeout, + .ndo_change_mtu = ag71xx_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = ag71xx_netpoll, +#endif +}; + +static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode) +{ + switch (mode) { + case PHY_INTERFACE_MODE_MII: + return "MII"; + case PHY_INTERFACE_MODE_GMII: + return "GMII"; + case PHY_INTERFACE_MODE_RMII: + return "RMII"; + case PHY_INTERFACE_MODE_RGMII: + return "RGMII"; + case PHY_INTERFACE_MODE_SGMII: + return "SGMII"; + default: + break; + } + + return "unknown"; +} + + +static int ag71xx_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct resource *res; + struct ag71xx *ag; + struct ag71xx_platform_data *pdata; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data specified\n"); + err = -ENXIO; + goto err_out; + } + + if (pdata->mii_bus_dev == NULL && pdata->phy_mask) { + dev_err(&pdev->dev, "no MII bus device specified\n"); + err = -EINVAL; + goto err_out; + } + + dev = alloc_etherdev(sizeof(*ag)); + if (!dev) { + dev_err(&pdev->dev, "alloc_etherdev failed\n"); + err = -ENOMEM; + goto err_out; + } + + if (!pdata->max_frame_len || !pdata->desc_pktlen_mask) + return -EINVAL; + + SET_NETDEV_DEV(dev, &pdev->dev); + + ag = netdev_priv(dev); + ag->pdev = pdev; + ag->dev = dev; + ag->msg_enable = netif_msg_init(ag71xx_msg_level, + AG71XX_DEFAULT_MSG_ENABLE); + spin_lock_init(&ag->lock); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); + if (!res) { + dev_err(&pdev->dev, "no mac_base resource found\n"); + err = -ENXIO; + goto err_out; + } + + ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!ag->mac_base) { + dev_err(&pdev->dev, "unable to ioremap mac_base\n"); + err = -ENOMEM; + goto err_free_dev; + } + + dev->irq = platform_get_irq(pdev, 0); + err = request_irq(dev->irq, ag71xx_interrupt, + 0x0, + dev->name, dev); + if (err) { + dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); + goto err_unmap_base; + } + + dev->base_addr = (unsigned long)ag->mac_base; + dev->netdev_ops = &ag71xx_netdev_ops; + dev->ethtool_ops = &ag71xx_ethtool_ops; + + INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); + + init_timer(&ag->oom_timer); + ag->oom_timer.data = (unsigned long) dev; + ag->oom_timer.function = ag71xx_oom_timer_handler; + + ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT; + ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT; + + ag->max_frame_len = pdata->max_frame_len; + ag->desc_pktlen_mask = pdata->desc_pktlen_mask; + + if (!pdata->is_ar724x && !pdata->is_ar91xx) { + ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; + ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT; + } + + ag->stop_desc = dma_alloc_coherent(NULL, + sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL); + + if (!ag->stop_desc) + goto err_free_irq; + + ag->stop_desc->data = 0; + ag->stop_desc->ctrl = 0; + ag->stop_desc->next = (u32) ag->stop_desc_dma; + + memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); + + netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); + + ag71xx_dump_regs(ag); + + ag71xx_hw_init(ag); + + ag71xx_dump_regs(ag); + + err = ag71xx_phy_connect(ag); + if (err) + goto err_free_desc; + + err = ag71xx_debugfs_init(ag); + if (err) + goto err_phy_disconnect; + + platform_set_drvdata(pdev, dev); + + err = register_netdev(dev); + if (err) { + dev_err(&pdev->dev, "unable to register net device\n"); + goto err_debugfs_exit; + } + + pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", + dev->name, dev->base_addr, dev->irq, + ag71xx_get_phy_if_mode_name(pdata->phy_if_mode)); + + return 0; + +err_debugfs_exit: + ag71xx_debugfs_exit(ag); +err_phy_disconnect: + ag71xx_phy_disconnect(ag); +err_free_desc: + dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc, + ag->stop_desc_dma); +err_free_irq: + free_irq(dev->irq, dev); +err_unmap_base: + iounmap(ag->mac_base); +err_free_dev: + kfree(dev); +err_out: + platform_set_drvdata(pdev, NULL); + return err; +} + +static int ag71xx_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + struct ag71xx *ag = netdev_priv(dev); + + ag71xx_debugfs_exit(ag); + ag71xx_phy_disconnect(ag); + unregister_netdev(dev); + free_irq(dev->irq, dev); + iounmap(ag->mac_base); + kfree(dev); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver ag71xx_driver = { + .probe = ag71xx_probe, + .remove = ag71xx_remove, + .driver = { + .name = AG71XX_DRV_NAME, + } +}; + +static int __init ag71xx_module_init(void) +{ + int ret; + + ret = ag71xx_debugfs_root_init(); + if (ret) + goto err_out; + + ret = ag71xx_mdio_driver_init(); + if (ret) + goto err_debugfs_exit; + + ret = platform_driver_register(&ag71xx_driver); + if (ret) + goto err_mdio_exit; + + return 0; + +err_mdio_exit: + ag71xx_mdio_driver_exit(); +err_debugfs_exit: + ag71xx_debugfs_root_exit(); +err_out: + return ret; +} + +static void __exit ag71xx_module_exit(void) +{ + platform_driver_unregister(&ag71xx_driver); + ag71xx_mdio_driver_exit(); + ag71xx_debugfs_root_exit(); +} + +module_init(ag71xx_module_init); +module_exit(ag71xx_module_exit); + +MODULE_VERSION(AG71XX_DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_AUTHOR("Imre Kaloz "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" AG71XX_DRV_NAME); diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c new file mode 100644 index 0000000..71ae825 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c @@ -0,0 +1,318 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AG71XX_MDIO_RETRY 1000 +#define AG71XX_MDIO_DELAY 5 + +static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, + u32 value) +{ + void __iomem *r; + + r = am->mdio_base + reg; + __raw_writel(value, r); + + /* flush write */ + (void) __raw_readl(r); +} + +static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) +{ + return __raw_readl(am->mdio_base + reg); +} + +static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) +{ + DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", + am->mii_bus->name, + ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), + ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), + ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); + DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", + am->mii_bus->name, + ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), + ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), + ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); +} + +static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am) +{ + int i; + + for (i = 0; i < AG71XX_MDIO_RETRY; i++) { + u32 busy; + + udelay(AG71XX_MDIO_DELAY); + + busy = ag71xx_mdio_rr(am, AG71XX_REG_MII_IND); + if (!busy) + return 0; + + udelay(AG71XX_MDIO_DELAY); + } + + pr_err("%s: MDIO operation timed out\n", am->mii_bus->name); + + return -ETIMEDOUT; +} + +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) +{ + int err; + int ret; + + err = ag71xx_mdio_wait_busy(am); + if (err) + return 0xffff; + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); + + err = ag71xx_mdio_wait_busy(am); + if (err) + return 0xffff; + + ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + + DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); + + return ret; +} + +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val) +{ + DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); + + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); + ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); + + ag71xx_mdio_wait_busy(am); +} + +static const u32 ar71xx_mdio_div_table[] = { + 4, 4, 6, 8, 10, 14, 20, 28, +}; + +static const u32 ar7240_mdio_div_table[] = { + 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, +}; + +static const u32 ar933x_mdio_div_table[] = { + 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, +}; + +static int ag71xx_mdio_get_divider(struct ag71xx_mdio *am, u32 *div) +{ + unsigned long ref_clock, mdio_clock; + const u32 *table; + int ndivs; + int i; + + ref_clock = am->pdata->ref_clock; + mdio_clock = am->pdata->mdio_clock; + + if (!ref_clock || !mdio_clock) + return -EINVAL; + + if (am->pdata->is_ar9330 || am->pdata->is_ar934x) { + table = ar933x_mdio_div_table; + ndivs = ARRAY_SIZE(ar933x_mdio_div_table); + } else if (am->pdata->is_ar7240) { + table = ar7240_mdio_div_table; + ndivs = ARRAY_SIZE(ar7240_mdio_div_table); + } else { + table = ar71xx_mdio_div_table; + ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); + } + + for (i = 0; i < ndivs; i++) { + unsigned long t; + + t = ref_clock / table[i]; + if (t <= mdio_clock) { + *div = i; + return 0; + } + } + + dev_err(&am->mii_bus->dev, "no divider found for %lu/%lu\n", + ref_clock, mdio_clock); + return -ENOENT; +} + +static int ag71xx_mdio_reset(struct mii_bus *bus) +{ + struct ag71xx_mdio *am = bus->priv; + u32 t; + int err; + + err = ag71xx_mdio_get_divider(am, &t); + if (err) { + /* fallback */ + if (am->pdata->is_ar7240) + t = MII_CFG_CLK_DIV_6; + else if (am->pdata->builtin_switch && !am->pdata->is_ar934x) + t = MII_CFG_CLK_DIV_10; + else if (!am->pdata->builtin_switch && am->pdata->is_ar934x) + t = MII_CFG_CLK_DIV_58; + else + t = MII_CFG_CLK_DIV_28; + } + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); + udelay(100); + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); + udelay(100); + + if (am->pdata->reset) + am->pdata->reset(bus); + + return 0; +} + +static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) +{ + struct ag71xx_mdio *am = bus->priv; + + if (am->pdata->builtin_switch) + return ar7240sw_phy_read(bus, addr, reg); + else + return ag71xx_mdio_mii_read(am, addr, reg); +} + +static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct ag71xx_mdio *am = bus->priv; + + if (am->pdata->builtin_switch) + ar7240sw_phy_write(bus, addr, reg, val); + else + ag71xx_mdio_mii_write(am, addr, reg, val); + return 0; +} + +static int ag71xx_mdio_probe(struct platform_device *pdev) +{ + struct ag71xx_mdio_platform_data *pdata; + struct ag71xx_mdio *am; + struct resource *res; + int i; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + am = kzalloc(sizeof(*am), GFP_KERNEL); + if (!am) { + err = -ENOMEM; + goto err_out; + } + + am->pdata = pdata; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no iomem resource found\n"); + err = -ENXIO; + goto err_out; + } + + am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!am->mdio_base) { + dev_err(&pdev->dev, "unable to ioremap registers\n"); + err = -ENOMEM; + goto err_free_mdio; + } + + am->mii_bus = mdiobus_alloc(); + if (am->mii_bus == NULL) { + err = -ENOMEM; + goto err_iounmap; + } + + am->mii_bus->name = "ag71xx_mdio"; + am->mii_bus->read = ag71xx_mdio_read; + am->mii_bus->write = ag71xx_mdio_write; + am->mii_bus->reset = ag71xx_mdio_reset; + am->mii_bus->irq = am->mii_irq; + am->mii_bus->priv = am; + am->mii_bus->parent = &pdev->dev; + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); + am->mii_bus->phy_mask = pdata->phy_mask; + + for (i = 0; i < PHY_MAX_ADDR; i++) + am->mii_irq[i] = PHY_POLL; + + ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); + + err = mdiobus_register(am->mii_bus); + if (err) + goto err_free_bus; + + ag71xx_mdio_dump_regs(am); + + platform_set_drvdata(pdev, am); + return 0; + +err_free_bus: + mdiobus_free(am->mii_bus); +err_iounmap: + iounmap(am->mdio_base); +err_free_mdio: + kfree(am); +err_out: + return err; +} + +static int ag71xx_mdio_remove(struct platform_device *pdev) +{ + struct ag71xx_mdio *am = platform_get_drvdata(pdev); + + if (am) { + mdiobus_unregister(am->mii_bus); + mdiobus_free(am->mii_bus); + iounmap(am->mdio_base); + kfree(am); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver ag71xx_mdio_driver = { + .probe = ag71xx_mdio_probe, + .remove = ag71xx_mdio_remove, + .driver = { + .name = "ag71xx-mdio", + } +}; + +int __init ag71xx_mdio_driver_init(void) +{ + return platform_driver_register(&ag71xx_mdio_driver); +} + +void ag71xx_mdio_driver_exit(void) +{ + platform_driver_unregister(&ag71xx_mdio_driver); +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c new file mode 100644 index 0000000..9de77e9 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c @@ -0,0 +1,235 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +static void ag71xx_phy_link_adjust(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&ag->lock, flags); + + if (phydev->link) { + if (ag->duplex != phydev->duplex + || ag->speed != phydev->speed) { + status_change = 1; + } + } + + if (phydev->link != ag->link) + status_change = 1; + + ag->link = phydev->link; + ag->duplex = phydev->duplex; + ag->speed = phydev->speed; + + if (status_change) + ag71xx_link_adjust(ag); + + spin_unlock_irqrestore(&ag->lock, flags); +} + +void ag71xx_phy_start(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (ag->phy_dev) { + phy_start(ag->phy_dev); + } else if (pdata->mii_bus_dev && pdata->switch_data) { + ag71xx_ar7240_start(ag); + } else { + ag->link = 1; + ag71xx_link_adjust(ag); + } +} + +void ag71xx_phy_stop(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + unsigned long flags; + + if (ag->phy_dev) + phy_stop(ag->phy_dev); + else if (pdata->mii_bus_dev && pdata->switch_data) + ag71xx_ar7240_stop(ag); + + spin_lock_irqsave(&ag->lock, flags); + if (ag->link) { + ag->link = 0; + ag71xx_link_adjust(ag); + } + spin_unlock_irqrestore(&ag->lock, flags); +} + +static int ag71xx_phy_connect_fixed(struct ag71xx *ag) +{ + struct device *dev = &ag->pdev->dev; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + int ret = 0; + + /* use fixed settings */ + switch (pdata->speed) { + case SPEED_10: + case SPEED_100: + case SPEED_1000: + break; + default: + dev_err(dev, "invalid speed specified\n"); + ret = -EINVAL; + break; + } + + dev_dbg(dev, "using fixed link parameters\n"); + + ag->duplex = pdata->duplex; + ag->speed = pdata->speed; + + return ret; +} + +static int ag71xx_phy_connect_multi(struct ag71xx *ag) +{ + struct device *dev = &ag->pdev->dev; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct phy_device *phydev = NULL; + int phy_addr; + int ret = 0; + + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (!(pdata->phy_mask & (1 << phy_addr))) + continue; + + if (ag->mii_bus->phy_map[phy_addr] == NULL) + continue; + + DBG("%s: PHY found at %s, uid=%08x\n", + dev_name(dev), + dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), + ag->mii_bus->phy_map[phy_addr]->phy_id); + + if (phydev == NULL) + phydev = ag->mii_bus->phy_map[phy_addr]; + } + + if (!phydev) { + dev_err(dev, "no PHY found with phy_mask=%08x\n", + pdata->phy_mask); + return -ENODEV; + } + + ag->phy_dev = phy_connect(ag->dev, dev_name(&phydev->dev), + &ag71xx_phy_link_adjust, + pdata->phy_if_mode); + + if (IS_ERR(ag->phy_dev)) { + dev_err(dev, "could not connect to PHY at %s\n", + dev_name(&phydev->dev)); + return PTR_ERR(ag->phy_dev); + } + + /* mask with MAC supported features */ + if (pdata->has_gbit) + phydev->supported &= PHY_GBIT_FEATURES; + else + phydev->supported &= PHY_BASIC_FEATURES; + + phydev->advertising = phydev->supported; + + dev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n", + dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name); + + ag->link = 0; + ag->speed = 0; + ag->duplex = -1; + + return ret; +} + +static int dev_is_class(struct device *dev, void *class) +{ + if (dev->class != NULL && !strcmp(dev->class->name, class)) + return 1; + + return 0; +} + +static struct device *dev_find_class(struct device *parent, char *class) +{ + if (dev_is_class(parent, class)) { + get_device(parent); + return parent; + } + + return device_find_child(parent, class, dev_is_class); +} + +static struct mii_bus *dev_to_mii_bus(struct device *dev) +{ + struct device *d; + + d = dev_find_class(dev, "mdio_bus"); + if (d != NULL) { + struct mii_bus *bus; + + bus = to_mii_bus(d); + put_device(d); + + return bus; + } + + return NULL; +} + +int ag71xx_phy_connect(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (pdata->mii_bus_dev == NULL || + pdata->mii_bus_dev->bus == NULL ) + return ag71xx_phy_connect_fixed(ag); + + ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); + if (ag->mii_bus == NULL) { + dev_err(&ag->pdev->dev, "unable to find MII bus on device '%s'\n", + dev_name(pdata->mii_bus_dev)); + return -ENODEV; + } + + /* Reset the mdio bus explicitly */ + if (ag->mii_bus->reset) { + mutex_lock(&ag->mii_bus->mdio_lock); + ag->mii_bus->reset(ag->mii_bus); + mutex_unlock(&ag->mii_bus->mdio_lock); + } + + if (pdata->switch_data) + return ag71xx_ar7240_init(ag); + + if (pdata->phy_mask) + return ag71xx_phy_connect_multi(ag); + + return ag71xx_phy_connect_fixed(ag); +} + +void ag71xx_phy_disconnect(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (pdata->switch_data) + ag71xx_ar7240_cleanup(ag); + else if (ag->phy_dev) + phy_disconnect(ag->phy_dev); +} diff --git a/target/linux/ar71xx/files/drivers/spi/spi-ap83.c b/target/linux/ar71xx/files/drivers/spi/spi-ap83.c new file mode 100644 index 0000000..33843a6 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-ap83.c @@ -0,0 +1,283 @@ +/* + * Atheros AP83 board specific SPI Controller driver + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_DESC "Atheros AP83 board SPI Controller driver" +#define DRV_VERSION "0.1.0" +#define DRV_NAME "ap83-spi" + +#define AP83_SPI_CLK_HIGH (1 << 23) +#define AP83_SPI_CLK_LOW 0 +#define AP83_SPI_MOSI_HIGH (1 << 22) +#define AP83_SPI_MOSI_LOW 0 + +#define AP83_SPI_GPIO_CS 1 +#define AP83_SPI_GPIO_MISO 3 + +struct ap83_spi { + struct spi_bitbang bitbang; + void __iomem *base; + u32 addr; + + struct platform_device *pdev; +}; + +static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) +{ + return __raw_readl(sp->base + reg); +} + +static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static inline void setsck(struct spi_device *spi, int val) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + if (val) + sp->addr |= AP83_SPI_CLK_HIGH; + else + sp->addr &= ~AP83_SPI_CLK_HIGH; + + dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", + sp->addr, (val) ? "HIGH" : "LOW"); + + ap83_spi_rr(sp, sp->addr); +} + +static inline void setmosi(struct spi_device *spi, int val) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + if (val) + sp->addr |= AP83_SPI_MOSI_HIGH; + else + sp->addr &= ~AP83_SPI_MOSI_HIGH; + + dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", + sp->addr, (val) ? "HIGH" : "LOW"); + + ap83_spi_rr(sp, sp->addr); +} + +static inline u32 getmiso(struct spi_device *spi) +{ + u32 ret; + + ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; + dev_dbg(&spi->dev, "get MISO: %d\n", ret); + + return ret; +} + +static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) +{ + ndelay(nsecs); +} + +static void ap83_spi_chipselect(struct spi_device *spi, int on) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); + + if (on) { + ath79_flash_acquire(); + + sp->addr = 0; + ap83_spi_rr(sp, sp->addr); + + gpio_set_value(AP83_SPI_GPIO_CS, 0); + } else { + gpio_set_value(AP83_SPI_GPIO_CS, 1); + ath79_flash_release(); + } +} + +#define spidelay(nsecs) \ + do { \ + /* Steal the spi_device pointer from our caller. \ + * The bitbang-API should probably get fixed here... */ \ + do_spidelay(spi, nsecs); \ + } while (0) + +#define EXPAND_BITBANG_TXRX +#include +#include "spi-bitbang-txrx.h" + +static u32 ap83_spi_txrx_mode0(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode1(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode2(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode3(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); +} + +static int ap83_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct ap83_spi *sp; + struct ap83_spi_platform_data *pdata; + struct resource *r; + int ret; + + ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); + if (ret) { + dev_err(&pdev->dev, "gpio request failed for MISO\n"); + return ret; + } + + ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); + if (ret) { + dev_err(&pdev->dev, "gpio request failed for CS\n"); + goto err_free_miso; + } + + ret = gpio_direction_input(AP83_SPI_GPIO_MISO); + if (ret) { + dev_err(&pdev->dev, "unable to set direction of MISO\n"); + goto err_free_cs; + } + + ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set direction of CS\n"); + goto err_free_cs; + } + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); + return -ENOMEM; + } + + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + + pdata = pdev->dev.platform_data; + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ap83_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; + sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; + sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; + sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; + + sp->bitbang.master->bus_num = pdev->id; + sp->bitbang.master->num_chipselect = 1; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + ret = -ENOENT; + goto err_spi_put; + } + + sp->base = ioremap_nocache(r->start, r->end - r->start + 1); + if (!sp->base) { + ret = -ENXIO; + goto err_spi_put; + } + + ret = spi_bitbang_start(&sp->bitbang); + if (!ret) + goto err_unmap; + + dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); + + return 0; + +err_unmap: + iounmap(sp->base); +err_spi_put: + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + +err_free_cs: + gpio_free(AP83_SPI_GPIO_CS); +err_free_miso: + gpio_free(AP83_SPI_GPIO_MISO); + return ret; +} + +static int ap83_spi_remove(struct platform_device *pdev) +{ + struct ap83_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return 0; +} + +static struct platform_driver ap83_spi_drv = { + .probe = ap83_spi_probe, + .remove = ap83_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ap83_spi_init(void) +{ + return platform_driver_register(&ap83_spi_drv); +} +module_init(ap83_spi_init); + +static void __exit ap83_spi_exit(void) +{ + platform_driver_unregister(&ap83_spi_drv); +} +module_exit(ap83_spi_exit); + +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c new file mode 100644 index 0000000..a8d5282 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c @@ -0,0 +1,441 @@ +/* + * SPI driver for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "spi-rb4xx-cpld" +#define DRV_DESC "RB4xx CPLD driver" +#define DRV_VERSION "0.1.0" + +#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send indle */ +#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ +#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */ +#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ +#define CPLD_CMD_LED5_ON 0x0c /* send cmd */ +#define CPLD_CMD_LED5_OFF 0x0d /* send cmd */ + +struct rb4xx_cpld { + struct spi_device *spi; + struct mutex lock; + struct gpio_chip chip; + unsigned int config; +}; + +static struct rb4xx_cpld *rb4xx_cpld; + +static inline struct rb4xx_cpld *gpio_to_cpld(struct gpio_chip *chip) +{ + return container_of(chip, struct rb4xx_cpld, chip); +} + +static int rb4xx_cpld_write_cmd(struct rb4xx_cpld *cpld, unsigned char cmd) +{ + struct spi_transfer t[1]; + struct spi_message m; + unsigned char tx_buf[1]; + int err; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = tx_buf; + t[0].len = sizeof(tx_buf); + spi_message_add_tail(&t[0], &m); + + tx_buf[0] = cmd; + + err = spi_sync(cpld->spi, &m); + return err; +} + +static int rb4xx_cpld_write_cfg(struct rb4xx_cpld *cpld, unsigned char config) +{ + struct spi_transfer t[1]; + struct spi_message m; + unsigned char cmd[2]; + int err; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_WRITE_CFG; + cmd[1] = config; + + err = spi_sync(cpld->spi, &m); + return err; +} + +static int __rb4xx_cpld_change_cfg(struct rb4xx_cpld *cpld, unsigned mask, + unsigned value) +{ + unsigned int config; + int err; + + config = cpld->config & ~mask; + config |= value; + + if ((cpld->config ^ config) & 0xff) { + err = rb4xx_cpld_write_cfg(cpld, config); + if (err) + return err; + } + + if ((cpld->config ^ config) & CPLD_CFG_nLED5) { + err = rb4xx_cpld_write_cmd(cpld, (value) ? CPLD_CMD_LED5_ON : + CPLD_CMD_LED5_OFF); + if (err) + return err; + } + + cpld->config = config; + return 0; +} + +int rb4xx_cpld_change_cfg(unsigned mask, unsigned value) +{ + int ret; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + mutex_lock(&rb4xx_cpld->lock); + ret = __rb4xx_cpld_change_cfg(rb4xx_cpld, mask, value); + mutex_unlock(&rb4xx_cpld->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_change_cfg); + +int rb4xx_cpld_read_from(unsigned addr, unsigned char *rx_buf, + const unsigned char *verify_buf, unsigned count) +{ + const unsigned char cmd[5] = { + CPLD_CMD_READ_FAST, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + addr & 0xff, + 0 + }; + struct spi_transfer t[2] = { + { + .tx_buf = &cmd, + .len = 5, + }, + { + .tx_buf = verify_buf, + .rx_buf = rx_buf, + .len = count, + .verify = (verify_buf != NULL), + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + m.fast_read = 1; + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + return spi_sync(rb4xx_cpld->spi, &m); +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_read_from); + +#if 0 +int rb4xx_cpld_read(unsigned char *buf, unsigned char *verify_buf, + unsigned count) +{ + struct spi_transfer t[2]; + struct spi_message m; + unsigned char cmd[2]; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + /* send command */ + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_READ_NAND; + cmd[1] = 0; + + /* read data */ + t[1].rx_buf = buf; + t[1].len = count; + spi_message_add_tail(&t[1], &m); + + return spi_sync(rb4xx_cpld->spi, &m); +} +#else +int rb4xx_cpld_read(unsigned char *rx_buf, const unsigned char *verify_buf, + unsigned count) +{ + static const unsigned char cmd[2] = { CPLD_CMD_READ_NAND, 0 }; + struct spi_transfer t[2] = { + { + .tx_buf = &cmd, + .len = 2, + }, { + .tx_buf = verify_buf, + .rx_buf = rx_buf, + .len = count, + .verify = (verify_buf != NULL), + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + return spi_sync(rb4xx_cpld->spi, &m); +} +#endif +EXPORT_SYMBOL_GPL(rb4xx_cpld_read); + +int rb4xx_cpld_write(const unsigned char *buf, unsigned count) +{ +#if 0 + struct spi_transfer t[3]; + struct spi_message m; + unsigned char cmd[1]; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + memset(&t, 0, sizeof(t)); + spi_message_init(&m); + + /* send command */ + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_WRITE_NAND; + + /* write data */ + t[1].tx_buf = buf; + t[1].len = count; + spi_message_add_tail(&t[1], &m); + + /* send idle */ + t[2].len = 1; + spi_message_add_tail(&t[2], &m); + + return spi_sync(rb4xx_cpld->spi, &m); +#else + static const unsigned char cmd = CPLD_CMD_WRITE_NAND; + struct spi_transfer t[3] = { + { + .tx_buf = &cmd, + .len = 1, + }, { + .tx_buf = buf, + .len = count, + .fast_write = 1, + }, { + .len = 1, + .fast_write = 1, + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + return spi_sync(rb4xx_cpld->spi, &m); +#endif +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_write); + +static int rb4xx_cpld_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + int ret; + + mutex_lock(&cpld->lock); + ret = (cpld->config >> offset) & 1; + mutex_unlock(&cpld->lock); + + return ret; +} + +static void rb4xx_cpld_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + + mutex_lock(&cpld->lock); + __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); + mutex_unlock(&cpld->lock); +} + +static int rb4xx_cpld_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + return -EOPNOTSUPP; +} + +static int rb4xx_cpld_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + int ret; + + mutex_lock(&cpld->lock); + ret = __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); + mutex_unlock(&cpld->lock); + + return ret; +} + +static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base) +{ + int err; + + /* init config */ + cpld->config = CPLD_CFG_nLED1 | CPLD_CFG_nLED2 | CPLD_CFG_nLED3 | + CPLD_CFG_nLED4 | CPLD_CFG_nCE; + rb4xx_cpld_write_cfg(cpld, cpld->config); + + /* setup GPIO chip */ + cpld->chip.label = DRV_NAME; + + cpld->chip.get = rb4xx_cpld_gpio_get; + cpld->chip.set = rb4xx_cpld_gpio_set; + cpld->chip.direction_input = rb4xx_cpld_gpio_direction_input; + cpld->chip.direction_output = rb4xx_cpld_gpio_direction_output; + + cpld->chip.base = base; + cpld->chip.ngpio = CPLD_NUM_GPIOS; + cpld->chip.can_sleep = 1; + cpld->chip.dev = &cpld->spi->dev; + cpld->chip.owner = THIS_MODULE; + + err = gpiochip_add(&cpld->chip); + if (err) + dev_err(&cpld->spi->dev, "adding GPIO chip failed, err=%d\n", + err); + + return err; +} + +static int rb4xx_cpld_probe(struct spi_device *spi) +{ + struct rb4xx_cpld *cpld; + struct rb4xx_cpld_platform_data *pdata; + int err; + + pdata = spi->dev.platform_data; + if (!pdata) { + dev_dbg(&spi->dev, "no platform data\n"); + return -EINVAL; + } + + cpld = kzalloc(sizeof(*cpld), GFP_KERNEL); + if (!cpld) { + dev_err(&spi->dev, "no memory for private data\n"); + return -ENOMEM; + } + + mutex_init(&cpld->lock); + cpld->spi = spi_dev_get(spi); + dev_set_drvdata(&spi->dev, cpld); + + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + err = spi_setup(spi); + if (err) { + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); + goto err_drvdata; + } + + err = rb4xx_cpld_gpio_init(cpld, pdata->gpio_base); + if (err) + goto err_drvdata; + + rb4xx_cpld = cpld; + + return 0; + +err_drvdata: + dev_set_drvdata(&spi->dev, NULL); + kfree(cpld); + + return err; +} + +static int rb4xx_cpld_remove(struct spi_device *spi) +{ + struct rb4xx_cpld *cpld; + + rb4xx_cpld = NULL; + cpld = dev_get_drvdata(&spi->dev); + dev_set_drvdata(&spi->dev, NULL); + kfree(cpld); + + return 0; +} + +static struct spi_driver rb4xx_cpld_driver = { + .driver = { + .name = DRV_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = rb4xx_cpld_probe, + .remove = rb4xx_cpld_remove, +}; + +static int __init rb4xx_cpld_init(void) +{ + return spi_register_driver(&rb4xx_cpld_driver); +} +module_init(rb4xx_cpld_init); + +static void __exit rb4xx_cpld_exit(void) +{ + spi_unregister_driver(&rb4xx_cpld_driver); +} +module_exit(rb4xx_cpld_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c new file mode 100644 index 0000000..56260ff --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c @@ -0,0 +1,507 @@ +/* + * SPI controller driver for the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "rb4xx-spi" +#define DRV_DESC "Mikrotik RB4xx SPI controller driver" +#define DRV_VERSION "0.1.0" + +#define SPI_CTRL_FASTEST 0x40 +#define SPI_FLASH_HZ 33333334 +#define SPI_CPLD_HZ 33333334 + +#define CPLD_CMD_READ_FAST 0x0b + +#undef RB4XX_SPI_DEBUG + +struct rb4xx_spi { + void __iomem *base; + struct spi_master *master; + + unsigned spi_ctrl_flash; + unsigned spi_ctrl_fread; + + struct clk *ahb_clk; + unsigned long ahb_freq; + + spinlock_t lock; + struct list_head queue; + int busy:1; + int cs_wait; +}; + +static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1; + +#ifdef RB4XX_SPI_DEBUG +static inline void do_spi_delay(void) +{ + ndelay(20000); +} +#else +static inline void do_spi_delay(void) { } +#endif + +static inline void do_spi_init(struct spi_device *spi) +{ + unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1; + + if (!(spi->mode & SPI_CS_HIGH)) + cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 : + AR71XX_SPI_IOC_CS0; + + spi_clk_low = cs; +} + +static inline void do_spi_finish(void __iomem *base) +{ + do_spi_delay(); + __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1, + base + AR71XX_SPI_REG_IOC); +} + +static inline void do_spi_clk(void __iomem *base, int bit) +{ + unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0); + + do_spi_delay(); + __raw_writel(bval, base + AR71XX_SPI_REG_IOC); + do_spi_delay(); + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); +} + +static void do_spi_byte(void __iomem *base, unsigned char byte) +{ + do_spi_clk(base, byte >> 7); + do_spi_clk(base, byte >> 6); + do_spi_clk(base, byte >> 5); + do_spi_clk(base, byte >> 4); + do_spi_clk(base, byte >> 3); + do_spi_clk(base, byte >> 2); + do_spi_clk(base, byte >> 1); + do_spi_clk(base, byte); + + pr_debug("spi_byte sent 0x%02x got 0x%02x\n", + (unsigned)byte, + (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS)); +} + +static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, + unsigned bit2) +{ + unsigned bval = (spi_clk_low | + ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) | + ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0)); + do_spi_delay(); + __raw_writel(bval, base + AR71XX_SPI_REG_IOC); + do_spi_delay(); + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); +} + +static void do_spi_byte_fast(void __iomem *base, unsigned char byte) +{ + do_spi_clk_fast(base, byte >> 7, byte >> 6); + do_spi_clk_fast(base, byte >> 5, byte >> 4); + do_spi_clk_fast(base, byte >> 3, byte >> 2); + do_spi_clk_fast(base, byte >> 1, byte >> 0); + + pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n", + (unsigned)byte, + (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS)); +} + +static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t) +{ + const unsigned char *rxv_ptr = NULL; + const unsigned char *tx_ptr = t->tx_buf; + unsigned char *rx_ptr = t->rx_buf; + unsigned i; + + pr_debug("spi_txrx len %u tx %u rx %u\n", + t->len, + (t->tx_buf ? 1 : 0), + (t->rx_buf ? 1 : 0)); + + if (t->verify) { + rxv_ptr = tx_ptr; + tx_ptr = NULL; + } + + for (i = 0; i < t->len; ++i) { + unsigned char sdata = tx_ptr ? tx_ptr[i] : 0; + + if (t->fast_write) + do_spi_byte_fast(base, sdata); + else + do_spi_byte(base, sdata); + + if (rx_ptr) { + rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff; + } else if (rxv_ptr) { + unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS); + if (rxv_ptr[i] != c) + return i; + } + } + + return i; +} + +static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi, + struct spi_message *m) +{ + struct spi_transfer *t; + const unsigned char *tx_ptr; + unsigned addr; + void __iomem *base = rbspi->base; + + /* check for exactly two transfers */ + if (list_empty(&m->transfers) || + list_is_last(m->transfers.next, &m->transfers) || + !list_is_last(m->transfers.next->next, &m->transfers)) { + return -1; + } + + /* first transfer contains command and address */ + t = list_entry(m->transfers.next, + struct spi_transfer, transfer_list); + + if (t->len != 5 || t->tx_buf == NULL) + return -1; + + tx_ptr = t->tx_buf; + if (tx_ptr[0] != CPLD_CMD_READ_FAST) + return -1; + + addr = tx_ptr[1]; + addr = tx_ptr[2] | (addr << 8); + addr = tx_ptr[3] | (addr << 8); + addr += (unsigned) base; + + m->actual_length += t->len; + + /* second transfer contains data itself */ + t = list_entry(m->transfers.next->next, + struct spi_transfer, transfer_list); + + if (t->tx_buf && !t->verify) + return -1; + + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + + if (t->rx_buf) { + memcpy(t->rx_buf, (const void *)addr, t->len); + } else if (t->tx_buf) { + unsigned char buf[t->len]; + memcpy(buf, (const void *)addr, t->len); + if (memcmp(t->tx_buf, buf, t->len) != 0) + m->status = -EMSGSIZE; + } + m->actual_length += t->len; + + if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) { + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + } + + return 0; +} + +static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m) +{ + struct spi_transfer *t = NULL; + void __iomem *base = rbspi->base; + + m->status = 0; + if (list_empty(&m->transfers)) + return -1; + + if (m->fast_read) + if (rb4xx_spi_read_fast(rbspi, m) == 0) + return -1; + + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL); + do_spi_init(m->spi); + + list_for_each_entry(t, &m->transfers, transfer_list) { + int len; + + len = rb4xx_spi_txrx(base, t); + if (len != t->len) { + m->status = -EMSGSIZE; + break; + } + m->actual_length += len; + + if (t->cs_change) { + if (list_is_last(&t->transfer_list, &m->transfers)) { + /* wait for continuation */ + return m->spi->chip_select; + } + do_spi_finish(base); + ndelay(100); + } + } + + do_spi_finish(base); + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + return -1; +} + +static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi, + unsigned long *flags) +{ + int cs = rbspi->cs_wait; + + rbspi->busy = 1; + while (!list_empty(&rbspi->queue)) { + struct spi_message *m; + + list_for_each_entry(m, &rbspi->queue, queue) + if (cs < 0 || cs == m->spi->chip_select) + break; + + if (&m->queue == &rbspi->queue) + break; + + list_del_init(&m->queue); + spin_unlock_irqrestore(&rbspi->lock, *flags); + + cs = rb4xx_spi_msg(rbspi, m); + m->complete(m->context); + + spin_lock_irqsave(&rbspi->lock, *flags); + } + + rbspi->cs_wait = cs; + rbspi->busy = 0; + + if (cs >= 0) { + /* TODO: add timer to unlock cs after 1s inactivity */ + } +} + +static int rb4xx_spi_transfer(struct spi_device *spi, + struct spi_message *m) +{ + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); + unsigned long flags; + + m->actual_length = 0; + m->status = -EINPROGRESS; + + spin_lock_irqsave(&rbspi->lock, flags); + list_add_tail(&m->queue, &rbspi->queue); + if (rbspi->busy || + (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) { + /* job will be done later */ + spin_unlock_irqrestore(&rbspi->lock, flags); + return 0; + } + + /* process job in current context */ + rb4xx_spi_process_queue_locked(rbspi, &flags); + spin_unlock_irqrestore(&rbspi->lock, flags); + + return 0; +} + +static int rb4xx_spi_setup(struct spi_device *spi) +{ + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); + unsigned long flags; + + if (spi->mode & ~(SPI_CS_HIGH)) { + dev_err(&spi->dev, "mode %x not supported\n", + (unsigned) spi->mode); + return -EINVAL; + } + + if (spi->bits_per_word != 8 && spi->bits_per_word != 0) { + dev_err(&spi->dev, "bits_per_word %u not supported\n", + (unsigned) spi->bits_per_word); + return -EINVAL; + } + + spin_lock_irqsave(&rbspi->lock, flags); + if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) { + rbspi->cs_wait = -1; + rb4xx_spi_process_queue_locked(rbspi, &flags); + } + spin_unlock_irqrestore(&rbspi->lock, flags); + + return 0; +} + +static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max, + const char *name) +{ + unsigned div; + + div = (rbspi->ahb_freq - 1) / (2 * hz_max); + + /* + * CPU has a bug at (div == 0) - first bit read is random + */ + if (div == 0) + ++div; + + if (name) { + unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000; + unsigned div_real = 2 * (div + 1); + pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n", + name, + ahb_khz / div_real, + ahb_khz, div_real); + } + + return SPI_CTRL_FASTEST + div; +} + +static int rb4xx_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct rb4xx_spi *rbspi; + struct resource *r; + int err = 0; + + master = spi_alloc_master(&pdev->dev, sizeof(*rbspi)); + if (master == NULL) { + dev_err(&pdev->dev, "no memory for spi_master\n"); + err = -ENOMEM; + goto err_out; + } + + master->bus_num = 0; + master->num_chipselect = 3; + master->setup = rb4xx_spi_setup; + master->transfer = rb4xx_spi_transfer; + + rbspi = spi_master_get_devdata(master); + + rbspi->ahb_clk = clk_get(&pdev->dev, "ahb"); + if (IS_ERR(rbspi->ahb_clk)) { + err = PTR_ERR(rbspi->ahb_clk); + goto err_put_master; + } + + err = clk_enable(rbspi->ahb_clk); + if (err) + goto err_clk_put; + + rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk); + if (!rbspi->ahb_freq) { + err = -EINVAL; + goto err_clk_disable; + } + + platform_set_drvdata(pdev, rbspi); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + err = -ENOENT; + goto err_clk_disable; + } + + rbspi->base = ioremap(r->start, r->end - r->start + 1); + if (!rbspi->base) { + err = -ENXIO; + goto err_clk_disable; + } + + rbspi->master = master; + rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH"); + rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD"); + rbspi->cs_wait = -1; + + spin_lock_init(&rbspi->lock); + INIT_LIST_HEAD(&rbspi->queue); + + err = spi_register_master(master); + if (err) { + dev_err(&pdev->dev, "failed to register SPI master\n"); + goto err_iounmap; + } + + return 0; + +err_iounmap: + iounmap(rbspi->base); +err_clk_disable: + clk_disable(rbspi->ahb_clk); +err_clk_put: + clk_put(rbspi->ahb_clk); +err_put_master: + platform_set_drvdata(pdev, NULL); + spi_master_put(master); +err_out: + return err; +} + +static int rb4xx_spi_remove(struct platform_device *pdev) +{ + struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); + + iounmap(rbspi->base); + clk_disable(rbspi->ahb_clk); + clk_put(rbspi->ahb_clk); + platform_set_drvdata(pdev, NULL); + spi_master_put(rbspi->master); + + return 0; +} + +static struct platform_driver rb4xx_spi_drv = { + .probe = rb4xx_spi_probe, + .remove = rb4xx_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb4xx_spi_init(void) +{ + return platform_driver_register(&rb4xx_spi_drv); +} +subsys_initcall(rb4xx_spi_init); + +static void __exit rb4xx_spi_exit(void) +{ + platform_driver_unregister(&rb4xx_spi_drv); +} + +module_exit(rb4xx_spi_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c b/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c new file mode 100644 index 0000000..b712e71 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c @@ -0,0 +1,621 @@ +/* + * SPI driver for the Vitesse VSC7385 ethernet switch + * + * Copyright (C) 2009 Gabor Juhos + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "spi-vsc7385" +#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" +#define DRV_VERSION "0.1.0" + +#define VSC73XX_BLOCK_MAC 0x1 +#define VSC73XX_BLOCK_2 0x2 +#define VSC73XX_BLOCK_MII 0x3 +#define VSC73XX_BLOCK_4 0x4 +#define VSC73XX_BLOCK_5 0x5 +#define VSC73XX_BLOCK_SYSTEM 0x7 + +#define VSC73XX_SUBBLOCK_PORT_0 0 +#define VSC73XX_SUBBLOCK_PORT_1 1 +#define VSC73XX_SUBBLOCK_PORT_2 2 +#define VSC73XX_SUBBLOCK_PORT_3 3 +#define VSC73XX_SUBBLOCK_PORT_4 4 +#define VSC73XX_SUBBLOCK_PORT_MAC 6 + +/* MAC Block registers */ +#define VSC73XX_MAC_CFG 0x0 +#define VSC73XX_ADVPORTM 0x19 +#define VSC73XX_RXOCT 0x50 +#define VSC73XX_TXOCT 0x51 +#define VSC73XX_C_RX0 0x52 +#define VSC73XX_C_RX1 0x53 +#define VSC73XX_C_RX2 0x54 +#define VSC73XX_C_TX0 0x55 +#define VSC73XX_C_TX1 0x56 +#define VSC73XX_C_TX2 0x57 +#define VSC73XX_C_CFG 0x58 + +/* MAC_CFG register bits */ +#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) +#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) +#define VSC73XX_MAC_CFG_TX_EN (1 << 28) +#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) +#define VSC73XX_MAC_CFG_FDX (1 << 18) +#define VSC73XX_MAC_CFG_GIGE (1 << 17) +#define VSC73XX_MAC_CFG_RX_EN (1 << 16) +#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) +#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) +#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) +#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) +#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) +#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) +#define VSC73XX_MAC_CFG_BIT2 (1 << 2) +#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) + +/* ADVPORTM register bits */ +#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) +#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) +#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) +#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) +#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) +#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) +#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) +#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) + +/* MII Block registers */ +#define VSC73XX_MII_STAT 0x0 +#define VSC73XX_MII_CMD 0x1 +#define VSC73XX_MII_DATA 0x2 + +/* System Block registers */ +#define VSC73XX_ICPU_SIPAD 0x01 +#define VSC73XX_ICPU_CLOCK_DELAY 0x05 +#define VSC73XX_ICPU_CTRL 0x10 +#define VSC73XX_ICPU_ADDR 0x11 +#define VSC73XX_ICPU_SRAM 0x12 +#define VSC73XX_ICPU_MBOX_VAL 0x15 +#define VSC73XX_ICPU_MBOX_SET 0x16 +#define VSC73XX_ICPU_MBOX_CLR 0x17 +#define VSC73XX_ICPU_CHIPID 0x18 +#define VSC73XX_ICPU_GPIO 0x34 + +#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) +#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) +#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) +#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) +#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) +#define VSC73XX_ICPU_CTRL_SRST (1 << 0) + +#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 +#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff +#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 +#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf +#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 +#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 + +#define VSC73XX_CMD_MODE_READ 0 +#define VSC73XX_CMD_MODE_WRITE 1 +#define VSC73XX_CMD_MODE_SHIFT 4 +#define VSC73XX_CMD_BLOCK_SHIFT 5 +#define VSC73XX_CMD_BLOCK_MASK 0x7 +#define VSC73XX_CMD_SUBBLOCK_MASK 0xf + +#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) +#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) + +#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ + VSC73XX_ICPU_CTRL_BOOT_EN | \ + VSC73XX_ICPU_CTRL_EXT_ACC_EN) + +#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ + VSC73XX_ICPU_CTRL_BOOT_EN | \ + VSC73XX_ICPU_CTRL_CLK_EN | \ + VSC73XX_ICPU_CTRL_SRST) + +#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ + VSC73XX_ADVPORTM_EXC_COL_CONT | \ + VSC73XX_ADVPORTM_EXT_PORT | \ + VSC73XX_ADVPORTM_INV_GTX | \ + VSC73XX_ADVPORTM_ENA_GTX | \ + VSC73XX_ADVPORTM_DDR_MODE | \ + VSC73XX_ADVPORTM_IO_LOOPBACK | \ + VSC73XX_ADVPORTM_HOST_LOOPBACK) + +#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ + VSC73XX_ADVPORTM_ENA_GTX | \ + VSC73XX_ADVPORTM_DDR_MODE) + +#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ + VSC73XX_MAC_CFG_MAC_RX_RST | \ + VSC73XX_MAC_CFG_MAC_TX_RST) + +#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ + VSC73XX_MAC_CFG_FDX | \ + VSC73XX_MAC_CFG_GIGE | \ + VSC73XX_MAC_CFG_RX_EN) + +#define VSC73XX_RESET_DELAY 100 + +struct vsc7385 { + struct spi_device *spi; + struct mutex lock; + struct vsc7385_platform_data *pdata; +}; + +static int vsc7385_is_addr_valid(u8 block, u8 subblock) +{ + switch (block) { + case VSC73XX_BLOCK_MAC: + switch (subblock) { + case 0 ... 4: + case 6: + return 1; + } + break; + + case VSC73XX_BLOCK_2: + case VSC73XX_BLOCK_SYSTEM: + switch (subblock) { + case 0: + return 1; + } + break; + + case VSC73XX_BLOCK_MII: + case VSC73XX_BLOCK_4: + case VSC73XX_BLOCK_5: + switch (subblock) { + case 0 ... 1: + return 1; + } + break; + } + + return 0; +} + +static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) +{ + u8 ret; + + ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; + ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; + ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; + + return ret; +} + +static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, + u32 *value) +{ + u8 cmd[4]; + u8 buf[4]; + struct spi_transfer t[2]; + struct spi_message m; + int err; + + if (!vsc7385_is_addr_valid(block, subblock)) + return -EINVAL; + + spi_message_init(&m); + + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + t[1].rx_buf = buf; + t[1].len = sizeof(buf); + spi_message_add_tail(&t[1], &m); + + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); + cmd[1] = reg; + cmd[2] = 0; + cmd[3] = 0; + + mutex_lock(&vsc->lock); + err = spi_sync(vsc->spi, &m); + mutex_unlock(&vsc->lock); + + if (err) + return err; + + *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | + (((u32) buf[2]) << 8) | ((u32) buf[3]); + + return 0; +} + + +static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, + u32 value) +{ + u8 cmd[2]; + u8 buf[4]; + struct spi_transfer t[2]; + struct spi_message m; + int err; + + if (!vsc7385_is_addr_valid(block, subblock)) + return -EINVAL; + + spi_message_init(&m); + + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + t[1].tx_buf = buf; + t[1].len = sizeof(buf); + spi_message_add_tail(&t[1], &m); + + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); + cmd[1] = reg; + + buf[0] = (value >> 24) & 0xff; + buf[1] = (value >> 16) & 0xff; + buf[2] = (value >> 8) & 0xff; + buf[3] = value & 0xff; + + mutex_lock(&vsc->lock); + err = spi_sync(vsc->spi, &m); + mutex_unlock(&vsc->lock); + + return err; +} + +static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, + u8 subblock, u8 reg, u32 value, + u32 read_mask, u32 read_val) +{ + struct spi_device *spi = vsc->spi; + u32 t; + int err; + + err = vsc7385_write(vsc, block, subblock, reg, value); + if (err) + return err; + + err = vsc7385_read(vsc, block, subblock, reg, &t); + if (err) + return err; + + if ((t & read_mask) != read_val) { + dev_err(&spi->dev, "register write error\n"); + return -EIO; + } + + return 0; +} + +static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, val); +} + +static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) +{ + return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, val); +} + +static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, + VSC73XX_ICPU_CTRL_STOP); +} + +static inline int vsc7385_icpu_start(struct vsc7385 *vsc) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, + VSC73XX_ICPU_CTRL_START); +} + +static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) +{ + int rc; + + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, + 0x0000); + if (rc) + dev_err(&vsc->spi->dev, + "could not reset microcode, err=%d\n", rc); + + return rc; +} + +static int vsc7385_upload_ucode(struct vsc7385 *vsc) +{ + struct spi_device *spi = vsc->spi; + const struct firmware *firmware; + char *ucode_name; + unsigned char *dp; + unsigned int curVal; + int i; + int diffs; + int rc; + + ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name + : "vsc7385_ucode.bin"; + rc = request_firmware(&firmware, ucode_name, &spi->dev); + if (rc) { + dev_err(&spi->dev, "request_firmware failed, err=%d\n", + rc); + return rc; + } + + rc = vsc7385_icpu_stop(vsc); + if (rc) + goto out; + + rc = vsc7385_icpu_reset(vsc); + if (rc) + goto out; + + dev_info(&spi->dev, "uploading microcode...\n"); + + dp = (unsigned char *) firmware->data; + for (i = 0; i < firmware->size; i++) { + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_SRAM, *dp++); + if (rc) { + dev_err(&spi->dev, "could not load microcode, err=%d\n", + rc); + goto out; + } + } + + rc = vsc7385_icpu_reset(vsc); + if (rc) + goto out; + + dev_info(&spi->dev, "verifying microcode...\n"); + + dp = (unsigned char *) firmware->data; + diffs = 0; + for (i = 0; i < firmware->size; i++) { + rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_SRAM, &curVal); + if (rc) { + dev_err(&spi->dev, "could not read microcode %d\n", + rc); + goto out; + } + + if (curVal > 0xff) { + dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", + i, *dp, curVal); + rc = -EIO; + goto out; + } + + if ((curVal & 0xff) != *dp) { + diffs++; + dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", + i, *dp, curVal); + + if (diffs > 4) + break; + } + dp++; + } + + if (diffs) { + dev_err(&spi->dev, "microcode verification failed\n"); + rc = -EIO; + goto out; + } + + dev_info(&spi->dev, "microcode uploaded\n"); + + rc = vsc7385_icpu_start(vsc); + +out: + release_firmware(firmware); + return rc; +} + +static int vsc7385_setup(struct vsc7385 *vsc) +{ + struct vsc7385_platform_data *pdata = vsc->pdata; + u32 t; + int err; + + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, + VSC7385_CLOCK_DELAY, + VSC7385_CLOCK_DELAY_MASK, + VSC7385_CLOCK_DELAY); + if (err) + goto err; + + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, + VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, + VSC7385_ADVPORTM_INIT, + VSC7385_ADVPORTM_MASK, + VSC7385_ADVPORTM_INIT); + if (err) + goto err; + + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, + VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); + if (err) + goto err; + + t = VSC73XX_MAC_CFG_INIT; + t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); + t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); + if (pdata->mac_cfg.bit2) + t |= VSC73XX_MAC_CFG_BIT2; + + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, + VSC73XX_MAC_CFG, t); + if (err) + goto err; + + return 0; + +err: + return err; +} + +static int vsc7385_detect(struct vsc7385 *vsc) +{ + struct spi_device *spi = vsc->spi; + u32 t; + u32 id; + u32 rev; + int err; + + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_MBOX_VAL, &t); + if (err) { + dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); + return err; + } + + if (t == 0xffffffff) { + dev_dbg(&spi->dev, "assert chip reset\n"); + if (vsc->pdata->reset) + vsc->pdata->reset(); + + } + + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CHIPID, &t); + if (err) { + dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); + return err; + } + + id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; + switch (id) { + case VSC73XX_ICPU_CHIPID_ID_7385: + case VSC73XX_ICPU_CHIPID_ID_7395: + break; + default: + dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); + return -ENODEV; + } + + rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & + VSC73XX_ICPU_CHIPID_REV_MASK; + dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev); + + return 0; +} + +static int vsc7385_probe(struct spi_device *spi) +{ + struct vsc7385 *vsc; + struct vsc7385_platform_data *pdata; + int err; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); + + pdata = spi->dev.platform_data; + if (!pdata) { + dev_err(&spi->dev, "no platform data specified\n"); + return -ENODEV; + } + + vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); + if (!vsc) { + dev_err(&spi->dev, "no memory for private data\n"); + return -ENOMEM; + } + + mutex_init(&vsc->lock); + vsc->pdata = pdata; + vsc->spi = spi_dev_get(spi); + dev_set_drvdata(&spi->dev, vsc); + + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + err = spi_setup(spi); + if (err) { + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); + goto err_drvdata; + } + + err = vsc7385_detect(vsc); + if (err) { + dev_err(&spi->dev, "no chip found, err=%d\n", err); + goto err_drvdata; + } + + err = vsc7385_upload_ucode(vsc); + if (err) + goto err_drvdata; + + err = vsc7385_setup(vsc); + if (err) + goto err_drvdata; + + return 0; + +err_drvdata: + dev_set_drvdata(&spi->dev, NULL); + kfree(vsc); + return err; +} + +static int vsc7385_remove(struct spi_device *spi) +{ + struct vsc7385_data *vsc; + + vsc = dev_get_drvdata(&spi->dev); + dev_set_drvdata(&spi->dev, NULL); + kfree(vsc); + + return 0; +} + +static struct spi_driver vsc7385_driver = { + .driver = { + .name = DRV_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = vsc7385_probe, + .remove = vsc7385_remove, +}; + +static int __init vsc7385_init(void) +{ + return spi_register_driver(&vsc7385_driver); +} +module_init(vsc7385_init); + +static void __exit vsc7385_exit(void) +{ + spi_unregister_driver(&vsc7385_driver); +} +module_exit(vsc7385_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); + diff --git a/target/linux/ar71xx/files/include/linux/nxp_74hc153.h b/target/linux/ar71xx/files/include/linux/nxp_74hc153.h new file mode 100644 index 0000000..20b8845 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/nxp_74hc153.h @@ -0,0 +1,24 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer defines + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _NXP_74HC153_H +#define _NXP_74HC153_H + +#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" + +struct nxp_74hc153_platform_data { + unsigned gpio_base; + unsigned gpio_pin_s0; + unsigned gpio_pin_s1; + unsigned gpio_pin_1y; + unsigned gpio_pin_2y; +}; + +#endif /* _NXP_74HC153_H */ diff --git a/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h b/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h new file mode 100644 index 0000000..371aaee --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h @@ -0,0 +1,39 @@ +/* + * Platform data definition for the built-in NAND controller of the + * Atheros AR934x SoCs + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _AR934X_NFC_PLATFORM_H +#define _AR934X_NFC_PLATFORM_H + +#define AR934X_NFC_DRIVER_NAME "ar934x-nfc" + +struct mtd_info; +struct mtd_partition; + +enum ar934x_nfc_ecc_mode { + AR934X_NFC_ECC_SOFT = 0, + AR934X_NFC_ECC_HW, + AR934X_NFC_ECC_SOFT_BCH, +}; + +struct ar934x_nfc_platform_data { + const char *name; + struct mtd_partition *parts; + int nr_parts; + + bool swap_dma; + enum ar934x_nfc_ecc_mode ecc_mode; + + void (*hw_reset)(bool active); + void (*select_chip)(int chip_no); + int (*scan_fixup)(struct mtd_info *mtd); +}; + +#endif /* _AR934X_NFC_PLATFORM_H */ diff --git a/target/linux/ar71xx/files/include/linux/platform_data/gpio-latch.h b/target/linux/ar71xx/files/include/linux/platform_data/gpio-latch.h new file mode 100644 index 0000000..0450e67 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform_data/gpio-latch.h @@ -0,0 +1,14 @@ +#ifndef _GPIO_LATCH_H_ +#define _GPIO_LATCH_H_ + +#define GPIO_LATCH_DRIVER_NAME "gpio-latch" + +struct gpio_latch_platform_data { + int base; + int num_gpios; + int *gpios; + int le_gpio_index; + bool le_active_low; +}; + +#endif /* _GPIO_LATCH_H_ */ diff --git a/target/linux/ar71xx/files/include/linux/platform_data/rb91x_nand.h b/target/linux/ar71xx/files/include/linux/platform_data/rb91x_nand.h new file mode 100644 index 0000000..5f17fb8 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform_data/rb91x_nand.h @@ -0,0 +1,16 @@ +#ifndef _RB91X_NAND_H_ +#define _RB91X_NAND_H_ + +#define RB91X_NAND_DRIVER_NAME "rb91x-nand" + +struct rb91x_nand_platform_data { + int gpio_nce; /* chip enable, active low */ + int gpio_ale; /* address latch enable */ + int gpio_cle; /* command latch enable */ + int gpio_rdy; + int gpio_read; + int gpio_nrw; /* read/write enable, active low */ + int gpio_nle; /* latch enable, active low */ +}; + +#endif /* _RB91X_NAND_H_ */ \ No newline at end of file diff --git a/target/linux/ar71xx/files/include/linux/spi/vsc7385.h b/target/linux/ar71xx/files/include/linux/spi/vsc7385.h new file mode 100644 index 0000000..1072ad7 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/spi/vsc7385.h @@ -0,0 +1,19 @@ +/* + * Platform data definition for the Vitesse VSC7385 ethernet switch driver + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +struct vsc7385_platform_data { + void (*reset)(void); + char *ucode_name; + struct { + u32 tx_ipg:5; + u32 bit2:1; + u32 clk_sel:3; + } mac_cfg; +}; diff --git a/target/linux/ar71xx/files/net/dsa/mv88e6063.c b/target/linux/ar71xx/files/net/dsa/mv88e6063.c new file mode 100644 index 0000000..5638a9f --- /dev/null +++ b/target/linux/ar71xx/files/net/dsa/mv88e6063.c @@ -0,0 +1,294 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips + * Copyright (c) 2009 Gabor Juhos + * + * This driver was base on: net/dsa/mv88e6060.c + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips + * Copyright (c) 2008-2009 Marvell Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include "dsa_priv.h" + +#define REG_BASE 0x10 +#define REG_PHY(p) (REG_BASE + (p)) +#define REG_PORT(p) (REG_BASE + 8 + (p)) +#define REG_GLOBAL (REG_BASE + 0x0f) +#define NUM_PORTS 7 + +static int reg_read(struct dsa_switch *ds, int addr, int reg) +{ + return mdiobus_read(ds->master_mii_bus, addr, reg); +} + +#define REG_READ(addr, reg) \ + ({ \ + int __ret; \ + \ + __ret = reg_read(ds, addr, reg); \ + if (__ret < 0) \ + return __ret; \ + __ret; \ + }) + + +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) +{ + return mdiobus_write(ds->master_mii_bus, addr, reg, val); +} + +#define REG_WRITE(addr, reg, val) \ + ({ \ + int __ret; \ + \ + __ret = reg_write(ds, addr, reg, val); \ + if (__ret < 0) \ + return __ret; \ + }) + +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) +{ + int ret; + + ret = mdiobus_read(bus, REG_PORT(0), 0x03); + if (ret >= 0) { + ret &= 0xfff0; + if (ret == 0x1530) + return "Marvell 88E6063"; + } + + return NULL; +} + +static int mv88e6063_switch_reset(struct dsa_switch *ds) +{ + int i; + int ret; + + /* + * Set all ports to the disabled state. + */ + for (i = 0; i < NUM_PORTS; i++) { + ret = REG_READ(REG_PORT(i), 0x04); + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); + } + + /* + * Wait for transmit queues to drain. + */ + msleep(2); + + /* + * Reset the switch. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); + + /* + * Wait up to one second for reset to complete. + */ + for (i = 0; i < 1000; i++) { + ret = REG_READ(REG_GLOBAL, 0x00); + if ((ret & 0x8000) == 0x0000) + break; + + msleep(1); + } + if (i == 1000) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6063_setup_global(struct dsa_switch *ds) +{ + /* + * Disable discarding of frames with excessive collisions, + * set the maximum frame size to 1536 bytes, and mask all + * interrupt sources. + */ + REG_WRITE(REG_GLOBAL, 0x04, 0x0800); + + /* + * Enable automatic address learning, set the address + * database size to 1024 entries, and set the default aging + * time to 5 minutes. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); + + return 0; +} + +static int mv88e6063_setup_port(struct dsa_switch *ds, int p) +{ + int addr = REG_PORT(p); + + /* + * Do not force flow control, disable Ingress and Egress + * Header tagging, disable VLAN tunneling, and set the port + * state to Forwarding. Additionally, if this is the CPU + * port, enable Ingress and Egress Trailer tagging mode. + */ + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); + + /* + * Port based VLAN map: give each port its own address + * database, allow the CPU port to talk to each of the 'real' + * ports, and allow each of the 'real' ports to only talk to + * the CPU port. + */ + REG_WRITE(addr, 0x06, + ((p & 0xf) << 12) | + (dsa_is_cpu_port(ds, p) ? + ds->phys_port_mask : + (1 << ds->dst->cpu_port))); + + /* + * Port Association Vector: when learning source addresses + * of packets, add the address to the address database using + * a port bitmap that has only the bit for this port set and + * the other bits clear. + */ + REG_WRITE(addr, 0x0b, 1 << p); + + return 0; +} + +static int mv88e6063_setup(struct dsa_switch *ds) +{ + int i; + int ret; + + ret = mv88e6063_switch_reset(ds); + if (ret < 0) + return ret; + + /* @@@ initialise atu */ + + ret = mv88e6063_setup_global(ds); + if (ret < 0) + return ret; + + for (i = 0; i < NUM_PORTS; i++) { + ret = mv88e6063_setup_port(ds, i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) +{ + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); + + return 0; +} + +static int mv88e6063_port_to_phy_addr(int port) +{ + if (port >= 0 && port <= NUM_PORTS) + return REG_PHY(port); + return -1; +} + +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_read(ds, addr, regnum); +} + +static int +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_write(ds, addr, regnum, val); +} + +static void mv88e6063_poll_link(struct dsa_switch *ds) +{ + int i; + + for (i = 0; i < DSA_MAX_PORTS; i++) { + struct net_device *dev; + int uninitialized_var(port_status); + int link; + int speed; + int duplex; + int fc; + + dev = ds->ports[i]; + if (dev == NULL) + continue; + + link = 0; + if (dev->flags & IFF_UP) { + port_status = reg_read(ds, REG_PORT(i), 0x00); + if (port_status < 0) + continue; + + link = !!(port_status & 0x1000); + } + + if (!link) { + if (netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + continue; + } + + speed = (port_status & 0x0100) ? 100 : 10; + duplex = (port_status & 0x0200) ? 1 : 0; + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; + + if (!netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " + "flow control %sabled\n", dev->name, + speed, duplex ? "full" : "half", + fc ? "en" : "dis"); + netif_carrier_on(dev); + } + } +} + +static struct dsa_switch_driver mv88e6063_switch_driver = { + .tag_protocol = htons(ETH_P_TRAILER), + .probe = mv88e6063_probe, + .setup = mv88e6063_setup, + .set_addr = mv88e6063_set_addr, + .phy_read = mv88e6063_phy_read, + .phy_write = mv88e6063_phy_write, + .poll_link = mv88e6063_poll_link, +}; + +static int __init mv88e6063_init(void) +{ + register_switch_driver(&mv88e6063_switch_driver); + return 0; +} +module_init(mv88e6063_init); + +static void __exit mv88e6063_cleanup(void) +{ + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); diff --git a/target/linux/ar71xx/generic/config-default b/target/linux/ar71xx/generic/config-default new file mode 100644 index 0000000..4516968 --- /dev/null +++ b/target/linux/ar71xx/generic/config-default @@ -0,0 +1 @@ +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd" diff --git a/target/linux/ar71xx/generic/profiles/00-default.mk b/target/linux/ar71xx/generic/profiles/00-default.mk new file mode 100644 index 0000000..36c4aa6 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/00-default.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:= \ + kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/ar71xx/generic/profiles/01-minimal.mk b/target/linux/ar71xx/generic/profiles/01-minimal.mk new file mode 100644 index 0000000..dfaa3b0 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Minimal + NAME:=Minimal Profile (no drivers) + PACKAGES:=-kmod-ath9k -wpad-mini +endef + +define Profile/Minimal/Description + Minimal package set compatible with most boards. +endef +$(eval $(call Profile,Minimal)) diff --git a/target/linux/ar71xx/generic/profiles/02-ath5k.mk b/target/linux/ar71xx/generic/profiles/02-ath5k.mk new file mode 100644 index 0000000..7820349 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/02-ath5k.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ath5k + NAME:=Atheros 802.11abg WiFi (ath5k) + PACKAGES:=kmod-ath5k -kmod-ath9k +endef + +define Profile/ath5k/Description + Package set compatible with hardware using Atheros 802.11abg cards. +endef +$(eval $(call Profile,ath5k)) diff --git a/target/linux/ar71xx/generic/profiles/8devices.mk b/target/linux/ar71xx/generic/profiles/8devices.mk new file mode 100644 index 0000000..209403a --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/8devices.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CARAMBOLA2 + NAME:=Carambola2 board from 8Devices + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/CARAMBOLA2/Description + Package set optimized for the 8devices Carambola2 board. +endef + +$(eval $(call Profile,CARAMBOLA2)) diff --git a/target/linux/ar71xx/generic/profiles/alfa.mk b/target/linux/ar71xx/generic/profiles/alfa.mk new file mode 100644 index 0000000..6e259dc --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/alfa.mk @@ -0,0 +1,66 @@ +# +# Copyright (C) 2011-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ALFAAP96 + NAME:=ALFA Network AP96 board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-rtc-pcf2123 +endef + +define Profile/ALFAAP96/Description + Package set optimized for the ALFA Network AP96 board. +endef + +$(eval $(call Profile,ALFAAP96)) + + +define Profile/HORNETUB + NAME:=ALFA Network Hornet-UB board (8MB flash, 32MB ram) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/HORNETUB/Description + Package set optimized for the ALFA Network Hornet-UB board with 8MB + flash and 32MB ram. +endef + +$(eval $(call Profile,HORNETUB)) + + +define Profile/HORNETUBx2 + NAME:=ALFA Network Hornet-UB-x2 board (16MB flash, 64MB ram) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/HORNETUBx2/Description + Package set optimized for the ALFA Network Hornet-UB board with 16MB + flash and 64MB ram. +endef + +$(eval $(call Profile,HORNETUBx2)) + + +define Profile/ALFANX + NAME:=ALFA Network N2/N5 board + PACKAGES:= +endef + +define Profile/ALFANX/Description + Package set optimized for the ALFA Network N2/N5 boards. +endef + +$(eval $(call Profile,ALFANX)) + +define Profile/TUBE2H + NAME:=ALFA Network Tube2H board + PACKAGES:= +endef + +define Profile/TUBE2H/Description + Package set optimized for the ALFA Network Tube2H board. +endef + +$(eval $(call Profile,TUBE2H)) diff --git a/target/linux/ar71xx/generic/profiles/allnet.mk b/target/linux/ar71xx/generic/profiles/allnet.mk new file mode 100644 index 0000000..07ca964 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/allnet.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 20012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ALL0305 + NAME:=Allnet ALL0305 + PACKAGES:=fconfig kmod-ath5k -kmod-ath9k +endef + +define Profile/ALL0305/Description + Package set optimized for the Allnet ALL0305. +endef + +$(eval $(call Profile,ALL0305)) + +define Profile/ALL0258N + NAME:=Allnet ALL0258N + PACKAGES:=uboot-envtools rssileds +endef + +define Profile/ALL0258N/Description + Package set optimized for the Allnet ALL0258N. +endef + +$(eval $(call Profile,ALL0258N)) + +define Profile/ALL0315N + NAME:=Allnet ALL0315N + PACKAGES:=uboot-envtools rssileds +endef + +define Profile/ALL0315N/Description + Package set optimized for the Allnet ALL0315N. +endef + +$(eval $(call Profile,ALL0315N)) diff --git a/target/linux/ar71xx/generic/profiles/antminer.mk b/target/linux/ar71xx/generic/profiles/antminer.mk new file mode 100644 index 0000000..404133b --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/antminer.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ANTMINER_S1 + NAME:=Antminer S1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-crypto-manager kmod-i2c-gpio-custom kmod-usb-hid +endef + + +define Profile/ANTMINER_S1/Description + Package set optimized for the Bitmain Antminer S1. +endef +$(eval $(call Profile,ANTMINER_S1)) + +define Profile/ANTMINER_S3 + NAME:=Antminer S3 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-crypto-manager kmod-i2c-gpio-custom kmod-usb-hid +endef + + +define Profile/ANTMINER_S1/Description + Package set optimized for the Bitmain Antminer S3. +endef +$(eval $(call Profile,ANTMINER_S3)) diff --git a/target/linux/ar71xx/generic/profiles/atheros.mk b/target/linux/ar71xx/generic/profiles/atheros.mk new file mode 100644 index 0000000..3a312a4 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/atheros.mk @@ -0,0 +1,184 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AP113 + NAME:=Atheros AP113 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP113/description + Package set optimized for the Atheros AP113 reference board. +endef + +$(eval $(call Profile,AP113)) + +define Profile/AP121 + NAME:=Atheros AP121 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP121/Description + Package set optimized for the Atheros AP121 reference board. +endef + +$(eval $(call Profile,AP121)) + +define Profile/AP121MINI + NAME:=Atheros AP121-MINI reference board + PACKAGES:= +endef + +define Profile/AP121MINI/Description + Package set optimized for the Atheros AP121-MINI reference board. +endef + +$(eval $(call Profile,AP121MINI)) + +define Profile/AP132 + NAME:=Atheros AP132 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP132/Description + Package set optimized for the Atheros AP132 reference board. +endef + +$(eval $(call Profile,AP132)) + +define Profile/AP135 + NAME:=Atheros AP135 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP135/Description + Package set optimized for the Atheros AP135 reference board. +endef + +$(eval $(call Profile,AP135)) + +define Profile/AP136 + NAME:=Atheros AP136 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP136/Description + Package set optimized for the Atheros AP136 reference board. +endef + +$(eval $(call Profile,AP136)) + +define Profile/AP143 + NAME:=Qualcomm Atheros AP143 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP143/Description + Package set optimized for the Qualcomm Atheros AP143 reference board. +endef + +$(eval $(call Profile,AP143)) + +define Profile/AP147 + NAME:=Qualcomm Atheros AP147 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP147/Description + Package set optimized for the Atheros AP147 reference board. +endef + +$(eval $(call Profile,AP147)) + +define Profile/AP152 + NAME:=Qualcomm Atheros AP152 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP152/Description + Package set optimized for the Qualcomm Atheros AP152 reference board. +endef + +$(eval $(call Profile,AP152)) + +define Profile/AP81 + NAME:=Atheros AP81 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP81/Description + Package set optimized for the Atheros AP81 reference board. +endef + +$(eval $(call Profile,AP81)) + +define Profile/AP83 + NAME:=Atheros AP83 reference board + PACKAGES:=kmod-usb-core kmod-usb2 \ + vsc7385-ucode-ap83 vsc7395-ucode-ap83 +endef + +define Profile/AP83/Description + Package set optimized for the Atheros AP83 reference board. +endef + +$(eval $(call Profile,AP83)) + +define Profile/AP96 + NAME:=Atheros AP96 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP96/Description + Package set optimized for the Atheros AP96 reference board. +endef + +$(eval $(call Profile,AP96)) + +define Profile/DB120 + NAME:=Atheros DB120 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/DB120/Description + Package set optimized for the Atheros DB120 reference board. +endef + +$(eval $(call Profile,DB120)) + +define Profile/PB42 + NAME:=Atheros PB42 reference board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/PB42/Description + Package set optimized for the Atheros PB42 reference board. +endef + +$(eval $(call Profile,PB42)) + +define Profile/PB44 + NAME:=Atheros PB44 reference board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 \ + vsc7385-ucode-pb44 vsc7395-ucode-pb44 +endef + +define Profile/PB44/Description + Package set optimized for the Atheros PB44 reference board. +endef + +$(eval $(call Profile,PB44)) + +define Profile/PB92 + NAME:=Atheros PB92 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/PB92/Description + Package set optimized for the Atheros PB92 reference board. +endef + +$(eval $(call Profile,PB92)) diff --git a/target/linux/ar71xx/generic/profiles/atlantis.mk b/target/linux/ar71xx/generic/profiles/atlantis.mk new file mode 100644 index 0000000..073d8d1 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/atlantis.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/A02RBW300N + NAME:=Atlantis-Land A02-RB-W300N + PACKAGES:= +endef + +define Profile/A02RBW300N/Description + Package set optimized for the Atlantis-Land A02-RB-W300N. +endef + +$(eval $(call Profile,A02RBW300N)) diff --git a/target/linux/ar71xx/generic/profiles/belkin.mk b/target/linux/ar71xx/generic/profiles/belkin.mk new file mode 100644 index 0000000..c8f6bde --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/belkin.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/F9K1115V2 + NAME:=Belkin AC1750DB (F9K1115V2) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb3 kmod-ledtrig-usbdev \ + kmod-ath10k +endef + +define Profile/F9K1115V2/Description + Package set optimized for the Belkin AC1750DB (F9K1115V2) board. +endef + +$(eval $(call Profile,F9K1115V2)) diff --git a/target/linux/ar71xx/generic/profiles/bhu.mk b/target/linux/ar71xx/generic/profiles/bhu.mk new file mode 100644 index 0000000..f21b3c3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/bhu.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 BHU Networks. +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BXU2000N2 + NAME:=BHU BXU2000n-2 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-usb-storage +endef + +define Profile/BXU2000N2/Description + Package set optimized for the BHU BXU2000n-2. +endef + +$(eval $(call Profile,BXU2000N2)) diff --git a/target/linux/ar71xx/generic/profiles/buffalo.mk b/target/linux/ar71xx/generic/profiles/buffalo.mk new file mode 100644 index 0000000..900f6a8 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/buffalo.mk @@ -0,0 +1,118 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WZRHPG300NH + NAME:=Buffalo WZR-HP-G300NH + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG300NH/Description + Package set optimized for the Buffalo WZR-HP-G300NH and WZR-HP-G301NH +endef + +$(eval $(call Profile,WZRHPG300NH)) + +define Profile/WZRHPG300NH2 + NAME:=Buffalo WZR-HP-G300NH2 + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG300NH/Description + Package set optimized for the Buffalo WZR-HP-G300NH2 +endef + +$(eval $(call Profile,WZRHPG300NH2)) + +define Profile/WZRHPAG300H + NAME:=Buffalo WZR-HP-AG300H + PACKAGES:=kmod-usb-ohci kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPAG300H/Description + Package set optimized for the Buffalo WZR-HP-AG300H +endef + +$(eval $(call Profile,WZRHPAG300H)) + +define Profile/WZRHPG450H + NAME:=Buffalo WZR-HP-G450H + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG450H/Description + Package set optimized for the Buffalo WZR-HP-G450H +endef + +$(eval $(call Profile,WZRHPG450H)) + +define Profile/WZR450HP2 + NAME:=Buffalo WZR-450HP2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZR450HP2/Description + Package set optimized for the Buffalo WZR-450HP2 +endef + +$(eval $(call Profile,WZR450HP2)) + +define Profile/WZR600DHP + NAME:=Buffalo WZR-600DHP + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZR600DHP/Description + Package set optimized for the Buffalo WZR-600DHP +endef + +$(eval $(call Profile,WZR600DHP)) + +define Profile/WHRG301N + NAME:=Buffalo WHR-G301N + PACKAGES:= +endef + +define Profile/WHRG301N/Description + Package set optimized for the Buffalo WHR-G301N. +endef + +$(eval $(call Profile,WHRG301N)) + + +define Profile/WHRHPG300N + NAME:=Buffalo WHR-HP-G300N + PACKAGES:= +endef + +define Profile/WHRHPG300N/Description + Package set optimized for the Buffalo WHR-HP-G300N +endef + +$(eval $(call Profile,WHRHPG300N)) + + +define Profile/WHRHPGN + NAME:=Buffalo WHR-HP-GN + PACKAGES:= +endef + +define Profile/WHRHPGN/Description + Package set optimized for the Buffalo WHR-HP-GN. +endef + +$(eval $(call Profile,WHRHPGN)) + +define Profile/WLAEAG300N + NAME:=Buffalo WLAE-AG300N + PACKAGES:=kmod-ledtrig-netdev +endef + +define Profile/WLAEAG300N/Description + Package set optimized for the Buffalo WLAE-AG300N +endef + +$(eval $(call Profile,WLAEAG300N)) diff --git a/target/linux/ar71xx/generic/profiles/comfast.mk b/target/linux/ar71xx/generic/profiles/comfast.mk new file mode 100644 index 0000000..5d447e5 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/comfast.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CF-E316N-V2 + NAME:=COMFAST CF-E316N v2 + PACKAGES:= +endef + +define Profile/CF-E316N-V2/Description + Package set optimised for the COMFAST CF-E316N v2 + by Shenzhen Four Seas Global Link Network Technology Co., Ltd + aka CF-E316V2, CF-E316N-V2 and CF-E316Nv2.0 (no FCC ID) +endef + +$(eval $(call Profile,CF-E316N-V2)) diff --git a/target/linux/ar71xx/generic/profiles/compex.mk b/target/linux/ar71xx/generic/profiles/compex.mk new file mode 100644 index 0000000..2f6e0b2 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/compex.mk @@ -0,0 +1,58 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WP543 + NAME:=Compex WP543/WPJ543 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/WP543/Description + Package set optimized for the Compex WP543/WPJ543 boards. +endef + +$(eval $(call Profile,WP543)) + +define Profile/WPE72 + NAME:=Compex WPE72/WPE72NX + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/WPE72/Description + Package set optimized for the Compex WPE72 boards including Compex WPE72NX Indoor Access Point. +endef + +$(eval $(call Profile,WPE72)) + +define Profile/WPJ344 + NAME:=Compex WPJ344 +endef + +define Profile/WPJ344/Description + Package set optimized for the Compex WPJ344 board. +endef + +$(eval $(call Profile,WPJ344)) + +define Profile/WPJ531 + NAME:=Compex WPJ531 +endef + +define Profile/WPJ531/Description + Package set optimized for the Compex WPJ531 board. +endef + +$(eval $(call Profile,WPJ531)) + +define Profile/WPJ558 + NAME:=Compex WPJ558 +endef + +define Profile/WPJ558/Description + Package set optimized for the Compex WPJ558 board. +endef + +$(eval $(call Profile,WPJ558)) diff --git a/target/linux/ar71xx/generic/profiles/d-link.mk b/target/linux/ar71xx/generic/profiles/d-link.mk new file mode 100644 index 0000000..f782a41 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/d-link.mk @@ -0,0 +1,150 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DHP1565A1 + NAME:=D-Link DHP-1565 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/DHP1565A1/Description + Package set optimized for the D-Link DHP-1565 rev. A1. +endef + +$(eval $(call Profile,DHP1565A1)) + +define Profile/DIR505A1 + NAME:=D-Link DIR-505 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR505A1/Description + Package set optimized for the D-Link DIR-505 rev. A1. +endef + +$(eval $(call Profile,DIR505A1)) + +define Profile/DIR600A1 + NAME:=D-Link DIR-600 rev. A1 + PACKAGES:= +endef + +define Profile/DIR600A1/Description + Package set optimized for the D-Link DIR-600 rev. A1. +endef + +$(eval $(call Profile,DIR600A1)) + +define Profile/DIR601A1 + NAME:=D-Link DIR-601 rev. A1 + PACKAGES:= +endef + +define Profile/DIR601A1/Description + Package set optimized for the D-Link DIR-601 rev. A1. +endef + +$(eval $(call Profile,DIR601A1)) + +define Profile/DIR601B1 + NAME:=D-Link DIR-601 rev. B1 + PACKAGES:= +endef + +define Profile/DIR601B1/Description + Package set optimized for the D-Link DIR-601 rev. B1. +endef + +$(eval $(call Profile,DIR601B1)) + +define Profile/DIR615C1 + NAME:=D-Link DIR-615 rev. C1 + PACKAGES:= +endef + +define Profile/DIR615C1/Description + Package set optimized for the D-Link DIR-615 rev. C1. +endef + +$(eval $(call Profile,DIR615C1)) + +define Profile/DIR615E1 + NAME:=D-Link DIR-615 rev. E1 + PACKAGES:= +endef + +define Profile/DIR615E1/Description + Package set optimized for the D-Link DIR-615 rev. E1. +endef + +$(eval $(call Profile,DIR615E1)) + +define Profile/DIR615E4 + NAME:=D-Link DIR-615 rev. E4 + PACKAGES:= +endef + +define Profile/DIR615E4/Description + Package set optimized for the D-Link DIR-615 rev. E4. +endef + +$(eval $(call Profile,DIR615E4)) + +define Profile/DIR615IX + NAME:=D-Link DIR-615 rev. I1 + PACKAGES:= +endef + +define Profile/DIR615IX/Description + Package set optimized for the D-Link DIR-615 rev. I1. +endef + +$(eval $(call Profile,DIR615IX)) + +define Profile/DIR825B1 + NAME:=D-Link DIR-825 rev. B1 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR825B1/Description + Package set optimized for the D-Link DIR-825 rev. B1. +endef + +$(eval $(call Profile,DIR825B1)) + +define Profile/DIR825C1 + NAME:=D-Link DIR-825 rev. C1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR825C1/Description + Package set optimized for the D-Link DIR-825 rev. C1. +endef + +$(eval $(call Profile,DIR825C1)) + +define Profile/DIR835A1 + NAME:=D-Link DIR-835 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/DIR835A1/Description + Package set optimized for the D-Link DIR-835 rev. A1. +endef + +$(eval $(call Profile,DIR835A1)) + + +define Profile/DGL5500A1 + NAME:=D-Link DGL-5500 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ath10k +endef + +define Profile/DIR5500A1/Description + Package set optimized for the D-Link DGL-5500 rev. A1. +endef + +$(eval $(call Profile,DGL5500A1)) diff --git a/target/linux/ar71xx/generic/profiles/devolo-dlan.mk b/target/linux/ar71xx/generic/profiles/devolo-dlan.mk new file mode 100644 index 0000000..741f5d5 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/devolo-dlan.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/dLAN_pro_500_wp + NAME:=devolo dLAN pro 500 Wireless+ + PACKAGES:=open-plc-utils open-plc-utils-chkpib open-plc-utils-getpib open-plc-utils-modpib \ + open-plc-utils-setpib open-plc-utils-hpavkey open-plc-utils-amphost \ + open-plc-utils-plctool open-plc-utils-pibdump open-plc-utils-plcstat \ + ebtables hostapd-utils wifitoggle wpad +endef + +define Profile/dLAN_pro_500_wp/Description + Package set optimized for the devolo dLAN pro 500 Wireless+. +endef +$(eval $(call Profile,dLAN_pro_500_wp)) + +define Profile/dLAN_pro_1200_ac + NAME:=devolo dLAN pro 1200+ WiFi ac + PACKAGES:=open-plc-utils open-plc-utils-chkpib open-plc-utils-getpib open-plc-utils-modpib \ + open-plc-utils-setpib open-plc-utils-hpavkey open-plc-utils-plchost \ + open-plc-utils-plctool open-plc-utils-pibdump open-plc-utils-plcstat \ + ebtables hostapd-utils wifitoggle wpad ip-full kmod-ath10k kmod-leds-gpio \ + kmod-ledtrig-gpio +endef + +define Profile/dLAN_pro_1200_ac/Description + Package set optimized for the devolo dLAN pro 1200+ WiFi ac. +endef +$(eval $(call Profile,dLAN_pro_1200_ac)) diff --git a/target/linux/ar71xx/generic/profiles/dragino.mk b/target/linux/ar71xx/generic/profiles/dragino.mk new file mode 100644 index 0000000..ff222c1 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/dragino.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DRAGINO2 + NAME:=DRAGINO2 + PACKAGES:=kmod-ath9k kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DRAGINO2/Description + Package set optimized for the DRAGINO v2. +endef + +$(eval $(call Profile,DRAGINO2)) diff --git a/target/linux/ar71xx/generic/profiles/easylink.mk b/target/linux/ar71xx/generic/profiles/easylink.mk new file mode 100644 index 0000000..8d327b7 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/easylink.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ELM150 + NAME:=EasyLink EL-M150 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/ELM150/Description + Package set optimized for the EasyLink EL-M150. +endef +$(eval $(call Profile,ELM150)) + + +define Profile/ELMINI + NAME:=EasyLink EL-MINI + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/ELMINI/Description + Package set optimized for the EasyLink EL-MINI. +endef +$(eval $(call Profile,ELMINI)) diff --git a/target/linux/ar71xx/generic/profiles/engenius.mk b/target/linux/ar71xx/generic/profiles/engenius.mk new file mode 100644 index 0000000..7ea93e3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/engenius.mk @@ -0,0 +1,53 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EAP300V2 + NAME:=EnGenius EAP300V2 + PACKAGES:= +endef + +define Profile/EAP300V2/Description + Package set optimized for the EnGenius EAP300V2. +endef + +$(eval $(call Profile,EAP300V2)) + + +define Profile/ESR900 + NAME:=EnGenius ESR900 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/ESR900/Description + Package set optimized for the EnGenius ESR900 +endef + +$(eval $(call Profile,ESR900)) + + +define Profile/ESR1750 + NAME:=EnGenius ESR1750 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage kmod-ath10k wpad-mini +endef + +define Profile/ESR1750/Description + Package set optimized for the EnGenius ESR1750 +endef + +$(eval $(call Profile,ESR1750)) + + +define Profile/EPG5000 + NAME:=EnGenius EPG5000 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage kmod-ath10k wpad-mini +endef + +define Profile/EPG5000/Description + Package set optimized for the EnGenius EPG5000 +endef + +$(eval $(call Profile,EPG5000)) diff --git a/target/linux/ar71xx/generic/profiles/ew.mk b/target/linux/ar71xx/generic/profiles/ew.mk new file mode 100644 index 0000000..b4e15e3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/ew.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EWDORIN + NAME:=Embedded Wireless Dorin Platform + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev kmod-usb-storage \ + kmod-fs-vfat kmod-fs-msdos kmod-fs-ntfs kmod-fs-ext4 \ + kmod-nls-cp437 kmod-nls-cp850 kmod-nls-cp852 kmod-nls-iso8859-1 kmod-nls-utf8 +endef + +define Profile/EWDORIN/Description + Package set optimized for the Dorin Platform. +endef + +$(eval $(call Profile,EWDORIN)) + diff --git a/target/linux/ar71xx/generic/profiles/gl-connect.mk b/target/linux/ar71xx/generic/profiles/gl-connect.mk new file mode 100644 index 0000000..e9377db --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/gl-connect.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/GLINET + NAME:=GL.iNet + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/GLINET/Description + Package set optimized for the GL-Connect GL.iNet v1. +endef + +$(eval $(call Profile,GLINET)) diff --git a/target/linux/ar71xx/generic/profiles/hiwifi.mk b/target/linux/ar71xx/generic/profiles/hiwifi.mk new file mode 100644 index 0000000..5bd2476 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/hiwifi.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2012-2013 Hiwifi Wireless +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/HIWIFI_HC6361 + NAME:=HiWiFi HC6361 + PACKAGES:= kmod-usb-core kmod-usb2 kmod-usb-storage \ + kmod-crypto-deflate kmod-fs-ext4 kmod-ledtrig-gpio \ + kmod-nls-iso8859-1 e2fsprogs +endef + +define Profile/HIWIFI_HC6361/description + Package set optimized for the HiWiFi HC6361. +endef +$(eval $(call Profile,HIWIFI_HC6361)) diff --git a/target/linux/ar71xx/generic/profiles/jjplus.mk b/target/linux/ar71xx/generic/profiles/jjplus.mk new file mode 100644 index 0000000..3f97dbf --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/jjplus.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/JA76PF + NAME:=jjPlus JA76PF + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-hwmon-core kmod-i2c-core kmod-hwmon-lm75 +endef + +define Profile/JA76PF/Description + Package set optimized for the jjPlus JA76PF board. +endef + +$(eval $(call Profile,JA76PF)) + +define Profile/JA76PF2 + NAME:=jjPlus JA76PF2 + PACKAGES:= +endef + +define Profile/JA76PF2/Description + Package set optimized for the jjPlus JA76PF2 board. +endef + +$(eval $(call Profile,JA76PF2)) + +define Profile/JWAP003 + NAME:=jjPlus JWAP0003 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/JWAP003/Description + Package set optimized for the jjPlus JWAP003 board. +endef + +$(eval $(call Profile,JWAP003)) diff --git a/target/linux/ar71xx/generic/profiles/linksys.mk b/target/linux/ar71xx/generic/profiles/linksys.mk new file mode 100644 index 0000000..bedf3a3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/linksys.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRT160NL + NAME:=Linksys WRT160NL + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/WRT160NL/Description + Package set optimized for the Linksys WRT160NL. +endef + +define Profile/WRT400N + NAME:=Linksys WRT400N + PACKAGES:= +endef + +define Profile/WRT400N/Description + Package set optimized for the Linksys WRT400N. +endef + +$(eval $(call Profile,WRT160NL)) +$(eval $(call Profile,WRT400N)) diff --git a/target/linux/ar71xx/generic/profiles/meraki.mk b/target/linux/ar71xx/generic/profiles/meraki.mk new file mode 100644 index 0000000..0d5cda0 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/meraki.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2014-2015 Chris Blake (chrisrblake93@gmail.com) +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MR12 + NAME:=Meraki MR12 + PACKAGES:=kmod-spi-gpio kmod-ath9k +endef + +define Profile/MR12/description + Package set optimized for the Cisco Meraki MR12 Access Point. +endef + +define Profile/MR16 + NAME:=Meraki MR16 + PACKAGES:=kmod-spi-gpio kmod-ath9k +endef + +define Profile/MR16/description + Package set optimized for the Cisco Meraki MR16 Access Point. +endef + +$(eval $(call Profile,MR12)) +$(eval $(call Profile,MR16)) \ No newline at end of file diff --git a/target/linux/ar71xx/generic/profiles/mercury.mk b/target/linux/ar71xx/generic/profiles/mercury.mk new file mode 100644 index 0000000..e66d70d --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/mercury.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + + +define Profile/MAC1200R + NAME:=MERCURY MAC1200R + PACKAGES:=kmod-ath10k +endef + +define Profile/MAC1200R/Description + Package set optimized for the MERCURY MAC1200R. +endef +$(eval $(call Profile,MAC1200R)) diff --git a/target/linux/ar71xx/generic/profiles/nclink.mk b/target/linux/ar71xx/generic/profiles/nclink.mk new file mode 100644 index 0000000..04eb9ec --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/nclink.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/SMART-300 + NAME:=NC-LINK SMART-300 +endef + +define Profile/SMART-300/Description + Package set optimized for the NC-LINK SMART-300. +endef +$(eval $(call Profile,SMART-300)) diff --git a/target/linux/ar71xx/generic/profiles/netgear.mk b/target/linux/ar71xx/generic/profiles/netgear.mk new file mode 100644 index 0000000..16b1087 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/netgear.mk @@ -0,0 +1,84 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WNDAP360 + NAME:=NETGEAR WNDAP360 + PACKAGES:= +endef + +define Profile/WNDAP360/Description + Package set optimized for the NETGEAR WNDAP360 +endef + +$(eval $(call Profile,WNDAP360)) + +define Profile/WNDR3700 + NAME:=NETGEAR WNDR3700/WNDR3800/WNDRMAC + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev kmod-leds-wndr3700-usb +endef + +define Profile/WNDR3700/Description + Package set optimized for the NETGEAR WNDR3700/WNDR3800/WNDRMAC +endef + +$(eval $(call Profile,WNDR3700)) + + +define Profile/WNR2000V3 + NAME:=NETGEAR WNR2000V3 +endef + +define Profile/WNR2000V3/Description + Package set optimized for the NETGEAR WNR2000V3 +endef + +$(eval $(call Profile,WNR2000V3)) + + +define Profile/WNR2000V4 + NAME:=NETGEAR WNR2000V4 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WNR2000V4/Description + Package set optimized for the NETGEAR WNR2000V4 +endef + +$(eval $(call Profile,WNR2000V4)) + + +define Profile/WNR612V2 + NAME:=NETGEAR WNR612V2 / On Networks N150 +endef + +define Profile/WNR612V2/Description + Package set optimized for the NETGEAR WNR612V2 / On Networks N150 +endef + +$(eval $(call Profile,WNR612V2)) + + +define Profile/WNR1000V2 + NAME:=NETGEAR WNR1000V2 +endef + +define Profile/WNR1000V2/Description + Package set optimized for the NETGEAR WNR1000V2 +endef + +$(eval $(call Profile,WNR1000V2)) + + +define Profile/WNR2200 + NAME:=NETGEAR WNR2200 +endef + +define Profile/WNR2200/Description + Package set optimized for the NETGEAR WNR2200 +endef + +$(eval $(call Profile,WNR2200)) diff --git a/target/linux/ar71xx/generic/profiles/onion.mk b/target/linux/ar71xx/generic/profiles/onion.mk new file mode 100644 index 0000000..dd5874e --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/onion.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OMEGA + NAME:=Onion Omega + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage kmod-i2c-core kmod-i2c-gpio-custom kmod-spi-bitbang kmod-spi-dev kmod-spi-gpio kmod-spi-gpio-custom kmod-usb-serial +endef + +define Profile/OMEGA/Description + Package set optimized for the Onion Omega development platform. +endef +$(eval $(call Profile,OMEGA)) diff --git a/target/linux/ar71xx/generic/profiles/oolite.mk b/target/linux/ar71xx/generic/profiles/oolite.mk new file mode 100644 index 0000000..448f08d --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/oolite.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OOLITE + NAME:=OOLITE + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + + +define Profile/OOLITE/Description + Package set optimized for the OOLITE. +endef +$(eval $(call Profile,OOLITE)) + diff --git a/target/linux/ar71xx/generic/profiles/openmesh.mk b/target/linux/ar71xx/generic/profiles/openmesh.mk new file mode 100644 index 0000000..1c51e93 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/openmesh.mk @@ -0,0 +1,73 @@ +# +# Copyright (C) 2011-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OM2P + NAME:=OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-LC + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/OM2P/Description + Package set optimized for the OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-LC. +endef + +$(eval $(call Profile,OM2P)) + +define Profile/OM5P + NAME:=OpenMesh OM5P/OM5P-AN + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/OM5P/Description + Package set optimized for the OpenMesh OM5P/OM5P-AN. +endef + +$(eval $(call Profile,OM5P)) + +define Profile/MR600 + NAME:=OpenMesh MR600 + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/MR600/Description + Package set optimized for the OpenMesh MR600. +endef + +$(eval $(call Profile,MR600)) + +define Profile/MR900 + NAME:=OpenMesh MR900/MR900v2 + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/MR900/Description + Package set optimized for the OpenMesh MR900/MR900v2. +endef + +$(eval $(call Profile,MR900)) + +define Profile/MR1750 + NAME:=OpenMesh MR1750 + PACKAGES:=kmod-ath9k kmod-ath10k +endef + +define Profile/MR1750/Description + Package set optimized for the OpenMesh MR1750. +endef + +$(eval $(call Profile,MR1750)) + +define Profile/OPENMESH + NAME:=OpenMesh products + PACKAGES:=kmod-ath9k kmod-ath10k om-watchdog +endef + +define Profile/OPENMESH/Description + Build images for all OpenMesh products. +endef + +$(eval $(call Profile,OPENMESH)) + diff --git a/target/linux/ar71xx/generic/profiles/pcs.mk b/target/linux/ar71xx/generic/profiles/pcs.mk new file mode 100644 index 0000000..1399ef4 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/pcs.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2009 OpenWrt.org +# Copyright (C) 2012 PowerCloud Systems +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/UBDEV01 + NAME:=PowerCloud Systems ubdev01 model + PACKAGES:= +endef + +define Profile/UBDEV01/Description + Package set optimized for the PowerCloud Systems ubdev01 board. +endef + +$(eval $(call Profile,UBDEV01)) + +define Profile/DLRTDEV01 + NAME:=PowerCloud Systems dlrtdev01 model + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DLRTDEV01/Description + Package set optimized for the PowerCloud Systems dlrtdev01 board. +endef + +$(eval $(call Profile,DLRTDEV01)) diff --git a/target/linux/ar71xx/generic/profiles/planex.mk b/target/linux/ar71xx/generic/profiles/planex.mk new file mode 100644 index 0000000..3d192ba --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/planex.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MZKW04NU + NAME:=Planex MZK-W04NU + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/MZKW04NU/Description + Package set optimized for the Planex MZK-W04NU. +endef + +$(eval $(call Profile,MZKW04NU)) + +define Profile/MZKW300NH + NAME:=Planex MZK-W300NH + PACKAGES:= +endef + +define Profile/MZKW300NH/Description + Package set optimized for the Planex MZK-W300NH. +endef + +$(eval $(call Profile,MZKW300NH)) diff --git a/target/linux/ar71xx/generic/profiles/qihoo.mk b/target/linux/ar71xx/generic/profiles/qihoo.mk new file mode 100644 index 0000000..0ec778a --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/qihoo.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/QIHOO360 + NAME:=Qihoo 360 C301 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-ath10k +endef + +define Profile/QIHOO360/Description + Package set optimized for the Qihoo 360 C301 device. +endef +$(eval $(call Profile,QIHOO360)) diff --git a/target/linux/ar71xx/generic/profiles/redwave.mk b/target/linux/ar71xx/generic/profiles/redwave.mk new file mode 100644 index 0000000..069dd8f --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/redwave.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RW2458N + NAME:=Redwave RW2458N + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-ath9k wpad-mini +endef + +define Profile/RW2458N/Description + Package set optimized for the Redwave RW2458N board. +endef + +$(eval $(call Profile,RW2458N)) diff --git a/target/linux/ar71xx/generic/profiles/rosewill.mk b/target/linux/ar71xx/generic/profiles/rosewill.mk new file mode 100644 index 0000000..00c1d7d --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/rosewill.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RNXN360RT + NAME:=Rosewill RNX-N360RT + PACKAGES:= +endef + +define Profile/RNXN360RT/Description + Package set optimized for the Rosewill RNX-N360RT. +endef +$(eval $(call Profile,RNXN360RT)) diff --git a/target/linux/ar71xx/generic/profiles/senao.mk b/target/linux/ar71xx/generic/profiles/senao.mk new file mode 100644 index 0000000..20a79e9 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/senao.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CAP4200AG + NAME:=Senao CAP4200AG + PACKAGES:=kmod-ath9k +endef + +define Profile/CAP4200AG/Description + Package set optimized for the Senao CAP4200AG. +endef + +$(eval $(call Profile,CAP4200AG)) diff --git a/target/linux/ar71xx/generic/profiles/sitecom.mk b/target/linux/ar71xx/generic/profiles/sitecom.mk new file mode 100644 index 0000000..3dd8e43 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/sitecom.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +define Profile/WLR8100 + NAME:=Sitecom WLR-8100 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-usb3 +endef + +define Profile/WLR8100/Description + Package set optimized for the Sitecom WLR-8100 +endef + +$(eval $(call Profile,WLR8100)) diff --git a/target/linux/ar71xx/generic/profiles/smartelectronics.mk b/target/linux/ar71xx/generic/profiles/smartelectronics.mk new file mode 100644 index 0000000..6d3dc8c --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/smartelectronics.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BSB + NAME:=Smart Electronics Black Swift board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/BSB/Description + Package set optimized for the Smart Electronics Black Swift board. +endef + +$(eval $(call Profile,BSB)) diff --git a/target/linux/ar71xx/generic/profiles/tp-link.mk b/target/linux/ar71xx/generic/profiles/tp-link.mk new file mode 100644 index 0000000..2875290 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/tp-link.mk @@ -0,0 +1,409 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ARCHERC7 + NAME:=TP-LINK Archer C5/C7 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-ath10k +endef + +define Profile/ARCHERC7/Description + Package set optimized for the TP-LINK Archer C5/C7. +endef +$(eval $(call Profile,ARCHERC7)) + + +define Profile/CPE510 + NAME:=TP-LINK CPE210/220/510/520 + PACKAGES:=rssileds +endef + +define Profile/CPE510/Description + Package set optimized for the TP-LINK CPE210/220/510/520. +endef +$(eval $(call Profile,CPE510)) + + +define Profile/TLMR10U + NAME:=TP-LINK TL-MR10U + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/TLMR10U/Description + Package set optimized for the TP-LINK TL-MR10U. +endef +$(eval $(call Profile,TLMR10U)) + + +define Profile/TLMR11U + NAME:=TP-LINK TL-MR11U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR11U/Description + Package set optimized for the TP-LINK TL-MR11U. +endef +$(eval $(call Profile,TLMR11U)) + +define Profile/TLMR12U + NAME:=TP-LINK TL-MR12U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR12U/Description + Package set optimized for the TP-LINK TL-MR12U. +endef + +$(eval $(call Profile,TLMR12U)) + +define Profile/TLMR13U + NAME:=TP-LINK TL-MR13U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR13U/Description + Package set optimized for the TP-LINK TL-MR13U. +endef +$(eval $(call Profile,TLMR13U)) + + +define Profile/TLMR3020 + NAME:=TP-LINK TL-MR3020 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3020/Description + Package set optimized for the TP-LINK TL-MR3020. +endef +$(eval $(call Profile,TLMR3020)) + + +define Profile/TLMR3040 + NAME:=TP-LINK TL-MR3040 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3040/Description + Package set optimized for the TP-LINK TL-MR3040. +endef +$(eval $(call Profile,TLMR3040)) + + +define Profile/TLMR3220 + NAME:=TP-LINK TL-MR3220 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3220/Description + Package set optimized for the TP-LINK TL-MR3220. +endef +$(eval $(call Profile,TLMR3220)) + + +define Profile/TLMR3420 + NAME:=TP-LINK TL-MR3420 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3420/Description + Package set optimized for the TP-LINK TL-MR3420. +endef +$(eval $(call Profile,TLMR3420)) + + +define Profile/TLWR703 + NAME:=TP-LINK TL-WR703N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR703/Description + Package set optimized for the TP-LINK TL-WR703N. +endef +$(eval $(call Profile,TLWR703)) + + +define Profile/TLWR710 + NAME:=TP-LINK TL-WR710N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR710/Description + Package set optimized for the TP-LINK TL-WR710N. +endef +$(eval $(call Profile,TLWR710)) + + +define Profile/TLWR720 + NAME:=TP-LINK TL-WR720N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR720/Description + Package set optimized for the TP-LINK TL-WR720N. +endef +$(eval $(call Profile,TLWR720)) + + +define Profile/TLWA701 + NAME:=TP-LINK TL-WA701N/ND + PACKAGES:= +endef + +define Profile/TLWA701/Description + Package set optimized for the TP-LINK TL-WA701N/ND. +endef +$(eval $(call Profile,TLWA701)) + +define Profile/TLWA7210 + NAME:=TP-LINK TL-WA7210N + PACKAGES:=rssileds kmod-ledtrig-netdev +endef + +define Profile/TLWA7210/Description + Package set optimized for the TP-LINK TL-WA7210N. +endef +$(eval $(call Profile,TLWA7210)) + +define Profile/TLWA730RE + NAME:=TP-LINK TL-WA730RE + PACKAGES:= +endef + +define Profile/TLWA730RE/Description + Package set optimized for the TP-LINK TL-WA730RE. +endef +$(eval $(call Profile,TLWA730RE)) + +define Profile/TLWA750 + NAME:=TP-LINK TL-WA750RE + PACKAGES:=rssileds +endef + +define Profile/TLWA750/Description + Package set optimized for the TP-LINK TL-WA750RE. +endef +$(eval $(call Profile,TLWA750)) + + +define Profile/TLWA7510 + NAME:=TP-LINK TL-WA7510N + PACKAGES:= +endef + +define Profile/TLWA7510/Description + Package set optimized for the TP-LINK TL-WA7510N. +endef +$(eval $(call Profile,TLWA7510)) + +define Profile/TLWA801 + NAME:=TP-LINK TL-WA801N/ND + PACKAGES:= +endef + +define Profile/TLWA801/Description + Package set optimized for the TP-LINK TL-WA801N/ND. +endef +$(eval $(call Profile,TLWA801)) + +define Profile/TLWA830 + NAME:=TP-LINK TL-WA830RE + PACKAGES:= +endef + +define Profile/TLWA830/Description + Package set optimized for the TP-LINK TL-WA830RE. +endef +$(eval $(call Profile,TLWA830)) + + +define Profile/TLWA850 + NAME:=TP-LINK TL-WA850RE + PACKAGES:=rssileds +endef + +define Profile/TLWA850/Description + Package set optimized for the TP-LINK TL-WA850RE. +endef +$(eval $(call Profile,TLWA850)) + + +define Profile/TLWA860 + NAME:=TP-LINK TL-WA860RE + PACKAGES:= +endef + +define Profile/TLWA860/Description + Package set optimized for the TP-LINK TL-WA860RE. +endef +$(eval $(call Profile,TLWA860)) + + +define Profile/TLWA901 + NAME:=TP-LINK TL-WA901N/ND + PACKAGES:= +endef + +define Profile/TLWA901/Description + Package set optimized for the TP-LINK TL-WA901N/ND. +endef +$(eval $(call Profile,TLWA901)) + + +define Profile/TLWDR4300 + NAME:=TP-LINK TL-WDR3500/3600/4300/4310/MW4350R + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR4300/Description + Package set optimized for the TP-LINK TL-WDR3500/3600/4300/4310/MW4350R. +endef +$(eval $(call Profile,TLWDR4300)) + + +define Profile/TLWDR3320V2 + NAME:=TP-LINK TL-WDR3320v2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR3320V2/Description + Package set optimized for the TP-LINK TL-WDR3320v2. +endef +$(eval $(call Profile,TLWDR3320V2)) + + +define Profile/TLWDR4900V2 + NAME:=TP-LINK TL-WDR4900v2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR4900V2/Description + Package set optimized for the TP-LINK TL-WDR4900v2. +endef +$(eval $(call Profile,TLWDR4900V2)) + + +define Profile/TLWDR6500V2 + NAME:=TP-LINK TL-WDR6500v2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-ath10k +endef + +define Profile/TLWDR6500V2/Description + Package set optimized for the TP-LINK TL-WDR6500v2. +endef +$(eval $(call Profile,TLWDR6500V2)) + + +define Profile/TLWR740 + NAME:=TP-LINK TL-WR740N/ND + PACKAGES:= +endef + +define Profile/TLWR740/Description + Package set optimized for the TP-LINK TL-WR740N/ND. +endef +$(eval $(call Profile,TLWR740)) + + +define Profile/TLWR741 + NAME:=TP-LINK TL-WR741N/ND + PACKAGES:= +endef + +define Profile/TLWR741/Description + Package set optimized for the TP-LINK TL-WR741N/ND. +endef +$(eval $(call Profile,TLWR741)) + + +define Profile/TLWR743 + NAME:=TP-LINK TL-WR743N/ND + PACKAGES:= +endef + +define Profile/TLWR743/Description + Package set optimized for the TP-LINK TL-WR743N/ND. +endef +$(eval $(call Profile,TLWR743)) + + +define Profile/TLWR841 + NAME:=TP-LINK TL-WR841N/ND + PACKAGES:= +endef + +define Profile/TLWR841/Description + Package set optimized for the TP-LINK TL-WR841N/ND. +endef +$(eval $(call Profile,TLWR841)) + + +define Profile/TLWR842 + NAME:=TP-LINK TL-WR842N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR842/Description + Package set optimized for the TP-LINK TL-WR842N/ND. +endef +$(eval $(call Profile,TLWR842)) + + +define Profile/TLWR843 + NAME:=TP-LINK TL-WR843N/ND + PACKAGES:= +endef + +define Profile/TLWR843/Description + Package set optimized for the TP-LINK TL-WR843N/ND. +endef +$(eval $(call Profile,TLWR843)) + + +define Profile/TLWR941 + NAME:=TP-LINK TL-WR941N/ND + PACKAGES:= +endef + +define Profile/TLWR941/Description + Package set optimized for the TP-LINK TL-WR941N/ND. +endef +$(eval $(call Profile,TLWR941)) + + +define Profile/TLWR1041 + NAME:=TP-LINK TL-WR1041N + PACKAGES:= +endef + +define Profile/TLWR1041/Description + Package set optimized for the TP-LINK TL-WR1041N/ND. +endef +$(eval $(call Profile,TLWR1041)) + + +define Profile/TLWR1043 + NAME:=TP-LINK TL-WR1043N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR1043/Description + Package set optimized for the TP-LINK TL-WR1043N/ND. +endef +$(eval $(call Profile,TLWR1043)) + + +define Profile/TLWR2543 + NAME:=TP-LINK TL-WR2543N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR2543/Description + Package set optimized for the TP-LINK TL-WR2543N/ND. +endef +$(eval $(call Profile,TLWR2543)) diff --git a/target/linux/ar71xx/generic/profiles/trendnet.mk b/target/linux/ar71xx/generic/profiles/trendnet.mk new file mode 100644 index 0000000..42d05b6 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/trendnet.mk @@ -0,0 +1,62 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/TEW632BRP + NAME:=TRENDNet TEW-632BRP + PACKAGES:= +endef + +define Profile/TEW632BRP/Description + Package set optimized for the TRENDNet TEW-632BRP. +endef + +$(eval $(call Profile,TEW632BRP)) + +define Profile/TEW652BRP + NAME:=TRENDNet TEW-652BRP + PACKAGES:= +endef + +define Profile/TEW652BRP/Description + Package set optimized for the TRENDNet TEW-652BRP. +endef + +$(eval $(call Profile,TEW652BRP)) + +define Profile/TEW673GRU + NAME:=TRENDNet TEW-673GRU + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/TEW673GRU/Description + Package set optimized for the TRENDNet TEW-673GRU. +endef + +$(eval $(call Profile,TEW673GRU)) + +define Profile/TEW712BR + NAME:=TRENDNet TEW-712BR + PACKAGES:= +endef + +define Profile/TEW712BR/Description + Package set optimized for the TRENDNet TEW-712BR. +endef + +$(eval $(call Profile,TEW712BR)) + + +define Profile/TEW732BR + NAME:=TRENDNet TEW-732BR + PACKAGES:= +endef + +define Profile/TEW732BR/Description + Package set optimized for the TRENDNet TEW-732BR. +endef + +$(eval $(call Profile,TEW732BR)) diff --git a/target/linux/ar71xx/generic/profiles/ubnt.mk b/target/linux/ar71xx/generic/profiles/ubnt.mk new file mode 100644 index 0000000..d8e24d0 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/ubnt.mk @@ -0,0 +1,73 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/UBNTRS + NAME:=Ubiquiti RouterStation + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNTRS/Description + Package set optimized for the Ubiquiti RouterStation. +endef + +$(eval $(call Profile,UBNTRS)) + +define Profile/UBNTRSPRO + NAME:=Ubiquiti RouterStation Pro + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNTRSPRO/Description + Package set optimized for the Ubiquiti RouterStation Pro. +endef + +$(eval $(call Profile,UBNTRSPRO)) + +define Profile/UBNTUNIFI + NAME:=Ubiquiti UniFi AP + PACKAGES:= +endef + +define Profile/UBNTUNIFI/Description + Package set optimized for the Ubiquiti UniFi AP. +endef + +$(eval $(call Profile,UBNTUNIFI)) + +define Profile/UBNTUNIFIOUTDOOR + NAME:=Ubiquiti UniFiAP Outdoor + PACKAGES:= +endef + +define Profile/UBNTUNIFIOUTDOOR/Description + Package set optimized for the Ubiquiti UniFiAP Outdoor. +endef + +$(eval $(call Profile,UBNTUNIFIOUTDOOR)) + +define Profile/UAPPRO + NAME:=Ubiquiti UniFi AP Pro + PACKAGES:= +endef + +define Profile/UAPPRO/Description + Package set optimized for the Ubiquiti UniFi AP Pro. +endef + +$(eval $(call Profile,UAPPRO)) + + +define Profile/UBNT + NAME:=Ubiquiti Products + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNT/Description + Build images for all Ubiquiti products (including LS-SR71, RouterStation and RouterStation Pro) +endef + +$(eval $(call Profile,UBNT)) diff --git a/target/linux/ar71xx/generic/profiles/wd.mk b/target/linux/ar71xx/generic/profiles/wd.mk new file mode 100644 index 0000000..b8cb99b --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/wd.mk @@ -0,0 +1,36 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MYNETN600 + NAME:=WD My Net N600 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/MYNETN600/Description + Package set optimized for the WD My Net N600 device. +endef +$(eval $(call Profile,MYNETN600)) + +define Profile/MYNETN750 + NAME:=WD My Net N750 + PACKAGES:=kmod-usb-core kmod-usb2 +endef +define Profile/MYNETN750/Description + Package set optimized for the WD My Net N750 device. +endef + +$(eval $(call Profile,MYNETN750)) + +define Profile/MYNETREXT + NAME:=WD My Net Wi-Fi Range Extender + PACKAGES:=rssileds +endef + +define Profile/MYNETREXT/Description + Package set optimized for the WD My Net Wi-Fi Range Extender device. +endef +$(eval $(call Profile,MYNETREXT)) diff --git a/target/linux/ar71xx/generic/profiles/weio.mk b/target/linux/ar71xx/generic/profiles/weio.mk new file mode 100644 index 0000000..227cec9 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/weio.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WEIO + NAME:=WeIO + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/WEIO/Description + Package set optimized for the WeIO board. +endef + +$(eval $(call Profile,WEIO)) diff --git a/target/linux/ar71xx/generic/profiles/zcomax.mk b/target/linux/ar71xx/generic/profiles/zcomax.mk new file mode 100644 index 0000000..b9ab77e --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/zcomax.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ZCN1523H28 + NAME:=Zcomax ZCN-1523H-2-8 + PACKAGES:= +endef + +define Profile/ZCN1523H28/Description + Package set optimized for the Zcomax ZCN-1523H-2-8 board. +endef + +$(eval $(call Profile,ZCN1523H28)) + +define Profile/ZCN1523H516 + NAME:=Zcomax ZCN-1523H-5-16 + PACKAGES:= +endef + +define Profile/ZCN1523H516/Description + Package set optimized for the Zcomax ZCN-1523H-5-16 board. +endef + +$(eval $(call Profile,ZCN1523H516)) diff --git a/target/linux/ar71xx/generic/profiles/zyxel.mk b/target/linux/ar71xx/generic/profiles/zyxel.mk new file mode 100644 index 0000000..66258bd --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/zyxel.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NBG_460N_550N_550NH + NAME:=Zyxel NBG 460N/550N/550NH + PACKAGES:=kmod-rtc-pcf8563 +endef + +define Profile/NBG_460N_550N_550NH/Description + Package set optimized for the Zyxel NBG 460N/550N/550NH Routers. +endef + +$(eval $(call Profile,NBG_460N_550N_550NH)) diff --git a/target/linux/ar71xx/generic/target.mk b/target/linux/ar71xx/generic/target.mk new file mode 100644 index 0000000..64eb205 --- /dev/null +++ b/target/linux/ar71xx/generic/target.mk @@ -0,0 +1,8 @@ +BOARDNAME:=Generic +FEATURES += squashfs + +define Target/Description + Build firmware images for generic Atheros AR71xx/AR913x/AR934x based boards. +endef + + diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile new file mode 100644 index 0000000..ca63129 --- /dev/null +++ b/target/linux/ar71xx/image/Makefile @@ -0,0 +1,2381 @@ +# +# Copyright (C) 2008-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +JFFS2_BLOCKSIZE = 64k 128k 256k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +IMAGE_PROFILE:=$(if $(PROFILE),$(PROFILE),Default) + +KERNEL_LOADADDR = 0x80060000 + +DEVICE_VARS += NETGEAR_KERNEL_MAGIC NETGEAR_BOARD_ID NETGEAR_HW_ID CMDLINE CONSOLE IMAGE_SIZE BOARDNAME LOADER_FLASH_OFFS + +define Build/netgear-squashfs + rm -rf $@.fs $@.squashfs + mkdir -p $@.fs/image + cp $@ $@.fs/image/uImage + $(STAGING_DIR_HOST)/bin/mksquashfs-lzma \ + $@.fs $@.squashfs \ + -noappend -root-owned -be -b 65536 + dd if=/dev/zero bs=1k count=1 >> $@.squashfs + mkimage \ + -A mips -O linux -T filesystem -C none \ + -M $(NETGEAR_KERNEL_MAGIC) \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $@.squashfs $@ + rm -rf $@.squashfs $@.fs +endef + +define Build/netgear-uImage + $(call Build/uImage,$(1) -M $(NETGEAR_KERNEL_MAGIC)) +endef + +# combine kernel and rootfs into one image +# -a align the rootfs start on an bytes boundary +# -j add jffs2 end-of-filesystem markers +# -s strip padding from end of the image +# -X reserve bytes in the firmware image (hexval prefixed with 0x) +define Build/mktplinkfw + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) -N OpenWrt -V $(REVISION) \ + -k $(word 1,$^) \ + -r $@ \ + -o $@.new \ + -j -X 0x40000 \ + -a $(call rootfs_align,$(FILESYSTEM)) \ + $(if $(findstring sysupgrade,$1),-s) && mv $@.new $@ || rm -f $@ +endef + +define Build/mktplinkfw-chn-v2 + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) -N OpenWrt -V $(REVISION) -m 2 \ + -k $(word 1,$^) \ + -r $@ \ + -o $@.new \ + -j -X 0x40000 \ + -a $(call rootfs_align,$(FILESYSTEM)) \ + $(if $(findstring sysupgrade,$1),-s) && mv $@.new $@ || rm -f $@ +endef + +# -c combined image +define Build/mktplinkfw-initramfs + $(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) -N OpenWrt -V $(REVISION) \ + -k $@ \ + -o $@.new \ + -s -S \ + -c + @mv $@.new $@ +endef + +define Build/mktplinkfw-initramfs-chn-v2 + $(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) -N OpenWrt -V $(REVISION) -m 2 \ + -k $@ \ + -o $@.new \ + -s -S \ + -c + @mv $@.new $@ +endef + +define Build/loader-common + rm -rf $@.src + $(MAKE) -C lzma-loader \ + PKG_BUILD_DIR="$@.src" \ + TARGET_DIR="$(dir $@)" LOADER_NAME="$(notdir $@)" \ + KERNEL_CMDLINE="$(CMDLINE)" BOARD="$(BOARDNAME)" \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + $(1) compile loader.gz + mv "$@.gz" "$@" + rm -rf $@.src +endef + +define Build/loader-okli-compile + $(call Build/loader-common,FLASH_OFFS=$(LOADER_FLASH_OFFS) FLASH_MAX=0) +endef + +define Build/loader-kernel + $(call Build/loader-common,LOADER_DATA="$@") +endef + +define Build/loader-okli + dd if=$(KDIR)/loader-$(1).gz bs=7680 conv=sync of="$@.new" + cat "$@" >> "$@.new" + mv "$@.new" "$@" +endef + +define Build/copy-file + cat "$(1)" > "$@" +endef + +DEVICE_VARS += TPLINK_HWID TPLINK_HWREV TPLINK_FLASHLAYOUT + +# UBNT_BOARD e.g. one of (XS2, XS5, RS, XM) +# UBNT_TYPE e.g. one of (BZ, XM, XW) +# UBNT_CHIP e.g. one of (ar7240, ar933x, ar934x) + +# mkubntimage is using the kernel image direct +# routerboard creates partitions out of the ubnt header +define Build/mkubntimage + $(STAGING_DIR_HOST)/bin/mkfwimage \ + -B $(UBNT_BOARD) -v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-OpenWrt-$(REVISION) \ + -k $(word 1,$^) \ + -r $@ \ + -o $@ +endef + +# all UBNT XM device expect the kernel image to have 1024k while flash, when +# booting the image, the size doesn't matter. +define Build/mkubntimage-split + dd if=$@ of=$@.old1 bs=1024k count=1 + dd if=$@ of=$@.old2 bs=1024k skip=1 + $(STAGING_DIR_HOST)/bin/mkfwimage \ + -B $(UBNT_BOARD) -v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-OpenWrt-$(REVISION) \ + -k $@.old1 \ + -r $@.old2 \ + -o $@ + rm $@.old1 $@.old2 +endef + +define Build/mkubntimage2 + $(STAGING_DIR_HOST)/bin/mkfwimage2 -f 0x9f000000 \ + -v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-OpenWrt-$(REVISION) \ + -p jffs2:0x50000:0xf60000:0:0:$@ \ + -o $@.new + @mv $@.new $@ +endef + +DEVICE_VARS += UBNT_BOARD UBNT_CHIP UBNT_TYPE + +define Build/mkubntkernelimage + rm -rf $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image && \ + mkdir -p $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image && \ + cp $@ $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image/kernel0 && \ + $(STAGING_DIR_HOST)/bin/mkfs.jffs2 \ + --pad --big-endian --squash-uids -v -e 64KiB \ + -o $@.new \ + -d $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image \ + 2>&1 && \ + $(STAGING_DIR_HOST)/bin/padjffs2 $@.new -J 64 + -rm -rf $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image + @mv $@.new $@ +endef + +define Device/Default + BOARDNAME := + DEVICE_PROFILE = $$(BOARDNAME) + PROFILES = Default Minimal $$(DEVICE_PROFILE) + MTDPARTS := + IMAGES := sysupgrade.bin + BLOCKSIZE := 64k + FILESYSTEMS = $(filter-out jffs2-%,$(TARGET_FILESYSTEMS)) jffs2-$$(BLOCKSIZE) + CONSOLE = ttyS0,115200 + CMDLINE = $$(if $$(BOARDNAME),board=$$(BOARDNAME)) $$(if $$(MTDPARTS),mtdparts=$$(MTDPARTS)) $$(if $$(CONSOLE),console=$$(CONSOLE)) + KERNEL := kernel-bin | patch-cmdline | lzma | uImage lzma + COMPILE := + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/bsb + BOARDNAME = BSB + IMAGE_SIZE = 16000k + CONSOLE = ttyATH0,115200 + MTDPARTS = spi0.0:128k(u-boot)ro,64k(u-boot-env)ro,16128k(firmware),64k(art)ro +endef +TARGET_DEVICES += bsb + +define Device/carambola2 + BOARDNAME = CARAMBOLA2 + IMAGE_SIZE = 16000k + CONSOLE = ttyATH0,115200 + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,16000k(firmware),64k(art)ro +endef +TARGET_DEVICES += carambola2 + +define Device/cf-e316n-v2 + BOARDNAME = CF-E316N-V2 + IMAGE_SIZE = 16192k + CONSOLE = ttyS0,115200 + MTDPARTS = spi0.0:64k(u-boot)ro,64k(art)ro,16192k(firmware),64k(nvram)ro +endef +TARGET_DEVICES += cf-e316n-v2 + +define Device/weio + BOARDNAME = WEIO + IMAGE_SIZE = 16000k + CONSOLE = ttyATH0,115200 + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,16000k(firmware),64k(art)ro +endef +TARGET_DEVICES += weio + +define Device/wndr3700 + BOARDNAME = WNDR3700 + NETGEAR_KERNEL_MAGIC = 0x33373030 + NETGEAR_BOARD_ID = WNDR3700 + IMAGE_SIZE = 7680k + MTDPARTS = spi0.0:320k(u-boot)ro,128k(u-boot-env)ro,7680k(firmware),64k(art)ro + IMAGES := sysupgrade.bin factory.img factory-NA.img + KERNEL := kernel-bin | patch-cmdline | lzma -d20 | netgear-uImage lzma + IMAGE/default = append-kernel $$$$(BLOCKSIZE) | netgear-squashfs | append-rootfs | pad-rootfs + IMAGE/sysupgrade.bin = $$(IMAGE/default) | check-size $$$$(IMAGE_SIZE) + IMAGE/factory.img = $$(IMAGE/default) | netgear-dni | check-size $$$$(IMAGE_SIZE) + IMAGE/factory-NA.img = $$(IMAGE/default) | netgear-dni NA | check-size $$$$(IMAGE_SIZE) +endef + +define Device/wndr3700v2 +$(Device/wndr3700) + NETGEAR_BOARD_ID = WNDR3700v2 + NETGEAR_KERNEL_MAGIC = 0x33373031 + NETGEAR_HW_ID = 29763654+16+64 + IMAGE_SIZE = 15872k + MTDPARTS = spi0.0:320k(u-boot)ro,128k(u-boot-env)ro,15872k(firmware),64k(art)ro + IMAGES := sysupgrade.bin factory.img +endef + +define Device/wndr3800 +$(Device/wndr3700v2) + NETGEAR_BOARD_ID = WNDR3800 + NETGEAR_HW_ID = 29763654+16+128 +endef + +define Device/wndr3800ch +$(Device/wndr3800) + NETGEAR_BOARD_ID = WNDR3800CH +endef + +define Device/wndrmac +$(Device/wndr3700v2) + NETGEAR_BOARD_ID = WNDRMAC +endef + +define Device/wndrmacv2 +$(Device/wndr3800) + NETGEAR_BOARD_ID = WNDRMACv2 +endef + +TARGET_DEVICES += wndr3700 wndr3700v2 wndr3800 wndr3800ch wndrmac wndrmacv2 + +define Device/tplink + TPLINK_HWREV := 0x1 + KERNEL := kernel-bin | patch-cmdline | lzma + KERNEL_INITRAMFS := kernel-bin | patch-cmdline | lzma | mktplinkfw-initramfs + IMAGES := sysupgrade.bin factory.bin + IMAGE/sysupgrade.bin := append-rootfs | mktplinkfw sysupgrade + IMAGE/factory.bin := append-rootfs | mktplinkfw factory +endef + +define Device/tplink-chn-v2 + TPLINK_HWREV := 0x1 + KERNEL := kernel-bin | patch-cmdline | lzma + KERNEL_INITRAMFS := kernel-bin | patch-cmdline | lzma | mktplinkfw-initramfs-chn-v2 + IMAGES := sysupgrade.bin factory.bin + IMAGE/sysupgrade.bin := append-rootfs | mktplinkfw-chn-v2 sysupgrade + IMAGE/factory.bin := append-rootfs | mktplinkfw-chn-v2 factory +endef + +define Device/tplink-nolzma +$(Device/tplink) + LOADER_FLASH_OFFS := 0x22000 + COMPILE := loader-$(1).gz + COMPILE/loader-$(1).gz := loader-okli-compile + KERNEL := copy-file $(KDIR)/vmlinux.bin.lzma | uImage lzma -M 0x4f4b4c49 | loader-okli $(1) + KERNEL_INITRAMFS := copy-file $(KDIR)/vmlinux-initramfs.bin.lzma | loader-kernel | mktplinkfw-initramfs +endef + +define Device/tplink-4m +$(Device/tplink-nolzma) + TPLINK_FLASHLAYOUT := 4M + IMAGE_SIZE := 3904k +endef + +define Device/tplink-8m +$(Device/tplink-nolzma) + TPLINK_FLASHLAYOUT := 8M + IMAGE_SIZE := 7936k +endef + +define Device/tplink-4mlzma +$(Device/tplink) + TPLINK_FLASHLAYOUT := 4Mlzma + IMAGE_SIZE := 3904k +endef + +define Device/tplink-8mlzma +$(Device/tplink) + TPLINK_FLASHLAYOUT := 8Mlzma + IMAGE_SIZE := 7936k +endef + +define Device/tplink-16mlzma +$(Device/tplink) + TPLINK_FLASHLAYOUT := 16Mlzma + IMAGE_SIZE := 15872k +endef + +define Device/tplink-chn-v2-4mlzma +$(Device/tplink-chn-v2) + TPLINK_FLASHLAYOUT := 4Mlzma + IMAGE_SIZE := 3904k +endef + +define Device/tl-wdr4300-v1 +$(Device/tplink-8mlzma) + BOARDNAME = TL-WDR4300 + DEVICE_PROFILE = TLWDR4300 + TPLINK_HWID := 0x43000001 +endef + +define Device/tl-wdr3500-v1 +$(Device/tl-wdr4300-v1) + BOARDNAME = TL-WDR3500 + TPLINK_HWID := 0x35000001 +endef + +define Device/tl-wdr3600-v1 +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x36000001 +endef + +define Device/tl-wdr4300-v1-il +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x43008001 +endef + +define Device/tl-wdr4310-v1 +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x43100001 +endef + +define Device/mw4530r-v1 +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x45300001 +endef + +define Device/tl-wdr3320-v2 +$(Device/tplink-chn-v2-4mlzma) + BOARDNAME = TL-WDR3320-v2 + DEVICE_PROFILE = TLWDR3320V2 + TPLINK_HWID := 0x33200002 +endef + +TARGET_DEVICES += tl-wdr3500-v1 tl-wdr3600-v1 tl-wdr4300-v1 tl-wdr4300-v1-il tl-wdr4310-v1 mw4530r-v1 tl-wdr3320-v2 + +define Device/archer-c5 + $(Device/tplink-16mlzma) + BOARDNAME := ARCHER-C5 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0xc5000001 +endef + +define Device/archer-c7-v1 + $(Device/tplink-8mlzma) + BOARDNAME := ARCHER-C7 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0x75000001 +endef + +define Device/archer-c7-v2 + $(Device/tplink-16mlzma) + BOARDNAME := ARCHER-C7 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0xc7000002 +endef +TARGET_DEVICES += archer-c5 archer-c7-v1 archer-c7-v2 + +define Device/antminer-s1 + $(Device/tplink-8mlzma) + BOARDNAME := ANTMINER-S1 + DEVICE_PROFILE := ANTMINER_S1 + TPLINK_HWID := 0x04440001 + CONSOLE := ttyATH0,115200 +endef + +define Device/antminer-s3 + $(Device/tplink-8mlzma) + BOARDNAME := ANTMINER-S3 + DEVICE_PROFILE := ANTMINER_S3 + TPLINK_HWID := 0x04440003 + CONSOLE := ttyATH0,115200 +endef + +define Device/el-m150 + $(Device/tplink-8mlzma) + BOARDNAME := EL-M150 + DEVICE_PROFILE := ELM150 + TPLINK_HWID := 0x01500101 + CONSOLE := ttyATH0,115200 +endef + +define Device/el-mini + $(Device/tplink-8mlzma) + BOARDNAME := EL-MINI + DEVICE_PROFILE := ELMINI + TPLINK_HWID := 0x01530001 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += antminer-s1 antminer-s3 el-m150 el-mini + +define Device/gl-inet-6408A-v1 + $(Device/tplink-8mlzma) + BOARDNAME := GL-INET + DEVICE_PROFILE := GLINET + TPLINK_HWID := 0x08000001 + CONSOLE := ttyATH0,115200 +endef + +define Device/gl-inet-6416A-v1 + $(Device/tplink-16mlzma) + BOARDNAME := GL-INET + DEVICE_PROFILE := GLINET + TPLINK_HWID := 0x08000001 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += gl-inet-6408A-v1 gl-inet-6416A-v1 + +define Device/mc-mac1200r + $(Device/tplink-8mlzma) + BOARDNAME := MC-MAC1200R + DEVICE_PROFILE := MAC1200R + TPLINK_HWID := 0x12000001 +endef +TARGET_DEVICES += mc-mac1200r + +define Device/onion-omega + $(Device/tplink-16mlzma) + BOARDNAME := ONION-OMEGA + DEVICE_PROFILE := OMEGA + TPLINK_HWID := 0x04700001 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += onion-omega + +define Device/tl-mr10u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR10U + DEVICE_PROFILE := TLMR10U + TPLINK_HWID := 0x00100101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr11u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR11U + DEVICE_PROFILE := TLMR11U + TPLINK_HWID := 0x00110101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr11u-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR11U + DEVICE_PROFILE := TLMR11U + TPLINK_HWID := 0x00110102 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr12u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR13U + DEVICE_PROFILE := TLMR12U + TPLINK_HWID := 0x00120101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr13u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR13U + DEVICE_PROFILE := TLMR13U + TPLINK_HWID := 0x00130101 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-mr10u-v1 tl-mr11u-v1 tl-mr11u-v2 tl-mr12u-v1 tl-mr13u-v1 + +define Device/tl-mr3020-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3020 + DEVICE_PROFILE := TLMR3020 + TPLINK_HWID := 0x30200001 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3040-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3040 + DEVICE_PROFILE := TLMR3040 + TPLINK_HWID := 0x30400001 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3040-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3040-v2 + DEVICE_PROFILE := TLMR3040 + TPLINK_HWID := 0x30400002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3220-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3220-v2 + DEVICE_PROFILE := TLMR3220 + TPLINK_HWID := 0x32200002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3420-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3420-v2 + DEVICE_PROFILE := TLMR3420 + TPLINK_HWID := 0x34200002 +endef +TARGET_DEVICES += tl-mr3020-v1 tl-mr3040-v1 tl-mr3040-v2 tl-mr3220-v2 tl-mr3420-v2 + +define Device/tl-wr703n-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR703N + DEVICE_PROFILE := TLWR703 + TPLINK_HWID := 0x07030101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr710n-v1 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WR710N + DEVICE_PROFILE := TLWR710 + TPLINK_HWID := 0x07100001 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr710n-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR710N + DEVICE_PROFILE := TLWR710 + TPLINK_HWID := 0x07100002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr720n-v3 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR720N-v3 + DEVICE_PROFILE := TLWR720 + TPLINK_HWID := 0x07200103 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr720n-v4 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR720N-v3 + DEVICE_PROFILE := TLWR720 + TPLINK_HWID := 0x07200104 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-wr703n-v1 tl-wr710n-v1 tl-wr710n-v2 tl-wr720n-v3 tl-wr720n-v4 + +define Device/tl-wr740n-v4 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR740 + TPLINK_HWID := 0x07400004 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr740n-v5 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR740 + TPLINK_HWID := 0x07400005 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr741nd-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07410001 +endef + +define Device/tl-wr741nd-v2 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07410001 +endef + +define Device/tl-wr741nd-v4 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07410004 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr741nd-v5 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07400005 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr743nd-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR743 + TPLINK_HWID := 0x07430002 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-wr740n-v4 tl-wr740n-v5 tl-wr741nd-v1 tl-wr741nd-v2 tl-wr741nd-v4 tl-wr741nd-v5 tl-wr743nd-v2 + +define Device/tl-wr841n-v8 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v8 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410008 +endef + +define Device/tl-wr841n-v9 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v9 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410009 +endef + +define Device/tl-wr842n-v2 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WR842N-v2 + DEVICE_PROFILE := TLWR842 + TPLINK_HWID := 0x8420002 +endef + +define Device/tl-wr843nd-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v8 + DEVICE_PROFILE := TLWR843 + TPLINK_HWID := 0x08430001 +endef + +define Device/tl-wr847n-v8 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v8 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08470008 +endef +TARGET_DEVICES += tl-wr841n-v8 tl-wr841n-v9 tl-wr842n-v2 tl-wr843nd-v1 tl-wr847n-v8 + +define Device/tl-wr941nd-v5 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR941ND-v5 + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410005 +endef + +define Device/tl-wr941nd-v6 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WDR3500 + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410006 +endef +TARGET_DEVICES += tl-wr941nd-v5 tl-wr941nd-v6 + +define Device/tl-wr1041n-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR1041N-v2 + DEVICE_PROFILE := TLWR1041 + TPLINK_HWID := 0x10410002 +endef +TARGET_DEVICES += tl-wr1041n-v2 + +define Device/tl-wdr4900-v2 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WDR4900-v2 + DEVICE_PROFILE := TLWDR4900V2 + TPLINK_HWID := 0x49000002 +endef +TARGET_DEVICES += tl-wdr4900-v2 + +define Device/tl-wa701nd-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA701ND-v2 + DEVICE_PROFILE := TLWA701 + TPLINK_HWID := 0x07010002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wa750re-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA750RE + DEVICE_PROFILE := TLWA750 + TPLINK_HWID := 0x07500001 +endef +TARGET_DEVICES += tl-wa701nd-v2 tl-wa750re-v1 + +define Device/tl-wa801nd-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA801ND-v2 + DEVICE_PROFILE := TLWA801 + TPLINK_HWID := 0x08010002 +endef + +define Device/tl-wa830re-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA830RE-v2 + DEVICE_PROFILE := TLWA830 + TPLINK_HWID := 0x08300002 +endef + +define Device/tl-wa850re-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA850RE + DEVICE_PROFILE := TLWA850 + TPLINK_HWID := 0x08500001 +endef + +define Device/tl-wa860re-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA860RE + DEVICE_PROFILE := TLWA860 + TPLINK_HWID := 0x08600001 +endef +TARGET_DEVICES += tl-wa801nd-v2 tl-wa830re-v2 tl-wa850re-v1 tl-wa860re-v1 + +define Device/tl-wa901nd-v3 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA901ND-v3 + DEVICE_PROFILE := TLWA901 + TPLINK_HWID := 0x09010003 +endef +TARGET_DEVICES += tl-wa901nd-v3 + +define Device/tl-wa7210n-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA7210N-v2 + DEVICE_PROFILE := TLWA7210 + TPLINK_HWID := 0x72100002 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-wa7210n-v2 + +define Device/smart-300 + $(Device/tplink-8mlzma) + BOARDNAME := SMART-300 + DEVICE_PROFILE := SMART-300 + TPLINK_HWID := 0x93410001 +endef +TARGET_DEVICES += smart-300 + +define Device/oolite + $(Device/tplink-16mlzma) + BOARDNAME := GS-OOLITE + DEVICE_PROFILE := OOLITE + TPLINK_HWID := 0x3C000101 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += oolite + +# UBNT_BOARD e.g. one of (XS2, XS5, RS, XM) +# UBNT_TYPE e.g. one of (BZ, XM, XW) +# UBNT_CHIP e.g. one of (ar7240, ar933x, ar934x) +define Device/ubnt-xm + DEVICE_PROFILE := UBNT + IMAGE_SIZE := 7552k + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro + UBNT_TYPE := XM + UBNT_BOARD := XM + UBNT_CHIP := ar7240 + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage-split + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/ubnt-xw + DEVICE_PROFILE := UBNT + IMAGE_SIZE := 7552k + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro + UBNT_TYPE := XW + UBNT_BOARD := XM + UBNT_CHIP := ar934x + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage-split + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/ubnt-bz + DEVICE_PROFILE := UBNT + IMAGE_SIZE := 7552k + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro + UBNT_TYPE := BZ + UBNT_BOARD := XM + UBNT_CHIP := ar934x + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage-split + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/rw2458n + $(Device/ubnt-xm) + BOARDNAME := RW2458N +endef + +define Device/ubnt-airrouter + $(Device/ubnt-xm) + BOARDNAME := UBNT-AR +endef + +define Device/ubnt-bullet-m + $(Device/ubnt-xm) + BOARDNAME := UBNT-BM +endef + +define Device/ubnt-rocket-m + $(Device/ubnt-xm) + BOARDNAME := UBNT-RM +endef + +define Device/ubnt-nano-m + $(Device/ubnt-xm) + BOARDNAME := UBNT-NM +endef +TARGET_DEVICES += rw2458n ubnt-airrouter ubnt-bullet-m ubnt-rocket-m ubnt-nano-m + +define Device/ubnt-unifi + $(Device/ubnt-bz) + BOARDNAME := UBNT-UF + DEVICE_PROFILE := UBNT UBNTUNIFI +endef + +define Device/ubnt-unifi-outdoor + $(Device/ubnt-bz) + BOARDNAME := UBNT-U20 + DEVICE_PROFILE := UBNT UBNTUNIFIOUTDOOR +endef +TARGET_DEVICES += ubnt-unifi ubnt-unifi-outdoor + +define Device/ubnt-nano-m-xw + $(Device/ubnt-xw) + BOARDNAME := UBNT-NM-XW +endef + +define Device/ubnt-loco-m-xw + $(Device/ubnt-xw) + BOARDNAME := UBNT-LOCO-XW +endef + +define Device/ubnt-rocket-m-xw + $(Device/ubnt-xw) + BOARDNAME := UBNT-RM-XW +endef + +define Device/ubnt-rocket-m-ti + $(Device/ubnt-xw) + BOARDNAME := UBNT-RM-TI + UBNT_TYPE := TI + UBNT_BOARD := XM +endef +TARGET_DEVICES += ubnt-nano-m-xw ubnt-loco-m-xw ubnt-rocket-m-xw ubnt-rocket-m-ti + +define Device/ubnt-air-gateway + $(Device/ubnt-xm) + BOARDNAME := UBNT-AGW + UBNT_BOARD := XM + UBNT_TYPE := AirGW + UBNT_CHIP := ar933x + CONSOLE = ttyATH0,115200 +endef +TARGET_DEVICES += ubnt-air-gateway + +define Device/ubnt-air-gateway-pro + $(Device/ubnt-xm) + BOARDNAME := UBNT-AGWP + UBNT_TYPE := AirGWP + UBNT_CHIP := ar934x + CONSOLE = ttyS0,115200 +endef +TARGET_DEVICES += ubnt-air-gateway-pro + +define Device/ubdev01 + $(Device/ubnt-xm) + MTDPARTS := spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7488k(firmware),64k(certs),256k(cfg)ro,64k(EEPROM)ro + BOARDNAME := UBNT-UF + UBNT_BOARD := XM + UBNT_TYPE := XM + UBNT_CHIP := ar7240 +endef + +TARGET_DEVICES += ubdev01 + +define Device/ubnt-routerstation + IMAGE_SIZE := 16128k + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = append-rootfs | pad-rootfs | mkubntimage + IMAGE/sysupgrade.bin = append-rootfs | pad-rootfs | combined-image | check-size $$$$(IMAGE_SIZE) + KERNEL := kernel-bin | patch-cmdline | lzma | pad-to $$(BLOCKSIZE) +endef + +define Device/ubnt-rs +$(Device/ubnt-routerstation) + BOARDNAME := UBNT-RS + DEVICE_PROFILE := Madwifi UBNT UBNTRS + UBNT_BOARD := RS + UBNT_TYPE := RSx + UBNT_CHIP := ar7100 +endef + +define Device/ubnt-rspro +$(Device/ubnt-routerstation) + BOARDNAME := UBNT-RSPRO + DEVICE_PROFILE := Madwifi UBNT UBNTRSPRO + UBNT_BOARD := RSPRO + UBNT_TYPE := RSPRO + UBNT_CHIP := ar7100pro +endef + +define Device/ubnt-ls-sr71 +$(Device/ubnt-routerstation) + BOARDNAME := UBNT-LS-SR71 + DEVICE_PROFILE := Madwifi UBNT + UBNT_BOARD := LS-SR71 + UBNT_TYPE := LS-SR71 + UBNT_CHIP := ar7100 +endef + +TARGET_DEVICES += ubnt-rs ubnt-rspro ubnt-ls-sr71 + +define Device/ubnt-uap-pro + IMAGE_SIZE := 15744k + MTDPARTS := spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1536k(kernel),14208k(rootfs),256k(cfg)ro,64k(EEPROM)ro,15744k@0x50000(firmware) + UBNT_TYPE := BZ + UBNT_CHIP := ar934x + BOARDNAME := UAP-PRO + DEVICE_PROFILE := UBNT UAPPRO + KERNEL := kernel-bin | patch-cmdline | lzma | uImage lzma | mkubntkernelimage + IMAGES := sysupgrade.bin factory.bin + IMAGE/sysupgrade.bin = append-kernel 1536k | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage2 +endef + +define Device/ubnt-unifi-outdoor-plus +$(Device/ubnt-uap-pro) + UBNT_CHIP := ar7240 + BOARDNAME := UBNT-UOP + DEVICE_PROFILE := UBNT +endef + +TARGET_DEVICES += ubnt-uap-pro ubnt-unifi-outdoor-plus + +rootfs_type=$(patsubst jffs2-%,jffs2,$(patsubst squashfs-%,squashfs,$(1))) + +# $(1): rootfs type. +# $(2): board name. +define imgname +$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(call rootfs_type,$(1)) +endef + +define rootfs_align +$(patsubst %-256k,0x40000,$(patsubst %-128k,0x20000,$(patsubst %-64k,0x10000,$(patsubst squashfs%,0x4,$(patsubst root.%,%,$(1)))))) +endef + +define sysupname +$(call imgname,$(1),$(2))-sysupgrade.bin +endef + +define factoryname +$(call imgname,$(1),$(2))-factory.bin +endef + +COMMA:=, + +define mkcmdline +$(if $(1),board=$(1) )$(if $(2),console=$(2)$(COMMA)$(3)) +endef + +define mtdpartsize +$(shell sz=`echo '$(2)' | sed -ne 's/.*[:$(COMMA)]\([0-9]*\)k[@]*[0-9a-zx]*($(1)).*/\1/p'`; [ -n "$$sz" ] && echo $$(($$sz * 1024))) +endef + +SINGLE_PROFILES:= + +# $(1) : name of image build method to be used, e.g., TPLINK-LZMA, AthLzma. +# $(2) : name of the build template to be used, e.g. 64k, 64kraw, 128k, etc. +# $(3) : name of the profile to be defined. +# $(4) : board name. +# $(5)~$(7) : arguments for $(mkcmdline) +# board=$(1) console=$(2),$(3) +# $(8)~$(14): extra arguments. +define SingleProfile + # $(1): action name, e.g. loader, buildkernel, squashfs, etc. + define Image/Build/Profile/$(3) + $$(call Image/Build/Template/$(2)/$$(1),$(1),$(4),$$(call mkcmdline,$(5),$(6),$(7)),$(8),$(9),$(10),$(11),$(12),$(13),$(14)) + endef + SINGLE_PROFILES += $(3) +endef + +# $(1), name of the MultiProfile to be added. +# $(2), name of Profiles to be included in the MultiProfile. +define MultiProfile + define Image/Build/Profile/$(1) + $(foreach p,$(2), + $$(call Image/Build/Profile/$p,$$(1)) + ) + endef +endef + +LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR) + +VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux +UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage + +# $(1): input file. +# $(2): output file. +# $(3): extra arguments for lzma. +define CompressLzma + $(STAGING_DIR_HOST)/bin/lzma e $(1) -lc1 -lp2 -pb2 $(3) $(2) +endef + +define PatchKernel + cp $(KDIR)/vmlinux$(3) $(KDIR_TMP)/vmlinux$(3)-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux$(3)-$(1) "$(strip $(2))" +endef + +define PatchKernel/initramfs + $(call PatchKernel,$(1),$(2),-initramfs) + cp $(KDIR_TMP)/vmlinux-initramfs-$(1) $(call imgname,initramfs,$(1)).bin +endef + +# $(1): board name. +# $(2): kernel command line. +# $(3): extra argumetns for lzma. +# $(4): name suffix, e.g. "-initramfs". +define PatchKernelLzma + cp $(KDIR)/vmlinux$(4) $(KDIR_TMP)/vmlinux$(4)-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux$(4)-$(1) "$(strip $(2))" + $(call CompressLzma,$(KDIR_TMP)/vmlinux$(4)-$(1),$(KDIR_TMP)/vmlinux$(4)-$(1).bin.lzma,$(3)) +endef + +define PatchKernelGzip + cp $(KDIR)/vmlinux$(3) $(KDIR_TMP)/vmlinux$(3)-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux$(3)-$(1) "$(strip $(2))" + gzip -9n -c $(KDIR_TMP)/vmlinux$(3)-$(1) > $(KDIR_TMP)/vmlinux$(3)-$(1).bin.gz +endef + +ifneq ($(SUBTARGET),mikrotik) +# $(1): compression method of the data. +# $(2): extra arguments. +# $(3): input data file. +# $(4): output file. +define MkuImage + mkimage -A mips -O linux -T kernel -a 0x80060000 -C $(1) $(2) \ + -e 0x80060000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(3) $(4) +endef + +# $(1): board name. +# $(2): kernel command line. +# $(3): extra arguments for lzma. +# $(4): name suffix, e.g. "-initramfs". +# $(5): extra arguments for mkimage. +define MkuImageLzma + $(call PatchKernelLzma,$(1),$(2),$(3),$(4)) + $(call MkuImage,lzma,$(5),$(KDIR_TMP)/vmlinux$(4)-$(1).bin.lzma,$(KDIR_TMP)/vmlinux$(4)-$(1).uImage) +endef + +define MkuImageLzma/initramfs + $(call PatchKernelLzma,$(1),$(2),$(3),-initramfs) + $(call MkuImage,lzma,$(4),$(KDIR_TMP)/vmlinux-initramfs-$(1).bin.lzma,$(call imgname,initramfs,$(1))-uImage.bin) +endef + +define MkuImageGzip + $(call PatchKernelGzip,$(1),$(2)) + $(call MkuImage,gzip,,$(KDIR_TMP)/vmlinux-$(1).bin.gz,$(KDIR_TMP)/vmlinux-$(1).uImage) +endef + +define MkuImageGzip/initramfs + $(call PatchKernelGzip,$(1),$(2),-initramfs) + $(call MkuImage,gzip,,$(KDIR_TMP)/vmlinux-initramfs-$(1).bin.gz,$(call imgname,initramfs,$(1))-uImage.bin) +endef + +define MkuImageOKLI + $(call MkuImage,lzma,-M 0x4f4b4c49,$(KDIR)/vmlinux.bin.lzma,$(KDIR_TMP)/vmlinux-$(1).okli) +endef +endif + +# $(1): name of the 1st file. +# $(2): size limit of the 1st file if it is greater than 262144, or +# the erase size of the flash if it is greater than zero and less +# than 262144 +# $(3): name of the 2nd file. +# $(4): size limit of the 2nd file if $(2) is greater than 262144, otherwise +# it is the size limit of the output file +# $(5): name of the output file. +# $(6): padding size. +define CatFiles + if [ $(2) -eq 0 ]; then \ + filename="$(3)"; fstype=$$$${filename##*\.}; \ + case "$$$${fstype}" in \ + "jffs2-64k") bs=65536;; \ + "jffs2-128k") bs=131072;; \ + "jffs2-256k") bs=262144;; \ + *) bs=`stat -c%s $(1)`;; \ + esac; \ + ( dd if=$(1) bs=$$$${bs} conv=sync; cat $(3) ) > $(5); \ + if [ -n "$(6)" ]; then \ + case "$$$${fstype}" in \ + squashfs*) \ + padjffs2 $(5) $(6); \ + ;; \ + esac; \ + fi; \ + if [ `stat -c%s $(5)` -gt $(4) ]; then \ + echo "Warning: $(5) is too big (> $(4) bytes)" >&2; \ + rm -f $(5); \ + fi; \ + else if [ $(2) -gt 262144 ]; then \ + if [ `stat -c%s "$(1)"` -gt $(2) ]; then \ + echo "Warning: $(1) is too big (> $(2) bytes)" >&2; \ + else if [ `stat -c%s $(3)` -gt $(4) ]; then \ + echo "Warning: $(3) is too big (> $(4) bytes)" >&2; \ + else \ + ( dd if=$(1) bs=$(2) conv=sync; dd if=$(3) ) > $(5); \ + fi; fi; \ + else \ + ( dd if=$(1) bs=$(2) conv=sync; dd if=$(3) ) > $(5); \ + if [ `stat -c%s $(5)` -gt $(4) ]; then \ + echo "Warning: $(5) is too big (> $(4) bytes)" >&2; \ + rm -f $(5); \ + fi; \ + fi; fi +endef + +# $(1): rootfs type. +# $(2): board name. +# $(3): kernel image size limit. +# $(4): rootfs image size limit. +# $(5): padding argument for padjffs2. +Sysupgrade/KR=$(call CatFiles,$(2),$(3),$(KDIR)/root.$(1),$(4),$(call sysupname,$(1),$(5))) +Sysupgrade/KRuImage=$(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage,$(3),$(KDIR)/root.$(1),$(4),$(call sysupname,$(1),$(2)),$(5)) +Sysupgrade/RKuImage=$(call CatFiles,$(KDIR)/root.$(1),$(4),$(KDIR_TMP)/vmlinux-$(2).uImage,$(3),$(call sysupname,$(1),$(2))) + +# $(1): ubinize ini file +# $(2): working directory +# $(3): output file +# $(4): physical erase block size +# $(5): minimum I/O unit size +# $(6): custom options +define ubinize + $(CP) $(1) $(2) + ( cd $(2); $(STAGING_DIR_HOST)/bin/ubinize -o $(3) -p $(4) -m $(5) $(6) $(1)) +endef + +# +# Embed lzma-compressed kernel inside lzma-loader. +# +# $(1), suffix of output filename, e.g. generic, lowercase board name, etc. +# $(2), suffix of target file to build, e.g. bin, gz, elf +# $(3), kernel command line to pass from lzma-loader to kernel +# $(4), unused here +# $(5), suffix of kernel filename, e.g. -initramfs, or empty +define Image/BuildLoader + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) KERNEL_CMDLINE="$(3)"\ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + LOADER_DATA="$(KDIR)/vmlinux$(5).bin.lzma" BOARD="$(1)" \ + compile loader.$(2) + -$(CP) $(KDIR)/loader-$(1).$(2) $(KDIR)/loader-$(1)$(5).$(2) +endef + +# +# Embed patched lzma-compressed kernel inside lzma-loader. +# +# Specifying the command line via the lzma-loader doesn't work with some +# models (like the TP-LINK CPE series), so this version first patches the +# command line in the image and then builds the loader around it. +# +# $(1), suffix of output filename, e.g. generic, lowercase board name, etc. +# $(2), suffix of target file to build, e.g. bin, gz, elf +# $(3), kernel command line to pass from lzma-loader to kernel +# $(4), unused here +# $(5), suffix of kernel filename, e.g. -initramfs, or empty +define Image/BuildLoaderPatched + $(call PatchKernelLzma,$(1),$(3)) + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + LOADER_DATA="$(KDIR_TMP)/vmlinux-$(1)$(5).bin.lzma" BOARD="$(1)" \ + compile loader.$(2) + -$(CP) $(KDIR)/loader-$(1).$(2) $(KDIR)/loader-$(1)$(5).$(2) +endef + +# +# Build lzma-loader alone which will search for lzma-compressed kernel identified by +# uImage header with magic "OKLI" at boot time. +# +# $(4), offset into the flash space to start searching uImage magic "OKLI". +# $(5), size of search range starting at $(4). With 0 as the value, uImage +# header is expected to be at precisely $(4) +define Image/BuildLoaderAlone + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) KERNEL_CMDLINE="$(3)" \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + BOARD="$(1)" FLASH_OFFS=$(4) FLASH_MAX=$(5) \ + compile loader.$(2) +endef + +define Build/Clean + $(LOADER_MAKE) clean +endef + + +alfa_ap96_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13312k(rootfs),2048k(kernel),512k(caldata)ro,15360k@0x80000(firmware) +alfa_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1600k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +alfa_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,15936k(firmware),64k(nvram),64k(art)ro +all0258n_mtdlayout=mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),6272k(firmware),1536k(failsafe),64k(art) +all0315n_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env),13568k(firmware),2048k(failsafe),256k(art)ro +ap81_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,5120k(rootfs),2688k(kernel),64k(art)ro,7808k@0x50000(firmware) +ap83_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,128k(u-boot-env)ro,4096k(rootfs),3648k(kernel),64k(art)ro,7744k@0x60000(firmware) +ap96_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1728k(kernel),64k(art)ro,7872k@0x40000(firmware) +ap113_mtd_layout=mtdparts=spi0.0:64k(u-boot),3008k(rootfs),896k(uImage),64k(NVRAM),64k(ART),3904k@0x10000(firmware) +ap121_mtdlayout_2M=mtdparts=spi0.0:64k(u-boot)ro,1216k(rootfs),704k(kernel),64k(art)ro,1920k@0x10000(firmware) +ap121_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2448k(rootfs),1200k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware) +ap121_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1600k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +ap132_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),6400k(rootfs),64k(art),7808k@0x50000(firmware) +ap135_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art)ro,16000k@0x50000(firmware) +ap136_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(mib0),64k(art)ro,7744k@0x50000(firmware) +ap143_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1472k(kernel),64k(art)ro,7744k@0x50000(firmware) +ap143_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art)ro,16000k@0x50000(firmware) +ap147_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art),16000k@0x50000(firmware) +ap152_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art)ro,16000k@0x50000(firmware) +bxu2000n2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),8448k(rootfs),6016k(user),64k(cfg),64k(oem),64k(art)ro +cameo_ap81_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(config)ro,3840k(firmware),64k(art)ro +cameo_ap91_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,3712k(firmware),64k(mac)ro,64k(art)ro +cameo_ap99_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,3520k(firmware),64k(mac)ro,192k(lp)ro,64k(art)ro +cameo_ap121_mtdlayout=mtdparts=spi0.0:64k(u-boot)ro,64k(art)ro,64k(mac)ro,64k(nvram)ro,192k(language)ro,3648k(firmware) +cameo_ap121_mtdlayout_8M=mtdparts=spi0.0:64k(u-boot)ro,64k(art)ro,64k(mac)ro,64k(nvram)ro,256k(language)ro,7680k@0x80000(firmware) +cameo_ap123_mtdlayout_4M=mtdparts=spi0.0:64k(u-boot)ro,64k(nvram)ro,3712k(firmware),192k(lang)ro,64k(art)ro +cameo_db120_mtdlayout=mtdparts=spi0.0:64k(uboot)ro,64k(nvram)ro,15936k(firmware),192k(lang)ro,64k(mac)ro,64k(art)ro +cameo_db120_mtdlayout_8M=mtdparts=spi0.0:64k(uboot)ro,64k(nvram)ro,7872k(firmware),128k(lang)ro,64k(art)ro +cap4200ag_mtdlayout=mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),320k(custom)ro,1536k(kernel),12096k(rootfs),2048k(failsafe),64k(art),13632k@0xa0000(firmware) +cpe510_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(pation-table)ro,64k(product-info)ro,1536k(kernel),6144k(rootfs),192k(config)ro,64k(ART)ro,7680k@0x40000(firmware) +eap300v2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),320k(custom),13632k(firmware),2048k(failsafe),64k(art)ro +db120_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +dgl_5500_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,15296k(firmware),192k(lang)ro,512k(my-dlink)ro,64k(mac)ro,64k(art)ro +dlan_pro_500_wp_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,64k(Config1)ro,64k(Config2)ro,7680k@0x70000(firmware),64k(art)ro +dlan_pro_1200_ac_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,64k(Config1)ro,64k(Config2)ro,15872k@0x70000(firmware),64k(art)ro +cameo_ap94_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,6208k(firmware),64k(caldata)ro,1600k(unknown)ro,64k@0x7f0000(caldata_copy) +cameo_ap94_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,7808k(firmware),64k(caldata)ro,64k@0x660000(caldata_orig),6208k@0x50000(firmware_orig) +esr900_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware) +esr1750_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware) +epg5000_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware) +ew-dorin_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),3712k(firmware),64k(art) +ew-dorin_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),16000k(firmware),64k(art)ro +f9k1115v2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),14464k(rootfs),1408k(kernel),64k(nvram)ro,64k(envram)ro,64k(art)ro,15872k@0x50000(firmware) +dlrtdev_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,6208k(firmware),64k(caldata)ro,640k(certs),960k(unknown)ro,64k@0x7f0000(caldata_copy) +dlrtdev_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,7168k(firmware),640k(certs),64k(caldata)ro,64k@0x660000(caldata_orig),6208k@0x50000(firmware_orig) +dragino2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,16000k(firmware),64k(config)ro,64k(art)ro +hiwifi_hc6361_mtdlayout=mtdparts=spi0.0:64k(u-boot)ro,64k(bdinfo)ro,1280k(kernel),14848k(rootfs),64k(backup)ro,64k(art)ro,16128k@0x20000(firmware) +mr12_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13440k(rootfs),2304k(kernel),128k(art)ro,15744k@0x80000(firmware) +mr16_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13440k(rootfs),2304k(kernel),128k(art)ro,15744k@0x80000(firmware) +pb92_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2752k(rootfs),896k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware) +planex_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7744k(firmware),128k(art)ro +ubntxm_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro +uap_pro_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1536k(kernel),14208k(rootfs),256k(cfg)ro,64k(EEPROM)ro,15744k@0x50000(firmware) +ubdev_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7488k(firmware),64k(certs),256k(cfg)ro,64k(EEPROM)ro +whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro +wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware) +wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +wpj558_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +wndap360_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1728k(kernel),6016k(rootfs),64k(nvram)ro,64k(art)ro,7744k@0x50000(firmware) +wnr2200_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7808k(firmware),64k(art)ro +wnr2000v3_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,3712k(firmware),64k(art)ro +wnr2000v4_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,3776k(firmware),64k(art)ro +r6100_mtdlayout=mtdparts=ar934x-nfc:128k(u-boot)ro,256k(caldata),256k(caldata-backup),512k(config),512k(pot),2048k(kernel),122240k(ubi),25600k@0x1a0000(firmware),2048k(language),3072k(traffic_meter) +wndr4300_mtdlayout=mtdparts=ar934x-nfc:256k(u-boot)ro,256k(u-boot-env)ro,256k(caldata),512k(pot),2048k(language),512k(config),3072k(traffic_meter),2048k(kernel),23552k(ubi),25600k@0x6c0000(firmware),256k(caldata_backup),-(reserved) +zcn1523h_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6208k(rootfs),1472k(kernel),64k(configure)ro,64k(mfg)ro,64k(art)ro,7680k@0x50000(firmware) +mynet_n600_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,64k(devdata)ro,64k(devconf)ro,15872k(firmware),64k(radiocfg)ro +mynet_rext_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,7808k(firmware),64k(nvram)ro,64k(ART)ro +zyx_nbg6716_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(env)ro,64k(RFdata)ro,-(nbu);ar934x-nfc:2048k(zyxel_rfsd),2048k(romd),1024k(header),2048k(kernel),-(ubi) +qihoo_c301_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),64k(devdata),64k(devconf),15744k(firmware),64k(warm_start),64k(action_image_config),64k(radiocfg)ro;spi0.1:15360k(upgrade2),1024k(privatedata) + + +define Image/BuildKernel + cp $(KDIR)/vmlinux.elf $(VMLINUX).elf + cp $(KDIR)/vmlinux $(VMLINUX).bin + dd if=$(KDIR)/vmlinux.bin.lzma of=$(VMLINUX).lzma bs=65536 conv=sync + dd if=$(KDIR)/vmlinux.bin.gz of=$(VMLINUX).gz bs=65536 conv=sync + $(call MkuImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(UIMAGE)-gzip.bin) + $(call MkuImage,lzma,,$(KDIR)/vmlinux.bin.lzma,$(UIMAGE)-lzma.bin) + cp $(KDIR)/loader-generic.elf $(VMLINUX)-lzma.elf + -mkdir -p $(KDIR_TMP) + $(call Image/Build/Profile/$(IMAGE_PROFILE),buildkernel) +endef + +define Image/BuildKernel/Initramfs + cp $(KDIR)/vmlinux-initramfs.elf $(VMLINUX)-initramfs.elf + cp $(KDIR)/vmlinux-initramfs $(VMLINUX)-initramfs.bin + dd if=$(KDIR)/vmlinux-initramfs.bin.lzma of=$(VMLINUX)-initramfs.lzma bs=65536 conv=sync + dd if=$(KDIR)/vmlinux-initramfs.bin.gz of=$(VMLINUX)-initramfs.gz bs=65536 conv=sync + $(call MkuImage,gzip,,$(KDIR)/vmlinux-initramfs.bin.gz,$(UIMAGE)-initramfs-gzip.bin) + $(call MkuImage,lzma,,$(KDIR)/vmlinux-initramfs.bin.lzma,$(UIMAGE)-initramfs-lzma.bin) + cp $(KDIR)/loader-generic-initramfs.elf $(VMLINUX)-initramfs-lzma.elf + $(call Image/Build/Initramfs) +endef + +Image/Build/WRT400N/buildkernel=$(call MkuImageLzma,$(2),$(3)) + +define Image/Build/WRT400N + $(call Sysupgrade/KRuImage,$(1),$(2),1310720,6488064) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + wrt400n $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR)/root.$(1) $(call factoryname,$(1),$(2)); \ + fi +endef + + +define Image/Build/CameoAP94/buildkernel + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call MkuImageLzma,$(2)-fat,$(3) $(5)) +endef + +define Image/Build/CameoAP94 + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval fwsize_fat=$(call mtdpartsize,firmware,$(5))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + dd if=$(call sysupname,$(1),$(2)); \ + echo -n "$(6)"; \ + ) > $(call imgname,$(1),$(2))-backup-loader.bin; \ + if [ `stat -c%s $(call sysupname,$(1),$(2))` -gt 4194304 ]; then \ + echo "Warning: $(call sysupname,$(1),$(2)) is too big" >&2; \ + else \ + ( \ + dd if=$(call sysupname,$(1),$(2)) bs=4096k conv=sync; \ + echo -n "$(7)"; \ + ) > $(call factoryname,$(1),$(2)); \ + fi; \ + fi + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2)-fat.uImage,0,$(KDIR)/root.$(1),$$$$(($(fwsize_fat)-4*64*1024)),$(KDIR_TMP)/$(2)-fat.bin,64) + if [ -e "$(KDIR_TMP)/$(2)-fat.bin" ]; then \ + echo -n "" > $(KDIR_TMP)/$(2)-fat.dummy; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + "$(KDIR_TMP)/$(2)-fat.bin" \ + "$(KDIR_TMP)/$(2)-fat.dummy" \ + $(call sysupname,$(1),$(2)-fat); \ + fi +endef + +define Image/Build/WZRHP + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(3)-4*$(4)*1024)),$(4)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + echo -n -e "# Airstation Public Fmt1\x00\x00\x00\x00\x00\x00\x00\x00"; \ + dd if=$(call sysupname,$(1),$(2)); \ + ) > $(call imgname,$(1),$(2))-tftp.bin; \ + buffalo-enc -p $(5) -v 1.99 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(KDIR_TMP)/$(2).enc; \ + buffalo-tag -b $(5) -p $(5) -a ath -v 1.99 -m 1.01 -l mlang8 \ + -w 3 -c 0x80041000 -d 0x801e8000 -f 1 -r M_ \ + -i $(KDIR_TMP)/$(2).enc \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + +Image/Build/WZRHP64K/buildkernel=$(call MkuImageLzma,$(2),$(3)) +Image/Build/WZRHP64K/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +Image/Build/WZRHP64K=$(call Image/Build/WZRHP,$(1),$(2),33095680,64,$(4)) + +Image/Build/WZRHP128K/buildkernel=$(call MkuImageLzma,$(2),$(3)) +Image/Build/WZRHP128K/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +Image/Build/WZRHP128K=$(call Image/Build/WZRHP,$(1),$(2),33030144,128,$(4)) + + +Image/Build/WHRHPG300N/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/WHRHPG300N/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/WHRHPG300N + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + echo -n -e "# Airstation Public Fmt1\x00\x00\x00\x00\x00\x00\x00\x00"; \ + dd if=$(call sysupname,$(1),$(2)); \ + ) > $(call imgname,$(1),$(2))-tftp.bin; \ + buffalo-enc -p $(5) -v 1.99 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(KDIR_TMP)/$(2).enc; \ + buffalo-tag -b $(5) -p $(5) -a ath -v 1.99 -m 1.01 -l mlang8 \ + -w 3 -c 0x80041000 -d 0x801e8000 -f 1 -r M_ \ + -i $(KDIR_TMP)/$(2).enc \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + + +define Image/Build/Cameo + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + factory_size=$$$$(($(fwsize) - $(6))); \ + ( \ + dd if=$(call sysupname,$(1),$(2)) bs=$$$${factory_size} conv=sync; \ + echo -n $(5); \ + ) > $(call factoryname,$(1),$(2)); \ + fi +endef + +Image/Build/CameoAP81/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap81_mtdlayout)) +Image/Build/CameoAP81=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap81_mtdlayout),$(4),65536) +Image/Build/CameoAP81/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap81_mtdlayout)) + +Image/Build/CameoAP91/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap91_mtdlayout)) +Image/Build/CameoAP91=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap91_mtdlayout),$(4),65536) +Image/Build/CameoAP91/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap91_mtdlayout)) + +Image/Build/CameoAP99/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap99_mtdlayout)) +Image/Build/CameoAP99=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap99_mtdlayout),$(4),65536) +Image/Build/CameoAP99/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap99_mtdlayout)) + +Image/Build/CameoAP123_4M/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap123_mtdlayout_4M)) +Image/Build/CameoAP123_4M=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap123_mtdlayout_4M),$(4),26) +Image/Build/CameoAP123_4M/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap123_mtdlayout_4M)) + +Image/Build/CameoAP135/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/CameoAP135=$(call Image/Build/Cameo,$(1),$(2),$(3),$(4),$(5),26) +Image/Build/CameoAP135/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +Image/Build/CameoDB120/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_db120_mtdlayout)) +Image/Build/CameoDB120=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_db120_mtdlayout),$(4),26) +Image/Build/CameoDB120/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_db120_mtdlayout)) + +Image/Build/CameoDB120_8M/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_db120_mtdlayout_8M)) +Image/Build/CameoDB120_8M=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_db120_mtdlayout_8M),$(4),26) +Image/Build/CameoDB120_8M/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_db120_mtdlayout_8M)) + +define Image/Build/CameoHornet + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + for r in $(7); do \ + [ -n "$$$$r" ] && dashr="-$$$$r" || dashr=; \ + [ -z "$$$$r" ] && r="DEF"; \ + mkcameofw -M HORNET -R "$$$$r" -S $(5) -V $(6) -c \ + -K $(8) -I $(fwsize) \ + -k "$(call sysupname,$(1),$(2))" \ + -o $(call imgname,$(1),$(2))-factory$$$$dashr.bin; \ + true; \ + done; \ + fi +endef + +Image/Build/CameoAP121/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap121_mtdlayout)) +Image/Build/CameoAP121=$(call Image/Build/CameoHornet,$(1),$(2),$(3),$(cameo_ap121_mtdlayout),$(4),$(5),$(6),0xe0000) +Image/Build/CameoAP121/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap121_mtdlayout)) + +Image/Build/CameoAP121_8M/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap121_mtdlayout_8M)) +Image/Build/CameoAP121_8M=$(call Image/Build/CameoHornet,$(1),$(2),$(3),$(cameo_ap121_mtdlayout_8M),$(4),$(5),$(6),0x100000) +Image/Build/CameoAP121_8M/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap121_mtdlayout_8M)) + +define Image/Build/dLAN + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(call Sysupgrade/$(5),$(1),$(2),$(if $(6),$(6),$(kernsize)),$(if $(rootsize),$(rootsize),$(fwsize))) + if [ -e "$(call factoryname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + fi +endef + +Image/Build/dLANLzma/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/dLANLzma=$(call Image/Build/dLAN,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/dLANLzma/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Ath + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(call Sysupgrade/$(5),$(1),$(2),$(if $(6),$(6),$(kernsize)),$(if $(rootsize),$(rootsize),$(fwsize))) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + fi +endef + +Image/Build/AthGzip/buildkernel=$(call MkuImageGzip,$(2),$(3) $(4)) +Image/Build/AthGzip=$(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/AthGzip/initramfs=$(call MkuImageGzip/initramfs,$(2),$(3) $(4)) + +Image/Build/AthLzma/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/AthLzma=$(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/AthLzma/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + + +Image/Build/Belkin/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/Belkin/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Belkin + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(call Sysupgrade/RKuImage,$(1),$(2),$(kernsize),$(rootsize)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + edimax_fw_header -m $(5) -v "OpenWrt$(REVISION)" \ + -n "uImage" \ + -i $(KDIR_TMP)/vmlinux-$(2).uImage \ + -o $(KDIR_TMP)/$(2)-uImage; \ + edimax_fw_header -m $(5) -v "OpenWrt$(REVISION)" \ + -n "rootfs" \ + -i $(KDIR)/root.$(1) \ + -o $(KDIR_TMP)/$(2)-rootfs; \ + ( \ + dd if=$(KDIR_TMP)/$(2)-rootfs; \ + dd if=$(KDIR_TMP)/$(2)-uImage; \ + ) > "$(call factoryname,$(1),$(2))"; \ + fi +endef + +define Image/Build/EnGenius + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(call Sysupgrade/$(5),$(1),$(2),$(if $(6),$(6),$(kernsize)),$(if $(rootsize),$(rootsize),$(fwsize))) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + mksenaofw -e $(call sysupname,$(1),$(2)) \ + -o $(call imgname,$(1),$(2))-factory.dlf \ + -r 0x101 -p $(7) -t 2; \ + fi +endef + +Image/Build/EnGenius/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/EnGenius/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + + +define MkuImageHiWiFi + # Field ih_name needs to start with "tw150v1" + mkimage -A mips -O linux -T kernel -a 0x80060000 -C $(1) $(2) \ + -e 0x80060000 -n 'tw150v1 MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(3) $(4) +endef + +define MkuImageLzmaHiWiFi + $(call PatchKernelLzma,$(1),$(2),$(3),$(4)) + $(call MkuImageHiWiFi,lzma,$(5),$(KDIR_TMP)/vmlinux$(4)-$(1).bin.lzma,$(KDIR_TMP)/vmlinux$(4)-$(1).uImage) +endef + +Image/Build/HiWiFi/buildkernel=$(call MkuImageLzmaHiWiFi,$(2),$(3) $(4)) +Image/Build/HiWiFi=$(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/HiWiFi/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +Image/Build/PB4X/buildkernel=$(call PatchKernelLzma,$(2),$(3)) + +define Image/Build/PB4X + dd if=$(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync + -sh $(TOPDIR)/scripts/combined-image.sh \ + "$(call imgname,kernel,$(2)).bin" \ + "$(call imgname,$(1),$(2)-rootfs).bin" \ + $(call sysupname,$(1),$(2)) +endef + + +Image/Build/MyLoader/buildkernel=$(call PatchKernelLzma,$(2),$(3)) +Image/Build/MyLoader/initramfs=$(call PatchKernel/initramfs,$(2),$(3)) + +define Image/Build/MyLoader + $(eval fwsize=$(shell echo $$(($(4)-0x30000-4*64*1024)))) + $(eval fwimage=$(KDIR_TMP)/$(2)-$(5)-firmware.bin) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).bin.lzma,65536,$(KDIR)/root.$(1),$(fwsize),$(fwimage)) + if [ -e "$(fwimage)" ]; then \ + $(STAGING_DIR_HOST)/bin/mkmylofw -B $(2) -s $(4) -v \ + -p0x00030000:0:al:0x80060000:firmware:$(fwimage) \ + $(call imgname,$(1),$(2))-$(5)-factory.img; \ + echo -n "" > $(KDIR_TMP)/empty.bin; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + $(fwimage) $(KDIR_TMP)/empty.bin \ + $(call imgname,$(1),$(2))-$(5)-sysupgrade.bin; \ + fi +endef + +Image/Build/Planex/initramfs=$(call MkuImageGzip/initramfs,$(2),$(3) $(planex_mtdlayout)) +Image/Build/Planex/loader=$(call Image/BuildLoaderAlone,$(1),gz,$(2) $(planex_mtdlayout),0x52000,0) + +define Image/Build/Planex/buildkernel + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR)/loader-$(2).gz bs=8128 count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + $(call MkuImage,gzip,,$(KDIR_TMP)/kernel-$(2).bin,$(KDIR_TMP)/vmlinux-$(2).uImage) +endef + +define Image/Build/Planex + $(eval fwsize=$(call mtdpartsize,firmware,$(planex_mtdlayout))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + $(STAGING_DIR_HOST)/bin/mkplanexfw \ + -B $(2) \ + -v 2.00.00 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + + +Image/Build/ALFA/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/ALFA/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/ALFA + $(call Sysupgrade/RKuImage,$(1),$(2),$(5),$(6)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + rm -rf $(KDIR)/$(1); \ + mkdir -p $(KDIR)/$(1); \ + cd $(KDIR)/$(1); \ + cp $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR)/$(1)/$(7); \ + cp $(KDIR)/root.$(1) $(KDIR)/$(1)/$(8); \ + $(TAR) zcf $(call factoryname,$(1),$(2)) -C $(KDIR)/$(1) $(7) $(8); \ + ( \ + echo WRM7222C | dd bs=32 count=1 conv=sync; \ + echo -ne '\xfe'; \ + ) >> $(call factoryname,$(1),$(2)); \ + fi +endef + + +Image/Build/Seama/loader=$(call Image/BuildLoader,$(1),bin,$(2) $(3),0x80060000) + +define Image/Build/Seama + [ -e "$(KDIR)/loader-$(2).bin" ] + $(call CompressLzma,$(KDIR)/loader-$(2).bin,$(KDIR_TMP)/loader-$(2).bin.lzma) + -rm -f $(KDIR_TMP)/image-$(2).tmp + $(call CatFiles,$(KDIR_TMP)/loader-$(2).bin.lzma,$$$$(($(6) - 64)),$(KDIR)/root.$(1),$(7),$(KDIR_TMP)/image-$(2).tmp) + [ -e "$(KDIR_TMP)/image-$(2).tmp" ] && { \ + head -c -4 "$(KDIR_TMP)/image-$(2).tmp" > "$(KDIR_TMP)/image-$(2).no-jffs2mark.tmp"; \ + $(STAGING_DIR_HOST)/bin/seama \ + -i $(KDIR_TMP)/image-$(2).no-jffs2mark.tmp \ + -m "dev=/dev/mtdblock/1" -m "type=firmware"; \ + $(STAGING_DIR_HOST)/bin/seama \ + -s $(call imgname,$(1),$(2))-factory.bin \ + -m "signature=$(5)" \ + -i $(KDIR_TMP)/image-$(2).no-jffs2mark.tmp.seama; \ + tail -c 4 "$(KDIR_TMP)/image-$(2).tmp" >> $(call imgname,$(1),$(2))-factory.bin; \ + } + cat $(KDIR_TMP)/loader-$(2).bin.lzma > $(KDIR_TMP)/image-$(2)-sysupgrade.tmp + $(STAGING_DIR_HOST)/bin/seama \ + -i $(KDIR_TMP)/image-$(2)-sysupgrade.tmp \ + -m "dev=/dev/mtdblock/1" -m "type=firmware" + $(call CatFiles,$(KDIR_TMP)/image-$(2)-sysupgrade.tmp.seama,$(6),$(KDIR)/root.$(1),$(7),$(call sysupname,$(1),$(2))) +endef + +define Image/Build/Seama/initramfs + $(call PatchKernelLzma,$(2),$(3) $(4),,-initramfs) + $(STAGING_DIR_HOST)/bin/seama \ + -i $(KDIR_TMP)/vmlinux-initramfs-$(2).bin.lzma \ + -m "dev=/dev/mtdblock/1" -m "type=firmware" + cat $(KDIR_TMP)/vmlinux-initramfs-$(2).bin.lzma.seama > $(call imgname,initramfs,$(2))-seama.bin +endef + +Image/Build/Senao/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/Senao/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Senao + mkdir -p $(KDIR_TMP)/$(2)/ + touch $(KDIR_TMP)/$(2)/FWINFO-OpenWrt-$(REVISION)-$(2) + -$(CP) ./$(2)/* $(KDIR_TMP)/$(2)/ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(KDIR_TMP)/$(2)/openwrt-senao-$(2)-uImage-lzma.bin bs=64k conv=sync + dd if=$(KDIR)/root.$(1) \ + of=$(KDIR_TMP)/$(2)/openwrt-senao-$(2)-root.$(1) bs=64k conv=sync + ( \ + cd $(KDIR_TMP)/$(2)/; \ + $(TAR) -cz -f $(call factoryname,$(1),$(2)) * \ + ) + -rm -rf $(KDIR_TMP)/$(2)/ + -sh $(TOPDIR)/scripts/combined-image.sh \ + $(KDIR_TMP)/vmlinux-$(2).uImage \ + $(KDIR)/root.$(1) \ + $(call sysupname,$(1),$(2)) +endef + +Image/Build/TPLINKOLD/loader=$(call Image/BuildLoaderAlone,$(1),gz,$(2),0x22000,0) + +define Image/Build/TPLINKOLD + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR)/loader-$(2).gz bs=7680 count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli conv=sync; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION)\ + -X 0x40000 \ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -X 0x40000 \ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINKOLD/initramfs + $(call Image/BuildLoader,$(2),gz,$(3),0x80060000,-initramfs) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -k $(KDIR)/loader-$(2)-initramfs.gz \ + -o $(call imgname,$(1),$(2))-initramfs-uImage.bin +endef + + +Image/Build/TPLINK/loader=$(call Image/BuildLoaderAlone,$(1),gz,$(2),0x22000,0) + +define Image/Build/TPLINK + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR)/loader-$(2).gz bs=7680 count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli conv=sync; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION)\ + -X 0x40000 \ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -X 0x40000 \ + -k $(KDIR_TMP)/kernel-$(2).bin \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINK/initramfs + $(call Image/BuildLoader,$(2),gz,$(3),0x80060000,-initramfs) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) -s\ + -k $(KDIR)/loader-$(2)-initramfs.gz \ + -o $(call imgname,$(1),$(2))-uImage.bin +endef + + +Image/Build/TPLINK-LZMA/buildkernel=$(call PatchKernelLzma,$(2),$(3)) + +define Image/Build/TPLINK-LZMA + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) \ + -X 0x40000 \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) -s \ + -X 0x40000 \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINK-LZMA/initramfs + $(call PatchKernelLzma,$(2),$(3),,-initramfs) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) -s \ + -k $(KDIR_TMP)/vmlinux-initramfs-$(2).bin.lzma \ + -o $(call imgname,$(1),$(2))-uImage.bin +endef + +Image/Build/TPLINK-64K/buildkernel=$(call PatchKernelLzma,$(2),$(3)) + +define Image/Build/TPLINK-64K + -$(STAGING_DIR_HOST)/bin/mkimage \ + -A mips -O linux -T kernel -a 0x80060000 -C lzma \ + -e 0x80060000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $$(KDIR_TMP)/vmlinux-$(2).bin.lzma $(KDIR_TMP)/vmlinux-$(2).bin.lzma.img + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -m 2 -V $(REVISION) $(7) \ + -X 0x20000 \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma.img \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -m 2 -V $(REVISION) $(7) -s \ + -X 0x20000 \ + -k $(KDIR_TMP)/vmlinux-$(2).bin.lzma.img \ + -r $(KDIR)/root.$(1) \ + -a $(call rootfs_align,$(1)) -j \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/TPLINK-64K/initramfs + $(call PatchKernelLzma,$(2),$(3),,-initramfs) + -$(STAGING_DIR_HOST)/bin/mktplinkfw -c \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -m 2 -V $(REVISION) $(7) -s \ + -k $(KDIR_TMP)/vmlinux-initramfs-$(2).bin.lzma.img \ + -o $(call imgname,$(1),$(2))-uImage.bin +endef + + +Image/Build/TPLINK-SAFELOADER/loader = $(call Image/BuildLoaderPatched,$(1),elf,$(2) $(3)) + +define Image/Build/TPLINK-SAFELOADER + [ -e "$(KDIR)/loader-$(2).elf" ] + + -$(STAGING_DIR_HOST)/bin/tplink-safeloader \ + -B $(5) \ + -k $(KDIR)/loader-$(2).elf \ + -r $(KDIR)/root.$(1) \ + -V $(REVISION) \ + -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/tplink-safeloader \ + -B $(5) \ + -k $(KDIR)/loader-$(2).elf \ + -r $(KDIR)/root.$(1) \ + -V $(REVISION) \ + -j -S \ + -o $(call sysupname,$(1),$(2)) +endef + + +define Image/Build/CyberTAN + echo -n '' > $(KDIR_TMP)/empty.bin + $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/image.tmp \ + -f $(KDIR_TMP)/vmlinux-$(2).uImage -F $(KDIR_TMP)/empty.bin \ + -x 32 -a 0x10000 -x -32 -f $(KDIR)/root.$(1) + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(5) \ + -i $(KDIR)/image.tmp \ + -o $(call sysupname,$(1),$(2)) + $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/image.tmp -f $(KDIR_TMP)/vmlinux-$(2).uImage \ + -x 32 -a 0x10000 -x -32 -f $(KDIR)/root.$(1) + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(5) -g \ + -i $(KDIR)/image.tmp \ + -o $(call factoryname,$(1),$(2)) + rm $(KDIR)/image.tmp +endef + +Image/Build/CyberTANGZIP/loader=$(call Image/BuildLoader,$(1),gz,$(2),0x80060000) +Image/Build/CyberTANGZIP/buildkernel=$(call MkuImage,gzip,,$(KDIR)/loader-$(2).gz,$(KDIR_TMP)/vmlinux-$(2).uImage) +Image/Build/CyberTANGZIP=$(call Image/Build/CyberTAN,$(1),$(2),$(3),$(4),$(5)) + +Image/Build/CyberTANLZMA/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/CyberTANLZMA=$(call Image/Build/CyberTAN,$(1),$(2),$(3),$(4),$(5)) + + +Image/Build/Netgear/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4),,-M $(5)) + +define Image/Build/Netgear/buildkernel + $(call MkuImageLzma,$(2),$(3) $(4),-d20,,-M $(5)) + -rm -rf $(KDIR_TMP)/$(2) + mkdir -p $(KDIR_TMP)/$(2)/image + cat $(KDIR_TMP)/vmlinux-$(2).uImage > $(KDIR_TMP)/$(2)/image/uImage + $(STAGING_DIR_HOST)/bin/mksquashfs-lzma \ + $(KDIR_TMP)/$(2) $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp1 \ + -noappend -root-owned -be -b 65536 + ( \ + cat $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp1; \ + dd if=/dev/zero bs=1k count=1 \ + ) > $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp2 + mkimage -A mips -O linux -T filesystem -C none -M $(5) \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp2 \ + $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs +endef + +define Image/Build/Netgear + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage.squashfs,0,$(KDIR)/root.$(1),$(fwsize),$(call sysupname,$(1),$(2)),64) + if [ -e $(call sysupname,$(1),$(2)) ]; then \ + for r in $(7) ; do \ + [ -n "$$$$r" ] && dashr="-$$$$r" || dashr= ; \ + $(STAGING_DIR_HOST)/bin/mkdniimg \ + -B $(6) -v OpenWrt.$(REVISION) -r "$$$$r" $(8) \ + -i $(call sysupname,$(1),$(2)) \ + -o $(call imgname,$(1),$(2))-factory$$$$dashr.img; \ + done; \ + fi +endef + + +Image/Build/NetgearLzma/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4),,-M $(5)) +Image/Build/NetgearLzma/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4),-d20,,-M $(5)) + +define Image/Build/NetgearLzma + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage,0,$(KDIR)/root.$(1),$(fwsize),$(call sysupname,$(1),$(2)),64) +endef + + +Image/Build/NetgearNAND/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4),,-M $(5)) + +# $(1): (empty) +# $(2): Board name (small caps) +# $(3): Kernel board specific cmdline +# $(4): Kernel mtdparts definition +# $(5): U-Boot magic +define Image/Build/NetgearNAND/buildkernel + $(eval kernelsize=$(call mtdpartsize,kernel,$(4))) + $(call PatchKernelLzma,$(2),$(3) $(4),-d20) + dd if=$(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + of=$(KDIR_TMP)/vmlinux-$(2).bin.tmp \ + bs=$$$$(($(kernelsize)-131072-2*64-1)) \ + count=1 conv=sync + $(call MkuImage,lzma,-M $(5),$(KDIR_TMP)/vmlinux-$(2).bin.tmp,$(KDIR_TMP)/vmlinux-$(2).uImage) + echo -ne '\xff' >> $(KDIR_TMP)/vmlinux-$(2).uImage + # create a fake rootfs image + dd if=/dev/zero of=$(KDIR_TMP)/fakeroot-$(2) bs=131072 count=1 + mkimage -A mips -O linux -T filesystem -C none \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt fakeroot' \ + -d $(KDIR_TMP)/fakeroot-$(2) \ + -M $(5) \ + $(KDIR_TMP)/fakeroot-$(2).uImage + # append the fake rootfs image to the kernel, it will reside in the last + # erase block of the kernel partition + cat $(KDIR_TMP)/fakeroot-$(2).uImage >> $(KDIR_TMP)/vmlinux-$(2).uImage +endef + + +# $(1): rootfs image suffix +# $(2): Board name (small caps) +# $(3): Kernel board specific cmdline +# $(4): Kernel mtdparts definition +# $(5): U-Boot magic +# $(6): Board name (upper caps) +# $(7): firmware region code (not used yet) +# $(8): DNI Hardware version +# $(9): suffix of the configuration file for ubinize +define Image/Build/NetgearNAND + $(eval firmwaresize=$(call mtdpartsize,firmware,$(4))) + $(eval kernelsize=$(call mtdpartsize,kernel,$(4))) + $(eval imageraw=$(KDIR_TMP)/$(2)-raw.img) + $(CP) $(KDIR)/root.squashfs-raw $(KDIR_TMP)/root.squashfs + echo -ne '\xde\xad\xc0\xde' > $(KDIR_TMP)/jffs2.eof + $(call ubinize,ubinize-$(9).ini,$(KDIR_TMP),$(KDIR_TMP)/$(2)-root.ubi,128KiB,2048,-E 5) + ( \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage; \ + dd if=$(KDIR_TMP)/$(2)-root.ubi \ + ) > $(imageraw) + $(STAGING_DIR_HOST)/bin/mkdniimg \ + -B $(6) -v OpenWrt.$(REVISION) -r "$$$$r" $(8) \ + -i $(imageraw) \ + -o $(call imgname,ubi,$(2))-factory.img + + $(call Image/Build/SysupgradeNAND,$(2),squashfs,$(KDIR_TMP)/vmlinux-$(2).uImage) +endef + + +ifdef CONFIG_PACKAGE_uboot-ar71xx-nbg460n_550n_550nh + Image/Build/ZyXEL/buildkernel=$(call MkuImageLzma,$(2),$(3)) + + define Image/Build/ZyXEL + $(call Sysupgrade/KRuImage,$(1),$(2),917504,2752512) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + if [ ! -f $(BIN_DIR)/$(IMG_PREFIX)-$(2)-u-boot.bin ]; then \ + echo "Warning: $(IMG_PREFIX)-$(2)-u-boot.bin not found" >&2; \ + else \ + $(STAGING_DIR_HOST)/bin/mkzynfw \ + -B $(4) \ + -b $(BIN_DIR)/$(IMG_PREFIX)-$(2)-u-boot.bin \ + -r $(call sysupname,$(1),$(2)):0x10000 \ + -o $(call factoryname,$(1),$(2)); \ + fi; fi + endef +endif + + +define Image/Build/ZyXELNAND/buildkernel + $(eval kernelsize=$(call mtdpartsize,kernel,$(5))) + $(call MkuImageLzma,$(2),$(3) $(5) $(6)) + mkdir -p $(KDIR_TMP)/$(2)/image/boot + cp $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR_TMP)/$(2)/image/boot/vmlinux.lzma.uImage + $(STAGING_DIR_HOST)/bin/mkfs.jffs2 \ + --pad=$(kernelsize) --big-endian --squash-uids -v -e 128KiB \ + -o $(KDIR_TMP)/$(2)-kernel.jffs2 \ + -d $(KDIR_TMP)/$(2)/image \ + 2>&1 1>/dev/null | awk '/^.+$$$$/' + -rm -rf $(KDIR_TMP)/$(2) +endef + +define Image/Build/ZyXELNAND + if [ "$(1)" != "squashfs" ]; then \ + echo Only squashfs is supported; \ + return 0; \ + fi + $(eval firmwaresize=$(call mtdpartsize,firmware,$(4))) + $(eval kernelsize=$(call mtdpartsize,kernel,$(4))) + $(eval imageraw=$(KDIR_TMP)/$(2)-raw.img) + $(CP) $(KDIR)/root.$(1) $(KDIR_TMP)/ubi_root.img + $(call ubinize,ubinize-$(2).ini,$(KDIR_TMP),$(KDIR_TMP)/$(2)-root.ubi,128KiB,2048,-E 5) + ( \ + dd if=$(KDIR_TMP)/$(2)-kernel.jffs2; \ + dd if=$(KDIR_TMP)/$(2)-root.ubi \ + ) > $(imageraw) + dd if=$(imageraw) of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory.bin \ + bs=128k conv=sync + $(call Image/Build/SysupgradeNAND,$(2),squashfs,$(KDIR_TMP)/$(2)-kernel.jffs2) +endef + + +Image/Build/OpenMesh/buildkernel=$(call MkuImageLzma,$(2)) + +define Image/Build/OpenMesh + -sh $(TOPDIR)/scripts/om-fwupgradecfg-gen.sh \ + "$(4)" \ + "$(BUILD_DIR)/fwupgrade.cfg-$(4)" \ + "$(KDIR_TMP)/vmlinux-$(2).uImage" \ + "$(KDIR)/root.$(1)" + -sh $(TOPDIR)/scripts/combined-ext-image.sh \ + "$(4)" "$(call factoryname,$(1),$(2))" \ + "$(BUILD_DIR)/fwupgrade.cfg-$(4)" "fwupgrade.cfg" \ + "$(KDIR_TMP)/vmlinux-$(2).uImage" "kernel" \ + "$(KDIR)/root.$(1)" "rootfs" +endef + + +Image/Build/Zcomax/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/Zcomax/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Zcomax + $(call Sysupgrade/RKuImage,$(1),$(2),1507328,6356992) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + $(STAGING_DIR_HOST)/bin/mkzcfw \ + -B $(2) \ + -k $(KDIR_TMP)/vmlinux-$(2).uImage \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(call imgname,$(1),$(2))-factory.img; \ + fi +endef + + +# $(1): template name to be defined, etc. squashfs-only, 64k, 64kraw, etc. +# $(2): jffs2 blocksize. +define Jffs2Template + define Image/Build/Template/$(1)/jffs2-$(2) + $$(call Image/Build/$$(1),jffs2-$(2),$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef +endef + +# $(1): template name to be defined. +# $(2): squashfs suffix to be used. +# $(3): jffs2 suffix to be used. +define BuildTemplate + # $(1) : name of build method. + # $(2) : board name. + # $(3) : kernel command line. + # $(4)~$(8): extra arguments. + define Image/Build/Template/$(1)/initramfs + $$(call Image/Build/$$(1)/initramfs,initramfs,$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + define Image/Build/Template/$(1)/loader + $$(call Image/Build/$$(1)/loader,$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + define Image/Build/Template/$(1)/buildkernel + $$(call Image/Build/$$(1)/buildkernel,,$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + define Image/Build/Template/$(1)/squashfs + $$(call Image/Build/$$(1),squashfs$(2),$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + $(if $(3),$(foreach bs,$(3),$(eval $(call Jffs2Template,$(1),$(bs))))) +endef + +$(eval $(call BuildTemplate,squashfs-only)) +$(eval $(call BuildTemplate,64k,-64k,64k)) +$(eval $(call BuildTemplate,64kraw,-raw,64k)) +$(eval $(call BuildTemplate,64kraw-nojffs,-raw)) +$(eval $(call BuildTemplate,128k,,128k)) +$(eval $(call BuildTemplate,128kraw,-raw,128k)) +$(eval $(call BuildTemplate,256k,,256k)) +$(eval $(call BuildTemplate,all,,64k 128k 256k)) + +ifeq ($(SUBTARGET),generic) +$(eval $(call SingleProfile,ALFA,64k,ALFANX,alfa-nx,ALFA-NX,ttyS0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,vmlinux.gz.uImage,pb9x-2.6.31-jffs2)) +$(eval $(call SingleProfile,ALFA,64k,HORNETUB,hornet-ub,HORNET-UB,ttyATH0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,kernel_image,rootfs_image)) +$(eval $(call SingleProfile,ALFA,64k,TUBE2H8M,tube2h-8M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,kernel.image,rootfs.image)) + +$(eval $(call SingleProfile,AthGzip,64k,AP81,ap81,AP81,ttyS0,115200,$$(ap81_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthGzip,64k,AP83,ap83,AP83,ttyS0,115200,$$(ap83_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthGzip,64k,AP96,ap96,AP96,ttyS0,115200,$$(ap96_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthGzip,64k,WNDAP360,wndap360,WNDAP360,ttyS0,9600,$$(wndap360_mtdlayout),KRuImage)) + +$(eval $(call SingleProfile,AthLzma,64k,ALFAAP96,alfa-ap96,ALFA-AP96,ttyS0,115200,$$(alfa_ap96_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,ALL0258N,all0258n,ALL0258N,ttyS0,115200,$$(all0258n_mtdlayout),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,256k,ALL0315N,all0315n,ALL0315N,ttyS0,115200,$$(all0315n_mtdlayout),KRuImage,262144)) +$(eval $(call SingleProfile,AthLzma,64k,AP113,ap113,AP113,ttyS0,115200,$$(ap113_mtd_layout),RK)) +$(eval $(call SingleProfile,AthLzma,64k,AP121_2M,ap121-2M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_2M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP121_4M,ap121-4M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_4M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP121_8M,ap121-8M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_8M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP121MINI,ap121-mini,AP121-MINI,ttyATH0,115200,$$(ap121_mtdlayout_4M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP132,ap132,AP132,ttyS0,115200,$$(ap132_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP135,ap135-020,AP135-020,ttyS0,115200,$$(ap135_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP136_010,ap136-010,AP136-010,ttyS0,115200,$$(ap136_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP136_020,ap136-020,AP136-020,ttyS0,115200,$$(ap136_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP143_8M,ap143-8M,AP143,ttyS0,115200,$$(ap143_mtdlayout_8M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP143_16M,ap143-16M,AP143,ttyS0,115200,$$(ap143_mtdlayout_16M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP147_010,ap147-010,AP147-010,ttyS0,115200,$$(ap147_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP152_16M,ap152-16M,AP152,ttyS0,115200,$$(ap152_mtdlayout_16M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,BXU2000N2,bxu2000n-2-a1,BXU2000n-2-A1,ttyS0,115200,$$(bxu2000n2_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,CAP4200AG,cap4200ag,CAP4200AG,ttyS0,115200,$$(cap4200ag_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,DB120,db120,DB120,ttyS0,115200,$$(db120_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,DRAGINO2,dragino2,DRAGINO2,ttyATH0,115200,$$(dragino2_mtdlayout),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,EWDORINAP,ew-dorin,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,EWDORINRT,ew-dorin-router,EW-DORIN-ROUTER,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,EWDORIN16M,ew-dorin-16M,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,HORNETUBx2,hornet-ub-x2,HORNET-UB,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,MR12,mr12,MR12,ttyS0,115200,$$(mr12_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,MR16,mr16,MR16,ttyS0,115200,$$(mr16_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,PB92,pb92,PB92,ttyS0,115200,$$(pb92_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,WPJ558_16M,wpj558-16M,WPJ558,ttyS0,115200,$$(wpj558_mtdlayout_16M),KRuImage,65536)) + +$(eval $(call SingleProfile,Belkin,64k,F9K1115V2,f9k1115v2,F9K1115V2,ttyS0,115200,$$(f9k1115v2_mtdlayout),BR-6679BAC)) + +$(eval $(call SingleProfile,CameoAP91,64kraw,DIR600A1,dir-600-a1,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-00")) +$(eval $(call SingleProfile,CameoAP91,64kraw,DIR601A1,dir-601-a1,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-02")) +$(eval $(call SingleProfile,CameoAP91,64kraw,FR54RTR,fr-54rtr,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-01")) + +$(eval $(call SingleProfile,CameoAP99,64kraw,DIR615E1,dir-615-e1,DIR-615-E1,ttyS0,115200,"AP93-AR7240-RT-081028-00")) +$(eval $(call SingleProfile,CameoAP99,64kraw,DIR615E4,dir-615-e4,DIR-615-E4,ttyS0,115200,"AP99-AR7240-RT-091105-05")) + +$(eval $(call SingleProfile,CameoAP123_4M,64kraw,DIR615I1,dir-615-i1,DIR-615-I1,ttyS0,115200,"00DB120AR9341-RT-1012I1-00")) +$(eval $(call SingleProfile,CameoAP123_4M,64kraw,DIR615I3,dir-615-i3,DIR-615-I1,ttyS0,115200,"00DB120AR9341-RT-101214-00")) + +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,A02RBW300N,a02-rb-w300n,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-03")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,DIR615C1,dir-615-c1,DIR-615-C1,ttyS0,115200,"AP81-AR9130-RT-070614-02")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,TEW632BRP,tew-632brp,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-00")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,TEW652BRP_FW,tew-652brp,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-080609-05")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,TEW652BRP_RECOVERY,tew-652brp-recovery,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-02")) + +$(eval $(call SingleProfile,CameoAP121,64kraw-nojffs,TEW712BR,tew-712br,TEW-712BR,ttyATH0,115200,"HORNET-RT-TEW712BR-3",1.99,"")) +$(eval $(call SingleProfile,CameoAP121,64kraw-nojffs,DIR601B1,dir-601-b1,TEW-712BR,ttyATH0,115200,"HORNET-RT-DIR601B1-3",2.99.99,"" "NA")) +$(eval $(call SingleProfile,CameoAP121_8M,64kraw-nojffs,DIR505A1,dir-505-a1,DIR-505-A1,ttyATH0,115200,"HORNET-PACKET-DIR505A1-3",1.99.99,"")) + +$(eval $(call SingleProfile,CameoAP135,64kraw,DGL5500A1,dgl-5500-a1,DGL-5500-A1,ttyS0,115200,$$(dgl_5500_mtdlayout),"00AP135AR9558-RT-130508-00")) + +$(eval $(call SingleProfile,CameoDB120,64kraw,DHP1565A1,dhp-1565-a1,DHP-1565-A1,ttyS0,115200,"00DB120AR9344-RT-101214-00")) +$(eval $(call SingleProfile,CameoDB120,64kraw,DIR825C1,dir-825-c1,DIR-825-C1,ttyS0,115200,"00DB120AR9344-RT-101214-00")) +$(eval $(call SingleProfile,CameoDB120,64kraw,DIR835A1,dir-835-a1,DIR-835-A1,ttyS0,115200,"00DB120AR9344-RT-101214-00")) + +$(eval $(call SingleProfile,CameoDB120_8M,64kraw,TEW732BR,tew-732br,TEW-732BR,ttyS0,115200,"00DB120AR9341-RT-120906-NA")) + +$(eval $(call SingleProfile,CyberTANGZIP,64k,WRT160NL,wrt160nl,WRT160NL,ttyS0,115200,,1.00.01)) + +$(eval $(call SingleProfile,CyberTANLZMA,64k,MYNETREXT,mynet-rext,MYNET-REXT,ttyS0,115200,$$(mynet_rext_mtdlayout) root=31:2,1.00.01)) + +$(eval $(call SingleProfile,CameoAP94,64kraw,DIR825B1,dir-825-b1,DIR-825-B1,ttyS0,115200,$$(cameo_ap94_mtdlayout),$$(cameo_ap94_mtdlayout_fat),01AP94-AR7161-RT-080619-00,00AP94-AR7161-RT-080619-00)) +$(eval $(call SingleProfile,CameoAP94,64kraw,TEW673GRU,tew-673gru,TEW-673GRU,ttyS0,115200,$$(cameo_ap94_mtdlayout),$$(cameo_ap94_mtdlayout_fat),01AP94-AR7161-RT-080619-01,00AP94-AR7161-RT-080619-01)) +$(eval $(call SingleProfile,CameoAP94,64kraw,DLRTDEV01,dlrtdev01,DIR-825-B1,ttyS0,115200,$$(dlrtdev_mtdlayout),$$(dlrtdev_mtdlayout_fat),01AP94-AR7161-RT-080619-00,00AP94-AR7161-RT-080619-00)) + +$(eval $(call SingleProfile,dLANLzma,64k,dLAN_pro_500_wp,dlan-pro-500-wp,dLAN-pro-500-wp,ttyS0,115200,$$(dlan_pro_500_wp_mtdlayout) mem=128M,KRuImage,64k)) +$(eval $(call SingleProfile,dLANLzma,64k,dLAN_pro_1200_ac,dlan-pro-1200-ac,dLAN-pro-1200-ac,ttyS0,115200,$$(dlan_pro_1200_ac_mtdlayout) mem=128M,KRuImage,64k)) + +$(eval $(call SingleProfile,EnGenius,64k,ESR900,esr900,ESR900,ttyS0,115200,$$(esr900_mtdlayout),KRuImage,,0x4e)) +$(eval $(call SingleProfile,EnGenius,64k,ESR1750,esr1750,ESR1750,ttyS0,115200,$$(esr1750_mtdlayout),KRuImage,,0x61)) +$(eval $(call SingleProfile,EnGenius,64k,EPG5000,epg5000,EPG5000,ttyS0,115200,$$(epg5000_mtdlayout),KRuImage,,0x71)) + +$(eval $(call SingleProfile,HiWiFi,64k,HIWIFI_HC6361,hiwifi-hc6361,HiWiFi-HC6361,ttyATH0,115200,$$(hiwifi_hc6361_mtdlayout),KRuImage)) + +$(eval $(call SingleProfile,MyLoader,64k,WP543_2M,wp543,,ttyS0,115200,0x200000,2M)) +$(eval $(call SingleProfile,MyLoader,64k,WP543_4M,wp543,,ttyS0,115200,0x400000,4M)) +$(eval $(call SingleProfile,MyLoader,64k,WP543_8M,wp543,,ttyS0,115200,0x800000,8M)) +$(eval $(call SingleProfile,MyLoader,64k,WP543_16M,wp543,,ttyS0,115200,0x1000000,16M)) +$(eval $(call SingleProfile,MyLoader,64k,WPE72_4M,wpe72,,ttyS0,115200,0x400000,4M)) +$(eval $(call SingleProfile,MyLoader,64k,WPE72_8M,wpe72,,ttyS0,115200,0x800000,8M)) +$(eval $(call SingleProfile,MyLoader,64k,WPE72_16M,wpe72,,ttyS0,115200,0x1000000,16M)) + +$(eval $(call SingleProfile,Netgear,64kraw,WNR2000V3,wnr2000v3,WNR2000V3,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x32303033,WNR2000V3,"" NA,-H 29763551+04+32)) +$(eval $(call SingleProfile,NetgearLzma,64kraw,WNR2000V4,wnr2000v4,WNR2000V4,ttyS0,115200,$$(wnr2000v4_mtdlayout),0x32303034,WNR2000V4,"" NA,)) +$(eval $(call SingleProfile,Netgear,64kraw,WNR2200,wnr2200,WNR2200,ttyS0,115200,$$(wnr2200_mtdlayout),0x32323030,WNR2200,"" NA,)) +$(eval $(call SingleProfile,Netgear,64kraw,REALWNR612V2,wnr612v2,WNR612V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x32303631,WNR612V2,"",)) +$(eval $(call SingleProfile,Netgear,64kraw,N150R,n150r,WNR612V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x32303631,N150R,"",)) +$(eval $(call SingleProfile,Netgear,64kraw,REALWNR1000V2,wnr1000v2,WNR1000V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x31303031,WNR1000V2,"",)) +$(eval $(call SingleProfile,Netgear,64kraw,WNR1000V2_VC,wnr1000v2-vc,WNR1000V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x31303030,WNR1000V2-VC,"",)) + +$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM2P,om2p,,,,OM2P)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM5P,om5p,,,,OM5P)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR600,mr600,,,,MR600)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR900,mr900,,,,MR900)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR1750,mr1750,,,,MR1750)) + +$(eval $(call SingleProfile,PB4X,128k,ALL0305,all0305,ALL0305,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,128k,EAP7660D,eap7660d,EAP7660D,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,JA76PF,ja76pf,JA76PF,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,JA76PF2,ja76pf2,JA76PF2,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,JWAP003,jwap003,JWAP003,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,PB42,pb42,PB42,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,PB44,pb44,PB44,ttyS0,115200)) + +$(eval $(call SingleProfile,Planex,64kraw,MZKW04NU,mzk-w04nu,MZK-W04NU,ttyS0,115200)) +$(eval $(call SingleProfile,Planex,64kraw,MZKW300NH,mzk-w300nh,MZK-W300NH,ttyS0,115200)) + +$(eval $(call SingleProfile,Seama,64k,MYNETN600,mynet-n600,MYNET-N600,ttyS0,115200,$$(mynet_n600_mtdlayout),wrgnd16_wd_db600,65536,16187392)) +$(eval $(call SingleProfile,Seama,64k,MYNETN750,mynet-n750,MYNET-N750,ttyS0,115200,$$(mynet_n600_mtdlayout),wrgnd13_wd_av,65536,16187392)) + +$(eval $(call SingleProfile,Seama,64k,QIHOO360,qihoo-c301,QIHOO-C301,ttyS0,115200,$$(qihoo_c301_mtdlayout),wrgac26_qihoo360_360rg,65536,16121856)) + +$(eval $(call SingleProfile,Senao,squashfs-only,EAP300V2,eap300v2,EAP300V2,ttyS0,115200,$$(eap300v2_mtdlayout))) + +$(eval $(call SingleProfile,TPLINKOLD,squashfs-only,TLWR841NV15,tl-wr841nd-v1.5,TL-WR841N-v1.5,ttyS0,115200,0x08410002,2,4M)) + +$(eval $(call SingleProfile,TPLINK,64kraw,RNXN360RT,rnx-n360rt,TL-WR941ND,ttyS0,115200,0x09410002,0x00420001,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLMR3220V1,tl-mr3220-v1,TL-MR3220,ttyS0,115200,0x32200001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLMR3420V1,tl-mr3420-v1,TL-MR3420,ttyS0,115200,0x34200001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA701NV1,tl-wa701n-v1,TL-WA901ND,ttyS0,115200,0x07010001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA730REV1,tl-wa730rev1,TL-WA901ND,ttyS0,115200,0x07300001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA7510NV1,tl-wa7510n,TL-WA7510N,ttyS0,115200,0x75100001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA801NV1,tl-wa801nd-v1,TL-WA901ND,ttyS0,115200,0x08010001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA830RV1,tl-wa830re-v1,TL-WA901ND,ttyS0,115200,0x08300010,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA901NV1,tl-wa901nd-v1,TL-WA901ND,ttyS0,115200,0x09010001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWA901NV2,tl-wa901nd-v2,TL-WA901ND-v2,ttyS0,115200,0x09010002,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR740NV1,tl-wr740n-v1,TL-WR741ND,ttyS0,115200,0x07400001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR740NV3,tl-wr740n-v3,TL-WR741ND,ttyS0,115200,0x07400003,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR743NV1,tl-wr743nd-v1,TL-WR741ND,ttyS0,115200,0x07430001,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR841NV3,tl-wr841nd-v3,TL-WR941ND,ttyS0,115200,0x08410003,3,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR841NV5,tl-wr841nd-v5,TL-WR741ND,ttyS0,115200,0x08410005,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR841NV7,tl-wr841nd-v7,TL-WR841N-v7,ttyS0,115200,0x08410007,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR842V1,tl-wr842n-v1,TL-MR3420,ttyS0,115200,0x08420001,1,8M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR941NV2,tl-wr941nd-v2,TL-WR941ND,ttyS0,115200,0x09410002,2,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR941NV3,tl-wr941nd-v3,TL-WR941ND,ttyS0,115200,0x09410002,2,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR941NV4,tl-wr941nd-v4,TL-WR741ND,ttyS0,115200,0x09410004,1,4M)) +$(eval $(call SingleProfile,TPLINK,64kraw,TLWR1043V1,tl-wr1043nd-v1,TL-WR1043ND,ttyS0,115200,0x10430001,1,8M)) + +$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWR1043V2,tl-wr1043nd-v2,TL-WR1043ND-v2,ttyS0,115200,0x10430002,1,8M)) +$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWR2543,tl-wr2543-v1,TL-WR2543N,ttyS0,115200,0x25430001,1,8Mlzma,-v 3.13.99)) + +$(eval $(call SingleProfile,TPLINK-64K,64kraw,TLWDR6500V2,tl-wdr6500-v2,TL-WDR6500-v2,ttyS0,115200,0x65000002,1,8Mlzma)) + +$(eval $(call SingleProfile,TPLINK-SAFELOADER,64kraw,CPE510,cpe210-220-510-520,CPE510,ttyS0,115200,$$(cpe510_mtdlayout),CPE510)) + +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WHRG301N,whr-g301n,WHR-G301N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-G301N)) +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WHRHPG300N,whr-hp-g300n,WHR-HP-G300N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-HP-G300N)) +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WHRHPGN,whr-hp-gn,WHR-HP-GN,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-HP-GN)) +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WLAEAG300N,wlae-ag300n,WLAE-AG300N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WLAE-AG300N)) + +$(eval $(call SingleProfile,WRT400N,64k,WRT400N,wrt400n,WRT400N,ttyS0,115200)) + +$(eval $(call SingleProfile,WZRHP128K,128kraw,WZRHPG300NH,wzr-hp-g300nh,WZR-HP-G300NH,ttyS0,115200,WZR-HP-G300NH)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZRHPG300NH2,wzr-hp-g300nh2,WZR-HP-G300NH2,ttyS0,115200,WZR-HP-G300NH2)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZRHPAG300H,wzr-hp-ag300h,WZR-HP-AG300H,ttyS0,115200,WZR-HP-AG300H)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZRHPG450H,wzr-hp-g450h,WZR-HP-G450H,ttyS0,115200,WZR-HP-AG450H)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZR600DHP,wzr-600dhp,WZR-HP-AG300H,ttyS0,115200,WZR-600DHP)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZR450HP2,wzr-450hp2,WZR-450HP2,ttyS0,115200,WZR-450HP2)) + +$(eval $(call SingleProfile,Zcomax,64k,ZCN1523H28,zcn-1523h-2-8,ZCN-1523H-2,ttyS0,115200,$$(zcn1523h_mtdlayout))) +$(eval $(call SingleProfile,Zcomax,64k,ZCN1523H516,zcn-1523h-5-16,ZCN-1523H-5,ttyS0,115200,$$(zcn1523h_mtdlayout))) + +$(eval $(call SingleProfile,ZyXEL,64k,NBG_460N_550N_550NH,nbg460n_550n_550nh,NBG460N,ttyS0,115200,NBG-460N)) + +$(eval $(call MultiProfile,AP121,AP121_2M AP121_4M AP121_8M)) +$(eval $(call MultiProfile,AP136,AP136_010 AP136_020)) +$(eval $(call MultiProfile,AP143,AP143_8M AP143_16M)) +$(eval $(call MultiProfile,AP147,AP147_010)) +$(eval $(call MultiProfile,AP152,AP152_16M)) +$(eval $(call MultiProfile,DIR615IX,DIR615I1 DIR615I3)) +$(eval $(call MultiProfile,EWDORIN, EWDORINAP EWDORINRT EWDORIN16M)) +$(eval $(call MultiProfile,OPENMESH,OM2P OM5P MR600 MR900 MR1750)) +$(eval $(call MultiProfile,TEW652BRP,TEW652BRP_FW TEW652BRP_RECOVERY)) +$(eval $(call MultiProfile,TLMR3220,TLMR3220V1)) +$(eval $(call MultiProfile,TLMR3420,TLMR3420V1)) +$(eval $(call MultiProfile,TLWA701,TLWA701NV1)) +$(eval $(call MultiProfile,TLWA730RE,TLWA730REV1)) +$(eval $(call MultiProfile,TLWA801,TLWA801NV1)) +$(eval $(call MultiProfile,TLWA830,TLWA830RV1)) +$(eval $(call MultiProfile,TLWA901,TLWA901NV1 TLWA901NV2)) +$(eval $(call MultiProfile,TLWA7510,TLWA7510NV1)) +$(eval $(call MultiProfile,TLWR740,TLWR740NV1 TLWR740NV3)) +$(eval $(call MultiProfile,TLWR741,TLWR741NV1 TLWR741NV2)) +$(eval $(call MultiProfile,TLWR743,TLWR743NV1)) +$(eval $(call MultiProfile,TLWR841,TLWR841NV15 TLWR841NV3 TLWR841NV5 TLWR841NV7)) +$(eval $(call MultiProfile,TLWR842,TLWR842V1)) +$(eval $(call MultiProfile,TLWR941,TLWR941NV2 TLWR941NV3 TLWR941NV4)) +$(eval $(call MultiProfile,TLWR1043,TLWR1043V1 TLWR1043V2)) +$(eval $(call MultiProfile,TLWDR4300,TLWDR3500V1 TLWDR3600V1 TLWDR4300V1 TLWDR4300V1IL TLWDR4310V1 MW4530RV1)) +$(eval $(call MultiProfile,TUBE2H,TUBE2H8M TUBE2H16M)) +$(eval $(call MultiProfile,WNR612V2,REALWNR612V2 N150R)) +$(eval $(call MultiProfile,WNR1000V2,REALWNR1000V2 WNR1000V2_VC)) +$(eval $(call MultiProfile,WP543,WP543_2M WP543_4M WP543_8M WP543_16M)) +$(eval $(call MultiProfile,WPE72,WPE72_4M WPE72_8M WPE72_16M)) +$(eval $(call MultiProfile,WPJ344,WPJ344_16M)) +$(eval $(call MultiProfile,WPJ531,WPJ531_16M)) +$(eval $(call MultiProfile,WPJ558,WPJ558_16M)) + +$(eval $(call MultiProfile,Minimal,$(SINGLE_PROFILES))) +$(eval $(call MultiProfile,Madwifi,EAP7660D WP543)) +endif # ifeq ($(SUBTARGET),generic) + +ifeq ($(SUBTARGET),nand) +$(eval $(call SingleProfile,NetgearNAND,64k,WNDR3700V4,wndr3700v4,WNDR3700_V4,ttyS0,115200,$$(wndr4300_mtdlayout),0x33373033,WNDR3700v4,"",-H 29763948+128+128,wndr4300)) +$(eval $(call SingleProfile,NetgearNAND,64k,WNDR4300V1,wndr4300,WNDR4300,ttyS0,115200,$$(wndr4300_mtdlayout),0x33373033,WNDR4300,"",-H 29763948+0+128+128+2x2+3x3,wndr4300)) +$(eval $(call SingleProfile,NetgearNAND,64k,R6100,r6100,R6100,ttyS0,115200,$$(r6100_mtdlayout),0x36303030,R6100,"",-H 29764434+0+128+128+2x2+2x2,wndr4300)) + +$(eval $(call SingleProfile,ZyXELNAND,128k,NBG6716,nbg6716,NBG6716,ttyS0,115200,NBG6716,$$(zyx_nbg6716_mtdlayout),mem=256M)) + +$(eval $(call MultiProfile,WNDR4300,WNDR3700V4 WNDR4300V1)) +endif # ifeq ($(SUBTARGET),nand) + + +$(eval $(call MultiProfile,Default,$(SINGLE_PROFILES))) + +define Image/Build/squashfs + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-raw + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-64k + $(STAGING_DIR_HOST)/bin/padjffs2 $(KDIR)/root.squashfs-64k 64 + cp $(KDIR)/root.squashfs-64k $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs-64k + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +define Image/Build/jffs2 + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +define Image/Build/Initramfs + $(call Image/Build/Profile/$(IMAGE_PROFILE),initramfs) +endef + +define Image/Prepare + gzip -9n -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz + $(call CompressLzma,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.lzma) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + gzip -9n -c $(KDIR)/vmlinux-initramfs > $(KDIR)/vmlinux-initramfs.bin.gz + $(call CompressLzma,$(KDIR)/vmlinux-initramfs,$(KDIR)/vmlinux-initramfs.bin.lzma) + $(call Image/BuildLoader,generic,elf,,,-initramfs) +endif + $(call Image/BuildLoader,generic,elf) + $(call Image/Build/Profile/$(if $(CONFIG_IB),Default,$(IMAGE_PROFILE)),loader) +endef + +# $(1): filesystem type. +define Image/Build + $(call Image/Build/$(call rootfs_type,$(1)),$(1)) + $(call Image/Build/Profile/$(IMAGE_PROFILE),$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ar71xx/image/lzma-loader/Makefile b/target/linux/ar71xx/image/lzma-loader/Makefile new file mode 100644 index 0000000..2e0b911 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/Makefile @@ -0,0 +1,64 @@ +# +# Copyright (C) 2011 OpenWrt.org +# Copyright (C) 2011 Gabor Juhos +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +LZMA_TEXT_START := 0x80a00000 +LOADER := loader.bin +LOADER_NAME := $(basename $(notdir $(LOADER))) +LOADER_DATA := +TARGET_DIR := +FLASH_OFFS := +FLASH_MAX := +BOARD := + +ifeq ($(TARGET_DIR),) +TARGET_DIR := $(KDIR) +endif + +LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin +LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz +LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME) + +.PHONY : loader-compile loader.bin loader.elf loader.gz + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +loader-compile: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + LOADER_DATA=$(LOADER_DATA) \ + FLASH_OFFS=$(FLASH_OFFS) \ + FLASH_MAX=$(FLASH_MAX) \ + BOARD="$(BOARD)" \ + clean all + +loader.gz: $(PKG_BUILD_DIR)/loader.bin + gzip -nc9 $< > $(LOADER_GZ) + +loader.elf: $(PKG_BUILD_DIR)/loader.elf + $(CP) $< $(LOADER_ELF) + +loader.bin: $(PKG_BUILD_DIR)/loader.bin + $(CP) $< $(LOADER_BIN) + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: loader-compile + +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..cb83453 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,584 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..2870eeb --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h b/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h new file mode 100644 index 0000000..9c27290 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_NO_SYSTEM_SIZE_T */ +/* You can use it, if you don't want */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +#include +typedef size_t SizeT; +#endif +#endif + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/Makefile b/target/linux/ar71xx/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..5f10bdb --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/Makefile @@ -0,0 +1,106 @@ +# +# Makefile for the LZMA compressed kernel loader for +# Atheros AR7XXX/AR9XXX based boards +# +# Copyright (C) 2011 Gabor Juhos +# +# Some parts of this file was based on the OpenWrt specific lzma-loader +# for the BCM47xx and ADM5120 based boards: +# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) +# Copyright (C) 2005 Mineharu Takahara +# Copyright (C) 2005 by Oleg I. Vdovikin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. +# + +LOADADDR := +LZMA_TEXT_START := 0x80a00000 +LOADER_DATA := +BOARD := +FLASH_OFFS := +FLASH_MAX := + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug \ + -R .MIPS.abiflags -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \ + -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \ + -fno-common -ffreestanding -fhonour-copts \ + -mabi=32 -march=mips32r2 \ + -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap +CFLAGS += -D_LZMA_PROB32 + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o loader.o cache.o board.o printf.o LzmaDecode.o + +ifneq ($(strip $(LOADER_DATA)),) +OBJECTS += data.o +CFLAGS += -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR) +endif + +ifneq ($(strip $(KERNEL_CMDLINE)),) +CFLAGS += -DCONFIG_KERNEL_CMDLINE='"$(KERNEL_CMDLINE)"' +endif + +ifneq ($(strip $(FLASH_OFFS)),) +CFLAGS += -DCONFIG_FLASH_OFFS=$(FLASH_OFFS) +endif + +ifneq ($(strip $(FLASH_MAX)),) +CFLAGS += -DCONFIG_FLASH_MAX=$(FLASH_MAX) +endif + +BOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _) +ifneq ($(BOARD_DEF),) +CFLAGS += -DCONFIG_BOARD_$(BOARD_DEF) +endif + +all: loader.elf + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +data.o: $(LOADER_DATA) + $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $< + +loader: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +loader.bin: loader + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +loader2.o: loader.bin + $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $< + +loader.elf: loader2.o + $(LD) -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $< + +mrproper: clean + +clean: + rm -f loader *.elf *.bin *.o + + + diff --git a/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h b/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h new file mode 100644 index 0000000..19a4785 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h @@ -0,0 +1,725 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#define BIT(_x) (1UL << (_x)) + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9558 0x1130 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define AR944X_REV_ID_REVISION_MASK 0xf + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) + +#define AR934X_GPIO_OUT_GPIO 0x00 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/board.c b/target/linux/ar71xx/image/lzma-loader/src/board.c new file mode 100644 index 0000000..2f4dd6b --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/board.c @@ -0,0 +1,56 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include "config.h" +#include "ar71xx_regs.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) + +#define UART_BASE 0xb8020000 + +#define UART_TX 0 +#define UART_LSR 5 + +#define UART_LSR_THRE 0x20 + +#define UART_READ(r) READREG(UART_BASE + 4 * (r)) +#define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) + +void board_putc(int ch) +{ + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_TX, ch); + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + +#ifdef CONFIG_BOARD_TL_WR1043ND_V1 +static void tlwr1043nd_init(void) +{ + unsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE); + unsigned int t; + + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); + t |= AR71XX_RESET_GE0_PHY; + WRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t); + /* flush write */ + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); +} +#else +static inline void tlwr1043nd_init(void) {} +#endif + +void board_init(void) +{ + tlwr1043nd_init(); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/cache.c b/target/linux/ar71xx/image/lzma-loader/src/cache.c new file mode 100644 index 0000000..28cc848 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cache.c @@ -0,0 +1,43 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/cache.h b/target/linux/ar71xx/image/lzma-loader/src/cache.h new file mode 100644 index 0000000..506a235 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cache.h @@ -0,0 +1,17 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __CACHE_H +#define __CACHE_H + +void flush_cache(unsigned long start_addr, unsigned long size); + +#endif /* __CACHE_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/cacheops.h b/target/linux/ar71xx/image/lzma-loader/src/cacheops.h new file mode 100644 index 0000000..70bcad7 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cacheops.h @@ -0,0 +1,85 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/config.h b/target/linux/ar71xx/image/lzma-loader/src/config.h new file mode 100644 index 0000000..287392b --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/config.h @@ -0,0 +1,31 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define CONFIG_ICACHE_SIZE (32 * 1024) +#define CONFIG_DCACHE_SIZE (64 * 1024) +#define CONFIG_CACHELINE_SIZE 32 + +#ifndef CONFIG_FLASH_OFFS +#define CONFIG_FLASH_OFFS 0 +#endif + +#ifndef CONFIG_FLASH_MAX +#define CONFIG_FLASH_MAX 0 +#endif + +#ifndef CONFIG_FLASH_STEP +#define CONFIG_FLASH_STEP 0x1000 +#endif + +#endif /* _CONFIG_H_ */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h b/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h new file mode 100644 index 0000000..c1188ad --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * + * Copyright (C) 2001, Monta Vista Software + * Author: jsun@mvista.com or jsun@junsun.net + */ +#ifndef _cp0regdef_h_ +#define _cp0regdef_h_ + +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/head.S b/target/linux/ar71xx/image/lzma-loader/src/head.S new file mode 100644 index 0000000..543996a --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/head.S @@ -0,0 +1,118 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "cp0regdef.h" +#include "cacheops.h" +#include "config.h" + +#define KSEG0 0x80000000 + + .macro ehb + sll zero, 3 + .endm + + .text + +LEAF(startup) + .set noreorder + .set mips32 + + mtc0 zero, CP0_WATCHLO # clear watch registers + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_CAUSE # clear before writing status register + + mfc0 t0, CP0_STATUS + li t1, 0x1000001f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS + ehb + + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + ehb + + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + + beqz t0, __reloc_done # if delta is 0 we are in the right place + nop + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + addu t0, t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + + /* flush cache */ + la t0, _code_start + la t1, _code_end + + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __flush_check + nop + +__flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__flush_check: + bne t0, t1, __flush_line + nop + + sync + +__reloc_done: + + /* clear bss */ + la t0, _bss_start + la t1, _bss_end + b __bss_check + nop + +__bss_fill: + sw zero, 0(t0) + addi t0, 4 + +__bss_check: + bne t0, t1, __bss_fill + nop + + /* Setup new "C" stack */ + la sp, _stack + + /* jump to the decompressor routine */ + la t0, loader_main + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader.c b/target/linux/ar71xx/image/lzma-loader/src/loader.c new file mode 100644 index 0000000..cc73eb1 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader.c @@ -0,0 +1,264 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 Mineharu Takahara + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * The image_header structure has been taken from the U-Boot project. + * (C) Copyright 2008 Semihalf + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "config.h" +#include "cache.h" +#include "printf.h" +#include "LzmaDecode.h" + +#define AR71XX_FLASH_START 0x1f000000 +#define AR71XX_FLASH_END 0x1fe00000 + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#undef LZMA_DEBUG + +#ifdef LZMA_DEBUG +# define DBG(f, a...) printf(f, ## a) +#else +# define DBG(f, a...) do {} while (0) +#endif + +#define IH_MAGIC_OKLI 0x4f4b4c49 /* 'OKLI' */ + +#define IH_NMLEN 32 /* Image Name Length */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +/* beyond the image end, size not known in advance */ +extern unsigned char workspace[]; +extern void board_init(void); + +static CLzmaDecoderState lzma_state; +static unsigned char *lzma_data; +static unsigned long lzma_datasize; +static unsigned long lzma_outsize; +static unsigned long kernel_la; + +#ifdef CONFIG_KERNEL_CMDLINE +#define kernel_argc 2 +static const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE; +static const char *kernel_argv[] = { + NULL, + kernel_cmdline, + NULL, +}; +#endif /* CONFIG_KERNEL_CMDLINE */ + +static void halt(void) +{ + printf("\nSystem halted!\n"); + for(;;); +} + +static __inline__ unsigned long get_be32(void *buf) +{ + unsigned char *p = buf; + + return (((unsigned long) p[0] << 24) + + ((unsigned long) p[1] << 16) + + ((unsigned long) p[2] << 8) + + (unsigned long) p[3]); +} + +static __inline__ unsigned char lzma_get_byte(void) +{ + unsigned char c; + + lzma_datasize--; + c = *lzma_data++; + + return c; +} + +static int lzma_init_props(void) +{ + unsigned char props[LZMA_PROPERTIES_SIZE]; + int res; + int i; + + /* read lzma properties */ + for (i = 0; i < LZMA_PROPERTIES_SIZE; i++) + props[i] = lzma_get_byte(); + + /* read the lower half of uncompressed size in the header */ + lzma_outsize = ((SizeT) lzma_get_byte()) + + ((SizeT) lzma_get_byte() << 8) + + ((SizeT) lzma_get_byte() << 16) + + ((SizeT) lzma_get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + lzma_get_byte(); + + res = LzmaDecodeProperties(&lzma_state.Properties, props, + LZMA_PROPERTIES_SIZE); + return res; +} + +static int lzma_decompress(unsigned char *outStream) +{ + SizeT ip, op; + int ret; + + lzma_state.Probs = (CProb *) workspace; + + ret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream, + lzma_outsize, &op); + + if (ret != LZMA_RESULT_OK) { + int i; + + DBG("LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\n", + ret, lzma_data + ip, lzma_outsize, ip, op); + + for (i = 0; i < 16; i++) + DBG("%02x ", lzma_data[ip + i]); + + DBG("\n"); + } + + return ret; +} + +#if (LZMA_WRAPPER) +static void lzma_init_data(void) +{ + extern unsigned char _lzma_data_start[]; + extern unsigned char _lzma_data_end[]; + + kernel_la = LOADADDR; + lzma_data = _lzma_data_start; + lzma_datasize = _lzma_data_end - _lzma_data_start; +} +#else +static void lzma_init_data(void) +{ + struct image_header *hdr = NULL; + unsigned char *flash_base; + unsigned long flash_ofs; + unsigned long kernel_ofs; + unsigned long kernel_size; + + flash_base = (unsigned char *) KSEG1ADDR(AR71XX_FLASH_START); + + printf("Looking for OpenWrt image... "); + + for (flash_ofs = CONFIG_FLASH_OFFS; + flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX); + flash_ofs += CONFIG_FLASH_STEP) { + unsigned long magic; + unsigned char *p; + + p = flash_base + flash_ofs; + magic = get_be32(p); + if (magic == IH_MAGIC_OKLI) { + hdr = (struct image_header *) p; + break; + } + } + + if (hdr == NULL) { + printf("not found!\n"); + halt(); + } + + printf("found at 0x%08x\n", flash_base + flash_ofs); + + kernel_ofs = sizeof(struct image_header); + kernel_size = get_be32(&hdr->ih_size); + kernel_la = get_be32(&hdr->ih_load); + + lzma_data = flash_base + flash_ofs + kernel_ofs; + lzma_datasize = kernel_size; +} +#endif /* (LZMA_WRAPPER) */ + +void loader_main(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3) +{ + void (*kernel_entry) (unsigned long, unsigned long, unsigned long, + unsigned long); + int res; + + board_init(); + + printf("\n\nOpenWrt kernel loader for AR7XXX/AR9XXX\n"); + printf("Copyright (C) 2011 Gabor Juhos \n"); + + lzma_init_data(); + + res = lzma_init_props(); + if (res != LZMA_RESULT_OK) { + printf("Incorrect LZMA stream properties!\n"); + halt(); + } + + printf("Decompressing kernel... "); + + res = lzma_decompress((unsigned char *) kernel_la); + if (res != LZMA_RESULT_OK) { + printf("failed, "); + switch (res) { + case LZMA_RESULT_DATA_ERROR: + printf("data error!\n"); + break; + default: + printf("unknown error %d!\n", res); + } + halt(); + } else { + printf("done!\n"); + } + + flush_cache(kernel_la, lzma_outsize); + + printf("Starting kernel at %08x...\n\n", kernel_la); + +#ifdef CONFIG_KERNEL_CMDLINE + reg_a0 = kernel_argc; + reg_a1 = (unsigned long) kernel_argv; + reg_a2 = 0; + reg_a3 = 0; +#endif + + kernel_entry = (void *) kernel_la; + kernel_entry(reg_a0, reg_a1, reg_a2, reg_a3); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader.lds b/target/linux/ar71xx/image/lzma-loader/src/loader.lds new file mode 100644 index 0000000..80cc7ca --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader.lds @@ -0,0 +1,35 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.data.lzma) + } + + . = ALIGN(32); + .data : { + *(.data) + *(.data.*) + . = . + 524288; /* workaround for buggy bootloaders */ + } + + . = ALIGN(32); + _code_end = .; + + _bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + } + + . = ALIGN(32); + _bss_end = .; + + . = . + 8192; + _stack = .; + + workspace = .; +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader2.lds b/target/linux/ar71xx/image/lzma-loader/src/loader2.lds new file mode 100644 index 0000000..db0bb46 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader2.lds @@ -0,0 +1,10 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + startup = .; + *(.text) + *(.text.*) + *(.data) + *(.data.*) + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds b/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds new file mode 100644 index 0000000..abf756b --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds @@ -0,0 +1,8 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .data.lzma : { + _lzma_data_start = .; + *(.data) + _lzma_data_end = .; + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/printf.c b/target/linux/ar71xx/image/lzma-loader/src/printf.c new file mode 100644 index 0000000..7bb5a86 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/printf.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" + +extern void board_putc(int ch); + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 256 + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +static int PrintChar(char *, char, int, int); +static int PrintString(char *, char *, int, int); +static int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +static void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +static int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +static int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +static int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} + +static void printf_output(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + board_putc(s[i]); + if (s[i] == '\n') board_putc('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(printf_output, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/printf.h b/target/linux/ar71xx/image/lzma-loader/src/printf.h new file mode 100644 index 0000000..9b1c1df --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/ar71xx/image/ubinize-nbg6716.ini b/target/linux/ar71xx/image/ubinize-nbg6716.ini new file mode 100644 index 0000000..814b0fb --- /dev/null +++ b/target/linux/ar71xx/image/ubinize-nbg6716.ini @@ -0,0 +1,24 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=ubi_root.img +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs + +[rootfs_data] +# Volume mode (other option is static) +mode=ubi +# Volume ID in UBI image +vol_id=1 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs_data +# Autoresize volume at first mount +vol_size=1MiB +vol_flags=autoresize diff --git a/target/linux/ar71xx/image/ubinize-wndr4300.ini b/target/linux/ar71xx/image/ubinize-wndr4300.ini new file mode 100644 index 0000000..5bff906 --- /dev/null +++ b/target/linux/ar71xx/image/ubinize-wndr4300.ini @@ -0,0 +1,26 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.squashfs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +# vol_flags=autoresize + +[rootfs_data] +# Volume mode (other option is static) +mode=ubi +# Volume ID in UBI image +vol_id=1 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs_data +# Autoresize volume at first mount +vol_flags=autoresize +vol_size=1MiB diff --git a/target/linux/ar71xx/mikrotik/config-default b/target/linux/ar71xx/mikrotik/config-default new file mode 100644 index 0000000..de91e4b --- /dev/null +++ b/target/linux/ar71xx/mikrotik/config-default @@ -0,0 +1,169 @@ +# CONFIG_ATH79_DEV_DSA is not set +# CONFIG_ATH79_MACH_ALFA_AP96 is not set +# CONFIG_ATH79_MACH_ALFA_NX is not set +# CONFIG_ATH79_MACH_ALL0258N is not set +# CONFIG_ATH79_MACH_ALL0315N is not set +# CONFIG_ATH79_MACH_ANTMINER_S1 is not set +# CONFIG_ATH79_MACH_AP113 is not set +# CONFIG_ATH79_MACH_AP121 is not set +# CONFIG_ATH79_MACH_AP132 is not set +# CONFIG_ATH79_MACH_AP136 is not set +# CONFIG_ATH79_MACH_AP147 is not set +# CONFIG_ATH79_MACH_AP81 is not set +# CONFIG_ATH79_MACH_AP83 is not set +# CONFIG_ATH79_MACH_AP96 is not set +# CONFIG_ATH79_MACH_ARCHER_C7 is not set +# CONFIG_ATH79_MACH_AW_NR580 is not set +# CONFIG_ATH79_MACH_BHU_BXU2000N2_A is not set +# CONFIG_ATH79_MACH_CAP4200AG is not set +# CONFIG_ATH79_MACH_CARAMBOLA2 is not set +# CONFIG_ATH79_MACH_CPE510 is not set +# CONFIG_ATH79_MACH_DB120 is not set +# CONFIG_ATH79_MACH_DGL_5500_A1 is not set +# CONFIG_ATH79_MACH_DHP_1565_A1 is not set +# CONFIG_ATH79_MACH_DIR_505_A1 is not set +# CONFIG_ATH79_MACH_DIR_600_A1 is not set +# CONFIG_ATH79_MACH_DIR_615_C1 is not set +# CONFIG_ATH79_MACH_DIR_825_B1 is not set +# CONFIG_ATH79_MACH_DIR_825_C1 is not set +# CONFIG_ATH79_MACH_DRAGINO2 is not set +# CONFIG_ATH79_MACH_EAP300V2 is not set +# CONFIG_ATH79_MACH_EAP7660D is not set +# CONFIG_ATH79_MACH_EL_M150 is not set +# CONFIG_ATH79_MACH_EL_MINI is not set +# CONFIG_ATH79_MACH_EPG5000 is not set +# CONFIG_ATH79_MACH_ESR1750 is not set +# CONFIG_ATH79_MACH_ESR900 is not set +# CONFIG_ATH79_MACH_EW_DORIN is not set +# CONFIG_ATH79_MACH_F9K1115V2 is not set +# CONFIG_ATH79_MACH_GL_INET is not set +# CONFIG_ATH79_MACH_GS_OOLITE is not set +# CONFIG_ATH79_MACH_HIWIFI_HC6361 is not set +# CONFIG_ATH79_MACH_HORNET_UB is not set +# CONFIG_ATH79_MACH_JA76PF is not set +# CONFIG_ATH79_MACH_JWAP003 is not set +# CONFIG_ATH79_MACH_MC_MAC1200R is not set +# CONFIG_ATH79_MACH_MR12 is not set +# CONFIG_ATH79_MACH_MR16 is not set +# CONFIG_ATH79_MACH_MR600 is not set +# CONFIG_ATH79_MACH_MR900 is not set +# CONFIG_ATH79_MACH_MYNET_N600 is not set +# CONFIG_ATH79_MACH_MYNET_N750 is not set +# CONFIG_ATH79_MACH_MYNET_REXT is not set +# CONFIG_ATH79_MACH_MZK_W04NU is not set +# CONFIG_ATH79_MACH_MZK_W300NH is not set +# CONFIG_ATH79_MACH_NBG460N is not set +# CONFIG_ATH79_MACH_NBG6716 is not set +# CONFIG_ATH79_MACH_OM2P is not set +# CONFIG_ATH79_MACH_OM5P is not set +# CONFIG_ATH79_MACH_PB42 is not set +# CONFIG_ATH79_MACH_PB44 is not set +# CONFIG_ATH79_MACH_PB92 is not set +# CONFIG_ATH79_MACH_QIHOO_C301 is not set +# CONFIG_ATH79_MACH_R6100 is not set +CONFIG_ATH79_MACH_RB2011=y +CONFIG_ATH79_MACH_RB4XX=y +CONFIG_ATH79_MACH_RB750=y +CONFIG_ATH79_MACH_RB91X=y +CONFIG_ATH79_MACH_RB922=y +CONFIG_ATH79_MACH_RB95X=y +CONFIG_ATH79_MACH_RBSXTLITE=y +# CONFIG_ATH79_MACH_RW2458N is not set +# CONFIG_ATH79_MACH_SMART_300 is not set +# CONFIG_ATH79_MACH_TEW_632BRP is not set +# CONFIG_ATH79_MACH_TEW_673GRU is not set +# CONFIG_ATH79_MACH_TEW_712BR is not set +# CONFIG_ATH79_MACH_TEW_732BR is not set +# CONFIG_ATH79_MACH_TL_MR11U is not set +# CONFIG_ATH79_MACH_TL_MR13U is not set +# CONFIG_ATH79_MACH_TL_MR3020 is not set +# CONFIG_ATH79_MACH_TL_MR3X20 is not set +# CONFIG_ATH79_MACH_TL_WA701ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WA7210N_V2 is not set +# CONFIG_ATH79_MACH_TL_WA830RE_V2 is not set +# CONFIG_ATH79_MACH_TL_WA901ND is not set +# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WAX50RE is not set +# CONFIG_ATH79_MACH_TL_WDR3500 is not set +# CONFIG_ATH79_MACH_TL_WDR4300 is not set +# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set +# CONFIG_ATH79_MACH_TL_WR1043ND is not set +# CONFIG_ATH79_MACH_TL_WR1043ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WR2543N is not set +# CONFIG_ATH79_MACH_TL_WR703N is not set +# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set +# CONFIG_ATH79_MACH_TL_WR741ND is not set +# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V9 is not set +# CONFIG_ATH79_MACH_TL_WR941ND is not set +# CONFIG_ATH79_MACH_TUBE2H is not set +# CONFIG_ATH79_MACH_UBNT is not set +# CONFIG_ATH79_MACH_UBNT_XM is not set +# CONFIG_ATH79_MACH_WHR_HP_G300N is not set +# CONFIG_ATH79_MACH_WLAE_AG300N is not set +# CONFIG_ATH79_MACH_WLR8100 is not set +# CONFIG_ATH79_MACH_WNDAP360 is not set +# CONFIG_ATH79_MACH_WNDR3700 is not set +# CONFIG_ATH79_MACH_WNDR4300 is not set +# CONFIG_ATH79_MACH_WNR2000 is not set +# CONFIG_ATH79_MACH_WNR2000_V3 is not set +# CONFIG_ATH79_MACH_WNR2000_V4 is not set +# CONFIG_ATH79_MACH_WNR2200 is not set +# CONFIG_ATH79_MACH_WP543 is not set +# CONFIG_ATH79_MACH_WPE72 is not set +# CONFIG_ATH79_MACH_WPJ344 is not set +# CONFIG_ATH79_MACH_WPJ531 is not set +# CONFIG_ATH79_MACH_WPJ558 is not set +# CONFIG_ATH79_MACH_WRT160NL is not set +# CONFIG_ATH79_MACH_WRT400N is not set +# CONFIG_ATH79_MACH_WZR_450HP2 is not set +# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set +# CONFIG_ATH79_MACH_WZR_HP_G450H is not set +# CONFIG_ATH79_MACH_ZCN_1523H is not set +# CONFIG_ATH79_NVRAM is not set +CONFIG_ATH79_ROUTERBOOT=y +CONFIG_CMDLINE="rootfstype=yaffs noinitrd" +CONFIG_GPIO_74X164=y +CONFIG_GPIO_LATCH=y +# CONFIG_JFFS2_FS is not set +CONFIG_LEDS_RB750=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MYLOADER_PARTS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AR934X=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_RB4XX=y +CONFIG_MTD_NAND_RB750=y +CONFIG_MTD_NAND_RB91X=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_TPLINK_PARTS is not set +# CONFIG_OVERLAY_FS is not set +CONFIG_RLE_DECOMPRESS=y +# CONFIG_SOC_AR913X is not set +# CONFIG_SOC_AR933X is not set +# CONFIG_SOC_QCA953X is not set +CONFIG_SPI_RB4XX=y +CONFIG_SPI_RB4XX_CPLD=y +# CONFIG_SQUASHFS is not set +CONFIG_YAFFS_9BYTE_TAGS=y +CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_BACKGROUND is not set +# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_XATTR=y +CONFIG_YAFFS_YAFFS1=y +CONFIG_YAFFS_YAFFS2=y diff --git a/target/linux/ar71xx/mikrotik/profiles/01-minimal.mk b/target/linux/ar71xx/mikrotik/profiles/01-minimal.mk new file mode 100644 index 0000000..3651c88 --- /dev/null +++ b/target/linux/ar71xx/mikrotik/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DefaultNoWifi + NAME:=Default Profile (no WiFi) + PACKAGES:= +endef + +define Profile/DefaultNoWifi/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,DefaultNoWifi)) diff --git a/target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk b/target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk new file mode 100644 index 0000000..a291ff6 --- /dev/null +++ b/target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Ath5k + NAME:=Atheros WiFi (ath5k) + PACKAGES:=kmod-ath5k -kmod-ath9k +endef + +define Profile/Ath5k/Description + Package set compatible with hardware using Atheros WiFi cards. +endef +$(eval $(call Profile,Ath5k)) diff --git a/target/linux/ar71xx/mikrotik/target.mk b/target/linux/ar71xx/mikrotik/target.mk new file mode 100644 index 0000000..a2a41ed --- /dev/null +++ b/target/linux/ar71xx/mikrotik/target.mk @@ -0,0 +1,9 @@ +BOARDNAME:=Mikrotik devices with NAND flash +FEATURES += targz + +define Target/Description + Build firmware images for Atheros AR71xx/AR913x based Mikrotik boards. + e.g. MikroTik RB-4xx or RB-750 +endef + + diff --git a/target/linux/ar71xx/modules.mk b/target/linux/ar71xx/modules.mk new file mode 100644 index 0000000..a6a13d2 --- /dev/null +++ b/target/linux/ar71xx/modules.mk @@ -0,0 +1,53 @@ +# +# Copyright (C) 2006-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/leds-rb750 + SUBMENU:=$(LEDS_MENU) + TITLE:=RouterBOARD 750 LED support + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_LEDS_RB750 + FILES:=$(LINUX_DIR)/drivers/leds/leds-rb750.ko + AUTOLOAD:=$(call AutoLoad,60,leds-rb750) +endef + +define KernelPackage/leds-rb750/description + Kernel module for the LEDs on the MikroTik RouterBOARD 750. +endef + +$(eval $(call KernelPackage,leds-rb750)) + + +define KernelPackage/leds-wndr3700-usb + SUBMENU:=$(LEDS_MENU) + TITLE:=WNDR3700 USB LED support + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_LEDS_WNDR3700_USB + FILES:=$(LINUX_DIR)/drivers/leds/leds-wndr3700-usb.ko + AUTOLOAD:=$(call AutoLoad,60,leds-wndr3700-usb) +endef + +define KernelPackage/leds-wndr3700-usb/description + Kernel module for the USB LED on the NETGEAR WNDR3700 board. +endef + +$(eval $(call KernelPackage,leds-wndr3700-usb)) + + +define KernelPackage/spi-vsc7385 + SUBMENU:=$(SPI_MENU) + TITLE:=Vitesse VSC7385 ethernet switch driver + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_SPI_VSC7385 + FILES:=$(LINUX_DIR)/drivers/spi/spi-vsc7385.ko + AUTOLOAD:=$(call AutoLoad,93,spi-vsc7385) +endef + +define KernelPackage/spi-vsc7385/description + This package contains the SPI driver for the Vitesse VSC7385 ethernet switch. +endef + +$(eval $(call KernelPackage,spi-vsc7385)) diff --git a/target/linux/ar71xx/nand/config-default b/target/linux/ar71xx/nand/config-default new file mode 100644 index 0000000..50b6dbe --- /dev/null +++ b/target/linux/ar71xx/nand/config-default @@ -0,0 +1,112 @@ +# CONFIG_ATH79_DEV_DSA is not set +# CONFIG_ATH79_MACH_ALFA_AP96 is not set +# CONFIG_ATH79_MACH_ALFA_NX is not set +# CONFIG_ATH79_MACH_ALL0258N is not set +# CONFIG_ATH79_MACH_ALL0315N is not set +# CONFIG_ATH79_MACH_AP113 is not set +# CONFIG_ATH79_MACH_AP121 is not set +# CONFIG_ATH79_MACH_AP132 is not set +# CONFIG_ATH79_MACH_AP136 is not set +# CONFIG_ATH79_MACH_AP147 is not set +# CONFIG_ATH79_MACH_AP81 is not set +# CONFIG_ATH79_MACH_AP83 is not set +# CONFIG_ATH79_MACH_AP96 is not set +# CONFIG_ATH79_MACH_ARCHER_C7 is not set +# CONFIG_ATH79_MACH_AW_NR580 is not set +# CONFIG_ATH79_MACH_CAP4200AG is not set +# CONFIG_ATH79_MACH_CARAMBOLA2 is not set +# CONFIG_ATH79_MACH_DB120 is not set +# CONFIG_ATH79_MACH_DIR_505_A1 is not set +# CONFIG_ATH79_MACH_DIR_600_A1 is not set +# CONFIG_ATH79_MACH_DIR_615_C1 is not set +# CONFIG_ATH79_MACH_DIR_825_B1 is not set +# CONFIG_ATH79_MACH_DIR_825_C1 is not set +# CONFIG_ATH79_MACH_EAP7660D is not set +# CONFIG_ATH79_MACH_EW_DORIN is not set +# CONFIG_ATH79_MACH_HORNET_UB is not set +# CONFIG_ATH79_MACH_JA76PF is not set +# CONFIG_ATH79_MACH_JWAP003 is not set +# CONFIG_ATH79_MACH_MR600 is not set +# CONFIG_ATH79_MACH_MYNET_N600 is not set +# CONFIG_ATH79_MACH_MZK_W04NU is not set +# CONFIG_ATH79_MACH_MZK_W300NH is not set +# CONFIG_ATH79_MACH_NBG460N is not set +# CONFIG_ATH79_MACH_OM2P is not set +# CONFIG_ATH79_MACH_PB42 is not set +# CONFIG_ATH79_MACH_PB44 is not set +# CONFIG_ATH79_MACH_PB92 is not set +# CONFIG_ATH79_MACH_RW2458N is not set +# CONFIG_ATH79_MACH_TEW_632BRP is not set +# CONFIG_ATH79_MACH_TEW_673GRU is not set +# CONFIG_ATH79_MACH_TEW_712BR is not set +# CONFIG_ATH79_MACH_TEW_732BR is not set +# CONFIG_ATH79_MACH_TL_MR11U is not set +# CONFIG_ATH79_MACH_TL_MR13U is not set +# CONFIG_ATH79_MACH_TL_MR3020 is not set +# CONFIG_ATH79_MACH_TL_MR3X20 is not set +# CONFIG_ATH79_MACH_TL_WA901ND is not set +# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WDR3500 is not set +# CONFIG_ATH79_MACH_TL_WDR4300 is not set +# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set +# CONFIG_ATH79_MACH_TL_WR1043ND is not set +# CONFIG_ATH79_MACH_TL_WR2543N is not set +# CONFIG_ATH79_MACH_TL_WR703N is not set +# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set +# CONFIG_ATH79_MACH_TL_WR741ND is not set +# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set +# CONFIG_ATH79_MACH_TL_WR941ND is not set +# CONFIG_ATH79_MACH_UBNT is not set +# CONFIG_ATH79_MACH_UBNT_XM is not set +# CONFIG_ATH79_MACH_WHR_HP_G300N is not set +# CONFIG_ATH79_MACH_WLAE_AG300N is not set +# CONFIG_ATH79_MACH_WNDAP360 is not set +# CONFIG_ATH79_MACH_WNDR3700 is not set +# CONFIG_ATH79_MACH_WNR2000 is not set +# CONFIG_ATH79_MACH_WNR2000_V3 is not set +# CONFIG_ATH79_MACH_WNR2200 is not set +# CONFIG_ATH79_MACH_WP543 is not set +# CONFIG_ATH79_MACH_WPE72 is not set +# CONFIG_ATH79_MACH_WRT160NL is not set +# CONFIG_ATH79_MACH_WRT400N is not set +# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set +# CONFIG_ATH79_MACH_WZR_HP_G450H is not set +# CONFIG_ATH79_MACH_ZCN_1523H is not set +# CONFIG_ATH79_NVRAM is not set +CONFIG_CMDLINE="rootfstype=squashfs noinitrd" +# CONFIG_IP17XX_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MYLOADER_PARTS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AR934X=y +CONFIG_MTD_NAND_AR934X_HW_ECC=y +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_SPLIT_SEAMA_FW is not set +# CONFIG_MTD_TPLINK_PARTS is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_RTL8306_PHY is not set +# CONFIG_RTL8366_SMI is not set +# CONFIG_SOC_AR71XX is not set +# CONFIG_SOC_AR724X is not set +# CONFIG_SOC_AR913X is not set +CONFIG_SPI_ATH79=y +# CONFIG_SPI_BITBANG is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set diff --git a/target/linux/ar71xx/nand/profiles/netgear.mk b/target/linux/ar71xx/nand/profiles/netgear.mk new file mode 100644 index 0000000..738aaba --- /dev/null +++ b/target/linux/ar71xx/nand/profiles/netgear.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2009-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/R6100 + NAME:=NETGEAR R6100 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/R6100/Description + Package set optimized for the NETGEAR R6100 +endef + +$(eval $(call Profile,R6100)) + + +define Profile/WNDR4300 + NAME:=NETGEAR WNDR3700v4/WNDR4300 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WNDR4300/Description + Package set optimized for the NETGEAR WNDR3700v4/WNDR4300 +endef + +$(eval $(call Profile,WNDR4300)) diff --git a/target/linux/ar71xx/nand/profiles/zyxel.mk b/target/linux/ar71xx/nand/profiles/zyxel.mk new file mode 100644 index 0000000..ec813e5 --- /dev/null +++ b/target/linux/ar71xx/nand/profiles/zyxel.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NBG6716 + NAME:=Zyxel NBG 6716 + PACKAGES:=kmod-rtc-pcf8563 kmod-ath10k +endef + +define Profile/NBG6716/Description + Package set optimized for the Zyxel NBG 6716 Routers. +endef + +$(eval $(call Profile,NBG6716)) + diff --git a/target/linux/ar71xx/nand/target.mk b/target/linux/ar71xx/nand/target.mk new file mode 100644 index 0000000..7532ec6 --- /dev/null +++ b/target/linux/ar71xx/nand/target.mk @@ -0,0 +1,7 @@ +BOARDNAME := Generic devices with NAND flash +FEATURES += squashfs nand rtc + +define Target/Description + Build firmware images for Atheros AR71xx/AR913x based boards with + NAND flash, e.g. Netgear WNDR4300. +endef diff --git a/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch b/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch new file mode 100644 index 0000000..79c7ab0 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch @@ -0,0 +1,42 @@ +From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001 +From: Markos Chandras +Date: Wed, 21 Aug 2013 11:47:22 +0100 +Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable + +Fixes the following build error: +arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used +uninitialized in this function [-Werror=maybe-uninitialized] +arch/mips/ath79/common.c:62:6: note: 'reg' was declared here +In file included from arch/mips/ath79/common.c:20:0: +arch/mips/ath79/common.c: In function 'ath79_device_reset_clear': +arch/mips/include/asm/mach-ath79/ath79.h:139:20: +error: 'reg' may be used uninitialized in this function +[-Werror=maybe-uninitialized] +arch/mips/ath79/common.c:90:6: note: 'reg' was declared here + +Signed-off-by: Markos Chandras +Acked-by: Gabor Juhos +--- + arch/mips/ath79/common.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -75,7 +75,7 @@ void ath79_device_reset_set(u32 mask) + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +- BUG(); ++ panic("Reset register not defined for this SOC"); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); +@@ -103,7 +103,7 @@ void ath79_device_reset_clear(u32 mask) + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +- BUG(); ++ panic("Reset register not defined for this SOC"); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); diff --git a/target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch b/target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch new file mode 100644 index 0000000..b30087c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch @@ -0,0 +1,28 @@ +This exports some clock functions used by some modules. +This fixes this linking problem: + +ERROR: "clk_set_rate" [drivers/usb/phy/phy-generic.ko] undefined! +ERROR: "clk_round_rate" [drivers/media/v4l2-core/videodev.ko] undefined! +ERROR: "clk_set_rate" [drivers/media/v4l2-core/videodev.ko] undefined! + +In the upstream kernel it is fixed here: +https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=411520af8ec9456886359b42628e583ac58e7e44 + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -488,3 +488,15 @@ unsigned long clk_get_rate(struct clk *c + return clk->rate; + } + EXPORT_SYMBOL(clk_get_rate); ++ ++int clk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(clk_set_rate); ++ ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(clk_round_rate); diff --git a/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch new file mode 100644 index 0000000..e0821a7 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi + + static int ar933x_wmac_reset(void) + { ++ int retries = 20; ++ + ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); + +- return 0; ++ while (1) { ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) ++ return 0; ++ ++ if (retries-- == 0) ++ break; ++ ++ udelay(10000); ++ retries++; ++ } ++ ++ pr_err("ar933x: WMAC reset timed out"); ++ return -ETIMEDOUT; + } + + static int ar933x_r1_get_wmac_revision(void) diff --git a/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch b/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch new file mode 100644 index 0000000..9b704a3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac + }, + }; + +-static void __init ar913x_wmac_setup(void) ++static int ar913x_wmac_reset(void) + { + /* reset the WMAC */ + ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); +@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi + ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); + mdelay(10); + ++ return 0; ++} ++ ++static void __init ar913x_wmac_setup(void) ++{ ++ ar913x_wmac_reset(); ++ + ath79_wmac_resources[0].start = AR913X_WMAC_BASE; + ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); + ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); ++ ++ ath79_wmac_data.external_reset = ar913x_wmac_reset; + } + + diff --git a/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch b/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch new file mode 100644 index 0000000..c91ecdf --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -140,6 +140,8 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; ++ ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + } + + static void qca955x_wmac_setup(void) diff --git a/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch b/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch new file mode 100644 index 0000000..713a191 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP + + static void ath79_restart(char *command) + { ++ local_irq_disable(); + ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); + for (;;) + if (cpu_wait) +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -132,6 +132,7 @@ static inline u32 ath79_pll_rr(unsigned + static inline void ath79_reset_wr(unsigned reg, u32 val) + { + __raw_writel(val, ath79_reset_base + reg); ++ (void) __raw_readl(ath79_reset_base + reg); /* flush */ + } + + static inline u32 ath79_reset_rr(unsigned reg) diff --git a/target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch new file mode 100644 index 0000000..76c067a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch @@ -0,0 +1,191 @@ +From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Jan 2012 22:25:11 +0100 +Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/mach-pb44.c | 6 ++ + .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++- + drivers/spi/spi-ath79.c | 67 +++++++++++++------- + 8 files changed, 88 insertions(+), 23 deletions(-) + +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio + } + }; + ++static struct ath79_spi_controller_data pb44_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .controller_data = &pb44_spi0_data, + }, + }; + +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -16,8 +16,14 @@ struct ath79_spi_platform_data { + unsigned num_chipselect; + }; + ++enum ath79_spi_cs_type { ++ ATH79_SPI_CS_TYPE_INTERNAL, ++ ATH79_SPI_CS_TYPE_GPIO, ++}; ++ + struct ath79_spi_controller_data { +- unsigned gpio; ++ enum ath79_spi_cs_type cs_type; ++ unsigned cs_line; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -33,6 +33,8 @@ + #define ATH79_SPI_RRW_DELAY_FACTOR 12000 + #define MHZ (1000 * 1000) + ++#define ATH79_SPI_CS_LINE_MAX 2 ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -67,6 +69,7 @@ static void ath79_spi_chipselect(struct + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; ++ struct ath79_spi_controller_data *cdata = spi->controller_data; + + if (is_active) { + /* set initial clock polarity */ +@@ -78,20 +81,24 @@ static void ath79_spi_chipselect(struct + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- +- /* SPI is normally active-low */ +- gpio_set_value(cdata->gpio, cs_high); +- } else { ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: + if (cs_high) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; ++ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line); + else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ++ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line); + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); +- } ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: ++ /* SPI is normally active-low */ ++ if (gpio_cansleep(cdata->cs_line)) ++ gpio_set_value_cansleep(cdata->cs_line, cs_high); ++ else ++ gpio_set_value(cdata->cs_line, cs_high); ++ break; ++ } + } + + static void ath79_spi_enable(struct ath79_spi *sp) +@@ -118,24 +125,30 @@ static void ath79_spi_disable(struct ath + static int ath79_spi_setup_cs(struct spi_device *spi) + { + struct ath79_spi_controller_data *cdata; ++ unsigned long flags; + int status; + + cdata = spi->controller_data; +- if (spi->chip_select && !cdata) ++ if (!cdata) + return -EINVAL; + + status = 0; +- if (spi->chip_select) { +- unsigned long flags; ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX) ++ status = -EINVAL; ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: + flags = GPIOF_DIR_OUT; + if (spi->mode & SPI_CS_HIGH) + flags |= GPIOF_INIT_LOW; + else + flags |= GPIOF_INIT_HIGH; + +- status = gpio_request_one(cdata->gpio, flags, ++ status = gpio_request_one(cdata->cs_line, flags, + dev_name(&spi->dev)); ++ break; + } + + return status; +@@ -143,9 +156,19 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- gpio_free(cdata->gpio); ++ struct ath79_spi_controller_data *cdata; ++ ++ cdata = spi->controller_data; ++ if (!cdata) ++ return; ++ ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ /* nothing to do */ ++ break; ++ case ATH79_SPI_CS_TYPE_GPIO: ++ gpio_free(cdata->cs_line); ++ break; + } + } + +@@ -210,6 +233,10 @@ static int ath79_spi_probe(struct platfo + unsigned long rate; + int ret; + ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; ++ + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); +@@ -219,15 +246,11 @@ static int ath79_spi_probe(struct platfo + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + +- pdata = dev_get_platdata(&pdev->dev); +- + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; +- if (pdata) { +- master->bus_num = pdata->bus_num; +- master->num_chipselect = pdata->num_chipselect; +- } ++ master->bus_num = pdata->bus_num; ++ master->num_chipselect = pdata->num_chipselect; + + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch b/target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch new file mode 100644 index 0000000..d925f92 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch @@ -0,0 +1,28 @@ +--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h ++++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +@@ -36,6 +36,7 @@ + #define cpu_has_mdmx 0 + #define cpu_has_mips3d 0 + #define cpu_has_smartmips 0 ++#define cpu_has_rixi 0 + + #define cpu_has_mips32r1 1 + #define cpu_has_mips32r2 1 +@@ -43,6 +44,7 @@ + #define cpu_has_mips64r2 0 + + #define cpu_has_mipsmt 0 ++#define cpu_has_userlocal 0 + + #define cpu_has_64bits 0 + #define cpu_has_64bit_zero_reg 0 +@@ -51,5 +53,9 @@ + + #define cpu_dcache_line_size() 32 + #define cpu_icache_line_size() 32 ++#define cpu_has_vtag_icache 0 ++#define cpu_has_dc_aliases 1 ++#define cpu_has_ic_fills_f_dc 0 ++#define cpu_has_pindexed_dcache 0 + + #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch b/target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch new file mode 100644 index 0000000..0bc64b7 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/include/asm/mips_machine.h ++++ b/arch/mips/include/asm/mips_machine.h +@@ -36,6 +36,18 @@ static struct mips_machine machine_##_ty + .mach_setup = _setup, \ + }; + ++#define MIPS_MACHINE_NONAME(_type, _id, _setup) \ ++static const char machine_id_##_type[] __initconst \ ++ __aligned(1) = _id; \ ++static struct mips_machine machine_##_type \ ++ __used __section(.mips.machines.init) = \ ++{ \ ++ .mach_type = _type, \ ++ .mach_id = machine_id_##_type, \ ++ .mach_name = NULL, \ ++ .mach_setup = _setup, \ ++}; ++ + extern long __mips_machines_start; + extern long __mips_machines_end; + diff --git a/target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch b/target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch new file mode 100644 index 0000000..d23edf8 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch @@ -0,0 +1,124 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -241,6 +241,9 @@ config LZMA_COMPRESS + config LZMA_DECOMPRESS + tristate + ++config RLE_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -101,6 +101,7 @@ obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ + obj-$(CONFIG_LZMA_COMPRESS) += lzma/ + obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ ++obj-$(CONFIG_RLE_DECOMPRESS) += rle.o + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/include/linux/rle.h +@@ -0,0 +1,18 @@ ++#ifndef _RLE_H_ ++#define _RLE_H_ ++ ++#ifdef CONFIG_RLE_DECOMPRESS ++int rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done); ++#else ++static inline int ++rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_RLE_DECOMPRESS */ ++ ++#endif /* _RLE_H_ */ +--- /dev/null ++++ b/lib/rle.c +@@ -0,0 +1,78 @@ ++/* ++ * RLE decoding routine ++ * ++ * Copyright (C) 2012 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++int rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done) ++{ ++ size_t srcpos, dstpos; ++ int ret; ++ ++ srcpos = 0; ++ dstpos = 0; ++ ret = -EINVAL; ++ ++ /* sanity checks */ ++ if (!src || !srclen || !dst || !dstlen) ++ goto out; ++ ++ while (1) { ++ char count; ++ ++ if (srcpos >= srclen) ++ break; ++ ++ count = (char) src[srcpos++]; ++ if (count == 0) { ++ ret = 0; ++ break; ++ } ++ ++ if (count > 0) { ++ unsigned char c; ++ ++ if (srcpos >= srclen) ++ break; ++ ++ c = src[srcpos++]; ++ ++ while (count--) { ++ if (dstpos >= dstlen) ++ break; ++ ++ dst[dstpos++] = c; ++ } ++ } else { ++ count *= -1; ++ ++ while (count--) { ++ if (srcpos >= srclen) ++ break; ++ if (dstpos >= dstlen) ++ break; ++ dst[dstpos++] = src[srcpos++]; ++ } ++ } ++ } ++ ++out: ++ if (src_done) ++ *src_done = srcpos; ++ if (dst_done) ++ *dst_done = dstpos; ++ ++ return ret; ++} ++ ++EXPORT_SYMBOL_GPL(rle_decode); diff --git a/target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch b/target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch new file mode 100644 index 0000000..db7b3ca --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch @@ -0,0 +1,94 @@ +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -31,6 +31,66 @@ struct physmap_flash_info { + int vpp_refcnt; + }; + ++static struct platform_device *physmap_map2pdev(struct map_info *map) ++{ ++ return (struct platform_device *) map->map_priv_1; ++} ++ ++static void physmap_lock(struct map_info *map) ++{ ++ struct platform_device *pdev; ++ struct physmap_flash_data *physmap_data; ++ ++ pdev = physmap_map2pdev(map); ++ physmap_data = pdev->dev.platform_data; ++ physmap_data->lock(pdev); ++} ++ ++static void physmap_unlock(struct map_info *map) ++{ ++ struct platform_device *pdev; ++ struct physmap_flash_data *physmap_data; ++ ++ pdev = physmap_map2pdev(map); ++ physmap_data = pdev->dev.platform_data; ++ physmap_data->unlock(pdev); ++} ++ ++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs) ++{ ++ map_word ret; ++ ++ physmap_lock(map); ++ ret = inline_map_read(map, ofs); ++ physmap_unlock(map); ++ ++ return ret; ++} ++ ++static void physmap_flash_write_lock(struct map_info *map, map_word d, ++ unsigned long ofs) ++{ ++ physmap_lock(map); ++ inline_map_write(map, d, ofs); ++ physmap_unlock(map); ++} ++ ++static void physmap_flash_copy_from_lock(struct map_info *map, void *to, ++ unsigned long from, ssize_t len) ++{ ++ physmap_lock(map); ++ inline_map_copy_from(map, to, from, len); ++ physmap_unlock(map); ++} ++ ++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to, ++ const void *from, ssize_t len) ++{ ++ physmap_lock(map); ++ inline_map_copy_to(map, to, from, len); ++ physmap_unlock(map); ++} ++ + static int physmap_flash_remove(struct platform_device *dev) + { + struct physmap_flash_info *info; +@@ -153,6 +213,13 @@ static int physmap_flash_probe(struct pl + + simple_map_init(&info->map[i]); + ++ if (physmap_data->lock && physmap_data->unlock) { ++ info->map[i].read = physmap_flash_read_lock; ++ info->map[i].write = physmap_flash_write_lock; ++ info->map[i].copy_from = physmap_flash_copy_from_lock; ++ info->map[i].copy_to = physmap_flash_copy_to_lock; ++ } ++ + probe_type = rom_probe_types; + if (physmap_data->probe_type == NULL) { + for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++) +--- a/include/linux/mtd/physmap.h ++++ b/include/linux/mtd/physmap.h +@@ -25,6 +25,8 @@ struct physmap_flash_data { + unsigned int width; + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); ++ void (*lock)(struct platform_device *); ++ void (*unlock)(struct platform_device *); + void (*set_vpp)(struct platform_device *, int); + unsigned int nr_parts; + unsigned int pfow_base; diff --git a/target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch new file mode 100644 index 0000000..0d483ab --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch @@ -0,0 +1,29 @@ +--- a/drivers/mtd/chips/jedec_probe.c ++++ b/drivers/mtd/chips/jedec_probe.c +@@ -148,6 +148,7 @@ + #define SST39LF160 0x2782 + #define SST39VF1601 0x234b + #define SST39VF3201 0x235b ++#define SST39VF6401B 0x236d + #define SST39WF1601 0x274b + #define SST39WF1602 0x274a + #define SST39LF512 0x00D4 +@@ -1569,6 +1570,18 @@ static const struct amd_flash_info jedec + ERASEINFO(0x10000,64), + } + }, { ++ .mfr_id = CFI_MFR_SST, ++ .dev_id = SST39VF6401B, ++ .name = "SST 39VF6401B", ++ .devtypes = CFI_DEVICETYPE_X16, ++ .uaddr = MTD_UADDR_0xAAAA_0x5555, ++ .dev_size = SIZE_8MiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x10000,128) ++ } ++ }, { + .mfr_id = CFI_MFR_ST, + .dev_id = M29F800AB, + .name = "ST M29F800AB", diff --git a/target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch new file mode 100644 index 0000000..1ccce4e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch @@ -0,0 +1,69 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1632,8 +1632,8 @@ static int __xipram do_write_oneword(str + break; + } + +- if (chip_ready(map, adr)) +- break; ++ if (chip_good(map, adr, datum)) ++ goto enable_xip; + + /* Latency issues. Drop the lock, wait a while and retry */ + UDELAY(map, chip, adr, 1); +@@ -1649,6 +1649,8 @@ static int __xipram do_write_oneword(str + + ret = -EIO; + } ++ ++ enable_xip: + xip_enable(map, chip, adr); + op_done: + if (mode == FL_OTP_WRITE) +@@ -2227,7 +2229,6 @@ static int cfi_amdstd_panic_write(struct + return 0; + } + +- + /* + * Handle devices with one erase region, that only implement + * the chip erase command. +@@ -2291,8 +2292,8 @@ static int __xipram do_erase_chip(struct + chip->erase_suspended = 0; + } + +- if (chip_ready(map, adr)) +- break; ++ if (chip_good(map, adr, map_word_ff(map))) ++ goto op_done; + + if (time_after(jiffies, timeo)) { + printk(KERN_WARNING "MTD %s(): software timeout\n", +@@ -2312,6 +2313,7 @@ static int __xipram do_erase_chip(struct + ret = -EIO; + } + ++ op_done: + chip->state = FL_READY; + xip_enable(map, chip, adr); + DISABLE_VPP(map); +@@ -2380,9 +2382,9 @@ static int __xipram do_erase_oneblock(st + chip->erase_suspended = 0; + } + +- if (chip_ready(map, adr)) { ++ if (chip_good(map, adr, map_word_ff(map))) { + xip_enable(map, chip, adr); +- break; ++ goto op_done; + } + + if (time_after(jiffies, timeo)) { +@@ -2404,6 +2406,7 @@ static int __xipram do_erase_oneblock(st + ret = -EIO; + } + ++ op_done: + chip->state = FL_READY; + DISABLE_VPP(map); + put_chip(map, chip, adr); diff --git a/target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch b/target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch new file mode 100644 index 0000000..f4dbb92 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -184,6 +184,12 @@ config MTD_BCM47XX_PARTS + This provides partitions parser for devices based on BCM47xx + boards. + ++config MTD_CYBERTAN_PARTS ++ tristate "Cybertan partitioning support" ++ depends on ATH79 ++ ---help--- ++ Cybertan partitioning support ++ + config MTD_MYLOADER_PARTS + tristate "MyLoader partition parsing" + depends on ADM5120 || ATH25 || ATH79 +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch b/target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch new file mode 100644 index 0000000..11a9beb --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -206,6 +206,12 @@ config MTD_MYLOADER_PARTS + You will still need the parsing functions to be called by the driver + for your particular device. It won't happen automatically. + ++config MTD_TPLINK_PARTS ++ tristate "TP-Link AR7XXX/AR9XXX partitioning support" ++ depends on ATH79 ++ ---help--- ++ TBD. ++ + comment "User Modules And Translation Layers" + + # +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o + obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o + + # 'Users' - code which presents functionality to userspace. diff --git a/target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch new file mode 100644 index 0000000..bdfa887 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -234,7 +234,9 @@ static int m25p_probe(struct spi_device + + ppdata.of_node = spi->dev.of_node; + +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ return mtd_device_parse_register(&flash->mtd, ++ data ? data->part_probes : NULL, ++ &ppdata, + data ? data->parts : NULL, + data ? data->nr_parts : 0); + } +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -24,6 +24,7 @@ struct flash_platform_data { + unsigned int nr_parts; + + char *type; ++ const char **part_probes; + + /* we'll likely add more ... use JEDEC IDs, etc */ + }; diff --git a/target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch b/target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch new file mode 100644 index 0000000..cd41e7c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch @@ -0,0 +1,44 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; + while (mtd_block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; +@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; + + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); +@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; diff --git a/target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch new file mode 100644 index 0000000..408086f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -530,4 +530,8 @@ config MTD_NAND_HISI504 + help + Enables support for NAND controller on Hisilicon SoC Hip04. + ++config MTD_NAND_RB4XX ++ tristate "NAND flash driver for RouterBoard 4xx series" ++ depends on MTD_NAND && ATH79_MACH_RB4XX ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27 + obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch b/target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch new file mode 100644 index 0000000..666f7d2 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -534,4 +534,8 @@ config MTD_NAND_RB4XX + tristate "NAND flash driver for RouterBoard 4xx series" + depends on MTD_NAND && ATH79_MACH_RB4XX + ++config MTD_NAND_RB750 ++ tristate "NAND flash driver for the RouterBoard 750" ++ depends on MTD_NAND && ATH79_MACH_RB750 ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o + obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o ++obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch new file mode 100644 index 0000000..39c5478 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch @@ -0,0 +1,61 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -40,7 +40,7 @@ + #include + + #define AMD_BOOTLOC_BUG +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + #define MAX_WORD_RETRIES 3 + +@@ -51,7 +51,9 @@ + + static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); + static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#if !FORCE_WORD_WRITE + static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#endif + static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); + static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); + static void cfi_amdstd_sync (struct mtd_info *); +@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m + } + #endif + ++#if !FORCE_WORD_WRITE + static void fixup_use_write_buffers(struct mtd_info *mtd) + { + struct map_info *map = mtd->priv; +@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru + mtd->_write = cfi_amdstd_write_buffers; + } + } ++#endif /* !FORCE_WORD_WRITE */ + + /* Atmel chips don't use the same PRI format as AMD chips */ + static void fixup_convert_atmel_pri(struct mtd_info *mtd) +@@ -1791,6 +1795,7 @@ static int cfi_amdstd_write_words(struct + /* + * FIXME: interleaved mode not tested, and probably not supported! + */ ++#if !FORCE_WORD_WRITE + static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, + unsigned long adr, const u_char *buf, + int len) +@@ -1919,7 +1924,6 @@ static int __xipram do_write_buffer(stru + return ret; + } + +- + static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) + { +@@ -1994,6 +1998,7 @@ static int cfi_amdstd_write_buffers(stru + + return 0; + } ++#endif /* !FORCE_WORD_WRITE */ + + /* + * Wait for the flash chip to become ready to write data diff --git a/target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch new file mode 100644 index 0000000..7cade53 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch @@ -0,0 +1,10 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -232,6 +232,7 @@ static int m25p_probe(struct spi_device + if (ret) + return ret; + ++ memset(&ppdata, '\0', sizeof(ppdata)); + ppdata.of_node = spi->dev.of_node; + + return mtd_device_parse_register(&flash->mtd, diff --git a/target/linux/ar71xx/patches-4.1/413-mtd-ar934x-nand-driver.patch b/target/linux/ar71xx/patches-4.1/413-mtd-ar934x-nand-driver.patch new file mode 100644 index 0000000..44fdba4 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/413-mtd-ar934x-nand-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -538,4 +538,12 @@ config MTD_NAND_RB750 + tristate "NAND flash driver for the RouterBoard 750" + depends on MTD_NAND && ATH79_MACH_RB750 + ++config MTD_NAND_AR934X ++ tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs" ++ depends on (SOC_AR934X || SOC_QCA955X) ++ ++config MTD_NAND_AR934X_HW_ECC ++ bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)" ++ depends on MTD_NAND_AR934X ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams- + obj-$(CONFIG_MTD_NAND_DENALI) += denali.o + obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o + obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o ++obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nfc.o + obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o + obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o + obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o diff --git a/target/linux/ar71xx/patches-4.1/414-mtd-rb91x-nand-driver.patch b/target/linux/ar71xx/patches-4.1/414-mtd-rb91x-nand-driver.patch new file mode 100644 index 0000000..bad95c1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/414-mtd-rb91x-nand-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -538,6 +538,10 @@ config MTD_NAND_RB750 + tristate "NAND flash driver for the RouterBoard 750" + depends on MTD_NAND && ATH79_MACH_RB750 + ++config MTD_NAND_RB91X ++ tristate "NAND flash driver for the RouterBOARD 91x series" ++ depends on MTD_NAND && ATH79_MACH_RB91X ++ + config MTD_NAND_AR934X + tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs" + depends on (SOC_AR934X || SOC_QCA955X) +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nan + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o + obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o ++obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.1/420-net-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-4.1/420-net-ar71xx_mac_driver.patch new file mode 100644 index 0000000..5da869a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/420-net-ar71xx_mac_driver.patch @@ -0,0 +1,28 @@ +--- a/drivers/net/ethernet/atheros/Kconfig ++++ b/drivers/net/ethernet/atheros/Kconfig +@@ -5,7 +5,7 @@ + config NET_VENDOR_ATHEROS + bool "Atheros devices" + default y +- depends on PCI ++ depends on (PCI || ATH79) + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from +@@ -80,4 +80,6 @@ config ALX + To compile this driver as a module, choose M here. The module + will be called alx. + ++source drivers/net/ethernet/atheros/ag71xx/Kconfig ++ + endif # NET_VENDOR_ATHEROS +--- a/drivers/net/ethernet/atheros/Makefile ++++ b/drivers/net/ethernet/atheros/Makefile +@@ -2,6 +2,7 @@ + # Makefile for the Atheros network device drivers. + # + ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_ATL1) += atlx/ + obj-$(CONFIG_ATL2) += atlx/ + obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ar71xx/patches-4.1/422-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-4.1/422-dsa-trailer-tag-validation-fix.patch new file mode 100644 index 0000000..eeeeaf5 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/422-dsa-trailer-tag-validation-fix.patch @@ -0,0 +1,11 @@ +--- a/net/dsa/tag_trailer.c ++++ b/net/dsa/tag_trailer.c +@@ -84,7 +84,7 @@ static int trailer_rcv(struct sk_buff *s + + trailer = skb_tail_pointer(skb) - 4; + if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || +- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00) ++ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00) + goto out_drop; + + source_port = trailer[1] & 7; diff --git a/target/linux/ar71xx/patches-4.1/423-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-4.1/423-dsa-add-88e6063-driver.patch new file mode 100644 index 0000000..1348cd9 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/423-dsa-add-88e6063-driver.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -13,6 +13,13 @@ config NET_DSA_MV88E6060 + This enables support for the Marvell 88E6060 ethernet switch + chip. + ++config NET_DSA_MV88E6063 ++ bool "Marvell 88E6063 ethernet switch chip support" ++ select NET_DSA_TAG_TRAILER ++ ---help--- ++ This enables support for the Marvell 88E6063 ethernet switch ++ chip ++ + config NET_DSA_MV88E6XXX_NEED_PPU + bool + default n +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -1,4 +1,5 @@ + obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o ++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o + obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o + mv88e6xxx_drv-y += mv88e6xxx.o + ifdef CONFIG_NET_DSA_MV88E6123_61_65 diff --git a/target/linux/ar71xx/patches-4.1/425-net-phy-at803x-allow-to-configure-via-pdata.patch b/target/linux/ar71xx/patches-4.1/425-net-phy-at803x-allow-to-configure-via-pdata.patch new file mode 100644 index 0000000..53abcc3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/425-net-phy-at803x-allow-to-configure-via-pdata.patch @@ -0,0 +1,180 @@ +--- a/drivers/net/phy/at803x.c ++++ b/drivers/net/phy/at803x.c +@@ -12,12 +12,14 @@ + */ + + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #define AT803X_INTR_ENABLE 0x12 + #define AT803X_INTR_STATUS 0x13 +@@ -34,8 +36,16 @@ + #define AT803X_INER 0x0012 + #define AT803X_INER_INIT 0xec00 + #define AT803X_INSR 0x0013 ++ ++#define AT803X_PCS_SMART_EEE_CTRL3 0x805D ++#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3 ++#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12 ++#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8) ++ + #define AT803X_DEBUG_ADDR 0x1D + #define AT803X_DEBUG_DATA 0x1E ++#define AT803X_DBG0_REG 0x00 ++#define AT803X_DEBUG_RGMII_RX_CLK_DLY BIT(8) + #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05 + #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8) + +@@ -50,6 +60,7 @@ MODULE_LICENSE("GPL"); + struct at803x_priv { + bool phy_reset:1; + struct gpio_desc *gpiod_reset; ++ int prev_speed; + }; + + struct at803x_context { +@@ -61,6 +72,43 @@ struct at803x_context { + u16 led_control; + }; + ++static u16 ++at803x_dbg_reg_rmw(struct phy_device *phydev, u16 reg, u16 clear, u16 set) ++{ ++ struct mii_bus *bus = phydev->bus; ++ int val; ++ ++ mutex_lock(&bus->mdio_lock); ++ ++ bus->write(bus, phydev->addr, AT803X_DEBUG_ADDR, reg); ++ val = bus->read(bus, phydev->addr, AT803X_DEBUG_DATA); ++ if (val < 0) { ++ val = 0xffff; ++ goto out; ++ } ++ ++ val &= ~clear; ++ val |= set; ++ bus->write(bus, phydev->addr, AT803X_DEBUG_DATA, val); ++ ++out: ++ mutex_unlock(&bus->mdio_lock); ++ return val; ++} ++ ++static inline void ++at803x_dbg_reg_set(struct phy_device *phydev, u16 reg, u16 set) ++{ ++ at803x_dbg_reg_rmw(phydev, reg, 0, set); ++} ++ ++static inline void ++at803x_dbg_reg_clr(struct phy_device *phydev, u16 reg, u16 clear) ++{ ++ at803x_dbg_reg_rmw(phydev, reg, clear, 0); ++} ++ ++ + /* save relevant PHY registers to private copy */ + static void at803x_context_save(struct phy_device *phydev, + struct at803x_context *context) +@@ -209,8 +257,16 @@ static int at803x_probe(struct phy_devic + return 0; + } + ++static void at803x_disable_smarteee(struct phy_device *phydev) ++{ ++ phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3, ++ 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT); ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); ++} ++ + static int at803x_config_init(struct phy_device *phydev) + { ++ struct at803x_platform_data *pdata; + int ret; + + ret = genphy_config_init(phydev); +@@ -228,6 +284,26 @@ static int at803x_config_init(struct phy + return ret; + } + ++ pdata = dev_get_platdata(&phydev->dev); ++ if (pdata) { ++ if (pdata->disable_smarteee) ++ at803x_disable_smarteee(phydev); ++ ++ if (pdata->enable_rgmii_rx_delay) ++ at803x_dbg_reg_set(phydev, AT803X_DBG0_REG, ++ AT803X_DEBUG_RGMII_RX_CLK_DLY); ++ else ++ at803x_dbg_reg_clr(phydev, AT803X_DBG0_REG, ++ AT803X_DEBUG_RGMII_RX_CLK_DLY); ++ ++ if (pdata->enable_rgmii_tx_delay) ++ at803x_dbg_reg_set(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ else ++ at803x_dbg_reg_clr(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ } ++ + return 0; + } + +@@ -259,6 +335,8 @@ static int at803x_config_intr(struct phy + static void at803x_link_change_notify(struct phy_device *phydev) + { + struct at803x_priv *priv = phydev->priv; ++ struct at803x_platform_data *pdata; ++ pdata = dev_get_platdata(&phydev->dev); + + /* + * Conduct a hardware reset for AT8030 every time a link loss is +@@ -289,6 +367,26 @@ static void at803x_link_change_notify(st + priv->phy_reset = false; + } + } ++ if (pdata && pdata->fixup_rgmii_tx_delay && ++ phydev->speed != priv->prev_speed) { ++ switch (phydev->speed) { ++ case SPEED_10: ++ case SPEED_100: ++ at803x_dbg_reg_set(phydev, ++ AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ break; ++ case SPEED_1000: ++ at803x_dbg_reg_clr(phydev, ++ AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ break; ++ default: ++ break; ++ } ++ ++ priv->prev_speed = phydev->speed; ++ } + } + + static struct phy_driver at803x_driver[] = { +--- /dev/null ++++ b/include/linux/platform_data/phy-at803x.h +@@ -0,0 +1,11 @@ ++#ifndef _PHY_AT803X_PDATA_H ++#define _PHY_AT803X_PDATA_H ++ ++struct at803x_platform_data { ++ int disable_smarteee:1; ++ int enable_rgmii_tx_delay:1; ++ int enable_rgmii_rx_delay:1; ++ int fixup_rgmii_tx_delay:1; ++}; ++ ++#endif /* _PHY_AT803X_PDATA_H */ diff --git a/target/linux/ar71xx/patches-4.1/430-drivers-link-spi-before-mtd.patch b/target/linux/ar71xx/patches-4.1/430-drivers-link-spi-before-mtd.patch new file mode 100644 index 0000000..02c7064 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/430-drivers-link-spi-before-mtd.patch @@ -0,0 +1,12 @@ +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -71,8 +71,8 @@ obj-$(CONFIG_IDE) += ide/ + obj-$(CONFIG_SCSI) += scsi/ + obj-$(CONFIG_ATA) += ata/ + obj-$(CONFIG_TARGET_CORE) += target/ +-obj-$(CONFIG_MTD) += mtd/ + obj-$(CONFIG_SPI) += spi/ ++obj-$(CONFIG_MTD) += mtd/ + obj-$(CONFIG_SPMI) += spmi/ + obj-y += hsi/ + obj-y += net/ diff --git a/target/linux/ar71xx/patches-4.1/431-spi-add-various-flags.patch b/target/linux/ar71xx/patches-4.1/431-spi-add-various-flags.patch new file mode 100644 index 0000000..8b25c93 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/431-spi-add-various-flags.patch @@ -0,0 +1,19 @@ +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -618,6 +618,8 @@ struct spi_transfer { + unsigned cs_change:1; + unsigned tx_nbits:3; + unsigned rx_nbits:3; ++ unsigned verify:1; ++ unsigned fast_write:1; + #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ + #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ + #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ +@@ -663,6 +665,7 @@ struct spi_message { + struct spi_device *spi; + + unsigned is_dma_mapped:1; ++ unsigned fast_read:1; + + /* REVISIT: we might want a flag affecting the behavior of the + * last transfer ... allowing things like "read 16 bit length L" diff --git a/target/linux/ar71xx/patches-4.1/432-spi-rb4xx-spi-driver.patch b/target/linux/ar71xx/patches-4.1/432-spi-rb4xx-spi-driver.patch new file mode 100644 index 0000000..2870e19 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/432-spi-rb4xx-spi-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -457,6 +457,12 @@ config SPI_QUP + This driver can also be built as a module. If so, the module + will be called spi_qup. + ++config SPI_RB4XX ++ tristate "Mikrotik RB4XX SPI master" ++ depends on SPI_MASTER && ATH79_MACH_RB4XX ++ help ++ SPI controller driver for the Mikrotik RB4xx series boards. ++ + config SPI_S3C24XX + tristate "Samsung S3C24XX series SPI" + depends on ARCH_S3C24XX +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -65,6 +65,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_ + spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o + obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o + obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o ++obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o + obj-$(CONFIG_SPI_QUP) += spi-qup.o + obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o + obj-$(CONFIG_SPI_RSPI) += spi-rspi.o diff --git a/target/linux/ar71xx/patches-4.1/433-spi-rb4xx-cpld-driver.patch b/target/linux/ar71xx/patches-4.1/433-spi-rb4xx-cpld-driver.patch new file mode 100644 index 0000000..ccce5b1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/433-spi-rb4xx-cpld-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -676,6 +676,13 @@ config SPI_TLE62X0 + sysfs interface, with each line presented as a kind of GPIO + exposing both switch control and diagnostic feedback. + ++config SPI_RB4XX_CPLD ++ tristate "MikroTik RB4XX CPLD driver" ++ depends on ATH79_MACH_RB4XX ++ help ++ SPI driver for the Xilinx CPLD chip present on the ++ MikroTik RB4xx boards. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -66,6 +66,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_ + obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o + obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o ++obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o + obj-$(CONFIG_SPI_QUP) += spi-qup.o + obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o + obj-$(CONFIG_SPI_RSPI) += spi-rspi.o diff --git a/target/linux/ar71xx/patches-4.1/434-spi-ap83_spi_controller.patch b/target/linux/ar71xx/patches-4.1/434-spi-ap83_spi_controller.patch new file mode 100644 index 0000000..a67e808 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/434-spi-ap83_spi_controller.patch @@ -0,0 +1,27 @@ +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o + # SPI master controller drivers (bus) + obj-$(CONFIG_SPI_ALTERA) += spi-altera.o + obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o ++obj-$(CONFIG_SPI_AP83) += spi-ap83.o + obj-$(CONFIG_SPI_ATH79) += spi-ath79.o + obj-$(CONFIG_SPI_AU1550) += spi-au1550.o + obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -59,6 +59,14 @@ config SPI_ALTERA + help + This is the driver for the Altera SPI Controller. + ++config SPI_AP83 ++ tristate "Atheros AP83 specific SPI Controller" ++ depends on SPI_MASTER && ATH79_MACH_AP83 ++ select SPI_BITBANG ++ help ++ This is a specific SPI controller driver for the Atheros AP83 ++ reference board. ++ + config SPI_ATH79 + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" + depends on ATH79 && GPIOLIB diff --git a/target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch b/target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch new file mode 100644 index 0000000..f860dfe --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch @@ -0,0 +1,24 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -691,6 +691,11 @@ config SPI_RB4XX_CPLD + SPI driver for the Xilinx CPLD chip present on the + MikroTik RB4xx boards. + ++config SPI_VSC7385 ++ tristate "Vitesse VSC7385 ethernet switch driver" ++ help ++ SPI driver for the Vitesse VSC7385 ethernet switch. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -90,6 +90,7 @@ obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi- + obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o + obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o + obj-$(CONFIG_SPI_TXX9) += spi-txx9.o ++obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o + obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o + obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o diff --git a/target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch new file mode 100644 index 0000000..77ed60e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -534,6 +534,13 @@ config LEDS_PM8941_WLED + This option enables support for the 'White' LED block + on Qualcomm PM8941 PMICs. + ++config LEDS_WNDR3700_USB ++ tristate "NETGEAR WNDR3700 USB LED driver" ++ depends on LEDS_CLASS && ATH79_MACH_WNDR3700 ++ help ++ This option enables support for the USB LED found on the ++ NETGEAR WNDR3700 board. ++ + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -43,6 +43,7 @@ obj-$(CONFIG_LEDS_DA9052) += leds-da905 + obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o + obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o + obj-$(CONFIG_LEDS_PWM) += leds-pwm.o ++obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o + obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o + obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o + obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o diff --git a/target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch b/target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch new file mode 100644 index 0000000..55ea26b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -541,6 +541,10 @@ config LEDS_WNDR3700_USB + This option enables support for the USB LED found on the + NETGEAR WNDR3700 board. + ++config LEDS_RB750 ++ tristate "LED driver for the Mikrotik RouterBOARD 750" ++ depends on LEDS_CLASS && ATH79_MACH_RB750 ++ + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359 + obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o + obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o + obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o ++obj-$(CONFIG_LEDS_RB750) += leds-rb750.o + obj-$(CONFIG_LEDS_NS2) += leds-ns2.o + obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o + obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o diff --git a/target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch new file mode 100644 index 0000000..30b1c65 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -988,4 +988,12 @@ config GPIO_VIPERBOARD + + endmenu + ++comment "Other GPIO expanders" ++ ++config GPIO_NXP_74HC153 ++ tristate "NXP 74HC153 Dual 4-input multiplexer" ++ help ++ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This ++ provides a GPIO interface supporting input mode only. ++ + endif +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -64,6 +64,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2 + obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o ++obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o + obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o + obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o + obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o diff --git a/target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch b/target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch new file mode 100644 index 0000000..95e5b5a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch @@ -0,0 +1,111 @@ +--- a/drivers/gpio/gpio-74x164.c ++++ b/drivers/gpio/gpio-74x164.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -107,8 +108,18 @@ static int gen_74x164_direction_output(s + static int gen_74x164_probe(struct spi_device *spi) + { + struct gen_74x164_chip *chip; ++ struct gen_74x164_chip_platform_data *pdata; ++ struct device_node *np; + int ret; + ++ pdata = spi->dev.platform_data; ++ np = spi->dev.of_node; ++ ++ if (!np && !pdata) { ++ dev_err(&spi->dev, "No configuration data available.\n"); ++ return -EINVAL; ++ } ++ + /* + * bits_per_word cannot be configured in platform data + */ +@@ -130,18 +141,28 @@ static int gen_74x164_probe(struct spi_d + chip->gpio_chip.set = gen_74x164_set_value; + chip->gpio_chip.base = -1; + +- if (of_property_read_u32(spi->dev.of_node, "registers-number", +- &chip->registers)) { +- dev_err(&spi->dev, +- "Missing registers-number property in the DT.\n"); +- return -EINVAL; ++ if (np) { ++ if (of_property_read_u32(spi->dev.of_node, "registers-number", &chip->registers)) { ++ dev_err(&spi->dev, "Missing registers-number property in the DT.\n"); ++ ret = -EINVAL; ++ goto exit_destroy; ++ } ++ } else if (pdata) { ++ chip->gpio_chip.base = pdata->base; ++ chip->registers = pdata->num_registers; + } + ++ if (!chip->registers) ++ chip->registers = 1; ++ + chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; + chip->buffer = devm_kzalloc(&spi->dev, chip->registers, GFP_KERNEL); + if (!chip->buffer) + return -ENOMEM; + ++ if (pdata && pdata->init_data) ++ memcpy(chip->buffer, pdata->init_data, chip->registers); ++ + chip->gpio_chip.can_sleep = true; + chip->gpio_chip.dev = &spi->dev; + chip->gpio_chip.owner = THIS_MODULE; +@@ -174,17 +195,19 @@ static int gen_74x164_remove(struct spi_ + return 0; + } + ++#ifdef CONFIG_OF + static const struct of_device_id gen_74x164_dt_ids[] = { + { .compatible = "fairchild,74hc595" }, + {}, + }; + MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids); ++#endif /* CONFIG_OF */ + + static struct spi_driver gen_74x164_driver = { + .driver = { + .name = "74x164", + .owner = THIS_MODULE, +- .of_match_table = gen_74x164_dt_ids, ++ .of_match_table = of_match_ptr(gen_74x164_dt_ids), + }, + .probe = gen_74x164_probe, + .remove = gen_74x164_remove, +--- /dev/null ++++ b/include/linux/spi/74x164.h +@@ -0,0 +1,13 @@ ++#ifndef LINUX_SPI_74X164_H ++#define LINUX_SPI_74X164_H ++ ++struct gen_74x164_chip_platform_data { ++ /* number assigned to the first GPIO */ ++ unsigned base; ++ /* number of chained registers */ ++ unsigned num_registers; ++ /* address of a buffer containing initial data */ ++ u8 *init_data; ++}; ++ ++#endif +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -941,7 +941,7 @@ menu "SPI GPIO expanders" + + config GPIO_74X164 + tristate "74x164 serial-in/parallel-out 8-bits shift register" +- depends on SPI_MASTER && OF ++ depends on SPI_MASTER + help + Driver for 74x164 compatible serial-in/parallel-out 8-outputs + shift registers. This driver can be used to provide access diff --git a/target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch b/target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch new file mode 100644 index 0000000..080a718 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch @@ -0,0 +1,22 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -996,4 +996,9 @@ config GPIO_NXP_74HC153 + Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This + provides a GPIO interface supporting input mode only. + ++config GPIO_LATCH ++ tristate "GPIO latch driver" ++ help ++ Say yes here to enable a GPIO latch driver. ++ + endif +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz + obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o + obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o + obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o ++obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o + obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o + obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o + obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o diff --git a/target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch b/target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch new file mode 100644 index 0000000..4f0de01 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch @@ -0,0 +1,28 @@ +--- a/drivers/spi/spi-bitbang.c ++++ b/drivers/spi/spi-bitbang.c +@@ -230,13 +230,14 @@ void spi_bitbang_cleanup(struct spi_devi + } + EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); + +-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) ++int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) + { + struct spi_bitbang_cs *cs = spi->controller_state; + unsigned nsecs = cs->nsecs; + + return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); + } ++EXPORT_SYMBOL_GPL(spi_bitbang_bufs); + + /*----------------------------------------------------------------------*/ + +--- a/include/linux/spi/spi_bitbang.h ++++ b/include/linux/spi/spi_bitbang.h +@@ -39,6 +39,7 @@ extern int spi_bitbang_setup(struct spi_ + extern void spi_bitbang_cleanup(struct spi_device *spi); + extern int spi_bitbang_setup_transfer(struct spi_device *spi, + struct spi_transfer *t); ++extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t); + + /* start or stop queue processing */ + extern int spi_bitbang_start(struct spi_bitbang *spi); diff --git a/target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch b/target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch new file mode 100644 index 0000000..ce1b69c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch @@ -0,0 +1,23 @@ +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -506,6 +506,12 @@ extern struct spi_master *spi_busnum_to_ + + /*---------------------------------------------------------------------------*/ + ++enum spi_transfer_type { ++ SPI_TRANSFER_GENERIC = 0, ++ SPI_TRANSFER_FLASH_READ_CMD, ++ SPI_TRANSFER_FLASH_READ_DATA, ++}; ++ + /* + * I/O INTERFACE between SPI controller and protocol drivers + * +@@ -626,6 +632,7 @@ struct spi_transfer { + u8 bits_per_word; + u16 delay_usecs; + u32 speed_hz; ++ enum spi_transfer_type type; + + struct list_head transfer_list; + }; diff --git a/target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch new file mode 100644 index 0000000..b011c28 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch @@ -0,0 +1,15 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -139,10 +139,12 @@ static int m25p80_read(struct spi_nor *n + flash->command[0] = nor->read_opcode; + m25p_addr2cmd(nor, from, flash->command); + ++ t[0].type = SPI_TRANSFER_FLASH_READ_CMD; + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(nor) + dummy; + spi_message_add_tail(&t[0], &m); + ++ t[1].type = SPI_TRANSFER_FLASH_READ_DATA; + t[1].rx_buf = buf; + t[1].rx_nbits = m25p80_rx_nbits(nor); + t[1].len = len; diff --git a/target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch new file mode 100644 index 0000000..0e0e28f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch @@ -0,0 +1,185 @@ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -35,6 +35,11 @@ + + #define ATH79_SPI_CS_LINE_MAX 2 + ++enum ath79_spi_state { ++ ATH79_SPI_STATE_WAIT_CMD = 0, ++ ATH79_SPI_STATE_WAIT_READ, ++}; ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -42,6 +47,11 @@ struct ath79_spi { + void __iomem *base; + struct clk *clk; + unsigned rrw_delay; ++ ++ enum ath79_spi_state state; ++ u32 clk_div; ++ unsigned long read_addr; ++ unsigned long ahb_rate; + }; + + static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +@@ -109,9 +119,6 @@ static void ath79_spi_enable(struct ath7 + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); +- +- /* TODO: setup speed? */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + } + + static void ath79_spi_disable(struct ath79_spi *sp) +@@ -224,6 +231,110 @@ static u32 ath79_spi_txrx_mode0(struct s + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); + } + ++static int ath79_spi_do_read_flash_data(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++ ++ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len); ++ ++ /* enable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); ++ ++ /* restore IOC register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); ++ ++ return t->len; ++} ++ ++static int ath79_spi_do_read_flash_cmd(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ int len; ++ const u8 *p; ++ ++ sp->read_addr = 0; ++ ++ len = t->len - 1; ++ p = t->tx_buf; ++ ++ while (len--) { ++ p++; ++ sp->read_addr <<= 8; ++ sp->read_addr |= *p; ++ } ++ ++ return t->len; ++} ++ ++static bool ath79_spi_is_read_cmd(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ return t->type == SPI_TRANSFER_FLASH_READ_CMD; ++} ++ ++static bool ath79_spi_is_data_read(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ return t->type == SPI_TRANSFER_FLASH_READ_DATA; ++} ++ ++static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ int ret; ++ ++ switch (sp->state) { ++ case ATH79_SPI_STATE_WAIT_CMD: ++ if (ath79_spi_is_read_cmd(spi, t)) { ++ ret = ath79_spi_do_read_flash_cmd(spi, t); ++ sp->state = ATH79_SPI_STATE_WAIT_READ; ++ } else { ++ ret = spi_bitbang_bufs(spi, t); ++ } ++ break; ++ ++ case ATH79_SPI_STATE_WAIT_READ: ++ if (ath79_spi_is_data_read(spi, t)) { ++ ret = ath79_spi_do_read_flash_data(spi, t); ++ } else { ++ dev_warn(&spi->dev, "flash data read expected\n"); ++ ret = -EIO; ++ } ++ sp->state = ATH79_SPI_STATE_WAIT_CMD; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ return ret; ++} ++ ++static int ath79_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ struct ath79_spi_controller_data *cdata; ++ int ret; ++ ++ ret = spi_bitbang_setup_transfer(spi, t); ++ if (ret) ++ return ret; ++ ++ cdata = spi->controller_data; ++ if (cdata->is_flash) ++ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs; ++ else ++ sp->bitbang.txrx_bufs = spi_bitbang_bufs; ++ ++ return ret; ++} ++ + static int ath79_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -246,6 +357,8 @@ static int ath79_spi_probe(struct platfo + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + ++ sp->state = ATH79_SPI_STATE_WAIT_CMD; ++ + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; +@@ -255,7 +368,7 @@ static int ath79_spi_probe(struct platfo + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; +- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ sp->bitbang.setup_transfer = ath79_spi_setup_transfer; + sp->bitbang.flags = SPI_CS_HIGH; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -280,7 +393,8 @@ static int ath79_spi_probe(struct platfo + if (ret) + goto err_put_master; + +- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); ++ sp->ahb_rate = clk_get_rate(sp->clk); ++ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ); + if (!rate) { + ret = -EINVAL; + goto err_clk_disable; +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -24,6 +24,7 @@ enum ath79_spi_cs_type { + struct ath79_spi_controller_data { + enum ath79_spi_cs_type cs_type; + unsigned cs_line; ++ bool is_flash; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ diff --git a/target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch b/target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch new file mode 100644 index 0000000..65eb875 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -139,6 +139,9 @@ static int m25p80_read(struct spi_nor *n + flash->command[0] = nor->read_opcode; + m25p_addr2cmd(nor, from, flash->command); + ++ if (dummy == 1) ++ t[0].dummy = true; ++ + t[0].type = SPI_TRANSFER_FLASH_READ_CMD; + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(nor) + dummy; +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -260,6 +260,10 @@ static int ath79_spi_do_read_flash_cmd(s + sp->read_addr = 0; + + len = t->len - 1; ++ ++ if (t->dummy) ++ len -= 1; ++ + p = t->tx_buf; + + while (len--) { +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -633,6 +633,7 @@ struct spi_transfer { + u16 delay_usecs; + u32 speed_hz; + enum spi_transfer_type type; ++ bool dummy; + + struct list_head transfer_list; + }; diff --git a/target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch new file mode 100644 index 0000000..520c652 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch @@ -0,0 +1,111 @@ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2012 Gabor Juhos ++ * ++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H ++#define __ASM_MACH_ATH79_MANGLE_PORT_H ++ ++#ifdef CONFIG_PCI ++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); ++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); ++#else ++#define ath79_pci_swizzle_b(port) (port) ++#define ath79_pci_swizzle_w(port) (port) ++#endif ++ ++#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) ++#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) ++#define __swizzle_addr_l(port) (port) ++#define __swizzle_addr_q(port) (port) ++ ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) (x) ++# define __mem_ioswabw(a, x) cpu_to_le16(x) ++# define ioswabl(a, x) (x) ++# define __mem_ioswabl(a, x) cpu_to_le32(x) ++# define ioswabq(a, x) (x) ++# define __mem_ioswabq(a, x) cpu_to_le64(x) ++ ++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -13,6 +13,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st + static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; + static unsigned ath79_pci_nr_irqs __initdata; + ++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); ++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); ++ + static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { + { + .slot = 17, +@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id, + return pdev; + } + ++static inline bool ar71xx_is_pci_addr(unsigned long port) ++{ ++ unsigned long phys = CPHYSADDR(port); ++ ++ return (phys >= AR71XX_PCI_MEM_BASE && ++ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); ++} ++ ++static unsigned long ar71xx_pci_swizzle_b(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; ++} ++ ++static unsigned long ar71xx_pci_swizzle_w(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; ++} ++ ++unsigned long ath79_pci_swizzle_b(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_b) ++ return __ath79_pci_swizzle_b(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_b); ++ ++unsigned long ath79_pci_swizzle_w(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_w) ++ return __ath79_pci_swizzle_w(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_w); ++ + int __init ath79_register_pci(void) + { + struct platform_device *pdev = NULL; + + if (soc_is_ar71xx()) { + pdev = ath79_register_pci_ar71xx(); ++ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; ++ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; + } else if (soc_is_ar724x()) { + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, diff --git a/target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch b/target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch new file mode 100644 index 0000000..162510b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch @@ -0,0 +1,103 @@ +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -252,6 +252,37 @@ static int ehci_reset (struct ehci_hcd * + command |= CMD_RESET; + dbg_cmd (ehci, "reset", command); + ehci_writel(ehci, command, &ehci->regs->command); ++ ++ if (ehci->qca_force_host_mode) { ++ u32 usbmode; ++ ++ udelay(1000); ++ ++ usbmode = ehci_readl(ehci, &ehci->regs->usbmode); ++ usbmode |= USBMODE_CM_HC | (1 << 4); ++ ehci_writel(ehci, usbmode, &ehci->regs->usbmode); ++ ++ ehci_dbg(ehci, "forced host mode, usbmode: %08x\n", ++ ehci_readl(ehci, &ehci->regs->usbmode)); ++ } ++ ++ if (ehci->qca_force_16bit_ptw) { ++ u32 port_status; ++ ++ udelay(1000); ++ ++ /* enable 16-bit UTMI interface */ ++ port_status = ehci_readl(ehci, &ehci->regs->port_status[0]); ++ port_status |= BIT(28); ++ ehci_writel(ehci, port_status, &ehci->regs->port_status[0]); ++ ++ ehci_dbg(ehci, "16-bit UTMI interface enabled, status: %08x\n", ++ ehci_readl(ehci, &ehci->regs->port_status[0])); ++ } ++ ++ if (ehci->reset_notifier) ++ ehci->reset_notifier(ehci_to_hcd(ehci)); ++ + ehci->rh_state = EHCI_RH_HALTED; + ehci->next_statechange = jiffies; + retval = ehci_handshake(ehci, &ehci->regs->command, +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -227,6 +227,10 @@ struct ehci_hcd { /* one per controlle + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ + unsigned ignore_oc:1; ++ unsigned qca_force_host_mode:1; ++ unsigned qca_force_16bit_ptw:1; /* force 16 bit UTMI */ ++ ++ void (*reset_notifier)(struct usb_hcd *hcd); + + /* required for usb32 quirk */ + #define OHCI_CTRL_HCFS (3 << 6) +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -50,6 +50,8 @@ struct usb_ehci_pdata { + unsigned reset_on_resume:1; + unsigned dma_mask_64:1; + unsigned ignore_oc:1; ++ unsigned qca_force_host_mode:1; ++ unsigned qca_force_16bit_ptw:1; + + /* Turn on all power and clocks */ + int (*power_on)(struct platform_device *pdev); +@@ -59,6 +61,7 @@ struct usb_ehci_pdata { + * turn off everything else */ + void (*power_suspend)(struct platform_device *pdev); + int (*pre_setup)(struct usb_hcd *hcd); ++ void (*reset_notifier)(struct platform_device *pdev); + }; + + #endif /* __USB_CORE_EHCI_PDRIVER_H */ +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -49,6 +49,14 @@ struct ehci_platform_priv { + + static const char hcd_name[] = "ehci-platform"; + ++static void ehci_platform_reset_notifier(struct usb_hcd *hcd) ++{ ++ struct platform_device *pdev = to_platform_device(hcd->self.controller); ++ struct usb_ehci_pdata *pdata = pdev->dev.platform_data; ++ ++ pdata->reset_notifier(pdev); ++} ++ + static int ehci_platform_reset(struct usb_hcd *hcd) + { + struct platform_device *pdev = to_platform_device(hcd->self.controller); +@@ -266,6 +274,13 @@ static int ehci_platform_probe(struct pl + ehci->big_endian_mmio = 1; + if (pdata->ignore_oc) + ehci->ignore_oc = 1; ++ if (pdata->qca_force_host_mode) ++ ehci->qca_force_host_mode = 1; ++ if (pdata->qca_force_16bit_ptw) ++ ehci->qca_force_16bit_ptw = 1; ++ ++ if (pdata->reset_notifier) ++ ehci->reset_notifier = ehci_platform_reset_notifier; + + #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO + if (ehci->big_endian_mmio) { diff --git a/target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch new file mode 100644 index 0000000..1aa6097 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -225,6 +225,7 @@ endif + # + libs-$(CONFIG_FW_ARC) += arch/mips/fw/arc/ + libs-$(CONFIG_FW_CFE) += arch/mips/fw/cfe/ ++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ + libs-$(CONFIG_FW_SNIPROM) += arch/mips/fw/sni/ + libs-y += arch/mips/fw/lib/ + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1067,6 +1067,9 @@ config MIPS_MSC + config MIPS_NILE4 + bool + ++config MYLOADER ++ bool ++ + config SYNC_R4K + bool + diff --git a/target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch new file mode 100644 index 0000000..fdf353c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch @@ -0,0 +1,81 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -22,6 +23,7 @@ + #include + #include "dev-wmac.h" + ++static u8 ath79_wmac_mac[ETH_ALEN]; + static struct ath9k_platform_data ath79_wmac_data; + + static struct resource ath79_wmac_resources[] = { +@@ -162,7 +164,7 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + +-void __init ath79_register_wmac(u8 *cal_data) ++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) + ar913x_wmac_setup(); +@@ -179,5 +181,10 @@ void __init ath79_register_wmac(u8 *cal_ + memcpy(ath79_wmac_data.eeprom_data, cal_data, + sizeof(ath79_wmac_data.eeprom_data)); + ++ if (mac_addr) { ++ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac)); ++ ath79_wmac_data.macaddr = ath79_wmac_mac; ++ } ++ + platform_device_register(&ath79_wmac_device); + } +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -12,6 +12,6 @@ + #ifndef _ATH79_DEV_WMAC_H + #define _ATH79_DEV_WMAC_H + +-void ath79_register_wmac(u8 *cal_data); ++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + + #endif /* _ATH79_DEV_WMAC_H */ +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -92,7 +92,7 @@ static void __init ap81_setup(void) + ap81_gpio_keys); + ath79_register_spi(&ap81_spi_data, ap81_spi_info, + ARRAY_SIZE(ap81_spi_info)); +- ath79_register_wmac(cal_data); ++ ath79_register_wmac(cal_data, NULL); + ath79_register_usb(); + } + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -128,7 +128,7 @@ static void __init db120_setup(void) + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); ++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); + } + +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -85,7 +85,7 @@ static void __init ap121_setup(void) + ath79_register_spi(&ap121_spi_data, ap121_spi_info, + ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(cal_data); ++ ath79_register_wmac(cal_data, NULL); + } + + MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", diff --git a/target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch b/target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch new file mode 100644 index 0000000..73eb8e1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch @@ -0,0 +1,23 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -25,7 +25,9 @@ + #include + #include "common.h" + +-static void __iomem *ath79_gpio_base; ++void __iomem *ath79_gpio_base; ++EXPORT_SYMBOL_GPL(ath79_gpio_base); ++ + static unsigned long ath79_gpio_count; + static DEFINE_SPINLOCK(ath79_gpio_lock); + +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -116,6 +116,7 @@ static inline int soc_is_qca955x(void) + } + + extern void __iomem *ath79_ddr_base; ++extern void __iomem *ath79_gpio_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; + diff --git a/target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch new file mode 100644 index 0000000..108f659 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch @@ -0,0 +1,37 @@ +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -22,6 +22,7 @@ + #include "common.h" + + static DEFINE_SPINLOCK(ath79_device_reset_lock); ++static DEFINE_MUTEX(ath79_flash_mutex); + + u32 ath79_cpu_freq; + EXPORT_SYMBOL_GPL(ath79_cpu_freq); +@@ -111,3 +112,16 @@ void ath79_device_reset_clear(u32 mask) + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); + } + EXPORT_SYMBOL_GPL(ath79_device_reset_clear); ++ ++void ath79_flash_acquire(void) ++{ ++ mutex_lock(&ath79_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ath79_flash_acquire); ++ ++void ath79_flash_release(void) ++{ ++ mutex_unlock(&ath79_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ath79_flash_release); ++ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -144,4 +144,7 @@ static inline u32 ath79_reset_rr(unsigne + void ath79_device_reset_set(u32 mask); + void ath79_device_reset_clear(u32 mask); + ++void ath79_flash_acquire(void); ++void ath79_flash_release(void); ++ + #endif /* __ASM_MACH_ATH79_H */ diff --git a/target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch new file mode 100644 index 0000000..8748aa3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch @@ -0,0 +1,45 @@ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -143,6 +143,7 @@ static inline u32 ath79_reset_rr(unsigne + + void ath79_device_reset_set(u32 mask); + void ath79_device_reset_clear(u32 mask); ++u32 ath79_device_reset_get(u32 mask); + + void ath79_flash_acquire(void); + void ath79_flash_release(void); +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -113,6 +113,32 @@ void ath79_device_reset_clear(u32 mask) + } + EXPORT_SYMBOL_GPL(ath79_device_reset_clear); + ++u32 ath79_device_reset_get(u32 mask) ++{ ++ unsigned long flags; ++ u32 reg; ++ u32 ret; ++ ++ if (soc_is_ar71xx()) ++ reg = AR71XX_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar724x()) ++ reg = AR724X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar913x()) ++ reg = AR913X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar933x()) ++ reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; ++ else ++ BUG(); ++ ++ spin_lock_irqsave(&ath79_device_reset_lock, flags); ++ ret = ath79_reset_rr(reg); ++ spin_unlock_irqrestore(&ath79_device_reset_lock, flags); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ath79_device_reset_get); ++ + void ath79_flash_acquire(void) + { + mutex_lock(&ath79_flash_mutex); diff --git a/target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch new file mode 100644 index 0000000..4c4c891 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -27,6 +27,7 @@ void ath79_ddr_wb_flush(unsigned int reg + void ath79_gpio_function_enable(u32 mask); + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); ++void ath79_gpio_output_select(unsigned gpio, u8 val); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -180,6 +180,34 @@ void ath79_gpio_function_disable(u32 mas + ath79_gpio_function_setup(0, mask); + } + ++void __init ath79_gpio_output_select(unsigned gpio, u8 val) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ unsigned int reg; ++ u32 t, s; ++ ++ BUG_ON(!soc_is_ar934x()); ++ ++ if (gpio >= AR934X_GPIO_COUNT) ++ return; ++ ++ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); ++ s = 8 * (gpio % 4); ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ t = __raw_readl(base + reg); ++ t &= ~(0xff << s); ++ t |= val << s; ++ __raw_writel(t, base + reg); ++ ++ /* flush write */ ++ (void) __raw_readl(base + reg); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++} ++ + void __init ath79_gpio_init(void) + { + int err; diff --git a/target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch b/target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch new file mode 100644 index 0000000..46beeff --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -22,10 +22,39 @@ + + #include "common.h" + ++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata; ++ ++static void __init ath79_prom_append_cmdline(const char *name, ++ const char *value) ++{ ++ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf), ++ " %s=%s", name, value); ++ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); ++} ++ + void __init prom_init(void) + { ++ const char *env; ++ + fw_init_cmdline(); + ++ env = fw_getenv("ethaddr"); ++ if (env) ++ ath79_prom_append_cmdline("ethaddr", env); ++ ++ env = fw_getenv("board"); ++ if (env) { ++ /* Workaround for buggy bootloaders */ ++ if (strcmp(env, "RouterStation") == 0 || ++ strcmp(env, "Ubiquiti AR71xx-based board") == 0) ++ env = "UBNT-RS"; ++ ++ if (strcmp(env, "RouterStation PRO") == 0) ++ env = "UBNT-RSPRO"; ++ ++ ath79_prom_append_cmdline("board", env); ++ } ++ + #ifdef CONFIG_BLK_DEV_INITRD + /* Read the initrd address from the firmware environment */ + initrd_start = fw_getenvl("initrd_start"); diff --git a/target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch b/target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch new file mode 100644 index 0000000..17a9733 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch @@ -0,0 +1,55 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include "common.h" + +@@ -32,10 +33,44 @@ static void __init ath79_prom_append_cmd + strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); + } + ++static int __init ath79_prom_init_myloader(void) ++{ ++ struct myloader_info *mylo; ++ char mac_buf[32]; ++ unsigned char *mac; ++ ++ mylo = myloader_get_info(); ++ if (!mylo) ++ return 0; ++ ++ switch (mylo->did) { ++ case DEVID_COMPEX_WP543: ++ ath79_prom_append_cmdline("board", "WP543"); ++ break; ++ case DEVID_COMPEX_WPE72: ++ ath79_prom_append_cmdline("board", "WPE72"); ++ break; ++ default: ++ pr_warn("prom: unknown device id: %x\n", mylo->did); ++ return 0; ++ } ++ ++ mac = mylo->macs[0]; ++ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++ ++ ath79_prom_append_cmdline("ethaddr", mac_buf); ++ ++ return 1; ++} ++ + void __init prom_init(void) + { + const char *env; + ++ if (ath79_prom_init_myloader()) ++ return; ++ + fw_init_cmdline(); + + env = fw_getenv("ethaddr"); diff --git a/target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch b/target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch new file mode 100644 index 0000000..ff9f1aa --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch @@ -0,0 +1,57 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -33,6 +33,35 @@ static void __init ath79_prom_append_cmd + strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); + } + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static int __init ath79_use_image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return 0; ++ ++ if (replace) { ++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++ ++ return 1; ++} ++#else ++static inline int ath79_use_image_cmdline(void) { return 0; } ++#endif ++ + static int __init ath79_prom_init_myloader(void) + { + struct myloader_info *mylo; +@@ -61,6 +90,8 @@ static int __init ath79_prom_init_myload + + ath79_prom_append_cmdline("ethaddr", mac_buf); + ++ ath79_use_image_cmdline(); ++ + return 1; + } + +@@ -71,7 +102,8 @@ void __init prom_init(void) + if (ath79_prom_init_myloader()) + return; + +- fw_init_cmdline(); ++ if (!ath79_use_image_cmdline()) ++ fw_init_cmdline(); + + env = fw_getenv("ethaddr"); + if (env) diff --git a/target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch new file mode 100644 index 0000000..2366c40 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -236,6 +236,8 @@ void __init plat_time_init(void) + mips_hpt_frequency = cpu_clk_rate / 2; + } + ++__setup("board=", mips_machtype_setup); ++ + static int __init ath79_setup(void) + { + ath79_gpio_init(); diff --git a/target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch b/target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch new file mode 100644 index 0000000..2d2235e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -24,7 +24,10 @@ + #include "dev-wmac.h" + + static u8 ath79_wmac_mac[ETH_ALEN]; +-static struct ath9k_platform_data ath79_wmac_data; ++ ++static struct ath9k_platform_data ath79_wmac_data = { ++ .led_pin = -1, ++}; + + static struct resource ath79_wmac_resources[] = { + { diff --git a/target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch b/target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch new file mode 100644 index 0000000..019e558 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch @@ -0,0 +1,18 @@ +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -80,6 +80,15 @@ void __init ath79_register_uart(void) + + uart_clk_rate = ath79_get_sys_clk_rate("uart"); + ++ if (soc_is_ar71xx()) ++ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar724x()) ++ ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar913x()) ++ ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar933x()) ++ ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); ++ + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || diff --git a/target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch new file mode 100644 index 0000000..3d6ddfe --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch @@ -0,0 +1,61 @@ +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned + /* nothing to do */ + } + ++static void prom_enable_uart(u32 id) ++{ ++ void __iomem *gpio_base; ++ u32 uart_en; ++ u32 t; ++ ++ switch (id) { ++ case REV_ID_MAJOR_AR71XX: ++ uart_en = AR71XX_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR7240: ++ case REV_ID_MAJOR_AR7241: ++ case REV_ID_MAJOR_AR7242: ++ uart_en = AR724X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR913X: ++ uart_en = AR913X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR9330: ++ case REV_ID_MAJOR_AR9331: ++ uart_en = AR933X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR9341: ++ case REV_ID_MAJOR_AR9342: ++ case REV_ID_MAJOR_AR9344: ++ /* TODO */ ++ default: ++ return; ++ } ++ ++ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE)); ++ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); ++ t |= uart_en; ++ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); ++} ++ + static void prom_putchar_init(void) + { + void __iomem *base; +@@ -86,8 +126,10 @@ static void prom_putchar_init(void) + + default: + _prom_putchar = prom_putchar_dummy; +- break; ++ return; + } ++ ++ prom_enable_uart(id); + } + + void prom_putchar(unsigned char ch) diff --git a/target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch b/target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch new file mode 100644 index 0000000..a29c7be --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -191,3 +191,9 @@ void __init ath79_register_wmac(u8 *cal_ + + platform_device_register(&ath79_wmac_device); + } ++ ++void __init ath79_register_wmac_simple(void) ++{ ++ ath79_register_wmac(NULL, NULL); ++ ath79_wmac_data.eeprom_name = "soc_wmac.eeprom"; ++} +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -13,5 +13,6 @@ + #define _ATH79_DEV_WMAC_H + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); ++void ath79_register_wmac_simple(void); + + #endif /* _ATH79_DEV_WMAC_H */ diff --git a/target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch new file mode 100644 index 0000000..e030d7c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch @@ -0,0 +1,166 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -167,6 +167,137 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static bool __init ++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) ++{ ++ int timeout = 1000; ++ u32 val; ++ ++ __raw_readl(base + AR9300_OTP_BASE + (4 * addr)); ++ while (timeout--) { ++ val = __raw_readl(base + AR9300_OTP_STATUS); ++ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID) ++ break; ++ ++ udelay(10); ++ } ++ ++ if (!timeout) ++ return false; ++ ++ *data = __raw_readl(base + AR9300_OTP_READ_DATA); ++ return true; ++} ++ ++static bool __init ++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len) ++{ ++ u32 data; ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ int offset = 8 * ((addr - i) % 4); ++ ++ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data)) ++ return false; ++ ++ dest[i] = (data >> offset) & 0xff; ++ } ++ ++ return true; ++} ++ ++static bool __init ++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest, ++ int dest_start, int dest_len) ++{ ++ int dest_bytes = 0; ++ int offset = 0; ++ int end = addr - len; ++ u8 hdr[2]; ++ ++ while (addr > end) { ++ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2)) ++ return false; ++ ++ addr -= 2; ++ offset += hdr[0]; ++ ++ if (offset <= dest_start + dest_len && ++ offset + len >= dest_start) { ++ int data_offset = 0; ++ int dest_offset = 0; ++ int copy_len; ++ ++ if (offset < dest_start) ++ data_offset = dest_start - offset; ++ else ++ dest_offset = offset - dest_start; ++ ++ copy_len = len - data_offset; ++ if (copy_len > dest_len - dest_offset) ++ copy_len = dest_len - dest_offset; ++ ++ ar93xx_wmac_otp_read(base, addr - data_offset, ++ dest + dest_offset, ++ copy_len); ++ ++ dest_bytes += copy_len; ++ } ++ addr -= hdr[1]; ++ } ++ return !!dest_bytes; ++} ++ ++bool __init ar93xx_wmac_read_mac_address(u8 *dest) ++{ ++ void __iomem *base; ++ bool ret = false; ++ int addr = 0x1ff; ++ unsigned int len; ++ u32 hdr_u32; ++ u8 *hdr = (u8 *) &hdr_u32; ++ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 }; ++ int mac_start = 2, mac_end = 8; ++ ++ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x()); ++ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE); ++ while (addr > sizeof(hdr)) { ++ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr))) ++ break; ++ ++ if (hdr_u32 == 0 || hdr_u32 == ~0) ++ break; ++ ++ len = (hdr[1] << 4) | (hdr[2] >> 4); ++ addr -= 4; ++ ++ switch (hdr[0] >> 5) { ++ case 0: ++ if (len < mac_end) ++ break; ++ ++ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6); ++ ret = true; ++ break; ++ case 3: ++ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac, ++ mac_start, 6); ++ break; ++ default: ++ break; ++ } ++ ++ addr -= len + 2; ++ } ++ ++ iounmap(base); ++ if (ret) ++ memcpy(dest, mac, 6); ++ ++ return ret; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -14,5 +14,6 @@ + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + void ath79_register_wmac_simple(void); ++bool ar93xx_wmac_read_mac_address(u8 *dest); + + #endif /* _ATH79_DEV_WMAC_H */ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -112,6 +112,14 @@ + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 + ++#define AR9300_OTP_BASE 0x14000 ++#define AR9300_OTP_STATUS 0x15f18 ++#define AR9300_OTP_STATUS_TYPE 0x7 ++#define AR9300_OTP_STATUS_VALID 0x4 ++#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 ++#define AR9300_OTP_STATUS_SM_BUSY 0x1 ++#define AR9300_OTP_READ_DATA 0x15f1c ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch new file mode 100644 index 0000000..31f885f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -298,6 +298,16 @@ bool __init ar93xx_wmac_read_mac_address + return ret; + } + ++void __init ath79_wmac_disable_2ghz(void) ++{ ++ ath79_wmac_data.disable_2ghz = true; ++} ++ ++void __init ath79_wmac_disable_5ghz(void) ++{ ++ ath79_wmac_data.disable_5ghz = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -14,6 +14,9 @@ + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + void ath79_register_wmac_simple(void); ++void ath79_wmac_disable_2ghz(void); ++void ath79_wmac_disable_5ghz(void); ++ + bool ar93xx_wmac_read_mac_address(u8 *dest); + + #endif /* _ATH79_DEV_WMAC_H */ diff --git a/target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch b/target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch new file mode 100644 index 0000000..0e33674 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch @@ -0,0 +1,101 @@ +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -37,6 +37,8 @@ static struct usb_ehci_pdata ath79_ehci_ + static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { + .caps_offset = 0x100, + .has_tt = 1, ++ .qca_force_host_mode = 1, ++ .qca_force_16bit_ptw = 1, + }; + + static void __init ath79_usb_register(const char *name, int id, +@@ -159,6 +161,9 @@ static void __init ar913x_usb_setup(void + ath79_device_reset_clear(AR913X_RESET_USB_PHY); + mdelay(10); + ++ ath79_ehci_pdata_v2.qca_force_host_mode = 0; ++ ath79_ehci_pdata_v2.qca_force_16bit_ptw = 0; ++ + ath79_usb_register("ehci-platform", -1, + AR913X_EHCI_BASE, AR913X_EHCI_SIZE, + ATH79_CPU_IRQ(3), +@@ -182,14 +187,34 @@ static void __init ar933x_usb_setup(void + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + +-static void __init ar934x_usb_setup(void) ++static void enable_tx_tx_idp_violation_fix(unsigned base) + { +- u32 bootstrap; ++ void __iomem *phy_reg; ++ u32 t; ++ ++ phy_reg = ioremap(base, 4); ++ if (!phy_reg) ++ return; ++ ++ t = ioread32(phy_reg); ++ t &= ~0xff; ++ t |= 0x58; ++ iowrite32(t, phy_reg); ++ ++ iounmap(phy_reg); ++} + +- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); +- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) ++static void ar934x_usb_reset_notifier(struct platform_device *pdev) ++{ ++ if (pdev->id != -1) + return; + ++ enable_tx_tx_idp_violation_fix(0x18116c94); ++ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n"); ++} ++ ++static void __init ar934x_usb_setup(void) ++{ + ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); + udelay(1000); + +@@ -202,14 +227,40 @@ static void __init ar934x_usb_setup(void + ath79_device_reset_clear(AR934X_RESET_USB_HOST); + udelay(1000); + ++ if (ath79_soc_rev >= 3) ++ ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier; ++ + ath79_usb_register("ehci-platform", -1, + AR934X_EHCI_BASE, AR934X_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void qca955x_usb_reset_notifier(struct platform_device *pdev) ++{ ++ u32 base; ++ ++ switch (pdev->id) { ++ case 0: ++ base = 0x18116c94; ++ break; ++ ++ case 1: ++ base = 0x18116e54; ++ break; ++ ++ default: ++ return; ++ } ++ ++ enable_tx_tx_idp_violation_fix(base); ++ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n"); ++} ++ + static void __init qca955x_usb_setup(void) + { ++ ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier; ++ + ath79_usb_register("ehci-platform", 0, + QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, + ATH79_IP3_IRQ(0), diff --git a/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch new file mode 100644 index 0000000..8bf7658 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch @@ -0,0 +1,363 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -20,6 +20,10 @@ + #include + + #define AR71XX_APB_BASE 0x18000000 ++#define AR71XX_GE0_BASE 0x19000000 ++#define AR71XX_GE0_SIZE 0x10000 ++#define AR71XX_GE1_BASE 0x1a000000 ++#define AR71XX_GE1_SIZE 0x10000 + #define AR71XX_EHCI_BASE 0x1b000000 + #define AR71XX_EHCI_SIZE 0x1000 + #define AR71XX_OHCI_BASE 0x1c000000 +@@ -39,6 +43,8 @@ + #define AR71XX_PLL_SIZE 0x100 + #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) + #define AR71XX_RESET_SIZE 0x100 ++#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR71XX_MII_SIZE 0x100 + + #define AR71XX_PCI_MEM_BASE 0x10000000 + #define AR71XX_PCI_MEM_SIZE 0x07000000 +@@ -81,15 +87,21 @@ + + #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) + #define AR933X_UART_SIZE 0x14 ++#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR933X_GMAC_SIZE 0x04 + #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR933X_WMAC_SIZE 0x20000 + #define AR933X_EHCI_BASE 0x1b000000 + #define AR933X_EHCI_SIZE 0x1000 + ++#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR934X_GMAC_SIZE 0x14 + #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR934X_WMAC_SIZE 0x20000 + #define AR934X_EHCI_BASE 0x1b000000 + #define AR934X_EHCI_SIZE 0x200 ++#define AR934X_NFC_BASE 0x1b000200 ++#define AR934X_NFC_SIZE 0xb8 + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + +@@ -106,11 +118,15 @@ + #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) + #define QCA955X_PCI_CTRL_SIZE 0x100 + ++#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA955X_GMAC_SIZE 0x40 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 ++#define QCA955X_NFC_BASE 0x1b800200 ++#define QCA955X_NFC_SIZE 0xb8 + + #define AR9300_OTP_BASE 0x14000 + #define AR9300_OTP_STATUS 0x15f18 +@@ -174,6 +190,9 @@ + #define AR71XX_AHB_DIV_SHIFT 20 + #define AR71XX_AHB_DIV_MASK 0x7 + ++#define AR71XX_ETH0_PLL_SHIFT 17 ++#define AR71XX_ETH1_PLL_SHIFT 19 ++ + #define AR724X_PLL_REG_CPU_CONFIG 0x00 + #define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +@@ -186,6 +205,8 @@ + #define AR724X_DDR_DIV_SHIFT 22 + #define AR724X_DDR_DIV_MASK 0x3 + ++#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c ++ + #define AR913X_PLL_REG_CPU_CONFIG 0x00 + #define AR913X_PLL_REG_ETH_CONFIG 0x04 + #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +@@ -198,6 +219,9 @@ + #define AR913X_AHB_DIV_SHIFT 19 + #define AR913X_AHB_DIV_MASK 0x1 + ++#define AR913X_ETH0_PLL_SHIFT 20 ++#define AR913X_ETH1_PLL_SHIFT 22 ++ + #define AR933X_PLL_CPU_CONFIG_REG 0x00 + #define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +@@ -219,6 +243,8 @@ + #define AR934X_PLL_CPU_CONFIG_REG 0x00 + #define AR934X_PLL_DDR_CONFIG_REG 0x04 + #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 ++#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + + #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -251,9 +277,13 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 ++#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 ++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + + #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -378,16 +408,83 @@ + #define AR913X_RESET_USB_HOST BIT(5) + #define AR913X_RESET_USB_PHY BIT(4) + ++#define AR933X_RESET_GE1_MDIO BIT(23) ++#define AR933X_RESET_GE0_MDIO BIT(22) ++#define AR933X_RESET_GE1_MAC BIT(13) + #define AR933X_RESET_WMAC BIT(11) ++#define AR933X_RESET_GE0_MAC BIT(9) + #define AR933X_RESET_USB_HOST BIT(5) + #define AR933X_RESET_USB_PHY BIT(4) + #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + ++#define AR934X_RESET_HOST BIT(31) ++#define AR934X_RESET_SLIC BIT(30) ++#define AR934X_RESET_HDMA BIT(29) ++#define AR934X_RESET_EXTERNAL BIT(28) ++#define AR934X_RESET_RTC BIT(27) ++#define AR934X_RESET_PCIE_EP_INT BIT(26) ++#define AR934X_RESET_CHKSUM_ACC BIT(25) ++#define AR934X_RESET_FULL_CHIP BIT(24) ++#define AR934X_RESET_GE1_MDIO BIT(23) ++#define AR934X_RESET_GE0_MDIO BIT(22) ++#define AR934X_RESET_CPU_NMI BIT(21) ++#define AR934X_RESET_CPU_COLD BIT(20) ++#define AR934X_RESET_HOST_RESET_INT BIT(19) ++#define AR934X_RESET_PCIE_EP BIT(18) ++#define AR934X_RESET_UART1 BIT(17) ++#define AR934X_RESET_DDR BIT(16) ++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define AR934X_RESET_NANDF BIT(14) ++#define AR934X_RESET_GE1_MAC BIT(13) ++#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) + #define AR934X_RESET_USB_PHY_ANALOG BIT(11) ++#define AR934X_RESET_HOST_DMA_INT BIT(10) ++#define AR934X_RESET_GE0_MAC BIT(9) ++#define AR934X_RESET_ETH_SWITCH BIT(8) ++#define AR934X_RESET_PCIE_PHY BIT(7) ++#define AR934X_RESET_PCIE BIT(6) + #define AR934X_RESET_USB_HOST BIT(5) + #define AR934X_RESET_USB_PHY BIT(4) + #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) ++#define AR934X_RESET_LUT BIT(2) ++#define AR934X_RESET_MBOX BIT(1) ++#define AR934X_RESET_I2S BIT(0) ++ ++#define QCA955X_RESET_HOST BIT(31) ++#define QCA955X_RESET_SLIC BIT(30) ++#define QCA955X_RESET_HDMA BIT(29) ++#define QCA955X_RESET_EXTERNAL BIT(28) ++#define QCA955X_RESET_RTC BIT(27) ++#define QCA955X_RESET_PCIE_EP_INT BIT(26) ++#define QCA955X_RESET_CHKSUM_ACC BIT(25) ++#define QCA955X_RESET_FULL_CHIP BIT(24) ++#define QCA955X_RESET_GE1_MDIO BIT(23) ++#define QCA955X_RESET_GE0_MDIO BIT(22) ++#define QCA955X_RESET_CPU_NMI BIT(21) ++#define QCA955X_RESET_CPU_COLD BIT(20) ++#define QCA955X_RESET_HOST_RESET_INT BIT(19) ++#define QCA955X_RESET_PCIE_EP BIT(18) ++#define QCA955X_RESET_UART1 BIT(17) ++#define QCA955X_RESET_DDR BIT(16) ++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define QCA955X_RESET_NANDF BIT(14) ++#define QCA955X_RESET_GE1_MAC BIT(13) ++#define QCA955X_RESET_SGMII_ANALOG BIT(12) ++#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) ++#define QCA955X_RESET_HOST_DMA_INT BIT(10) ++#define QCA955X_RESET_GE0_MAC BIT(9) ++#define QCA955X_RESET_SGMII BIT(8) ++#define QCA955X_RESET_PCIE_PHY BIT(7) ++#define QCA955X_RESET_PCIE BIT(6) ++#define QCA955X_RESET_USB_HOST BIT(5) ++#define QCA955X_RESET_USB_PHY BIT(4) ++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) ++#define QCA955X_RESET_LUT BIT(2) ++#define QCA955X_RESET_MBOX BIT(1) ++#define QCA955X_RESET_I2S BIT(0) + ++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) ++#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + + #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +@@ -529,6 +626,12 @@ + #define AR71XX_GPIO_REG_INT_ENABLE 0x24 + #define AR71XX_GPIO_REG_FUNC 0x28 + ++#define AR934X_GPIO_REG_OUT_FUNC0 0x2c ++#define AR934X_GPIO_REG_OUT_FUNC1 0x30 ++#define AR934X_GPIO_REG_OUT_FUNC2 0x34 ++#define AR934X_GPIO_REG_OUT_FUNC3 0x38 ++#define AR934X_GPIO_REG_OUT_FUNC4 0x3c ++#define AR934X_GPIO_REG_OUT_FUNC5 0x40 + #define AR934X_GPIO_REG_FUNC 0x6c + + #define AR71XX_GPIO_COUNT 16 +@@ -560,4 +663,153 @@ + #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + ++#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) ++#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) ++#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) ++#define AR71XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) ++#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) ++ ++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) ++#define AR724X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) ++#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) ++#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) ++#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) ++#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR724X_GPIO_FUNC_UART_EN BIT(1) ++#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) ++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) ++#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) ++#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) ++#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) ++#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) ++#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) ++#define AR913X_GPIO_FUNC_UART_EN BIT(8) ++#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) ++ ++#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) ++#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) ++#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) ++#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) ++#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) ++#define AR933X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR933X_GPIO_FUNC_UART_EN BIT(1) ++#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) ++#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) ++#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) ++#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) ++#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) ++#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) ++#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) ++#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) ++#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) ++ ++#define AR934X_GPIO_OUT_GPIO 0 ++#define AR934X_GPIO_OUT_SPI_CS1 7 ++#define AR934X_GPIO_OUT_LED_LINK0 41 ++#define AR934X_GPIO_OUT_LED_LINK1 42 ++#define AR934X_GPIO_OUT_LED_LINK2 43 ++#define AR934X_GPIO_OUT_LED_LINK3 44 ++#define AR934X_GPIO_OUT_LED_LINK4 45 ++#define AR934X_GPIO_OUT_EXT_LNA0 46 ++#define AR934X_GPIO_OUT_EXT_LNA1 47 ++ ++/* ++ * MII_CTRL block ++ */ ++#define AR71XX_MII_REG_MII0_CTRL 0x00 ++#define AR71XX_MII_REG_MII1_CTRL 0x04 ++ ++#define AR71XX_MII_CTRL_IF_MASK 3 ++#define AR71XX_MII_CTRL_SPEED_SHIFT 4 ++#define AR71XX_MII_CTRL_SPEED_MASK 3 ++#define AR71XX_MII_CTRL_SPEED_10 0 ++#define AR71XX_MII_CTRL_SPEED_100 1 ++#define AR71XX_MII_CTRL_SPEED_1000 2 ++ ++#define AR71XX_MII0_CTRL_IF_GMII 0 ++#define AR71XX_MII0_CTRL_IF_MII 1 ++#define AR71XX_MII0_CTRL_IF_RGMII 2 ++#define AR71XX_MII0_CTRL_IF_RMII 3 ++ ++#define AR71XX_MII1_CTRL_IF_RGMII 0 ++#define AR71XX_MII1_CTRL_IF_RMII 1 ++ ++/* ++ * AR933X GMAC interface ++ */ ++#define AR933X_GMAC_REG_ETH_CFG 0x00 ++ ++#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) ++#define AR933X_ETH_CFG_MII_GE0 BIT(1) ++#define AR933X_ETH_CFG_GMII_GE0 BIT(2) ++#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) ++#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) ++#define AR933X_ETH_CFG_RMII_GE0 BIT(9) ++#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 ++#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) ++ ++/* ++ * AR934X GMAC Interface ++ */ ++#define AR934X_GMAC_REG_ETH_CFG 0x00 ++ ++#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) ++#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) ++#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) ++#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) ++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) ++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) ++#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) ++#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) ++#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) ++#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) ++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++#define AR934X_ETH_CFG_RXD_DELAY BIT(14) ++#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 ++#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 ++#define AR934X_ETH_CFG_RDV_DELAY BIT(16) ++#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 ++#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 ++ ++/* ++ * QCA955X GMAC Interface ++ */ ++ ++#define QCA955X_GMAC_REG_ETH_CFG 0x00 ++ ++#define QCA955X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) ++ + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch b/target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch new file mode 100644 index 0000000..a772d9b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch @@ -0,0 +1,76 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -98,6 +98,20 @@ config SOC_QCA955X + select PCI_AR724X if PCI + def_bool n + ++config ATH79_DEV_M25P80 ++ select ATH79_DEV_SPI ++ def_bool n ++ ++config ATH79_DEV_AP9X_PCI ++ select ATH79_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config ATH79_DEV_DSA ++ def_bool n ++ ++config ATH79_DEV_ETH ++ def_bool n ++ + config PCI_AR724X + def_bool n + +@@ -107,6 +121,10 @@ config ATH79_DEV_GPIO_BUTTONS + config ATH79_DEV_LEDS_GPIO + def_bool n + ++config ATH79_DEV_NFC ++ depends on (SOC_AR934X || SOC_QCA955X) ++ def_bool n ++ + config ATH79_DEV_SPI + def_bool n + +@@ -117,4 +135,13 @@ config ATH79_DEV_WMAC + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) + def_bool n + ++config ATH79_NVRAM ++ def_bool n ++ ++config ATH79_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config ATH79_ROUTERBOOT ++ def_bool n ++ + endif +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -17,13 +17,25 @@ obj-$(CONFIG_PCI) += pci.o + # Devices + # + obj-y += dev-common.o ++obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o ++obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o ++obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o + obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o + obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o ++obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o ++obj-$(CONFIG_ATH79_DEV_NFC) += dev-nfc.o + obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o + obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o + obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o + + # ++# Miscellaneous objects ++# ++obj-$(CONFIG_ATH79_NVRAM) += nvram.o ++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o ++obj-$(CONFIG_ATH79_ROUTERBOOT) += routerboot.o ++ ++# + # Machines + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o diff --git a/target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch new file mode 100644 index 0000000..706e5af --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch @@ -0,0 +1,159 @@ +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -1,19 +1,21 @@ + /* + * Atheros AP121 board support + * +- * Copyright (C) 2011 Gabor Juhos ++ * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +-#include "machtypes.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" ++#include "dev-m25p80.h" + #include "dev-spi.h" + #include "dev-usb.h" + #include "dev-wmac.h" ++#include "machtypes.h" + + #define AP121_GPIO_LED_WLAN 0 + #define AP121_GPIO_LED_USB 1 +@@ -24,7 +26,14 @@ + #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) + +-#define AP121_CAL_DATA_ADDR 0x1fff1000 ++#define AP121_MAC0_OFFSET 0x0000 ++#define AP121_MAC1_OFFSET 0x0006 ++#define AP121_CALDATA_OFFSET 0x1000 ++#define AP121_WMAC_MAC_OFFSET 0x1002 ++ ++#define AP121_MINI_GPIO_LED_WLAN 0 ++#define AP121_MINI_GPIO_BTN_JUMPSTART 12 ++#define AP121_MINI_GPIO_BTN_RESET 11 + + static struct gpio_led ap121_leds_gpio[] __initdata = { + { +@@ -58,35 +67,78 @@ static struct gpio_keys_button ap121_gpi + } + }; + +-static struct spi_board_info ap121_spi_info[] = { ++static struct gpio_led ap121_mini_leds_gpio[] __initdata = { + { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l1606e", +- } ++ .name = "ap121:green:wlan", ++ .gpio = AP121_MINI_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, + }; + +-static struct ath79_spi_platform_data ap121_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = { ++ { ++ .desc = "jumpstart button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ }, ++ { ++ .desc = "reset button", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_RESET, ++ .active_low = 1, ++ } + }; + ++static void __init ap121_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_wmac(art + AP121_CALDATA_OFFSET, ++ art + AP121_WMAC_MAC_OFFSET); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ /* LAN ports */ ++ ath79_register_eth(1); ++ ++ /* WAN port */ ++ ath79_register_eth(0); ++} ++ + static void __init ap121_setup(void) + { +- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); ++ ap121_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), + ap121_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap121_gpio_keys), + ap121_gpio_keys); +- +- ath79_register_spi(&ap121_spi_data, ap121_spi_info, +- ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(cal_data, NULL); + } + + MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", + ap121_setup); ++ ++static void __init ap121_mini_setup(void) ++{ ++ ap121_common_setup(); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio), ++ ap121_mini_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap121_mini_gpio_keys), ++ ap121_mini_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI", ++ ap121_mini_setup); +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi + config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -17,6 +17,7 @@ + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ ++ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ diff --git a/target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch b/target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch new file mode 100644 index 0000000..3112eab --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch @@ -0,0 +1,84 @@ +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -9,12 +9,16 @@ + * by the Free Software Foundation. + */ + +-#include "machtypes.h" +-#include "dev-wmac.h" ++#include ++#include ++ ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" + #include "dev-usb.h" ++#include "dev-wmac.h" ++#include "machtypes.h" + + #define AP81_GPIO_LED_STATUS 1 + #define AP81_GPIO_LED_AOSS 3 +@@ -67,20 +71,6 @@ static struct gpio_keys_button ap81_gpio + } + }; + +-static struct spi_board_info ap81_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "m25p64", +- } +-}; +- +-static struct ath79_spi_platform_data ap81_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; +- + static void __init ap81_setup(void) + { + u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); +@@ -90,10 +80,24 @@ static void __init ap81_setup(void) + ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap81_gpio_keys), + ap81_gpio_keys); +- ath79_register_spi(&ap81_spi_data, ap81_spi_info, +- ARRAY_SIZE(ap81_spi_info)); ++ ath79_register_m25p80(NULL); + ath79_register_wmac(cal_data, NULL); + ath79_register_usb(); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0); ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ath79_eth0_data.speed = SPEED_100; ++ ath79_eth0_data.duplex = DUPLEX_FULL; ++ ath79_eth0_data.has_ar8216 = 1; ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ath79_eth1_data.phy_mask = 0x10; ++ ++ ath79_register_eth(0); ++ ath79_register_eth(1); + } + + MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -30,9 +30,10 @@ config ATH79_MACH_AP136 + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help diff --git a/target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch new file mode 100644 index 0000000..080165a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch @@ -0,0 +1,204 @@ +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -2,7 +2,7 @@ + * Atheros DB120 reference board support + * + * Copyright (c) 2011 Qualcomm Atheros +- * Copyright (c) 2011 Gabor Juhos ++ * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -19,16 +19,26 @@ + */ + + #include ++#include ++#include + #include ++#include + +-#include "machtypes.h" ++#include ++ ++#include "common.h" ++#include "dev-ap9x-pci.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-nfc.h" + #include "dev-spi.h" + #include "dev-usb.h" + #include "dev-wmac.h" +-#include "pci.h" ++#include "machtypes.h" + ++#define DB120_GPIO_LED_USB 11 + #define DB120_GPIO_LED_WLAN_5G 12 + #define DB120_GPIO_LED_WLAN_2G 13 + #define DB120_GPIO_LED_STATUS 14 +@@ -39,8 +49,10 @@ + #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ + #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) + +-#define DB120_WMAC_CALDATA_OFFSET 0x1000 +-#define DB120_PCIE_CALDATA_OFFSET 0x5000 ++#define DB120_MAC0_OFFSET 0 ++#define DB120_MAC1_OFFSET 6 ++#define DB120_WMAC_CALDATA_OFFSET 0x1000 ++#define DB120_PCIE_CALDATA_OFFSET 0x5000 + + static struct gpio_led db120_leds_gpio[] __initdata = { + { +@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[] + .gpio = DB120_GPIO_LED_WLAN_2G, + .active_low = 1, + }, ++ { ++ .name = "db120:green:usb", ++ .gpio = DB120_GPIO_LED_USB, ++ .active_low = 1, ++ } + }; + + static struct gpio_keys_button db120_gpio_keys[] __initdata = { +@@ -76,60 +93,85 @@ static struct gpio_keys_button db120_gpi + }, + }; + +-static struct spi_board_info db120_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "s25sl064a", +- } ++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + }; + +-static struct ath79_spi_platform_data db120_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct ar8327_led_cfg db120_ar8327_led_cfg = { ++ .led_ctrl0 = 0x00000000, ++ .led_ctrl1 = 0xc737c737, ++ .led_ctrl2 = 0x00000000, ++ .led_ctrl3 = 0x00c30c00, ++ .open_drain = true, + }; + +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data db120_ath9k_data; +- +-static int db120_pci_plat_dev_init(struct pci_dev *dev) +-{ +- switch (PCI_SLOT(dev->devfn)) { +- case 0: +- dev->dev.platform_data = &db120_ath9k_data; +- break; +- } +- +- return 0; +-} +- +-static void __init db120_pci_init(u8 *eeprom) +-{ +- memcpy(db120_ath9k_data.eeprom_data, eeprom, +- sizeof(db120_ath9k_data.eeprom_data)); ++static struct ar8327_platform_data db120_ar8327_data = { ++ .pad0_cfg = &db120_ar8327_pad0_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .led_cfg = &db120_ar8327_led_cfg, ++}; + +- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); +- ath79_register_pci(); +-} +-#else +-static inline void db120_pci_init(u8 *eeprom) {} +-#endif /* CONFIG_PCI */ ++static struct mdio_board_info db120_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &db120_ar8327_data, ++ }, ++}; + + static void __init db120_setup(void) + { + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + ++ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); ++ ath79_register_m25p80(NULL); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), + db120_leds_gpio); + ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, + ARRAY_SIZE(db120_gpio_keys), + db120_gpio_keys); +- ath79_register_spi(&db120_spi_data, db120_spi_info, +- ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); +- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); ++ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | ++ AR934X_ETH_CFG_SW_ONLY_MODE); ++ ++ ath79_register_mdio(1, 0x0); ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); ++ ++ mdiobus_register_board_info(db120_mdio0_info, ++ ARRAY_SIZE(db120_mdio0_info)); ++ ++ /* GMAC0 is connected to an AR8327 switch */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++ ++ /* GMAC1 is connected to the internal switch */ ++ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ++ ath79_register_eth(1); ++ ++ ath79_register_nfc(); + } + + MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -43,9 +43,12 @@ config ATH79_MACH_AP81 + config ATH79_MACH_DB120 + bool "Atheros DB120 reference board" + select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help diff --git a/target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch b/target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch new file mode 100644 index 0000000..f9ec775 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch @@ -0,0 +1,153 @@ +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -8,23 +8,48 @@ + * by the Free Software Foundation. + */ + ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include + +-#include "machtypes.h" ++#include ++#include ++ ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" + #include "dev-usb.h" ++#include "machtypes.h" + #include "pci.h" + + #define PB44_GPIO_I2C_SCL 0 + #define PB44_GPIO_I2C_SDA 1 + ++#define PB44_PCF8757_VSC7395_CS 0 ++#define PB44_PCF8757_STEREO_CS 1 ++#define PB44_PCF8757_SLIC_CS0 2 ++#define PB44_PCF8757_SLIC_TEST 3 ++#define PB44_PCF8757_SLIC_INT0 4 ++#define PB44_PCF8757_SLIC_INT1 5 ++#define PB44_PCF8757_SW_RESET 6 ++#define PB44_PCF8757_SW_JUMP 8 ++#define PB44_PCF8757_LED_JUMP1 9 ++#define PB44_PCF8757_LED_JUMP2 10 ++#define PB44_PCF8757_TP24 11 ++#define PB44_PCF8757_TP25 12 ++#define PB44_PCF8757_TP26 13 ++#define PB44_PCF8757_TP27 14 ++#define PB44_PCF8757_TP28 15 ++ + #define PB44_GPIO_EXP_BASE 16 ++#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) + #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) + #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) + #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data + .cs_line = 0, + }; + ++static struct ath79_spi_controller_data pb44_spi1_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_GPIO, ++ .cs_line = PB44_GPIO_VSC7395_CS, ++}; ++ ++static void pb44_vsc7395_reset(void) ++{ ++ ath79_device_reset_set(AR71XX_RESET_GE1_PHY); ++ udelay(10); ++ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); ++ mdelay(50); ++} ++ ++static struct vsc7385_platform_data pb44_vsc7395_data = { ++ .reset = pb44_vsc7395_reset, ++ .ucode_name = "vsc7395_ucode_pb44.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 1, ++ .clk_sel = 0, ++ }, ++}; ++ ++static const char *pb44_part_probes[] = { ++ "RedBoot", ++ NULL, ++}; ++ ++static struct flash_platform_data pb44_flash_data = { ++ .part_probes = pb44_part_probes, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .platform_data = &pb44_flash_data, + .controller_data = &pb44_spi0_data, + }, ++ { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &pb44_vsc7395_data, ++ .controller_data = &pb44_spi1_data, ++ } + }; + + static struct ath79_spi_platform_data pb44_spi_data = { + .bus_num = 0, +- .num_chipselect = 1, ++ .num_chipselect = 2, + }; + ++#define PB44_WAN_PHYMASK BIT(0) ++#define PB44_LAN_PHYMASK 0 ++#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) ++ + static void __init pb44_init(void) + { + i2c_register_board_info(0, pb44_i2c_board_info, +@@ -122,6 +192,22 @@ static void __init pb44_init(void) + ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); + ath79_register_pci(); ++ ++ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK; ++ ++ ath79_register_eth(0); ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ath79_eth1_pll_data.pll_1000 = 0x110000; ++ ++ ath79_register_eth(1); + } + + MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -58,6 +58,7 @@ config ATH79_MACH_DB120 + config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI diff --git a/target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch new file mode 100644 index 0000000..50be509 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch @@ -0,0 +1,103 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -70,9 +70,10 @@ config ATH79_MACH_PB44 + config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM (rev 1.0) board" + select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -16,10 +16,11 @@ + + #include + +-#include "machtypes.h" ++#include "dev-ap9x-pci.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" ++#include "machtypes.h" + #include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 +@@ -32,7 +33,7 @@ + #define UBNT_XM_KEYS_POLL_INTERVAL 20 + #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +-#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) ++#define UBNT_XM_EEPROM_ADDR 0x1fff1000 + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { +@@ -65,48 +66,10 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + +-static struct spi_board_info ubnt_xm_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l6405d", +- } +-}; +- +-static struct ath79_spi_platform_data ubnt_xm_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; +- +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data ubnt_xm_eeprom_data; +- +-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) +-{ +- switch (PCI_SLOT(dev->devfn)) { +- case 0: +- dev->dev.platform_data = &ubnt_xm_eeprom_data; +- break; +- } +- +- return 0; +-} +- +-static void __init ubnt_xm_pci_init(void) +-{ +- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, +- sizeof(ubnt_xm_eeprom_data.eeprom_data)); +- +- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); +- ath79_register_pci(); +-} +-#else +-static inline void ubnt_xm_pci_init(void) {} +-#endif /* CONFIG_PCI */ +- + static void __init ubnt_xm_init(void) + { ++ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); + +@@ -114,10 +77,8 @@ static void __init ubnt_xm_init(void) + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + +- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, +- ARRAY_SIZE(ubnt_xm_spi_info)); +- +- ubnt_xm_pci_init(); ++ ath79_register_m25p80(NULL); ++ ap91_pci_init(eeprom, NULL); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch b/target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch new file mode 100644 index 0000000..24b0f27 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch @@ -0,0 +1,659 @@ +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -12,16 +12,26 @@ + + #include + #include ++#include + #include ++#include ++#include + ++#include + #include ++#include + ++#include ++ ++#include "common.h" + #include "dev-ap9x-pci.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-m25p80.h" ++#include "dev-usb.h" ++#include "dev-wmac.h" + #include "machtypes.h" +-#include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 + #define UBNT_XM_GPIO_LED_L2 1 +@@ -37,19 +47,19 @@ + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { +- .name = "ubnt-xm:red:link1", ++ .name = "ubnt:red:link1", + .gpio = UBNT_XM_GPIO_LED_L1, + .active_low = 0, + }, { +- .name = "ubnt-xm:orange:link2", ++ .name = "ubnt:orange:link2", + .gpio = UBNT_XM_GPIO_LED_L2, + .active_low = 0, + }, { +- .name = "ubnt-xm:green:link3", ++ .name = "ubnt:green:link3", + .gpio = UBNT_XM_GPIO_LED_L3, + .active_low = 0, + }, { +- .name = "ubnt-xm:green:link4", ++ .name = "ubnt:green:link4", + .gpio = UBNT_XM_GPIO_LED_L4, + .active_low = 0, + }, +@@ -66,9 +76,13 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + ++#define UBNT_M_WAN_PHYMASK BIT(4) ++ + static void __init ubnt_xm_init(void) + { + u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); +@@ -79,9 +93,552 @@ static void __init ubnt_xm_init(void) + + ath79_register_m25p80(NULL); + ap91_pci_init(eeprom, NULL); ++ ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, + "UBNT-XM", + "Ubiquiti Networks XM (rev 1.0) board", + ubnt_xm_init); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", ++ ubnt_xm_init); ++ ++static void __init ubnt_rocket_m_setup(void) ++{ ++ ubnt_xm_init(); ++ ath79_register_usb(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", ++ ubnt_rocket_m_setup); ++ ++static void __init ubnt_nano_m_setup(void) ++{ ++ ubnt_xm_init(); ++ ath79_register_eth(1); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", ++ ubnt_nano_m_setup); ++ ++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:globe", ++ .gpio = 0, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:power", ++ .gpio = 11, ++ .active_low = 1, ++ .default_state = LEDS_GPIO_DEFSTATE_ON, ++ } ++}; ++ ++static void __init ubnt_airrouter_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1); ++ ++ ath79_register_eth(1); ++ ath79_register_eth(0); ++ ath79_register_usb(); ++ ++ ap91_pci_init(ee, NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio), ++ ubnt_airrouter_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter", ++ ubnt_airrouter_setup); ++ ++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:orange:dome", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:dome", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:orange:front", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:front", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led ubnt_unifi_outdoor_plus_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:white:front", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:blue:front", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++ ++static void __init ubnt_unifi_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ++ ath79_register_eth(0); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio), ++ ubnt_unifi_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi", ++ ubnt_unifi_setup); ++ ++ ++#define UBNT_UNIFIOD_PRI_PHYMASK BIT(4) ++#define UBNT_UNIFIOD_2ND_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) ++ ++static void __init ubnt_unifi_outdoor_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK | ++ UBNT_UNIFIOD_2ND_PHYMASK)); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); ++ ath79_register_eth(1); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio), ++ ubnt_unifi_outdoor_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20", ++ "Ubiquiti UniFiAP Outdoor", ++ ubnt_unifi_outdoor_setup); ++ ++ ++static void __init ubnt_unifi_outdoor_plus_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK | ++ UBNT_UNIFIOD_2ND_PHYMASK)); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); ++ ath79_register_eth(1); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_plus_leds_gpio), ++ ubnt_unifi_outdoor_plus_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, "UBNT-UOP", ++ "Ubiquiti UniFiAP Outdoor+", ++ ubnt_unifi_outdoor_plus_setup); ++ ++ ++static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = { ++ { ++ .name = "ubnt:white:dome", ++ .gpio = 12, ++ }, { ++ .name = "ubnt:blue:dome", ++ .gpio = 13, ++ } ++}; ++ ++static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 17, ++ .active_low = 1, ++ } ++}; ++ ++static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, ++}; ++ ++static struct ar8327_platform_data uap_pro_ar8327_data = { ++ .pad0_cfg = &uap_pro_ar8327_pad0_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++}; ++ ++static struct mdio_board_info uap_pro_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &uap_pro_ar8327_data, ++ }, ++}; ++ ++#define UAP_PRO_MAC0_OFFSET 0x0000 ++#define UAP_PRO_MAC1_OFFSET 0x0006 ++#define UAP_PRO_WMAC_CALDATA_OFFSET 0x1000 ++#define UAP_PRO_PCI_CALDATA_OFFSET 0x5000 ++ ++static void __init ubnt_uap_pro_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds), ++ ubnt_uap_pro_gpio_leds); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(uap_pro_gpio_keys), ++ uap_pro_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ath79_register_mdio(0, 0x0); ++ mdiobus_register_board_info(uap_pro_mdio0_info, ++ ARRAY_SIZE(uap_pro_mdio0_info)); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ++ /* GMAC0 is connected to an AR8327 switch */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro", ++ ubnt_uap_pro_setup); ++ ++#define UBNT_XW_GPIO_LED_L1 11 ++#define UBNT_XW_GPIO_LED_L2 16 ++#define UBNT_XW_GPIO_LED_L3 13 ++#define UBNT_XW_GPIO_LED_L4 14 ++ ++static struct gpio_led ubnt_xw_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:red:link1", ++ .gpio = UBNT_XW_GPIO_LED_L1, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:orange:link2", ++ .gpio = UBNT_XW_GPIO_LED_L2, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link3", ++ .gpio = UBNT_XW_GPIO_LED_L3, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link4", ++ .gpio = UBNT_XW_GPIO_LED_L4, ++ .active_low = 1, ++ }, ++}; ++ ++#define UBNT_ROCKET_TI_GPIO_LED_L1 16 ++#define UBNT_ROCKET_TI_GPIO_LED_L2 17 ++#define UBNT_ROCKET_TI_GPIO_LED_L3 18 ++#define UBNT_ROCKET_TI_GPIO_LED_L4 19 ++#define UBNT_ROCKET_TI_GPIO_LED_L5 20 ++#define UBNT_ROCKET_TI_GPIO_LED_L6 21 ++static struct gpio_led ubnt_rocket_ti_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:link1", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L1, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link2", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L2, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link3", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L3, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link4", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L4, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link5", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L5, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link6", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L6, ++ .active_low = 0, ++ }, ++}; ++ ++static void __init ubnt_xw_init(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio), ++ ubnt_xw_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0_SLAVE); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++} ++ ++static void __init ubnt_nano_m_xw_setup(void) ++{ ++ ubnt_xw_init(); ++ ++ /* GMAC0 is connected to an AR8326 switch */ ++ ath79_register_mdio(0, ~(BIT(0) | BIT(1) | BIT(5))); ++ ath79_eth0_data.phy_mask = (BIT(0) | BIT(1) | BIT(5)); ++ ath79_eth0_data.speed = SPEED_100; ++ ath79_eth0_data.duplex = DUPLEX_FULL; ++ ath79_register_eth(0); ++} ++ ++static void __init ubnt_loco_m_xw_setup(void) ++{ ++ ubnt_xw_init(); ++ ++ ath79_register_mdio(0, ~BIT(1)); ++ ath79_eth0_data.phy_mask = BIT(1); ++ ath79_register_eth(0); ++} ++ ++static void __init ubnt_rocket_m_xw_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio), ++ ubnt_xw_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ++ ath79_register_mdio(0, ~BIT(4)); ++ ath79_eth0_data.phy_mask = BIT(4); ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++} ++ ++static struct at803x_platform_data ubnt_rocket_m_ti_at803_data = { ++ .disable_smarteee = 1, ++ .enable_rgmii_rx_delay = 1, ++ .enable_rgmii_tx_delay = 1, ++}; ++static struct mdio_board_info ubnt_rocket_m_ti_mdio_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 4, ++ .platform_data = &ubnt_rocket_m_ti_at803_data, ++ }, ++}; ++ ++static void __init ubnt_rocket_m_ti_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rocket_ti_leds_gpio), ++ ubnt_rocket_ti_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++ ++ ap91_pci_init(eeprom + 0x1000, NULL); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ++ ath79_setup_ar934x_eth_rx_delay(3, 3); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, ++ eeprom + UAP_PRO_MAC1_OFFSET, 0); ++ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; ++ ++ mdiobus_register_board_info(ubnt_rocket_m_ti_mdio_info, ++ ARRAY_SIZE(ubnt_rocket_m_ti_mdio_info)); ++ ath79_register_mdio(0, 0x0); ++ ++ ++ ath79_eth0_data.phy_mask = BIT(4); ++ /* read out from vendor */ ++ ath79_eth0_pll_data.pll_1000 = 0x2000000; ++ ath79_eth0_pll_data.pll_10 = 0x1313; ++ ath79_register_eth(0); ++ ++ ath79_register_mdio(1, 0x0); ++ ath79_eth1_data.phy_mask = BIT(3); ++ ath79_register_eth(1); ++} ++ ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M_XW, "UBNT-NM-XW", "Ubiquiti Nanostation M XW", ++ ubnt_nano_m_xw_setup); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_LOCO_M_XW, "UBNT-LOCO-XW", "Ubiquiti Loco M XW", ++ ubnt_loco_m_xw_setup); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_XW, "UBNT-RM-XW", "Ubiquiti Rocket M XW", ++ ubnt_rocket_m_xw_setup); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_TI, "UBNT-RM-TI", "Ubiquiti Rocket M TI", ++ ubnt_rocket_m_ti_setup); ++ ++static struct gpio_led ubnt_airgateway_gpio_leds[] __initdata = { ++ { ++ .name = "ubnt:blue:wlan", ++ .gpio = 0, ++ }, { ++ .name = "ubnt:white:status", ++ .gpio = 1, ++ }, ++}; ++ ++static struct gpio_keys_button airgateway_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 12, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ubnt_airgateway_setup(void) ++{ ++ u32 t; ++ u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ++ ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); ++ ++ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; ++ ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_gpio_leds), ++ ubnt_airgateway_gpio_leds); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(airgateway_gpio_keys), ++ airgateway_gpio_keys); ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_register_eth(1); ++ ath79_register_eth(0); ++ ++ ath79_register_wmac(ee, NULL); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRGW, "UBNT-AGW", "Ubiquiti AirGateway", ++ ubnt_airgateway_setup); ++ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -68,12 +68,16 @@ config ATH79_MACH_PB44 + Atheros PB44 reference board. + + config ATH79_MACH_UBNT_XM +- bool "Ubiquiti Networks XM (rev 1.0) board" ++ bool "Ubiquiti Networks XM/UniFi boards" + select SOC_AR724X ++ select SOC_AR934X + select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -22,6 +22,15 @@ enum ath79_mach_type { + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ ++ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ ++ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ ++ ATH79_MACH_UBNT_ROCKET_M_XW, /* Ubiquiti Rocket M XW*/ ++ ATH79_MACH_UBNT_ROCKET_M_TI, /* Ubiquiti Rocket M TI*/ ++ ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */ ++ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ ++ ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ + }; + diff --git a/target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch new file mode 100644 index 0000000..bf64fc6 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch @@ -0,0 +1,312 @@ +--- a/arch/mips/ath79/mach-ap136.c ++++ b/arch/mips/ath79/mach-ap136.c +@@ -18,23 +18,29 @@ + * + */ + +-#include +-#include ++#include ++#include + +-#include "machtypes.h" ++#include ++ ++#include "common.h" ++#include "pci.h" ++#include "dev-ap9x-pci.h" + #include "dev-gpio-buttons.h" ++#include "dev-eth.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" ++#include "dev-nfc.h" + #include "dev-usb.h" + #include "dev-wmac.h" +-#include "pci.h" ++#include "machtypes.h" + +-#define AP136_GPIO_LED_STATUS_RED 14 +-#define AP136_GPIO_LED_STATUS_GREEN 19 + #define AP136_GPIO_LED_USB 4 +-#define AP136_GPIO_LED_WLAN_2G 13 + #define AP136_GPIO_LED_WLAN_5G 12 ++#define AP136_GPIO_LED_WLAN_2G 13 ++#define AP136_GPIO_LED_STATUS_RED 14 + #define AP136_GPIO_LED_WPS_RED 15 ++#define AP136_GPIO_LED_STATUS_GREEN 19 + #define AP136_GPIO_LED_WPS_GREEN 20 + + #define AP136_GPIO_BTN_WPS 16 +@@ -43,37 +49,39 @@ + #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) + +-#define AP136_WMAC_CALDATA_OFFSET 0x1000 +-#define AP136_PCIE_CALDATA_OFFSET 0x5000 ++#define AP136_MAC0_OFFSET 0 ++#define AP136_MAC1_OFFSET 6 ++#define AP136_WMAC_CALDATA_OFFSET 0x1000 ++#define AP136_PCIE_CALDATA_OFFSET 0x5000 + + static struct gpio_led ap136_leds_gpio[] __initdata = { + { +- .name = "qca:green:status", ++ .name = "ap136:green:status", + .gpio = AP136_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { +- .name = "qca:red:status", ++ .name = "ap136:red:status", + .gpio = AP136_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { +- .name = "qca:green:wps", ++ .name = "ap136:green:wps", + .gpio = AP136_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { +- .name = "qca:red:wps", ++ .name = "ap136:red:wps", + .gpio = AP136_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { +- .name = "qca:red:wlan-2g", ++ .name = "ap136:red:wlan-2g", + .gpio = AP136_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { +- .name = "qca:red:usb", ++ .name = "ap136:red:usb", + .gpio = AP136_GPIO_LED_USB, + .active_low = 1, + } +@@ -98,59 +106,151 @@ static struct gpio_keys_button ap136_gpi + }, + }; + +-static struct spi_board_info ap136_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l6405d", +- } ++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg; ++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg; ++ ++static struct ar8327_platform_data ap136_ar8327_data = { ++ .pad0_cfg = &ap136_ar8327_pad0_cfg, ++ .pad6_cfg = &ap136_ar8327_pad6_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .port6_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, + }; + +-static struct ath79_spi_platform_data ap136_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct mdio_board_info ap136_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &ap136_ar8327_data, ++ }, + }; + +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data ap136_ath9k_data; ++static void __init ap136_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), ++ ap136_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap136_gpio_keys), ++ ap136_gpio_keys); ++ ++ ath79_register_usb(); ++ ath79_register_nfc(); ++ ++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); ++ ++ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ ath79_register_mdio(0, 0x0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); ++ ++ mdiobus_register_board_info(ap136_mdio0_info, ++ ARRAY_SIZE(ap136_mdio0_info)); ++ ++ /* GMAC0 is connected to the RMGII interface */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ++ ath79_register_eth(0); ++ ++ /* GMAC1 is connected tot eh SGMII interface */ ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ++ ath79_register_eth(1); ++} ++ ++static void __init ap136_010_setup(void) + { +- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) +- dev->dev.platform_data = &ap136_ath9k_data; ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + +- return 0; ++ /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */ ++ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; ++ ap136_ar8327_pad0_cfg.txclk_delay_en = true; ++ ap136_ar8327_pad0_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; ++ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; ++ ++ /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */ ++ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; ++ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; ++ ++ ath79_eth0_pll_data.pll_1000 = 0xa6000000; ++ ath79_eth1_pll_data.pll_1000 = 0x03000101; ++ ++ ap136_common_setup(); ++ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); + } + +-static void __init ap136_pci_init(u8 *eeprom) ++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", ++ "Atheros AP136-010 reference board", ++ ap136_010_setup); ++ ++static void __init ap136_020_common_setup(void) + { +- memcpy(ap136_ath9k_data.eeprom_data, eeprom, +- sizeof(ap136_ath9k_data.eeprom_data)); ++ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ ++ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; ++ ap136_ar8327_pad0_cfg.sgmii_delay_en = true; ++ ++ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ ++ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; ++ ap136_ar8327_pad6_cfg.txclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; ++ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); ++ ath79_eth0_pll_data.pll_1000 = 0x56000000; ++ ath79_eth1_pll_data.pll_1000 = 0x03000101; ++ ++ ap136_common_setup(); + } +-#else +-static inline void ap136_pci_init(u8 *eeprom) {} +-#endif /* CONFIG_PCI */ + +-static void __init ap136_setup(void) ++static void __init ap136_020_setup(void) + { + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + +- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), +- ap136_leds_gpio); +- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, +- ARRAY_SIZE(ap136_gpio_keys), +- ap136_gpio_keys); +- ath79_register_spi(&ap136_spi_data, ap136_spi_info, +- ARRAY_SIZE(ap136_spi_info)); +- ath79_register_usb(); +- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); +- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); ++ ap136_020_common_setup(); ++ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); + } + +-MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", +- "Atheros AP136-010 reference board", +- ap136_setup); ++MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020", ++ "Atheros AP136-020 reference board", ++ ap136_020_setup); ++ ++/* ++ * AP135-020 is similar to AP136-020, any future AP135 specific init ++ * code can be added here. ++ */ ++static void __init ap135_020_setup(void) ++{ ++ ap136_leds_gpio[0].name = "ap135:green:status"; ++ ap136_leds_gpio[1].name = "ap135:red:status"; ++ ap136_leds_gpio[2].name = "ap135:green:wps"; ++ ap136_leds_gpio[3].name = "ap135:red:wps"; ++ ap136_leds_gpio[4].name = "ap135:red:wlan-2g"; ++ ap136_leds_gpio[5].name = "ap135:red:usb"; ++ ++ ap136_020_common_setup(); ++ ath79_register_pci(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020", ++ "Atheros AP135-020 reference board", ++ ap135_020_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -18,7 +18,9 @@ enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ ++ ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ ++ ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -16,16 +16,17 @@ config ATH79_MACH_AP121 + Atheros AP121 reference board. + + config ATH79_MACH_AP136 +- bool "Atheros AP136 reference board" ++ bool "Atheros AP136/AP135 reference board" + select SOC_QCA955X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC + select ATH79_DEV_SPI + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the +- Atheros AP136 reference board. ++ Atheros AP136 or AP135 reference boards. + + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" diff --git a/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch b/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch new file mode 100644 index 0000000..f7c62ef --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch @@ -0,0 +1,62 @@ +--- a/arch/mips/ath79/mach-ubnt-xm.c 2015-08-19 21:26:47.694157530 -0600 ++++ b/arch/mips/ath79/mach-ubnt-xm.c 2015-08-20 16:24:06.908537535 -0600 +@@ -642,3 +642,59 @@ static void __init ubnt_airgateway_setup + MIPS_MACHINE(ATH79_MACH_UBNT_AIRGW, "UBNT-AGW", "Ubiquiti AirGateway", + ubnt_airgateway_setup); + ++static struct gpio_led ubnt_airgateway_pro_gpio_leds[] __initdata = { ++ { ++ .name = "ubnt:blue:wlan", ++ .gpio = 13, ++ }, { ++ .name = "ubnt:white:status", ++ .gpio = 17, ++ }, ++}; ++ ++ ++static struct gpio_keys_button airgateway_pro_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 12, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ubnt_airgateway_pro_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_pro_gpio_leds), ++ ubnt_airgateway_pro_gpio_leds); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(airgateway_pro_gpio_keys), ++ airgateway_pro_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); ++ ++ ath79_register_mdio(1, 0x0); ++ ++ /* GMAC0 is left unused in this configuration */ ++ ++ /* GMAC1 is connected to MAC0 on the internal switch */ ++ /* The PoE/WAN port connects to port 5 on the internal switch */ ++ /* The LAN port connects to port 4 on the internal switch */ ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_register_eth(1); ++ ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRGWP, "UBNT-AGWP", "Ubiquiti AirGateway Pro", ++ ubnt_airgateway_pro_setup); diff --git a/target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch b/target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch new file mode 100644 index 0000000..7a70ac3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch @@ -0,0 +1,25 @@ +MIPS: ath79: fix maximum timeout + +If the userland tries to set a timeout higher than the max_timeout, then we should fallback to max_timeout. + +Signed-off-by: John Crispin + +--- a/drivers/watchdog/ath79_wdt.c ++++ b/drivers/watchdog/ath79_wdt.c +@@ -114,10 +114,14 @@ static inline void ath79_wdt_disable(voi + + static int ath79_wdt_set_timeout(int val) + { +- if (val < 1 || val > max_timeout) ++ if (val < 1) + return -EINVAL; + +- timeout = val; ++ if (val > max_timeout) ++ timeout = max_timeout; ++ else ++ timeout = val; ++ + ath79_wdt_keepalive(); + + return 0; diff --git a/target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch b/target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch new file mode 100644 index 0000000..4e3ac70 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch @@ -0,0 +1,24 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -308,6 +308,11 @@ void __init ath79_wmac_disable_5ghz(void + ath79_wmac_data.disable_5ghz = true; + } + ++void __init ath79_wmac_set_tx_gain_buffalo(void) ++{ ++ ath79_wmac_data.tx_gain_buffalo = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -16,6 +16,7 @@ void ath79_register_wmac(u8 *cal_data, u + void ath79_register_wmac_simple(void); + void ath79_wmac_disable_2ghz(void); + void ath79_wmac_disable_5ghz(void); ++void ath79_wmac_set_tx_gain_buffalo(void); + + bool ar93xx_wmac_read_mac_address(u8 *dest); + diff --git a/target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch b/target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch new file mode 100644 index 0000000..a832bf8 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch @@ -0,0 +1,76 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -18,9 +18,11 @@ + #include + #include + #include ++#include + + #include + #include ++#include "common.h" + #include "dev-wmac.h" + + static u8 ath79_wmac_mac[ETH_ALEN]; +@@ -313,6 +315,51 @@ void __init ath79_wmac_set_tx_gain_buffa + ath79_wmac_data.tx_gain_buffalo = true; + } + ++static int ath79_request_ext_lna_gpio(unsigned chain, int gpio) ++{ ++ char buf[32]; ++ char *label; ++ int err; ++ ++ scnprintf(buf, sizeof(buf), "external LNA%u", chain); ++ label = kstrdup(buf, GFP_KERNEL); ++ ++ err = gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label); ++ if (err) { ++ pr_err("unable to request GPIO%d for external LNA%u\n", ++ gpio, chain); ++ kfree(label); ++ } ++ ++ return err; ++} ++ ++static void ar934x_set_ext_lna_gpio(unsigned chain, int gpio) ++{ ++ unsigned int sel; ++ int err; ++ ++ if (WARN_ON(chain > 1)) ++ return; ++ ++ err = ath79_request_ext_lna_gpio(chain, gpio); ++ if (err) ++ return; ++ ++ if (chain == 0) ++ sel = AR934X_GPIO_OUT_EXT_LNA0; ++ else ++ sel = AR934X_GPIO_OUT_EXT_LNA1; ++ ++ ath79_gpio_output_select(gpio, sel); ++} ++ ++void __init ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio) ++{ ++ if (soc_is_ar934x()) ++ ar934x_set_ext_lna_gpio(chain, gpio); ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -17,6 +17,7 @@ void ath79_register_wmac_simple(void); + void ath79_wmac_disable_2ghz(void); + void ath79_wmac_disable_5ghz(void); + void ath79_wmac_set_tx_gain_buffalo(void); ++void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio); + + bool ar93xx_wmac_read_mac_address(u8 *dest); + diff --git a/target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch b/target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch new file mode 100644 index 0000000..60872ae --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/ath79/mach-ap83.c ++++ b/arch/mips/ath79/mach-ap83.c +@@ -42,41 +42,8 @@ + #define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) + +-static struct mtd_partition ap83_flash_partitions[] = { +- { +- .name = "u-boot", +- .offset = 0, +- .size = 0x040000, +- .mask_flags = MTD_WRITEABLE, +- }, { +- .name = "u-boot-env", +- .offset = 0x040000, +- .size = 0x020000, +- .mask_flags = MTD_WRITEABLE, +- }, { +- .name = "kernel", +- .offset = 0x060000, +- .size = 0x140000, +- }, { +- .name = "rootfs", +- .offset = 0x1a0000, +- .size = 0x650000, +- }, { +- .name = "art", +- .offset = 0x7f0000, +- .size = 0x010000, +- .mask_flags = MTD_WRITEABLE, +- }, { +- .name = "firmware", +- .offset = 0x060000, +- .size = 0x790000, +- } +-}; +- + static struct physmap_flash_data ap83_flash_data = { + .width = 2, +- .parts = ap83_flash_partitions, +- .nr_parts = ARRAY_SIZE(ap83_flash_partitions), + }; + + static struct resource ap83_flash_resources[] = { diff --git a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch new file mode 100644 index 0000000..58ca1d5 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -0,0 +1,721 @@ +From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001 +Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net> +From: Matthias Schiffer +Date: Sat, 29 Mar 2014 20:26:08 +0100 +Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC + +Note that the clock calculation looks very similar to the QCA955x, but the +meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. +--- + arch/mips/ath79/Kconfig | 6 +- + arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++ + arch/mips/ath79/common.c | 4 ++ + arch/mips/ath79/dev-common.c | 1 + + arch/mips/ath79/dev-wmac.c | 20 +++++++ + arch/mips/ath79/early_printk.c | 1 + + arch/mips/ath79/gpio.c | 4 +- + arch/mips/ath79/irq.c | 4 ++ + arch/mips/ath79/setup.c | 8 ++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++ + arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++ + 11 files changed, 182 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -105,6 +105,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA953X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config SOC_QCA955X + select HW_HAS_PCI + select PCI_AR724X if PCI +@@ -144,7 +148,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) + def_bool n + + config ATH79_NVRAM +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo + iounmap(dpll_base); + } + ++static void __init qca953x_clocks_init(void) ++{ ++ unsigned long ref_rate; ++ unsigned long cpu_rate; ++ unsigned long ddr_rate; ++ unsigned long ahb_rate; ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40) ++ ref_rate = 40 * 1000 * 1000; ++ else ++ ref_rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ref_rate / ref_div; ++ cpu_pll += frac * (ref_rate >> 6) / ref_div; ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ref_rate / ref_div; ++ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ cpu_rate = ref_rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ cpu_rate = cpu_pll / (postdiv + 1); ++ else ++ cpu_rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ddr_rate = ref_rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ddr_rate = ddr_pll / (postdiv + 1); ++ else ++ ddr_rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ahb_rate = ref_rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ahb_rate = ddr_pll / (postdiv + 1); ++ else ++ ahb_rate = cpu_pll / (postdiv + 1); ++ ++ ath79_add_sys_clkdev("ref", ref_rate); ++ ath79_add_sys_clkdev("cpu", cpu_rate); ++ ath79_add_sys_clkdev("ddr", ddr_rate); ++ ath79_add_sys_clkdev("ahb", ahb_rate); ++ ++ clk_add_alias("wdt", NULL, "ref", NULL); ++ clk_add_alias("uart", NULL, "ref", NULL); ++} ++ + static void __init qca955x_clocks_init(void) + { + unsigned long ref_rate; +@@ -447,6 +532,8 @@ void __init ath79_clocks_init(void) + ar933x_clocks_init(); + else if (soc_is_ar934x()) + ar934x_clocks_init(); ++ else if (soc_is_qca953x()) ++ qca953x_clocks_init(); + else if (soc_is_qca955x()) + qca955x_clocks_init(); + else +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca953x()) ++ reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca953x()) ++ reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -93,6 +93,7 @@ void __init ath79_register_uart(void) + soc_is_ar724x() || + soc_is_ar913x() || + soc_is_ar934x() || ++ soc_is_qca953x() || + soc_is_qca955x()) { + ath79_uart_data[0].uartclk = uart_clk_rate; + platform_device_register(&ath79_uart_device); +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void __init qca953x_usb_setup(void) ++{ ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ ++ ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE); ++ udelay(1000); ++ ++ ath79_device_reset_clear(QCA953X_RESET_USB_PHY); ++ udelay(1000); ++ ++ ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG); ++ udelay(1000); ++ ++ ath79_device_reset_clear(QCA953X_RESET_USB_HOST); ++ udelay(1000); ++ ++ ath79_usb_register("ehci-platform", -1, ++ QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++} ++ + static void qca955x_usb_reset_notifier(struct platform_device *pdev) + { + u32 base; +@@ -286,6 +310,8 @@ void __init ath79_register_usb(void) + ar933x_usb_setup(); + else if (soc_is_ar934x()) + ar934x_usb_setup(); ++ else if (soc_is_qca953x()) ++ qca953x_usb_setup(); + else if (soc_is_qca955x()) + qca955x_usb_setup(); + else +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void) + return -ETIMEDOUT; + } + +-static int ar933x_r1_get_wmac_revision(void) ++static int ar93xx_get_soc_revision(void) + { + return ath79_soc_rev; + } +@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi + ath79_wmac_data.is_clk_25mhz = true; + + if (ath79_soc_rev == 1) +- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + + ath79_wmac_data.external_reset = ar933x_wmac_reset; + } +@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + } + ++static void qca953x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca953x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ if (t & QCA953X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++ ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; ++} ++ + static void qca955x_wmac_setup(void) + { + u32 t; +@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_ + ar933x_wmac_setup(); + else if (soc_is_ar934x()) + ar934x_wmac_setup(); ++ else if (soc_is_qca953x()) ++ qca953x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); + else +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -114,6 +114,8 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: ++ case REV_ID_MAJOR_QCA9533: ++ case REV_ID_MAJOR_QCA9533_V2: + case REV_ID_MAJOR_QCA9556: + case REV_ID_MAJOR_QCA9558: + _prom_putchar = prom_putchar_ar71xx; +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func + soc_is_ar913x() || + soc_is_ar933x()) + reg = AR71XX_GPIO_REG_FUNC; +- else if (soc_is_ar934x()) ++ else if (soc_is_ar934x() || soc_is_qca953x()) + reg = AR934X_GPIO_REG_FUNC; + else + BUG(); +@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns + unsigned int reg; + u32 t, s; + +- BUG_ON(!soc_is_ar934x()); ++ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x()); + + if (gpio >= AR934X_GPIO_COUNT) + return; +@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; ++ else if (soc_is_qca953x()) ++ ath79_gpio_count = QCA953X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; + else +@@ -231,7 +233,7 @@ void __init ath79_gpio_init(void) + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x() || soc_is_qca955x()) { ++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v + else if (soc_is_ar724x() || + soc_is_ar933x() || + soc_is_ar934x() || ++ soc_is_qca953x() || + soc_is_qca955x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else +@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void) + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + } + ++static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); ++ ++ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { ++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE); ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { ++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC); ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } else { ++ spurious_interrupt(); ++ } ++ ++ enable_irq(irq); ++} ++ ++static void qca953x_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); ++} ++ + static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) + { + u32 status; +@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void) + do_IRQ(ATH79_CPU_IRQ(3)); + } + ++static void qca953x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); ++} ++ + void __init arch_init_irq(void) + { + if (soc_is_ar71xx()) { +@@ -352,6 +391,9 @@ void __init arch_init_irq(void) + } else if (soc_is_ar934x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ar934x_ip3_handler; ++ } else if (soc_is_qca953x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = qca953x_ip3_handler; + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; +@@ -364,6 +406,8 @@ void __init arch_init_irq(void) + + if (soc_is_ar934x()) + ar934x_ip2_irq_init(); ++ else if (soc_is_qca953x()) ++ qca953x_irq_init(); + else if (soc_is_qca955x()) + qca955x_irq_init(); + } +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type + u32 major; + u32 minor; + u32 rev = 0; ++ u32 ver = 1; + + id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; +@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9533_V2: ++ ver = 2; ++ /* drop through */ ++ ++ case REV_ID_MAJOR_QCA9533: ++ ath79_soc = ATH79_SOC_QCA9533; ++ chip = "9533"; ++ rev = id & QCA953X_REV_ID_REVISION_MASK; ++ break; ++ + case REV_ID_MAJOR_QCA9556: + ath79_soc = ATH79_SOC_QCA9556; + chip = "9556"; +@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type + + ath79_soc_rev = rev; + +- if (soc_is_qca955x()) ++ if (soc_is_qca953x() || soc_is_qca955x()) + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", + chip, rev); + else +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -105,6 +105,21 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA953X_GMAC_SIZE 0x14 ++#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA953X_WMAC_SIZE 0x20000 ++#define QCA953X_EHCI_BASE 0x1b000000 ++#define QCA953X_EHCI_SIZE 0x200 ++#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) ++#define QCA953X_SRIF_SIZE 0x1000 ++ ++#define QCA953X_PCI_CFG_BASE0 0x14000000 ++#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) ++#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) ++#define QCA953X_PCI_MEM_BASE0 0x10000000 ++#define QCA953X_PCI_MEM_SIZE 0x02000000 ++ + #define QCA955X_PCI_MEM_BASE0 0x10000000 + #define QCA955X_PCI_MEM_BASE1 0x12000000 + #define QCA955X_PCI_MEM_SIZE 0x02000000 +@@ -173,6 +188,12 @@ + #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 + #define AR934X_DDR_REG_FLUSH_WMAC 0xac + ++#define QCA953X_DDR_REG_FLUSH_GE0 0x9c ++#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 ++#define QCA953X_DDR_REG_FLUSH_USB 0xa4 ++#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 ++#define QCA953X_DDR_REG_FLUSH_WMAC 0xac ++ + /* + * PLL block + */ +@@ -279,6 +300,44 @@ + + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + ++#define QCA953X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA953X_PLL_DDR_CONFIG_REG 0x04 ++#define QCA953X_PLL_CLK_CTRL_REG 0x08 ++#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 ++#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c ++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 ++ ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 +@@ -355,6 +414,10 @@ + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + ++#define QCA953X_RESET_REG_RESET_MODULE 0x1c ++#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac ++ + #define QCA955X_RESET_REG_RESET_MODULE 0x1c + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac +@@ -450,6 +513,27 @@ + #define AR934X_RESET_MBOX BIT(1) + #define AR934X_RESET_I2S BIT(0) + ++#define QCA953X_RESET_USB_EXT_PWR BIT(29) ++#define QCA953X_RESET_EXTERNAL BIT(28) ++#define QCA953X_RESET_RTC BIT(27) ++#define QCA953X_RESET_FULL_CHIP BIT(24) ++#define QCA953X_RESET_GE1_MDIO BIT(23) ++#define QCA953X_RESET_GE0_MDIO BIT(22) ++#define QCA953X_RESET_CPU_NMI BIT(21) ++#define QCA953X_RESET_CPU_COLD BIT(20) ++#define QCA953X_RESET_DDR BIT(16) ++#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define QCA953X_RESET_GE1_MAC BIT(13) ++#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) ++#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) ++#define QCA953X_RESET_GE0_MAC BIT(9) ++#define QCA953X_RESET_ETH_SWITCH BIT(8) ++#define QCA953X_RESET_PCIE_PHY BIT(7) ++#define QCA953X_RESET_PCIE BIT(6) ++#define QCA953X_RESET_USB_HOST BIT(5) ++#define QCA953X_RESET_USB_PHY BIT(4) ++#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) ++ + #define QCA955X_RESET_HOST BIT(31) + #define QCA955X_RESET_SLIC BIT(30) + #define QCA955X_RESET_HDMA BIT(29) +@@ -503,6 +587,13 @@ + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) ++#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) ++#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) ++#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) ++#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) ++#define QCA953X_BOOTSTRAP_DDR1 BIT(0) ++ + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +@@ -523,6 +614,24 @@ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + ++#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) ++#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) ++#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) ++#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) ++#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ ++ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ ++ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) ++ ++#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ ++ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ ++ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ ++ QCA953X_PCIE_WMAC_INT_PCIE_RC3) ++ + #define QCA955X_EXT_INT_WMAC_MISC BIT(0) + #define QCA955X_EXT_INT_WMAC_TX BIT(1) + #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +@@ -565,6 +674,8 @@ + #define REV_ID_MAJOR_AR9341 0x0120 + #define REV_ID_MAJOR_AR9342 0x1120 + #define REV_ID_MAJOR_AR9344 0x2120 ++#define REV_ID_MAJOR_QCA9533 0x0140 ++#define REV_ID_MAJOR_QCA9533_V2 0x0160 + #define REV_ID_MAJOR_QCA9556 0x0130 + #define REV_ID_MAJOR_QCA9558 0x1130 + +@@ -587,6 +698,8 @@ + + #define AR934X_REV_ID_REVISION_MASK 0xf + ++#define QCA953X_REV_ID_REVISION_MASK 0xf ++ + #define QCA955X_REV_ID_REVISION_MASK 0xf + + /* +@@ -634,12 +747,32 @@ + #define AR934X_GPIO_REG_OUT_FUNC5 0x40 + #define AR934X_GPIO_REG_FUNC 0x6c + ++#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c ++#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 ++#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 ++#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 ++#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c ++#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 ++#define QCA953X_GPIO_REG_FUNC 0x6c ++ ++#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 ++#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 ++#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 ++#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 ++#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 ++ + #define AR71XX_GPIO_COUNT 16 + #define AR7240_GPIO_COUNT 18 + #define AR7241_GPIO_COUNT 20 + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 ++#define QCA953X_GPIO_COUNT 18 + #define QCA955X_GPIO_COUNT 24 + + /* +@@ -663,6 +796,24 @@ + #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + ++#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 ++#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 ++#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 ++ ++#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 ++#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 ++#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 ++ ++#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 ++#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f ++#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 ++#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff ++#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff ++ ++#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) ++#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 ++#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 ++ + #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) + #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) + #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +@@ -804,6 +955,16 @@ + #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + + /* ++ * QCA953X GMAC Interface ++ */ ++#define QCA953X_GMAC_REG_ETH_CFG 0x00 ++ ++#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) ++#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) ++#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++ ++/* + * QCA955X GMAC Interface + */ + +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,7 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + }; +@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9533(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9533; ++} ++ ++static inline int soc_is_qca953x(void) ++{ ++ return soc_is_qca9533(); ++} ++ + static inline int soc_is_qca9556(void) + { + return ath79_soc == ATH79_SOC_QCA9556; diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch new file mode 100644 index 0000000..b23c18e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch @@ -0,0 +1,700 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -114,6 +114,12 @@ config SOC_QCA955X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA956X ++ select USB_ARCH_HAS_EHCI ++ select HW_HAS_PCI ++ select PCI_AR724X if PCI ++ def_bool n ++ + config ATH79_DEV_M25P80 + select ATH79_DEV_SPI + def_bool n +@@ -148,7 +154,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X) + def_bool n + + config ATH79_NVRAM +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v + clk_add_alias("uart", NULL, "ref", NULL); + } + ++static void __init qca956x_clocks_init(void) ++{ ++ unsigned long ref_rate; ++ unsigned long cpu_rate; ++ unsigned long ddr_rate; ++ unsigned long ahb_rate; ++ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) ++ ref_rate = 40 * 1000 * 1000; ++ else ++ ref_rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; ++ ++ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); ++ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG1_NINT_MASK; ++ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK; ++ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK; ++ ++ cpu_pll = nint * ref_rate / ref_div; ++ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); ++ cpu_pll += (hfrac >> 13) * ref_rate / ref_div; ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; ++ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); ++ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG1_NINT_MASK; ++ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK; ++ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK; ++ ++ ddr_pll = nint * ref_rate / ref_div; ++ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); ++ ddr_pll += (hfrac >> 13) * ref_rate / ref_div; ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ cpu_rate = ref_rate; ++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) ++ cpu_rate = ddr_pll / (postdiv + 1); ++ else ++ cpu_rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ddr_rate = ref_rate; ++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) ++ ddr_rate = cpu_pll / (postdiv + 1); ++ else ++ ddr_rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ahb_rate = ref_rate; ++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ahb_rate = ddr_pll / (postdiv + 1); ++ else ++ ahb_rate = cpu_pll / (postdiv + 1); ++ ++ ath79_add_sys_clkdev("ref", ref_rate); ++ ath79_add_sys_clkdev("cpu", cpu_rate); ++ ath79_add_sys_clkdev("ddr", ddr_rate); ++ ath79_add_sys_clkdev("ahb", ahb_rate); ++ ++ clk_add_alias("wdt", NULL, "ref", NULL); ++ clk_add_alias("uart", NULL, "ref", NULL); ++} ++ + void __init ath79_clocks_init(void) + { + if (soc_is_ar71xx()) +@@ -536,6 +630,8 @@ void __init ath79_clocks_init(void) + qca953x_clocks_init(); + else if (soc_is_qca955x()) + qca955x_clocks_init(); ++ else if (soc_is_qca956x()) ++ qca956x_clocks_init(); + else + BUG(); + } +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca956x()) ++ reg = QCA956X_RESET_REG_RESET_MODULE; + else + panic("Reset register not defined for this SOC"); + +@@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca956x()) ++ reg = QCA956X_RESET_REG_RESET_MODULE; + else + panic("Reset register not defined for this SOC"); + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -94,7 +94,8 @@ void __init ath79_register_uart(void) + soc_is_ar913x() || + soc_is_ar934x() || + soc_is_qca953x() || +- soc_is_qca955x()) { ++ soc_is_qca955x() || ++ soc_is_qca956x()) { + ath79_uart_data[0].uartclk = uart_clk_rate; + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void __init qca956x_usb_setup(void) ++{ ++ ath79_usb_register("ehci-platform", 0, ++ QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE, ++ ATH79_IP3_IRQ(0), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++ ++ ath79_usb_register("ehci-platform", 1, ++ QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE, ++ ATH79_IP3_IRQ(1), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++} ++ + void __init ath79_register_usb(void) + { + if (soc_is_ar71xx()) +@@ -314,6 +327,8 @@ void __init ath79_register_usb(void) + qca953x_usb_setup(); + else if (soc_is_qca955x()) + qca955x_usb_setup(); ++ else if (soc_is_qca9561()) ++ qca956x_usb_setup(); + else + BUG(); + } +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static void qca956x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca956x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA956X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); ++ if (t & QCA956X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + static bool __init + ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) + { +@@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_ + qca953x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); ++ else if (soc_is_qca956x()) ++ qca956x_wmac_setup(); + else + BUG(); + +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -118,6 +118,8 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_QCA9533_V2: + case REV_ID_MAJOR_QCA9556: + case REV_ID_MAJOR_QCA9558: ++ case REV_ID_MAJOR_TP9343: ++ case REV_ID_MAJOR_QCA9561: + _prom_putchar = prom_putchar_ar71xx; + break; + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func + soc_is_ar913x() || + soc_is_ar933x()) + reg = AR71XX_GPIO_REG_FUNC; +- else if (soc_is_ar934x() || soc_is_qca953x()) ++ else if (soc_is_ar934x() || ++ soc_is_qca953x() || soc_is_qca956x()) + reg = AR934X_GPIO_REG_FUNC; + else + BUG(); +@@ -228,12 +229,15 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = QCA953X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; ++ else if (soc_is_qca956x()) ++ ath79_gpio_count = QCA956X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { ++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() || ++ soc_is_qca956x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v + soc_is_ar933x() || + soc_is_ar934x() || + soc_is_qca953x() || +- soc_is_qca955x()) ++ soc_is_qca955x() || ++ soc_is_qca956x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else + BUG(); +@@ -268,6 +269,97 @@ static void qca955x_irq_init(void) + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); + } + ++static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } ++ ++ if (status & QCA956X_EXT_INT_WMAC_ALL) { ++ /* TODO: flsuh DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA956X_EXT_INT_PCIE_RC2_ALL | ++ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA956X_EXT_INT_USB1) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(0)); ++ } ++ ++ if (status & QCA956X_EXT_INT_USB2) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(1)); ++ } ++ ++ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(2)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca956x_enable_timer_cb(void) { ++ u32 misc; ++ ++ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); ++ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; ++ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); ++} ++ ++static void qca956x_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); ++ ++ for (i = ATH79_IP3_IRQ_BASE; ++ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); ++ ++ /* QCA956x timer init workaround has to be applied right before setting ++ * up the clock. Else, there will be no jiffies */ ++ late_time_init = &qca956x_enable_timer_cb; ++} ++ + asmlinkage void plat_irq_dispatch(void) + { + unsigned long pending; +@@ -397,6 +489,9 @@ void __init arch_init_irq(void) + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; ++ } else if (soc_is_qca956x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = ath79_default_ip3_handler; + } else { + BUG(); + } +@@ -410,4 +505,6 @@ void __init arch_init_irq(void) + qca953x_irq_init(); + else if (soc_is_qca955x()) + qca955x_irq_init(); ++ else if (soc_is_qca956x()) ++ qca956x_irq_init(); + } +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955 + }, + }; + ++static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = { ++ { ++ .bus = 0, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, ++ { ++ .bus = 1, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(1), ++ }, ++}; ++ + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { + int irq = -1; +@@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct + } else if (soc_is_qca955x()) { + ath79_pci_irq_map = qca955x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); ++ } else if (soc_is_qca9561()) { ++ ath79_pci_irq_map = qca956x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map); + } else { + pr_crit("pci %s: invalid irq map\n", + pci_name((struct pci_dev *) dev)); +@@ -303,6 +321,15 @@ int __init ath79_register_pci(void) + QCA955X_PCI_MEM_SIZE, + 1, + ATH79_IP3_IRQ(2)); ++ } else if (soc_is_qca9561()) { ++ pdev = ath79_register_pci_ar724x(0, ++ QCA956X_PCI_CFG_BASE1, ++ QCA956X_PCI_CTRL_BASE1, ++ QCA956X_PCI_CRP_BASE1, ++ QCA956X_PCI_MEM_BASE1, ++ QCA956X_PCI_MEM_SIZE, ++ 1, ++ ATH79_IP3_IRQ(2)); + } else { + /* No PCI support */ + return -ENODEV; +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_TP9343: ++ ath79_soc = ATH79_SOC_TP9343; ++ chip = "9343"; ++ rev = id & QCA956X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_QCA9561: ++ ath79_soc = ATH79_SOC_QCA9561; ++ chip = "9561"; ++ rev = id & QCA956X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } + + ath79_soc_rev = rev; + +- if (soc_is_qca953x() || soc_is_qca955x()) +- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", ++ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", ++ chip, ver, rev); ++ else if (soc_is_tp9343()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", + chip, rev); + else + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -143,6 +143,23 @@ + #define QCA955X_NFC_BASE 0x1b800200 + #define QCA955X_NFC_SIZE 0xb8 + ++#define QCA956X_PCI_MEM_BASE1 0x12000000 ++#define QCA956X_PCI_MEM_SIZE 0x02000000 ++#define QCA956X_PCI_CFG_BASE1 0x16000000 ++#define QCA956X_PCI_CFG_SIZE 0x1000 ++#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) ++#define QCA956X_PCI_CRP_SIZE 0x1000 ++#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) ++#define QCA956X_PCI_CTRL_SIZE 0x100 ++ ++#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA956X_WMAC_SIZE 0x20000 ++#define QCA956X_EHCI0_BASE 0x1b000000 ++#define QCA956X_EHCI1_BASE 0x1b400000 ++#define QCA956X_EHCI_SIZE 0x200 ++#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA956X_GMAC_SIZE 0x64 ++ + #define AR9300_OTP_BASE 0x14000 + #define AR9300_OTP_STATUS 0x15f18 + #define AR9300_OTP_STATUS_TYPE 0x7 +@@ -375,6 +392,49 @@ + #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA956X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 ++#define QCA956X_PLL_DDR_CONFIG_REG 0x08 ++#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c ++#define QCA956X_PLL_CLK_CTRL_REG 0x10 ++ ++#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff ++#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 ++#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff ++ ++#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff ++#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 ++#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff ++ ++#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) ++#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) ++#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + /* + * USB_CONFIG block + */ +@@ -422,6 +482,11 @@ + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + ++#define QCA956X_RESET_REG_RESET_MODULE 0x1c ++#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac ++ ++#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) + #define MISC_INT_TIMER3 BIT(9) +@@ -596,6 +661,8 @@ + + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + ++#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) ++ + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) + #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) + #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +@@ -663,6 +730,37 @@ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + ++#define QCA956X_EXT_INT_WMAC_MISC BIT(0) ++#define QCA956X_EXT_INT_WMAC_TX BIT(1) ++#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) ++#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) ++#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) ++#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) ++#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) ++#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) ++#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) ++#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) ++#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) ++#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) ++#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) ++#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) ++#define QCA956X_EXT_INT_USB1 BIT(24) ++#define QCA956X_EXT_INT_USB2 BIT(28) ++ ++#define QCA956X_EXT_INT_WMAC_ALL \ ++ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ ++ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) ++ ++#define QCA956X_EXT_INT_PCIE_RC1_ALL \ ++ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ ++ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ ++ QCA956X_EXT_INT_PCIE_RC1_INT3) ++ ++#define QCA956X_EXT_INT_PCIE_RC2_ALL \ ++ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ ++ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ ++ QCA956X_EXT_INT_PCIE_RC2_INT3) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 +@@ -678,6 +776,8 @@ + #define REV_ID_MAJOR_QCA9533_V2 0x0160 + #define REV_ID_MAJOR_QCA9556 0x0130 + #define REV_ID_MAJOR_QCA9558 0x1130 ++#define REV_ID_MAJOR_TP9343 0x0150 ++#define REV_ID_MAJOR_QCA9561 0x1150 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 + #define AR71XX_REV_ID_MINOR_AR7130 0x0 +@@ -702,6 +802,8 @@ + + #define QCA955X_REV_ID_REVISION_MASK 0xf + ++#define QCA956X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +@@ -766,6 +868,19 @@ + #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 + #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + ++#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c ++#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 ++#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 ++#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 ++#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c ++#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 ++#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 ++#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 ++#define QCA956X_GPIO_REG_FUNC 0x6c ++ ++#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 ++#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 ++ + #define AR71XX_GPIO_COUNT 16 + #define AR7240_GPIO_COUNT 18 + #define AR7241_GPIO_COUNT 20 +@@ -774,6 +889,7 @@ + #define AR934X_GPIO_COUNT 23 + #define QCA953X_GPIO_COUNT 18 + #define QCA955X_GPIO_COUNT 24 ++#define QCA956X_GPIO_COUNT 23 + + /* + * SRIF block +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -35,6 +35,8 @@ enum ath79_soc_type { + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, ++ ATH79_SOC_TP9343, ++ ATH79_SOC_QCA9561, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void) + return soc_is_qca9556() || soc_is_qca9558(); + } + ++static inline int soc_is_tp9343(void) ++{ ++ return ath79_soc == ATH79_SOC_TP9343; ++} ++ ++static inline int soc_is_qca9561(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9561; ++} ++ ++static inline int soc_is_qca956x(void) ++{ ++ return soc_is_tp9343() || soc_is_qca9561(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_gpio_base; + extern void __iomem *ath79_pll_base; diff --git a/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch new file mode 100644 index 0000000..8c0cc95 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch @@ -0,0 +1,100 @@ +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -26,6 +26,8 @@ + + static void (*ath79_ip2_handler)(void); + static void (*ath79_ip3_handler)(void); ++static struct irq_chip ip2_chip; ++static struct irq_chip ip3_chip; + + static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) + { +@@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + } +@@ -182,7 +183,7 @@ static void qca953x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); + } +@@ -256,15 +257,13 @@ static void qca955x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); ++ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); + } +@@ -345,13 +344,13 @@ static void qca956x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); + +@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void) + do_IRQ(ATH79_CPU_IRQ(3)); + } + ++static void ath79_ip2_disable(struct irq_data *data) ++{ ++ disable_irq(ATH79_CPU_IRQ(2)); ++} ++ ++static void ath79_ip2_enable(struct irq_data *data) ++{ ++ enable_irq(ATH79_CPU_IRQ(2)); ++} ++ ++static void ath79_ip3_disable(struct irq_data *data) ++{ ++ disable_irq(ATH79_CPU_IRQ(3)); ++} ++ ++static void ath79_ip3_enable(struct irq_data *data) ++{ ++ enable_irq(ATH79_CPU_IRQ(3)); ++} ++ + void __init arch_init_irq(void) + { ++ ip2_chip = dummy_irq_chip; ++ ip3_chip = dummy_irq_chip; ++ ip2_chip.irq_disable = ath79_ip2_disable; ++ ip2_chip.irq_enable = ath79_ip2_enable; ++ ip3_chip.irq_disable = ath79_ip3_disable; ++ ip3_chip.irq_enable = ath79_ip3_enable; ++ + if (soc_is_ar71xx()) { + ath79_ip2_handler = ar71xx_ip2_handler; + ath79_ip3_handler = ar71xx_ip3_handler; diff --git a/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch b/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch new file mode 100644 index 0000000..03b32b1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch @@ -0,0 +1,24 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -398,6 +398,11 @@ void __init ath79_wmac_set_ext_lna_gpio( + ar934x_set_ext_lna_gpio(chain, gpio); + } + ++void __init ath79_wmac_set_led_pin(int gpio) ++{ ++ ath79_wmac_data.led_pin = gpio; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void); + void ath79_wmac_disable_5ghz(void); + void ath79_wmac_set_tx_gain_buffalo(void); + void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio); ++void ath79_wmac_set_led_pin(int gpio); + + bool ar93xx_wmac_read_mac_address(u8 *dest); + diff --git a/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch new file mode 100644 index 0000000..c628f1d --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch @@ -0,0 +1,43 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); + void ath79_gpio_output_select(unsigned gpio, u8 val); ++int ath79_gpio_direction_select(unsigned gpio, bool oe); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output( + return 0; + } + ++int ath79_gpio_direction_select(unsigned gpio, bool oe) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ bool ieq_1 = (soc_is_ar934x() || ++ soc_is_qca953x()); ++ ++ if (gpio >= ath79_gpio_count) ++ return -1; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ if ((ieq_1 && oe) || (!ieq_1 && !oe)) ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio), ++ base + AR71XX_GPIO_REG_OE); ++ else ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ + static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, diff --git a/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch b/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch new file mode 100644 index 0000000..e8183e7 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch @@ -0,0 +1,224 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -20,9 +20,14 @@ + #include + #include + #include ++#include ++#include ++ ++#include + + #include + #include ++#include + #include "common.h" + + void __iomem *ath79_gpio_base; +@@ -31,6 +36,13 @@ EXPORT_SYMBOL_GPL(ath79_gpio_base); + static unsigned long ath79_gpio_count; + static DEFINE_SPINLOCK(ath79_gpio_lock); + ++/* ++ * gpio_both_edge is a bitmask of which gpio pins need to have ++ * the detect priority flipped from the interrupt handler to ++ * emulate IRQ_TYPE_EDGE_BOTH. ++ */ ++static unsigned long gpio_both_edge = 0; ++ + static void __ath79_gpio_set_value(unsigned gpio, int value) + { + void __iomem *base = ath79_gpio_base; +@@ -233,6 +245,132 @@ void __init ath79_gpio_output_select(uns + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + ++static int ath79_gpio_irq_type(struct irq_data *d, unsigned type) ++{ ++ int offset = d->irq - ATH79_GPIO_IRQ_BASE; ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ unsigned long int_type; ++ unsigned long int_polarity; ++ unsigned long bit = (1 << offset); ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE); ++ int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY); ++ ++ gpio_both_edge &= ~bit; ++ ++ switch (type) { ++ case IRQ_TYPE_EDGE_RISING: ++ int_type &= ~bit; ++ int_polarity |= bit; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ int_type &= ~bit; ++ int_polarity &= ~bit; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ int_type |= bit; ++ int_polarity |= bit; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ int_type |= bit; ++ int_polarity &= ~bit; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ int_type |= bit; ++ /* set polarity based on current value */ ++ if (gpio_get_value(offset)) { ++ int_polarity &= ~bit; ++ } else { ++ int_polarity |= bit; ++ } ++ /* flip this gpio in the interrupt handler */ ++ gpio_both_edge |= bit; ++ break; ++ ++ default: ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ return -EINVAL; ++ } ++ ++ __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE); ++ __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 << offset), ++ base + AR71XX_GPIO_REG_INT_MODE); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset), ++ base + AR71XX_GPIO_REG_INT_ENABLE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ return 0; ++} ++ ++static void ath79_gpio_irq_enable(struct irq_data *d) ++{ ++ int offset = d->irq - ATH79_GPIO_IRQ_BASE; ++ void __iomem *base = ath79_gpio_base; ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 << offset), ++ base + AR71XX_GPIO_REG_INT_ENABLE); ++} ++ ++static void ath79_gpio_irq_disable(struct irq_data *d) ++{ ++ int offset = d->irq - ATH79_GPIO_IRQ_BASE; ++ void __iomem *base = ath79_gpio_base; ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset), ++ base + AR71XX_GPIO_REG_INT_ENABLE); ++} ++ ++static struct irq_chip ath79_gpio_irqchip = { ++ .name = "GPIO", ++ .irq_enable = ath79_gpio_irq_enable, ++ .irq_disable = ath79_gpio_irq_disable, ++ .irq_set_type = ath79_gpio_irq_type, ++}; ++ ++static irqreturn_t ath79_gpio_irq(int irq, void *dev) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING); ++ int bit_num; ++ ++ for_each_set_bit(bit_num, &stat, sizeof(stat) * BITS_PER_BYTE) { ++ unsigned long bit = BIT(bit_num); ++ ++ if (bit & gpio_both_edge) { ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY) ^ bit, ++ base + AR71XX_GPIO_REG_INT_POLARITY); ++ } ++ ++ generic_handle_irq(ATH79_GPIO_IRQ(bit_num)); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init ath79_gpio_irq_init(struct gpio_chip *chip) ++{ ++ int irq; ++ int irq_base = ATH79_GPIO_IRQ_BASE; ++ ++ for (irq = irq_base; irq < irq_base + chip->ngpio; irq++) { ++ irq_set_chip_data(irq, chip); ++ irq_set_chip_and_handler(irq, &ath79_gpio_irqchip, handle_simple_irq); ++ irq_set_noprobe(irq); ++ } ++ ++ return 0; ++} ++ + void __init ath79_gpio_init(void) + { + int err; +@@ -269,6 +407,10 @@ void __init ath79_gpio_init(void) + err = gpiochip_add(&ath79_gpio_chip); + if (err) + panic("cannot add AR71xx GPIO chip, error=%d", err); ++ ++ ath79_gpio_irq_init(&ath79_gpio_chip); ++ ++ request_irq(ATH79_MISC_IRQ(2), ath79_gpio_irq, 0, "ath79-gpio", NULL); + } + + int gpio_get_value(unsigned gpio) +@@ -291,14 +433,22 @@ EXPORT_SYMBOL(gpio_set_value); + + int gpio_to_irq(unsigned gpio) + { +- /* FIXME */ +- return -EINVAL; ++ if (gpio > ath79_gpio_count) { ++ return -EINVAL; ++ } ++ ++ return ATH79_GPIO_IRQ_BASE + gpio; + } + EXPORT_SYMBOL(gpio_to_irq); + + int irq_to_gpio(unsigned irq) + { +- /* FIXME */ +- return -EINVAL; ++ unsigned gpio = irq - ATH79_GPIO_IRQ_BASE; ++ ++ if (gpio > ath79_gpio_count) { ++ return -EINVAL; ++ } ++ ++ return gpio; + } + EXPORT_SYMBOL(irq_to_gpio); +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,7 +10,7 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 51 ++#define NR_IRQS 83 + + #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) + +@@ -30,6 +30,10 @@ + #define ATH79_IP3_IRQ_COUNT 3 + #define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) + ++#define ATH79_GPIO_IRQ_BASE (ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT) ++#define ATH79_GPIO_IRQ_COUNT 32 ++#define ATH79_GPIO_IRQ(_x) (ATH79_GPIO_IRQ_BASE + (_x)) ++ + #include_next + + #endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch new file mode 100644 index 0000000..16d4621 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -25,7 +25,7 @@ + #include "common.h" + + #define AR71XX_BASE_FREQ 40000000 +-#define AR724X_BASE_FREQ 5000000 ++#define AR724X_BASE_FREQ 40000000 + #define AR913X_BASE_FREQ 5000000 + + struct clk { +@@ -99,8 +99,8 @@ + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ref_rate; + +- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); +- freq *= div; ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; ++ freq /= div; + + cpu_rate = freq; + diff --git a/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch new file mode 100644 index 0000000..8ee0d3f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch @@ -0,0 +1,1737 @@ +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -16,24 +16,210 @@ + + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, ++ ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */ ++ ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */ ++ ATH79_MACH_ALL0258N, /* Allnet ALL0258N */ ++ ATH79_MACH_ALL0305, /* Allnet ALL0305 */ ++ ATH79_MACH_ALL0315N, /* Allnet ALL0315N */ ++ ATH79_MACH_ANTMINER_S1, /* Bitmain Antminer S1 */ ++ ATH79_MACH_ANTMINER_S3, /* Bitmain Antminer S3 */ ++ ATH79_MACH_AP113, /* Atheros AP113 reference board */ + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ ++ ATH79_MACH_AP132, /* Atheros AP132 reference board */ + ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ ++ ATH79_MACH_AP143, /* Atheros AP143 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ++ ATH79_MACH_AP83, /* Atheros AP83 */ ++ ATH79_MACH_AP96, /* Atheros AP96 */ ++ ATH79_MACH_ARCHER_C5, /* TP-LINK Archer C5 board */ ++ ATH79_MACH_ARCHER_C7, /* TP-LINK Archer C7 board */ ++ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */ ++ ATH79_MACH_BHU_BXU2000N2_A1, /* BHU BXU2000n-2 A1 */ ++ ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */ ++ ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */ ++ ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */ ++ ATH79_MACH_CPE510, /* TP-LINK CPE510 */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ ++ ATH79_MACH_DGL_5500_A1, /* D-link DGL-5500 rev. A1 */ ++ ATH79_MACH_DHP_1565_A1, /* D-Link DHP-1565 rev. A1 */ ++ ATH79_MACH_DIR_505_A1, /* D-Link DIR-505 rev. A1 */ ++ ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ ++ ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ ++ ATH79_MACH_DIR_615_E1, /* D-Link DIR-615 rev. E1 */ ++ ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */ ++ ATH79_MACH_DIR_615_I1, /* D-Link DIR-615 rev. I1 */ ++ ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ ++ ATH79_MACH_DIR_825_C1, /* D-Link DIR-825 rev. C1 */ ++ ATH79_MACH_DIR_835_A1, /* D-Link DIR-835 rev. A1 */ ++ ATH79_MACH_DLAN_PRO_500_WP, /* devolo dLAN pro 500 Wireless+ */ ++ ATH79_MACH_DLAN_PRO_1200_AC, /* devolo dLAN pro 1200+ WiFi ac*/ ++ ATH79_MACH_DRAGINO2, /* Dragino Version 2 */ ++ ATH79_MACH_ESR900, /* EnGenius ESR900 */ ++ ATH79_MACH_EW_DORIN, /* embedded wireless Dorin Platform */ ++ ATH79_MACH_EW_DORIN_ROUTER, /* embedded wireless Dorin Router Platform */ ++ ATH79_MACH_EAP300V2, /* EnGenius EAP300 v2 */ ++ ATH79_MACH_EAP7660D, /* Senao EAP7660D */ ++ ATH79_MACH_EL_M150, /* EasyLink EL-M150 */ ++ ATH79_MACH_EL_MINI, /* EasyLink EL-MINI */ ++ ATH79_MACH_ESR1750, /* EnGenius ESR1750 */ ++ ATH79_MACH_EPG5000, /* EnGenius EPG5000 */ ++ ATH79_MACH_F9K1115V2, /* Belkin AC1750DB */ ++ ATH79_MACH_GL_INET, /* GL-CONNECT GL-INET */ ++ ATH79_MACH_GS_OOLITE, /* GS OOLITE V1.0 */ ++ ATH79_MACH_HIWIFI_HC6361, /* HiWiFi HC6361 */ ++ ATH79_MACH_JA76PF, /* jjPlus JA76PF */ ++ ATH79_MACH_JA76PF2, /* jjPlus JA76PF2 */ ++ ATH79_MACH_JWAP003, /* jjPlus JWAP003 */ ++ ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */ ++ ATH79_MACH_MR12, /* Cisco Meraki MR12 */ ++ ATH79_MACH_MR16, /* Cisco Meraki MR16 */ ++ ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */ ++ ATH79_MACH_MR600, /* OpenMesh MR600 */ ++ ATH79_MACH_MR900, /* OpenMesh MR900 */ ++ ATH79_MACH_MR900v2, /* OpenMesh MR900v2 */ ++ ATH79_MACH_MYNET_N600, /* WD My Net N600 */ ++ ATH79_MACH_MYNET_N750, /* WD My Net N750 */ ++ ATH79_MACH_MYNET_REXT, /* WD My Net Wi-Fi Range Extender */ ++ ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */ ++ ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */ ++ ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ ++ ATH79_MACH_NBG6716, /* Zyxel NBG6716 */ ++ ATH79_MACH_OM2P_HSv2, /* OpenMesh OM2P-HSv2 */ ++ ATH79_MACH_OM2P_HS, /* OpenMesh OM2P-HS */ ++ ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */ ++ ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */ ++ ATH79_MACH_OM2P, /* OpenMesh OM2P */ ++ ATH79_MACH_OM5P_AN, /* OpenMesh OM5P-AN */ ++ ATH79_MACH_OM5P, /* OpenMesh OM5P */ ++ ATH79_MACH_ONION_OMEGA, /* ONION OMEGA */ ++ ATH79_MACH_PB42, /* Atheros PB42 */ ++ ATH79_MACH_PB92, /* Atheros PB92 */ ++ ATH79_MACH_QIHOO_C301, /* Qihoo 360 C301 */ ++ ATH79_MACH_R6100, /* NETGEAR R6100 */ ++ ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ ++ ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ ++ ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ ++ ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ ++ ATH79_MACH_RB_435G, /* MikroTik RouterBOARD 435G */ ++ ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ ++ ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */ ++ ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ ++ ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */ ++ ATH79_MACH_RB_711GR100, /* Mikrotik RouterBOARD 911/912 boards */ ++ ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */ ++ ATH79_MACH_RB_750G_R3, /* MikroTik RouterBOARD 750GL */ ++ ATH79_MACH_RB_751, /* MikroTik RouterBOARD 751 */ ++ ATH79_MACH_RB_751G, /* Mikrotik RouterBOARD 751G */ ++ ATH79_MACH_RB_922GS, /* Mikrotik RouterBOARD 911/922GS boards */ ++ ATH79_MACH_RB_951G, /* Mikrotik RouterBOARD 951G */ ++ ATH79_MACH_RB_951U, /* Mikrotik RouterBOARD 951Ui-2HnD */ ++ ATH79_MACH_RB_2011G, /* Mikrotik RouterBOARD 2011UAS-2HnD */ ++ ATH79_MACH_RB_2011L, /* Mikrotik RouterBOARD 2011L */ ++ ATH79_MACH_RB_2011US, /* Mikrotik RouterBOARD 2011UAS */ ++ ATH79_MACH_RB_2011R5, /* Mikrotik RouterBOARD 2011UiAS(-2Hnd) */ ++ ATH79_MACH_RB_SXTLITE2ND, /* Mikrotik RouterBOARD SXT Lite 2nD */ ++ ATH79_MACH_RB_SXTLITE5ND, /* Mikrotik RouterBOARD SXT Lite 5nD */ ++ ATH79_MACH_RW2458N, /* Redwave RW2458N */ ++ ATH79_MACH_SMART_300, /* NC-LINK SMART-300 */ ++ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ ++ ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */ ++ ATH79_MACH_TEW_712BR, /* TRENDnet TEW-712BR */ ++ ATH79_MACH_TEW_732BR, /* TRENDnet TEW-732BR */ ++ ATH79_MACH_MC_MAC1200R, /* MERCURY MAC1200R*/ ++ ATH79_MACH_TL_MR10U, /* TP-LINK TL-MR10U */ ++ ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */ ++ ATH79_MACH_TL_MR13U, /* TP-LINK TL-MR13U */ ++ ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */ ++ ATH79_MACH_TL_MR3040, /* TP-LINK TL-MR3040 */ ++ ATH79_MACH_TL_MR3040_V2, /* TP-LINK TL-MR3040 v2 */ ++ ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */ ++ ATH79_MACH_TL_MR3220_V2, /* TP-LINK TL-MR3220 v2 */ ++ ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */ ++ ATH79_MACH_TL_MR3420_V2, /* TP-LINK TL-MR3420 v2 */ ++ ATH79_MACH_TL_WA701ND_V2, /* TP-LINK TL-WA701ND v2 */ ++ ATH79_MACH_TL_WA750RE, /* TP-LINK TL-WA750RE */ ++ ATH79_MACH_TL_WA7210N_V2, /* TP-LINK TL-WA7210N v2 */ ++ ATH79_MACH_TL_WA7510N_V1, /* TP-LINK TL-WA7510N v1*/ ++ ATH79_MACH_TL_WA850RE, /* TP-LINK TL-WA850RE */ ++ ATH79_MACH_TL_WA860RE, /* TP-LINK TL-WA860RE */ ++ ATH79_MACH_TL_WA801ND_V2, /* TP-LINK TL-WA801ND v2 */ ++ ATH79_MACH_TL_WA830RE_V2, /* TP-LINK TL-WA830RE v2 */ ++ ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ ++ ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ ++ ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ ++ ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ ++ ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ ++ ATH79_MACH_TL_WDR4900_V2, /* TP-LINK TL-WDR4900 v2 */ ++ ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */ ++ ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */ ++ ATH79_MACH_TL_WR1043ND_V2, /* TP-LINK TL-WR1043ND v2 */ ++ ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */ ++ ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */ ++ ATH79_MACH_TL_WR710N, /* TP-LINK TL-WR710N */ ++ ATH79_MACH_TL_WR720N_V3, /* TP-LINK TL-WR720N v3/v4 */ ++ ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ ++ ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/ ++ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ ++ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */ ++ ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */ ++ ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */ ++ ATH79_MACH_TL_WR842N_V2, /* TP-LINK TL-WR842N/ND v2 */ ++ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ ++ ATH79_MACH_TL_WR941ND_V5, /* TP-LINK TL-WR941ND v5 */ ++ ATH79_MACH_TUBE2H, /* Alfa Network Tube2H */ ++ ATH79_MACH_UBNT_AIRGW, /* Ubiquiti AirGateway */ ++ ATH79_MACH_UBNT_AIRGWP, /* Ubiquiti AirGateway Pro */ + ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ + ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ ATH79_MACH_UBNT_LOCO_M_XW, /* Ubiquiti Loco M XW */ ++ ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ ++ ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */ + ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ ATH79_MACH_UBNT_NANO_M_XW, /* Ubiquiti NanoStation M XW */ + ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ + ATH79_MACH_UBNT_ROCKET_M_XW, /* Ubiquiti Rocket M XW*/ + ATH79_MACH_UBNT_ROCKET_M_TI, /* Ubiquiti Rocket M TI*/ ++ ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ ++ ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */ + ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */ + ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ + ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */ ++ ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ ++ ATH79_MACH_WEIO, /* WeIO board */ ++ ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */ ++ ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */ ++ ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */ ++ ATH79_MACH_WLAE_AG300N, /* Buffalo WLAE-AG300N */ ++ ATH79_MACH_WLR8100, /* SITECOM WLR-8100 */ ++ ATH79_MACH_WNDAP360, /* NETGEAR WNDAP360 */ ++ ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */ ++ ATH79_MACH_WNDR3700_V4, /* NETGEAR WNDR3700v4 */ ++ ATH79_MACH_WNDR4300, /* NETGEAR WNDR4300 */ ++ ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */ ++ ATH79_MACH_WNR2000_V3, /* NETGEAR WNR2000 v3 */ ++ ATH79_MACH_WNR2000_V4, /* NETGEAR WNR2000 v4 */ ++ ATH79_MACH_WNR2200, /* NETGEAR WNR2200 */ ++ ATH79_MACH_WNR612_V2, /* NETGEAR WNR612 v2 */ ++ ATH79_MACH_WNR1000_V2, /* NETGEAR WNR1000 v2 */ ++ ATH79_MACH_WP543, /* Compex WP543 */ ++ ATH79_MACH_WPE72, /* Compex WPE72 */ ++ ATH79_MACH_WPJ344, /* Compex WPJ344 */ ++ ATH79_MACH_WPJ531, /* Compex WPJ531 */ ++ ATH79_MACH_WPJ558, /* Compex WPJ558 */ ++ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */ ++ ATH79_MACH_WRT400N, /* Linksys WRT400N */ ++ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */ ++ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ ++ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */ ++ ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */ ++ ATH79_MACH_WZR_450HP2, /* Buffalo WZR-450HP2 */ ++ ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */ ++ ATH79_MACH_ZCN_1523H_5, /* Zcomax ZCN-1523H-5-xx */ + }; + + #endif /* _ATH79_MACHTYPE_H */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -2,6 +2,90 @@ if ATH79 + + menu "Atheros AR71XX/AR724X/AR913X machine selection" + ++config ATH79_MACH_ALFA_AP96 ++ bool "ALFA Network AP96 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_HORNET_UB ++ bool "ALFA Network Hornet-UB board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ALFA_NX ++ bool "ALFA Network N2/N5 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TUBE2H ++ bool "ALFA Network Tube2H board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ALL0258N ++ bool "Allnet ALL0258N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ALL0315N ++ bool "Allnet ALL0315N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ANTMINER_S1 ++ bool "Bitmain Antminer S1 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ANTMINER_S3 ++ bool "Bitmain Antminer S3 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_AP113 ++ bool "Atheros AP113 board support" ++ select SOC_AR724X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_PB9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_ETH ++ + config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X +@@ -11,62 +95,1107 @@ config ATH79_MACH_AP121 + select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros AP121 reference board. ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP121 reference board. ++ ++config ATH79_MACH_AP132 ++ bool "Atheros AP132 reference board" ++ select SOC_QCA955X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP132 reference boards. ++ ++config ATH79_MACH_AP136 ++ bool "Atheros AP136/AP135 reference board" ++ select SOC_QCA955X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP136 or AP135 reference boards. ++ ++config ATH79_MACH_AP143 ++ bool "Atheros AP143 reference board" ++ select SOC_QCA953X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ select ATH79_DEV_M25P80 ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP143 reference board. ++ ++config ATH79_MACH_AP81 ++ bool "Atheros AP81 reference board" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP81 reference board. ++ ++config ATH79_MACH_AP83 ++ bool "Atheros AP83 board support" ++ select SOC_AR913X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_AP96 ++ bool "Atheros AP96 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DB120 ++ bool "Atheros DB120 reference board" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros DB120 reference board. ++ ++config ATH79_MACH_PB42 ++ bool "Atheros PB42 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_PB44 ++ bool "Atheros PB44 reference board" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros PB44 reference board. ++ ++config ATH79_MACH_PB92 ++ bool "Atheros PB92 board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_PB9X_PCI if PCI ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_AW_NR580 ++ bool "AzureWave AW-NR580 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_F9K1115V2 ++ bool "Belkin AC1750DB board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EPG5000 ++ bool "EnGenius EPG5000 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_ESR1750 ++ bool "EnGenius ESR1750 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WHR_HP_G300N ++ bool "Buffalo WHR-HP-G300N board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WLAE_AG300N ++ bool "Buffalo WLAE-AG300N board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WLR8100 ++ bool "Sitecom WLR-8100 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WZR_HP_AG300H ++ bool "Buffalo WZR-HP-AG300H board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_HP_G300NH ++ bool "Buffalo WZR-HP-G300NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select RTL8366_SMI ++ ++config ATH79_MACH_WZR_HP_G300NH2 ++ bool "Buffalo WZR-HP-G300NH2 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_HP_G450H ++ bool "Buffalo WZR-HP-G450H board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_450HP2 ++ bool "Buffalo WZR-450HP2 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WP543 ++ bool "Compex WP543/WPJ543 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select MYLOADER ++ ++config ATH79_MACH_WPE72 ++ bool "Compex WPE72/WPE72NX board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select MYLOADER ++ ++config ATH79_MACH_WPJ344 ++ bool "Compex WPJ344 board support" ++ select SOC_AS934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WPJ531 ++ bool "Compex WPJ531 board support" ++ select SOC_QCA953X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WPJ558 ++ bool "Compex WPJ558 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_DGL_5500_A1 ++ bool "D-Link DGL-5500 A1 support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DHP_1565_A1 ++ bool "D-Link DHP-1565 rev. A1 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_DIR_505_A1 ++ bool "D-Link DIR-505-A1 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_600_A1 ++ bool "D-Link DIR-600 A1/DIR-615 E1/DIR-615 E4 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_615_C1 ++ bool "D-Link DIR-615 rev. C1 support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_615_I1 ++ bool "D-Link DIR-615 rev. I1 support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_825_B1 ++ bool "D-Link DIR-825 rev. B1 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DIR_825_C1 ++ bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_DLAN_PRO_500_WP ++ bool "devolo dLAN pro 500 Wireless+ support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DLAN_PRO_1200_AC ++ bool "devolo dLAN pro 1200+ WiFi ac support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DRAGINO2 ++ bool "DRAGINO V2 support" ++ select SOC_AR933X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_ESR900 ++ bool "EnGenius ESR900 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EW_DORIN ++ bool "embedded wireless Dorin Platform support" ++ select SOC_AR933X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ help ++ Say 'Y' here if you want your kernel to support the ++ Dorin Platform from www.80211.de . ++ ++config ATH79_MACH_EL_M150 ++ bool "EasyLink EL-M150 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EL_MINI ++ bool "EasyLink EL-MINI support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_GL_INET ++ bool "GL-INET support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EAP300V2 ++ bool "EnGenius EAP300 v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_GS_OOLITE ++ bool "GS Oolite V1 support" ++ select SOC_AR933X ++ select ARH79_DEV_ETH ++ select ARH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_HIWIFI_HC6361 ++ bool "HiWiFi HC6361 board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_JA76PF ++ bool "jjPlus JA76PF board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_JWAP003 ++ bool "jjPlus JWAP003 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WRT160NL ++ bool "Linksys WRT160NL board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_WRT400N ++ bool "Linksys WRT400N board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_R6100 ++ bool "NETGEAR R6100 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MC_MAC1200R ++ bool "MERCURY MAC1200R board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_RB4XX ++ bool "MikroTik RouterBOARD 4xx series support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_RB750 ++ bool "MikroTik RouterBOARD 750 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RB91X ++ bool "MikroTik RouterBOARD 91X support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_SPI ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RB922 ++ bool "MikroTik RouterBOARD 922 support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ select RLE_DECOMPRESS ++ ++config ATH79_MACH_RB95X ++ bool "MikroTik RouterBOARD 95X support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_NFC ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RB2011 ++ bool "MikroTik RouterBOARD 2011 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RBSXTLITE ++ bool "MikroTik RouterBOARD SXT Lite" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_NFC ++ select ATH79_DEV_WMAC ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_SMART_300 ++ bool "NC-LINK SMART-300 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WNDAP360 ++ bool "NETGEAR WNDAP360 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WNDR3700 ++ bool "NETGEAR WNDR3700 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WNDR4300 ++ bool "NETGEAR WNDR3700v4/WNDR4300 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WNR2000 ++ bool "NETGEAR WNR2000 board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WNR2000_V3 ++ bool "NETGEAR WNR2000 V3/WNR612 v2/WNR1000 v2 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++ config ATH79_MACH_WNR2200 ++ bool "NETGEAR WNR2200 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WNR2000_V4 ++ bool "NETGEAR WNR2000 V4" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_OM2P ++ bool "OpenMesh OM2P board support" ++ select SOC_AR724X ++ select SOC_AR933X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_OM5P ++ bool "OpenMesh OM5P board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ONION_OMEGA ++ bool "ONION OMEGA support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR12 ++ bool "Meraki MR12 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR16 ++ bool "Meraki MR16 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR600 ++ bool "OpenMesh MR600 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MZK_W04NU ++ bool "Planex MZK-W04NU board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MZK_W300NH ++ bool "Planex MZK-W300NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_RW2458N ++ bool "Redwave RW2458N board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_CAP4200AG ++ bool "Senao CAP4200AG support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR900 ++ bool "OpenMesh MR900 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EAP7660D ++ bool "Senao EAP7660D support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ARCHER_C7 ++ bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_CPE510 ++ bool "TP-LINK CPE510 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR11U ++ bool "TP-LINK TL-MR11U/TL-MR3040 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR13U ++ bool "TP-LINK TL-MR13U support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR3020 ++ bool "TP-LINK TL-MR3020 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR3X20 ++ bool "TP-LINK TL-MR3220/3420 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_TL_WAX50RE ++ bool "TP-LINK TL-WA750/850RE support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WA701ND_V2 ++ bool "TP-LINK TL-WA701ND v2 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC + +-config ATH79_MACH_AP136 +- bool "Atheros AP136/AP135 reference board" +- select SOC_QCA955X ++config ATH79_MACH_TL_WA7210N_V2 ++ bool "TP-LINK TL-WA7210N v2 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WA830RE_V2 ++ bool "TP-LINK TL-WA830RE v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_NFC +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros AP136 or AP135 reference boards. + +-config ATH79_MACH_AP81 +- bool "Atheros AP81 reference board" ++config ATH79_MACH_TL_WA901ND ++ bool "TP-LINK TL-WA901ND/TL-WA7510N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WA901ND_V2 ++ bool "TP-LINK TL-WA901ND v2 support" + select SOC_AR913X + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WDR3500 ++ bool "TP-LINK TL-WDR3500 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros AP81 reference board. + +-config ATH79_MACH_DB120 +- bool "Atheros DB120 reference board" ++config ATH79_MACH_TL_WDR4300 ++ bool "TP-LINK TL-WDR3600/4300/4310 board support" + select SOC_AR934X + select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 +- select ATH79_DEV_NFC + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros DB120 reference board. + +-config ATH79_MACH_PB44 +- bool "Atheros PB44 reference board" ++config ATH79_MACH_TL_WR703N ++ bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR720N_V3 ++ bool "TP-LINK TL-WR720N v3/v4 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR741ND ++ bool "TP-LINK TL-WR741ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WR741ND_V4 ++ bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR841N_V1 ++ bool "TP-LINK TL-WR841N v1 support" + select SOC_AR71XX ++ select ATH79_DEV_DSA + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WR841N_V8 ++ bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR841N_V9 ++ bool "TP-LINK TL-WR841N/ND v9 support" ++ select SOC_QCA953X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR941ND ++ bool "TP-LINK TL-WR941ND support" ++ select SOC_AR913X ++ select ATH79_DEV_DSA ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1041N_V2 ++ bool "TP-LINK TL-WR1041N v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1043ND ++ bool "TP-LINK TL-WR1043ND support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1043ND_V2 ++ bool "TP-LINK TL-WR1043ND v2 support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR2543N ++ bool "TP-LINK TL-WR2543N/ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_TEW_632BRP ++ bool "TRENDnet TEW-632BRP support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_673GRU ++ bool "TRENDnet TEW-673GRU support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_712BR ++ bool "TRENDnet TEW-712BR support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_732BR ++ bool "TRENDnet TEW-732BR support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_UBNT ++ bool "Ubiquiti AR71xx based boards support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB +- help +- Say 'Y' here if you want your kernel to support the +- Atheros PB44 reference board. + + config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM/UniFi boards" +@@ -83,6 +1212,116 @@ config ATH79_MACH_UBNT_XM + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. + ++config ATH79_MACH_WEIO ++ bool "WeIO board" ++ select SOC_AR933X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MYNET_N600 ++ bool "WD My Net N600 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_MYNET_N750 ++ bool "WD My Net N750 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_MYNET_REXT ++ bool "WD My Net Wi-Fi Range Extender board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_ZCN_1523H ++ bool "Zcomax ZCN-1523H support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_NBG460N ++ bool "Zyxel NBG460N/550N/550NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_NBG6716 ++ bool "Zyxel NBG6716 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_CARAMBOLA2 ++ bool "8devices Carambola2 board" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_CF_E316N_V2 ++ bool "COMFAST CF-E316N v2 board" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_BHU_BXU2000N2_A ++ bool "BHU BXU2000n-2 rev. A support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_QIHOO_C301 ++ bool "Qihoo 360 C301 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ select ATH79_NVRAM ++ + endmenu + + config SOC_AR71XX +@@ -134,7 +1373,10 @@ config ATH79_DEV_DSA + config ATH79_DEV_ETH + def_bool n + +-config PCI_AR724X ++config ATH79_DEV_DSA ++ def_bool n ++ ++config ATH79_DEV_ETH + def_bool n + + config ATH79_DEV_GPIO_BUTTONS +@@ -164,6 +1406,11 @@ config ATH79_PCI_ATH9K_FIXUP + def_bool n + + config ATH79_ROUTERBOOT ++ select RLE_DECOMPRESS ++ select LZO_DECOMPRESS ++ def_bool n ++ ++config PCI_AR724X + def_bool n + + endif +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -38,9 +38,135 @@ obj-$(CONFIG_ATH79_ROUTERBOOT) += route + # + # Machines + # ++obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o ++obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o ++obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o ++obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o ++obj-$(CONFIG_ATH79_MACH_ANTMINER_S1)+= mach-antminer-s1.o ++obj-$(CONFIG_ATH79_MACH_ANTMINER_S3)+= mach-antminer-s3.o ++obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o ++obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o ++obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o ++obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o ++obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7.o ++obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o ++obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o ++obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o ++obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o ++obj-$(CONFIG_ATH79_MACH_CPE510) += mach-cpe510.o + obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o ++obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP) += mach-dlan-pro-500-wp.o ++obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC) += mach-dlan-pro-1200-ac.o ++obj-$(CONFIG_ATH79_MACH_DGL_5500_A1) += mach-dgl-5500-a1.o ++obj-$(CONFIG_ATH79_MACH_DHP_1565_A1) += mach-dhp-1565-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_505_A1) += mach-dir-505-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o ++obj-$(CONFIG_ATH79_MACH_DIR_615_I1) += mach-dir-615-i1.o ++obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o ++obj-$(CONFIG_ATH79_MACH_DIR_825_C1) += mach-dir-825-c1.o ++obj-$(CONFIG_ATH79_MACH_DRAGINO2) += mach-dragino2.o ++obj-$(CONFIG_ATH79_MACH_ESR900) += mach-esr900.o ++obj-$(CONFIG_ATH79_MACH_EW_DORIN) += mach-ew-dorin.o ++obj-$(CONFIG_ATH79_MACH_EAP300V2) += mach-eap300v2.o ++obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o ++obj-$(CONFIG_ATH79_MACH_EL_M150) += mach-el-m150.o ++obj-$(CONFIG_ATH79_MACH_EL_MINI) += mach-el-mini.o ++obj-$(CONFIG_ATH79_MACH_EPG5000) += mach-epg5000.o ++obj-$(CONFIG_ATH79_MACH_ESR1750) += mach-esr1750.o ++obj-$(CONFIG_ATH79_MACH_F9K1115V2) += mach-f9k1115v2.o ++obj-$(CONFIG_ATH79_MACH_GL_INET) += mach-gl-inet.o ++obj-$(CONFIG_ATH79_MACH_GS_OOLITE) += mach-gs-oolite.o ++obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361) += mach-hiwifi-hc6361.o ++obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o ++obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o ++obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o ++obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o ++obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o ++obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o ++obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o ++obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o ++obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o ++obj-$(CONFIG_ATH79_MACH_MYNET_N750) += mach-mynet-n750.o ++obj-$(CONFIG_ATH79_MACH_MYNET_REXT) += mach-mynet-rext.o ++obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o ++obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o ++obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o ++obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o ++obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o ++obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o ++obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o ++obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o ++obj-$(CONFIG_ATH79_MACH_QIHOO_C301) += mach-qihoo-c301.o ++obj-$(CONFIG_ATH79_MACH_R6100) += mach-r6100.o ++obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o ++obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o ++obj-$(CONFIG_ATH79_MACH_RB91X) += mach-rb91x.o ++obj-$(CONFIG_ATH79_MACH_RB922) += mach-rb922.o ++obj-$(CONFIG_ATH79_MACH_RB95X) += mach-rb95x.o ++obj-$(CONFIG_ATH79_MACH_RB2011) += mach-rb2011.o ++obj-$(CONFIG_ATH79_MACH_RBSXTLITE) += mach-rbsxtlite.o ++obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o ++obj-$(CONFIG_ATH79_MACH_SMART_300) += mach-smart-300.o ++obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o ++obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o ++obj-$(CONFIG_ATH79_MACH_TEW_712BR) += mach-tew-712br.o ++obj-$(CONFIG_ATH79_MACH_TEW_732BR) += mach-tew-732br.o ++obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o ++obj-$(CONFIG_ATH79_MACH_TL_MR13U) += mach-tl-mr13u.o ++obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o ++obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o ++obj-$(CONFIG_ATH79_MACH_TL_WAX50RE) += mach-tl-wax50re.o ++obj-$(CONFIG_ATH79_MACH_TL_WA701ND_V2) += mach-tl-wa701nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2) += mach-tl-wa7210n-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2) += mach-tl-wa830re-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o ++obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o ++obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V2) += mach-tl-wr1043nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR720N_V3) += mach-tl-wr720n-v3.o ++obj-$(CONFIG_ATH79_MACH_TUBE2H) += mach-tube2h.o ++obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o + obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o ++obj-$(CONFIG_ATH79_MACH_WEIO) += mach-weio.o ++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o ++obj-$(CONFIG_ATH79_MACH_WLAE_AG300N) += mach-wlae-ag300n.o ++obj-$(CONFIG_ATH79_MACH_WLR8100) += mach-wlr8100.o ++obj-$(CONFIG_ATH79_MACH_WNDAP360) += mach-wndap360.o ++obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o ++obj-$(CONFIG_ATH79_MACH_WNDR4300) += mach-wndr4300.o ++obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o ++obj-$(CONFIG_ATH79_MACH_WNR2000_V3) += mach-wnr2000-v3.o ++obj-$(CONFIG_ATH79_MACH_WNR2000_V4) += mach-wnr2000-v4.o ++obj-$(CONFIG_ATH79_MACH_WNR2200) += mach-wnr2200.o ++obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o ++obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o ++obj-$(CONFIG_ATH79_MACH_WPJ344) += mach-wpj344.o ++obj-$(CONFIG_ATH79_MACH_WPJ531) += mach-wpj531.o ++obj-$(CONFIG_ATH79_MACH_WPJ558) += mach-wpj558.o ++obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o ++obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o ++obj-$(CONFIG_ATH79_MACH_WZR_450HP2) += mach-wzr-450hp2.o ++obj-$(CONFIG_ATH79_MACH_ZCN_1523H) += mach-zcn-1523h.o ++obj-$(CONFIG_ATH79_MACH_CARAMBOLA2) += mach-carambola2.o ++obj-$(CONFIG_ATH79_MACH_NBG6716) += mach-nbg6716.o +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -130,6 +130,13 @@ void __init prom_init(void) + initrd_end = initrd_start + fw_getenvl("initrd_size"); + } + #endif ++ ++ if (strstr(arcs_cmdline, "board=750Gr3") || ++ strstr(arcs_cmdline, "board=951G") || ++ strstr(arcs_cmdline, "board=2011L") || ++ strstr(arcs_cmdline, "board=711Gr100") || ++ strstr(arcs_cmdline, "board=922gs")) ++ ath79_prom_append_cmdline("console", "ttyS0,115200"); + } + + void __init prom_free_prom_memory(void) diff --git a/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch new file mode 100644 index 0000000..23425dc --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch @@ -0,0 +1,60 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -221,15 +221,27 @@ void __init ath79_gpio_output_select(uns + { + void __iomem *base = ath79_gpio_base; + unsigned long flags; +- unsigned int reg; ++ unsigned int reg, reg_base; ++ unsigned long gpio_count; + u32 t, s; + +- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x()); ++ if (soc_is_ar934x()) { ++ gpio_count = AR934X_GPIO_COUNT; ++ reg_base = AR934X_GPIO_REG_OUT_FUNC0; ++ } else if (soc_is_qca953x()) { ++ gpio_count = QCA953X_GPIO_COUNT; ++ reg_base = QCA953X_GPIO_REG_OUT_FUNC0; ++ } else if (soc_is_qca955x()) { ++ gpio_count = QCA955X_GPIO_COUNT; ++ reg_base = QCA955X_GPIO_REG_OUT_FUNC0; ++ } else { ++ BUG(); ++ } + +- if (gpio >= AR934X_GPIO_COUNT) ++ if (gpio >= gpio_count) + return; + +- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); ++ reg = reg_base + 4 * (gpio / 4); + s = 8 * (gpio % 4); + + spin_lock_irqsave(&ath79_gpio_lock, flags); +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -868,6 +868,14 @@ + #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 + #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + ++#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c ++#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 ++#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 ++#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 ++#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c ++#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 ++#define QCA955X_GPIO_REG_FUNC 0x6c ++ + #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c + #define QCA956X_GPIO_REG_OUT_FUNC1 0x30 + #define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +@@ -1007,6 +1015,8 @@ + #define AR934X_GPIO_OUT_EXT_LNA0 46 + #define AR934X_GPIO_OUT_EXT_LNA1 47 + ++#define QCA955X_GPIO_OUT_GPIO 0 ++ + /* + * MII_CTRL block + */ diff --git a/target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch new file mode 100644 index 0000000..a57351e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x + } + }; + ++static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = { ++ { ++ .bus = 0, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, ++}; ++ + static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { + { + .bus = 0, +@@ -98,6 +107,9 @@ int __init pcibios_map_irq(const struct + soc_is_ar9344()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); ++ } else if (soc_is_qca953x()) { ++ ath79_pci_irq_map = qca953x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map); + } else if (soc_is_qca955x()) { + ath79_pci_irq_map = qca955x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); +@@ -303,6 +315,15 @@ int __init ath79_register_pci(void) + AR724X_PCI_MEM_SIZE, + 0, + ATH79_IP2_IRQ(0)); ++ } else if (soc_is_qca9533()) { ++ pdev = ath79_register_pci_ar724x(0, ++ QCA953X_PCI_CFG_BASE0, ++ QCA953X_PCI_CTRL_BASE0, ++ QCA953X_PCI_CRP_BASE0, ++ QCA953X_PCI_MEM_BASE0, ++ QCA953X_PCI_MEM_SIZE, ++ 0, ++ ATH79_IP2_IRQ(0)); + } else if (soc_is_qca9558()) { + pdev = ath79_register_pci_ar724x(0, + QCA955X_PCI_CFG_BASE0, diff --git a/target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch b/target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch new file mode 100644 index 0000000..ed0d984 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -138,6 +138,19 @@ config ATH79_MACH_AP143 + Say 'Y' here if you want your kernel to support the + Atheros AP143 reference board. + ++config ATH79_MACH_AP147 ++ bool "Atheros AP147 reference board" ++ select SOC_QCA953X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_AP9X_PCI if PCI ++ help ++ Say 'Y' here if you want your kernel to support the ++ QCA AP147 reference boards. ++ + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -49,6 +49,7 @@ obj-$(CONFIG_ATH79_MACH_AP121) += mach- + obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o ++obj-$(CONFIG_ATH79_MACH_AP147) += mach-ap147.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o + obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o + obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -31,6 +31,7 @@ enum ath79_mach_type { + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP143, /* Atheros AP143 reference board */ ++ ATH79_MACH_AP147_010, /* Atheros AP147-010 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_AP83, /* Atheros AP83 */ + ATH79_MACH_AP96, /* Atheros AP96 */ diff --git a/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch new file mode 100644 index 0000000..cc01cd6 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -904,6 +904,16 @@ config ATH79_MACH_EAP7660D + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 + ++config ATH79_MACH_BSB ++ bool "Smart Electronics Black Swift board" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_ARCHER_C7 + bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support" + select SOC_QCA955X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -56,6 +56,7 @@ obj-$(CONFIG_ATH79_MACH_AP96) += mach-a + obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7.o + obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o + obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o ++obj-$(CONFIG_ATH79_MACH_BSB) += mach-bsb.o + obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o + obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o + obj-$(CONFIG_ATH79_MACH_CPE510) += mach-cpe510.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -39,6 +39,7 @@ enum ath79_mach_type { + ATH79_MACH_ARCHER_C7, /* TP-LINK Archer C7 board */ + ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */ + ATH79_MACH_BHU_BXU2000N2_A1, /* BHU BXU2000n-2 A1 */ ++ ATH79_MACH_BSB, /* Smart Electronics Black Swift board */ + ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */ + ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */ + ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */ diff --git a/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch new file mode 100644 index 0000000..1955bfa --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -1053,6 +1053,17 @@ config ATH79_MACH_TL_WDR4300 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + ++config ATH79_MACH_TL_WDR6500_V2 ++ bool "TP-LINK TL-WDR6500 v2 board support" ++ select SOC_QCA956X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_TL_WR703N + bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support" + select SOC_AR933X +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -155,6 +155,7 @@ enum ath79_mach_type { + ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ + ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ + ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ ++ ATH79_MACH_TL_WDR6500_V2, /* TP-LINK TL-WDR6500 v2 */ + ATH79_MACH_TL_WDR4900_V2, /* TP-LINK TL-WDR4900 v2 */ + ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */ + ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */ +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -131,6 +131,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += m + obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o + obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR6500_V2) += mach-tl-wdr6500-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o + obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o + obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o diff --git a/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch new file mode 100644 index 0000000..0b24886 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch @@ -0,0 +1,43 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -151,6 +151,20 @@ config ATH79_MACH_AP147 + Say 'Y' here if you want your kernel to support the + QCA AP147 reference boards. + ++config ATH79_MACH_AP152 ++ bool "Atheros AP152 reference board" ++ select SOC_QCA956X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_AP9X_PCI if PCI ++ help ++ Say 'Y' here if you want your kernel to support the ++ QCA AP152 reference boards. ++ ++ + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o + obj-$(CONFIG_ATH79_MACH_AP147) += mach-ap147.o ++obj-$(CONFIG_ATH79_MACH_AP152) += mach-ap152.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o + obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o + obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -32,6 +32,7 @@ enum ath79_mach_type { + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP143, /* Atheros AP143 reference board */ + ATH79_MACH_AP147_010, /* Atheros AP147-010 reference board */ ++ ATH79_MACH_AP152, /* Atheros AP152 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_AP83, /* Atheros AP83 */ + ATH79_MACH_AP96, /* Atheros AP96 */ diff --git a/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch new file mode 100644 index 0000000..d802a12 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -763,6 +763,16 @@ config ATH79_MACH_CAP4200AG + select ATH79_DEV_M25P80 + select ATH79_DEV_WMAC + ++config ATH79_MACH_MR1750 ++ bool "OpenMesh MR1750 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_MR900 + bool "OpenMesh MR900 board support" + select SOC_QCA955X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -80,6 +80,7 @@ obj-$(CONFIG_ATH79_MACH_HORNET_UB) += ma + obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o + obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o + obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o ++obj-$(CONFIG_ATH79_MACH_MR1750) += mach-mr1750.o + obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o + obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o + obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -69,6 +69,7 @@ enum ath79_mach_type { + ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */ + ATH79_MACH_MR12, /* Cisco Meraki MR12 */ + ATH79_MACH_MR16, /* Cisco Meraki MR16 */ ++ ATH79_MACH_MR1750, /* OpenMesh MR1750 */ + ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */ + ATH79_MACH_MR600, /* OpenMesh MR600 */ + ATH79_MACH_MR900, /* OpenMesh MR900 */ diff --git a/target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch b/target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch new file mode 100644 index 0000000..8d6d686 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -1031,6 +1031,17 @@ + select ATH79_DEV_M25P80 + select ATH79_DEV_WMAC + ++config ATH79_MACH_TL_WDR3320_V2 ++ bool "TP-LINK TL-WDR3320 v2 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_TL_WDR3500 + bool "TP-LINK TL-WDR3500 board support" + select SOC_AR934X +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -152,6 +152,7 @@ + ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ + ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ + ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ ++ ATH79_MACH_TL_WDR3320_V2, /* TP-LINK TL-WDR3320 v2 */ + ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ + ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ + ATH79_MACH_TL_WDR6500_V2, /* TP-LINK TL-WDR6500 v2 */ +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -128,6 +128,7 @@ + obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2) += mach-tl-wa830re-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o + obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR3320_V2) += mach-tl-wdr3320-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o + obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o + obj-$(CONFIG_ATH79_MACH_TL_WDR6500_V2) += mach-tl-wdr6500-v2.o diff --git a/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch new file mode 100644 index 0000000..39584aa --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/phy/mdio-bitbang.c ++++ b/drivers/net/phy/mdio-bitbang.c +@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b + + ctrl->ops->set_mdio_dir(ctrl, 0); + +- /* check the turnaround bit: the PHY should be driving it to zero */ +- if (mdiobb_get_bit(ctrl) != 0) { +- /* PHY didn't drive TA low -- flush any bits it +- * may be trying to send. +- */ +- for (i = 0; i < 32; i++) +- mdiobb_get_bit(ctrl); +- +- return 0xffff; +- } ++ mdiobb_get_bit(ctrl); + + ret = mdiobb_get_num(ctrl, 16); + mdiobb_get_bit(ctrl); diff --git a/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch new file mode 100644 index 0000000..68f86e0 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch @@ -0,0 +1,61 @@ +From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 16 Jun 2015 13:15:08 +0200 +Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command + +It seems some phys have some maximum timings for accessing the MDIO line, +resulting in bit errors under cpu stress. Prevent this from happening by +disabling interrupts when sending commands. + +Signed-off-by: Jonas Gorski +--- + drivers/net/phy/mdio-bitbang.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/phy/mdio-bitbang.c ++++ b/drivers/net/phy/mdio-bitbang.c +@@ -17,6 +17,7 @@ + * kind, whether express or implied. + */ + ++#include + #include + #include + #include +@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b + { + struct mdiobb_ctrl *ctrl = bus->priv; + int ret, i; ++ long flags; + ++ local_irq_save(flags); + if (reg & MII_ADDR_C45) { + reg = mdiobb_cmd_addr(ctrl, phy, reg); + mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); +@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b + + ret = mdiobb_get_num(ctrl, 16); + mdiobb_get_bit(ctrl); ++ local_irq_restore(flags); ++ + return ret; + } + + static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) + { + struct mdiobb_ctrl *ctrl = bus->priv; ++ long flags; + ++ local_irq_save(flags); + if (reg & MII_ADDR_C45) { + reg = mdiobb_cmd_addr(ctrl, phy, reg); + mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); +@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus * + + ctrl->ops->set_mdio_dir(ctrl, 0); + mdiobb_get_bit(ctrl); ++ local_irq_restore(flags); ++ + return 0; + } + diff --git a/target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch new file mode 100644 index 0000000..3a73aea --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch @@ -0,0 +1,893 @@ +--- a/arch/mips/include/asm/checksum.h ++++ b/arch/mips/include/asm/checksum.h +@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const + const unsigned int *stop = word + ihl; + unsigned int csum; + int carry; ++ unsigned int w; + +- csum = word[0]; +- csum += word[1]; +- carry = (csum < word[1]); ++ csum = net_hdr_word(word++); ++ ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[2]; +- carry = (csum < word[2]); ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[3]; +- carry = (csum < word[3]); ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- word += 4; + do { +- csum += *word; +- carry = (csum < *word); ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; +- word++; + } while (word != stop); + + return csum_fold(csum); +@@ -212,73 +216,6 @@ static inline __sum16 ip_compute_csum(co + return csum_fold(csum_partial(buff, len, 0)); + } + +-#define _HAVE_ARCH_IPV6_CSUM +-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, +- const struct in6_addr *daddr, +- __u32 len, unsigned short proto, +- __wsum sum) +-{ +- __wsum tmp; +- +- __asm__( +- " .set push # csum_ipv6_magic\n" +- " .set noreorder \n" +- " .set noat \n" +- " addu %0, %5 # proto (long in network byte order)\n" +- " sltu $1, %0, %5 \n" +- " addu %0, $1 \n" +- +- " addu %0, %6 # csum\n" +- " sltu $1, %0, %6 \n" +- " lw %1, 0(%2) # four words source address\n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 4(%2) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 8(%2) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 12(%2) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 0(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 4(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 8(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 12(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " addu %0, $1 # Add final carry\n" +- " .set pop" +- : "=&r" (sum), "=&r" (tmp) +- : "r" (saddr), "r" (daddr), +- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)); +- +- return csum_fold(sum); +-} +- + #include + #endif /* CONFIG_GENERIC_CSUM */ + +--- a/include/uapi/linux/ip.h ++++ b/include/uapi/linux/ip.h +@@ -102,7 +102,7 @@ struct iphdr { + __be32 saddr; + __be32 daddr; + /*The options start here. */ +-}; ++} __attribute__((packed, aligned(2))); + + + struct ip_auth_hdr { +--- a/include/uapi/linux/ipv6.h ++++ b/include/uapi/linux/ipv6.h +@@ -129,7 +129,7 @@ struct ipv6hdr { + + struct in6_addr saddr; + struct in6_addr daddr; +-}; ++} __attribute__((packed, aligned(2))); + + + /* index values for the variables in ipv6_devconf */ +--- a/include/uapi/linux/tcp.h ++++ b/include/uapi/linux/tcp.h +@@ -54,7 +54,7 @@ struct tcphdr { + __be16 window; + __sum16 check; + __be16 urg_ptr; +-}; ++} __attribute__((packed, aligned(2))); + + /* + * The union cast uses a gcc extension to avoid aliasing problems +@@ -64,7 +64,7 @@ struct tcphdr { + union tcp_word_hdr { + struct tcphdr hdr; + __be32 words[5]; +-}; ++} __attribute__((packed, aligned(2))); + + #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) + +--- a/include/uapi/linux/udp.h ++++ b/include/uapi/linux/udp.h +@@ -24,7 +24,7 @@ struct udphdr { + __be16 dest; + __be16 len; + __sum16 check; +-}; ++} __attribute__((packed, aligned(2))); + + /* UDP socket options */ + #define UDP_CORK 1 /* Never send partially complete segments */ +--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c ++++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c +@@ -41,8 +41,8 @@ static bool ipv4_pkt_to_tuple(const stru + if (ap == NULL) + return false; + +- tuple->src.u3.ip = ap[0]; +- tuple->dst.u3.ip = ap[1]; ++ tuple->src.u3.ip = net_hdr_word(ap++); ++ tuple->dst.u3.ip = net_hdr_word(ap); + + return true; + } +--- a/include/uapi/linux/icmp.h ++++ b/include/uapi/linux/icmp.h +@@ -80,7 +80,7 @@ struct icmphdr { + __be16 mtu; + } frag; + } un; +-}; ++} __attribute__((packed, aligned(2))); + + + /* +--- a/include/uapi/linux/in6.h ++++ b/include/uapi/linux/in6.h +@@ -42,7 +42,7 @@ struct in6_addr { + #define s6_addr16 in6_u.u6_addr16 + #define s6_addr32 in6_u.u6_addr32 + #endif +-}; ++} __attribute__((packed, aligned(2))); + #endif /* __UAPI_DEF_IN6_ADDR */ + + #if __UAPI_DEF_SOCKADDR_IN6 +--- a/net/ipv6/tcp_ipv6.c ++++ b/net/ipv6/tcp_ipv6.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -772,10 +773,10 @@ static void tcp_v6_send_response(struct + topt = (__be32 *)(t1 + 1); + + if (tsecr) { +- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | +- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP); +- *topt++ = htonl(tsval); +- *topt++ = htonl(tsecr); ++ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++); ++ put_unaligned_be32(tsval, topt++); ++ put_unaligned_be32(tsecr, topt++); + } + + #ifdef CONFIG_TCP_MD5SIG +--- a/include/linux/ipv6.h ++++ b/include/linux/ipv6.h +@@ -5,6 +5,7 @@ + + #define ipv6_optlen(p) (((p)->hdrlen+1) << 3) + #define ipv6_authlen(p) (((p)->hdrlen+2) << 2) ++ + /* + * This structure contains configuration options per IPv6 link. + */ +--- a/net/ipv6/datagram.c ++++ b/net/ipv6/datagram.c +@@ -414,7 +414,7 @@ int ipv6_recv_error(struct sock *sk, str + ipv6_iface_scope_id(&sin->sin6_addr, + IP6CB(skb)->iif); + } else { +- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset), ++ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset), + &sin->sin6_addr); + sin->sin6_scope_id = 0; + } +@@ -751,12 +751,12 @@ int ip6_datagram_send_ctl(struct net *ne + } + + if (fl6->flowlabel&IPV6_FLOWINFO_MASK) { +- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) { ++ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) { + err = -EINVAL; + goto exit_f; + } + } +- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg); ++ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg)); + break; + + case IPV6_2292HOPOPTS: +--- a/net/ipv6/ip6_gre.c ++++ b/net/ipv6/ip6_gre.c +@@ -393,7 +393,7 @@ static void ip6gre_err(struct sk_buff *s + + t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr, + flags & GRE_KEY ? +- *(((__be32 *)p) + (grehlen / 4) - 1) : 0, ++ net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1) : 0, + p[1]); + if (!t) + return; +@@ -475,11 +475,11 @@ static int ip6gre_rcv(struct sk_buff *sk + offset += 4; + } + if (flags&GRE_KEY) { +- key = *(__be32 *)(h + offset); ++ key = net_hdr_word(h + offset); + offset += 4; + } + if (flags&GRE_SEQ) { +- seqno = ntohl(*(__be32 *)(h + offset)); ++ seqno = ntohl(net_hdr_word(h + offset)); + offset += 4; + } + } +@@ -744,7 +744,7 @@ static netdev_tx_t ip6gre_xmit2(struct s + + if (tunnel->parms.o_flags&GRE_SEQ) { + ++tunnel->o_seqno; +- *ptr = htonl(tunnel->o_seqno); ++ net_hdr_word(ptr) = htonl(tunnel->o_seqno); + ptr--; + } + if (tunnel->parms.o_flags&GRE_KEY) { +@@ -840,7 +840,7 @@ static inline int ip6gre_xmit_ipv6(struc + + dsfield = ipv6_get_dsfield(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS) +- fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK); ++ fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK; + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL) + fl6.flowlabel |= ip6_flowlabel(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) +--- a/net/ipv6/ip6_tunnel.c ++++ b/net/ipv6/ip6_tunnel.c +@@ -1340,7 +1340,7 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str + + dsfield = ipv6_get_dsfield(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS) +- fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK); ++ fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK; + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL) + fl6.flowlabel |= ip6_flowlabel(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) +--- a/net/ipv6/exthdrs.c ++++ b/net/ipv6/exthdrs.c +@@ -573,7 +573,7 @@ static bool ipv6_hop_jumbo(struct sk_buf + goto drop; + } + +- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2)); ++ pkt_len = ntohl(net_hdr_word(nh + optoff + 2)); + if (pkt_len <= IPV6_MAXPLEN) { + IP6_INC_STATS_BH(net, ipv6_skb_idev(skb), + IPSTATS_MIB_INHDRERRORS); +--- a/include/linux/types.h ++++ b/include/linux/types.h +@@ -215,5 +215,11 @@ struct callback_head { + /* clocksource cycle base type */ + typedef u64 cycle_t; + ++struct net_hdr_word { ++ u32 words[1]; ++} __attribute__((packed, aligned(2))); ++ ++#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0]) ++ + #endif /* __ASSEMBLY__ */ + #endif /* _LINUX_TYPES_H */ +--- a/net/ipv4/af_inet.c ++++ b/net/ipv4/af_inet.c +@@ -1323,8 +1323,8 @@ static struct sk_buff **inet_gro_receive + if (unlikely(ip_fast_csum((u8 *)iph, 5))) + goto out_unlock; + +- id = ntohl(*(__be32 *)&iph->id); +- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF)); ++ id = ntohl(net_hdr_word(&iph->id)); ++ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF)); + id >>= 16; + + for (p = *head; p; p = p->next) { +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -453,7 +453,7 @@ static struct neighbour *ipv4_neigh_look + else if (skb) + pkey = &ip_hdr(skb)->daddr; + +- n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey); ++ n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey)); + if (n) + return n; + return neigh_create(&arp_tbl, pkey, dev); +--- a/net/ipv4/tcp_output.c ++++ b/net/ipv4/tcp_output.c +@@ -452,48 +452,53 @@ static void tcp_options_write(__be32 *pt + u16 options = opts->options; /* mungable copy */ + + if (unlikely(OPTION_MD5 & options)) { +- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | +- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | ++ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); + /* overload cookie hash location */ + opts->hash_location = (__u8 *)ptr; + ptr += 4; + } + + if (unlikely(opts->mss)) { +- *ptr++ = htonl((TCPOPT_MSS << 24) | +- (TCPOLEN_MSS << 16) | +- opts->mss); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) | ++ opts->mss); + } + + if (likely(OPTION_TS & options)) { + if (unlikely(OPTION_SACK_ADVERTISE & options)) { +- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) | +- (TCPOLEN_SACK_PERM << 16) | +- (TCPOPT_TIMESTAMP << 8) | +- TCPOLEN_TIMESTAMP); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_SACK_PERM << 24) | ++ (TCPOLEN_SACK_PERM << 16) | ++ (TCPOPT_TIMESTAMP << 8) | ++ TCPOLEN_TIMESTAMP); + options &= ~OPTION_SACK_ADVERTISE; + } else { +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_NOP << 16) | +- (TCPOPT_TIMESTAMP << 8) | +- TCPOLEN_TIMESTAMP); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | ++ TCPOLEN_TIMESTAMP); + } +- *ptr++ = htonl(opts->tsval); +- *ptr++ = htonl(opts->tsecr); ++ net_hdr_word(ptr++) = htonl(opts->tsval); ++ net_hdr_word(ptr++) = htonl(opts->tsecr); + } + + if (unlikely(OPTION_SACK_ADVERTISE & options)) { +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_NOP << 16) | +- (TCPOPT_SACK_PERM << 8) | +- TCPOLEN_SACK_PERM); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_SACK_PERM << 8) | ++ TCPOLEN_SACK_PERM); + } + + if (unlikely(OPTION_WSCALE & options)) { +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_WINDOW << 16) | +- (TCPOLEN_WINDOW << 8) | +- opts->ws); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_WINDOW << 16) | ++ (TCPOLEN_WINDOW << 8) | ++ opts->ws); + } + + if (unlikely(opts->num_sack_blocks)) { +@@ -501,16 +506,17 @@ static void tcp_options_write(__be32 *pt + tp->duplicate_sack : tp->selective_acks; + int this_sack; + +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_NOP << 16) | +- (TCPOPT_SACK << 8) | +- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_SACK << 8) | ++ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * + TCPOLEN_SACK_PERBLOCK))); + + for (this_sack = 0; this_sack < opts->num_sack_blocks; + ++this_sack) { +- *ptr++ = htonl(sp[this_sack].start_seq); +- *ptr++ = htonl(sp[this_sack].end_seq); ++ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq); ++ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq); + } + + tp->rx_opt.dsack = 0; +@@ -523,13 +529,14 @@ static void tcp_options_write(__be32 *pt + + if (foc->exp) { + len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; +- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) | ++ net_hdr_word(ptr) = ++ htonl((TCPOPT_EXP << 24) | (len << 16) | + TCPOPT_FASTOPEN_MAGIC); + p += TCPOLEN_EXP_FASTOPEN_BASE; + } else { + len = TCPOLEN_FASTOPEN_BASE + foc->len; +- *p++ = TCPOPT_FASTOPEN; +- *p++ = len; ++ net_hdr_word(p++) = TCPOPT_FASTOPEN; ++ net_hdr_word(p++) = len; + } + + memcpy(p, foc->val, foc->len); +--- a/net/ipv4/igmp.c ++++ b/net/ipv4/igmp.c +@@ -496,7 +496,7 @@ static struct sk_buff *add_grec(struct s + if (!skb) + return NULL; + psrc = (__be32 *)skb_put(skb, sizeof(__be32)); +- *psrc = psf->sf_inaddr; ++ net_hdr_word(psrc) = psf->sf_inaddr; + scount++; stotal++; + if ((type == IGMPV3_ALLOW_NEW_SOURCES || + type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) { +--- a/include/uapi/linux/igmp.h ++++ b/include/uapi/linux/igmp.h +@@ -32,7 +32,7 @@ struct igmphdr { + __u8 code; /* For newer IGMP */ + __sum16 csum; + __be32 group; +-}; ++} __attribute__((packed, aligned(2))); + + /* V3 group record types [grec_type] */ + #define IGMPV3_MODE_IS_INCLUDE 1 +@@ -48,7 +48,7 @@ struct igmpv3_grec { + __be16 grec_nsrcs; + __be32 grec_mca; + __be32 grec_src[0]; +-}; ++} __attribute__((packed, aligned(2))); + + struct igmpv3_report { + __u8 type; +@@ -57,7 +57,7 @@ struct igmpv3_report { + __be16 resv2; + __be16 ngrec; + struct igmpv3_grec grec[0]; +-}; ++} __attribute__((packed, aligned(2))); + + struct igmpv3_query { + __u8 type; +@@ -78,7 +78,7 @@ struct igmpv3_query { + __u8 qqic; + __be16 nsrcs; + __be32 srcs[0]; +-}; ++} __attribute__((packed, aligned(2))); + + #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */ + #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */ +--- a/net/core/flow_dissector.c ++++ b/net/core/flow_dissector.c +@@ -53,7 +53,7 @@ __be32 __skb_flow_get_ports(const struct + ports = __skb_header_pointer(skb, thoff + poff, + sizeof(_ports), data, hlen, &_ports); + if (ports) +- return *ports; ++ return (__be32)net_hdr_word(ports); + } + + return 0; +--- a/include/uapi/linux/icmpv6.h ++++ b/include/uapi/linux/icmpv6.h +@@ -76,7 +76,7 @@ struct icmp6hdr { + #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other + #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime + #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref +-}; ++} __attribute__((packed, aligned(2))); + + + #define ICMPV6_ROUTER_PREF_LOW 0x3 +--- a/include/net/ndisc.h ++++ b/include/net/ndisc.h +@@ -76,7 +76,7 @@ struct ra_msg { + struct icmp6hdr icmph; + __be32 reachable_time; + __be32 retrans_timer; +-}; ++} __attribute__((packed, aligned(2))); + + struct rd_msg { + struct icmp6hdr icmph; +@@ -148,10 +148,10 @@ static inline u32 ndisc_hashfn(const voi + { + const u32 *p32 = pkey; + +- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) + +- (p32[1] * hash_rnd[1]) + +- (p32[2] * hash_rnd[2]) + +- (p32[3] * hash_rnd[3])); ++ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) + ++ (net_hdr_word(&p32[1]) * hash_rnd[1]) + ++ (net_hdr_word(&p32[2]) * hash_rnd[2]) + ++ (net_hdr_word(&p32[3]) * hash_rnd[3])); + } + + static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey) +--- a/net/sched/cls_u32.c ++++ b/net/sched/cls_u32.c +@@ -151,7 +151,7 @@ next_knode: + data = skb_header_pointer(skb, toff, 4, &hdata); + if (!data) + goto out; +- if ((*data ^ key->val) & key->mask) { ++ if ((net_hdr_word(data) ^ key->val) & key->mask) { + n = rcu_dereference_bh(n->next); + goto next_knode; + } +@@ -204,8 +204,8 @@ check_terminal: + &hdata); + if (!data) + goto out; +- sel = ht->divisor & u32_hash_fold(*data, &n->sel, +- n->fshift); ++ sel = ht->divisor & u32_hash_fold(net_hdr_word(data), ++ &n->sel, n->fshift); + } + if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT))) + goto next_ht; +--- a/net/ipv6/ip6_offload.c ++++ b/net/ipv6/ip6_offload.c +@@ -221,7 +221,7 @@ static struct sk_buff **ipv6_gro_receive + continue; + + iph2 = (struct ipv6hdr *)(p->data + off); +- first_word = *(__be32 *)iph ^ *(__be32 *)iph2; ++ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2); + + /* All fields must match except length and Traffic Class. + * XXX skbs on the gro_list have all been parsed and pulled +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -43,7 +43,7 @@ struct prefix_info { + __be32 reserved2; + + struct in6_addr prefix; +-}; ++} __attribute__((packed, aligned(2))); + + + #include +--- a/include/net/inet_ecn.h ++++ b/include/net/inet_ecn.h +@@ -115,13 +115,13 @@ static inline int IP6_ECN_set_ce(struct + { + if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph))) + return 0; +- *(__be32*)iph |= htonl(INET_ECN_CE << 20); ++ net_hdr_word(iph) |= htonl(INET_ECN_CE << 20); + return 1; + } + + static inline void IP6_ECN_clear(struct ipv6hdr *iph) + { +- *(__be32*)iph &= ~htonl(INET_ECN_MASK << 20); ++ net_hdr_word(iph) &= ~htonl(INET_ECN_MASK << 20); + } + + static inline void ipv6_copy_dscp(unsigned int dscp, struct ipv6hdr *inner) +--- a/include/net/ipv6.h ++++ b/include/net/ipv6.h +@@ -107,7 +107,7 @@ struct frag_hdr { + __u8 reserved; + __be16 frag_off; + __be32 identification; +-}; ++} __attribute__((packed, aligned(2))); + + #define IP6_MF 0x0001 + #define IP6_OFFSET 0xFFF8 +@@ -396,8 +396,8 @@ static inline void __ipv6_addr_set_half( + } + #endif + #endif +- addr[0] = wh; +- addr[1] = wl; ++ net_hdr_word(&addr[0]) = wh; ++ net_hdr_word(&addr[1]) = wl; + } + + static inline void ipv6_addr_set(struct in6_addr *addr, +@@ -456,6 +456,8 @@ static inline bool ipv6_prefix_equal(con + const __be32 *a1 = addr1->s6_addr32; + const __be32 *a2 = addr2->s6_addr32; + unsigned int pdw, pbi; ++ /* Used for last <32-bit fraction of prefix */ ++ u32 pbia1, pbia2; + + /* check complete u32 in prefix */ + pdw = prefixlen >> 5; +@@ -464,7 +466,9 @@ static inline bool ipv6_prefix_equal(con + + /* check incomplete u32 in prefix */ + pbi = prefixlen & 0x1f; +- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi)))) ++ pbia1 = net_hdr_word(&a1[pdw]); ++ pbia2 = net_hdr_word(&a2[pdw]); ++ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi)))) + return false; + + return true; +@@ -607,13 +611,13 @@ static inline void ipv6_addr_set_v4mappe + */ + static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) + { +- const __be32 *a1 = token1, *a2 = token2; ++ const struct in6_addr *a1 = token1, *a2 = token2; + int i; + + addrlen >>= 2; + + for (i = 0; i < addrlen; i++) { +- __be32 xb = a1[i] ^ a2[i]; ++ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i]; + if (xb) + return i * 32 + 31 - __fls(ntohl(xb)); + } +@@ -739,17 +743,18 @@ static inline __be32 ip6_make_flowlabel( + static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, + __be32 flowlabel) + { +- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel; ++ net_hdr_word((__be32 *)hdr) = ++ htonl(0x60000000 | (tclass << 20)) | flowlabel; + } + + static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr) + { +- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK; ++ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK; + } + + static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr) + { +- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK; ++ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK; + } + + static inline u8 ip6_tclass(__be32 flowinfo) +--- a/include/net/secure_seq.h ++++ b/include/net/secure_seq.h +@@ -2,6 +2,7 @@ + #define _NET_SECURE_SEQ + + #include ++#include + + u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); + u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, +--- a/include/uapi/linux/in.h ++++ b/include/uapi/linux/in.h +@@ -81,7 +81,7 @@ enum { + /* Internet address. */ + struct in_addr { + __be32 s_addr; +-}; ++} __attribute__((packed, aligned(2))); + #endif + + #define IP_TOS 1 +--- a/net/core/secure_seq.c ++++ b/net/core/secure_seq.c +@@ -46,11 +46,12 @@ __u32 secure_tcpv6_sequence_number(const + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u32 i; ++ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; + + net_secret_init(); + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) +- secret[i] = net_secret[i] + (__force u32)daddr[i]; ++ secret[i] = net_secret[i] + (__force u32)daddr6->s6_addr32[i]; + secret[4] = net_secret[4] + + (((__force u16)sport << 16) + (__force u16)dport); + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) +@@ -68,11 +69,12 @@ u32 secure_ipv6_port_ephemeral(const __b + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u32 i; ++ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; + + net_secret_init(); + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) +- secret[i] = net_secret[i] + (__force u32) daddr[i]; ++ secret[i] = net_secret[i] + (__force u32) daddr6->s6_addr32[i]; + secret[4] = net_secret[4] + (__force u32)dport; + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) + secret[i] = net_secret[i]; +@@ -150,11 +152,12 @@ u64 secure_dccpv6_sequence_number(__be32 + u32 hash[MD5_DIGEST_WORDS]; + u64 seq; + u32 i; ++ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; + + net_secret_init(); + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) +- secret[i] = net_secret[i] + daddr[i]; ++ secret[i] = net_secret[i] + daddr6->s6_addr32[i]; + secret[4] = net_secret[4] + + (((__force u16)sport << 16) + (__force u16)dport); + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) +--- a/net/ipv6/ip6_fib.c ++++ b/net/ipv6/ip6_fib.c +@@ -137,7 +137,7 @@ static __be32 addr_bit_set(const void *t + * See include/asm-generic/bitops/le.h. + */ + return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) & +- addr[fn_bit >> 5]; ++ net_hdr_word(&addr[fn_bit >> 5]); + } + + static struct fib6_node *node_alloc(void) +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -456,7 +456,7 @@ static void tcp_sack(const struct sk_buf + + /* Fast path for timestamp-only option */ + if (length == TCPOLEN_TSTAMP_ALIGNED +- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24) ++ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24) + | (TCPOPT_NOP << 16) + | (TCPOPT_TIMESTAMP << 8) + | TCPOLEN_TIMESTAMP)) +--- a/net/xfrm/xfrm_input.c ++++ b/net/xfrm/xfrm_input.c +@@ -154,8 +154,8 @@ int xfrm_parse_spi(struct sk_buff *skb, + if (!pskb_may_pull(skb, hlen)) + return -EINVAL; + +- *spi = *(__be32 *)(skb_transport_header(skb) + offset); +- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq); ++ *spi = net_hdr_word(skb_transport_header(skb) + offset); ++ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq); + return 0; + } + +--- a/net/ipv4/tcp_input.c ++++ b/net/ipv4/tcp_input.c +@@ -3760,14 +3760,16 @@ static bool tcp_parse_aligned_timestamp( + { + const __be32 *ptr = (const __be32 *)(th + 1); + +- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) +- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { ++ if (net_hdr_word(ptr) == ++ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { + tp->rx_opt.saw_tstamp = 1; + ++ptr; +- tp->rx_opt.rcv_tsval = ntohl(*ptr); ++ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr); + ++ptr; +- if (*ptr) +- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset; ++ if (net_hdr_word(ptr)) ++ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) - ++ tp->tsoffset; + else + tp->rx_opt.rcv_tsecr = 0; + return true; +--- a/include/uapi/linux/if_pppox.h ++++ b/include/uapi/linux/if_pppox.h +@@ -47,6 +47,7 @@ struct pppoe_addr { + */ + struct pptp_addr { + __u16 call_id; ++ __u16 pad; + struct in_addr sin_addr; + }; + +--- a/net/ipv6/netfilter/nf_log_ipv6.c ++++ b/net/ipv6/netfilter/nf_log_ipv6.c +@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct nf_l + /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */ + nf_log_buf_add(m, "LEN=%Zu TC=%u HOPLIMIT=%u FLOWLBL=%u ", + ntohs(ih->payload_len) + sizeof(struct ipv6hdr), +- (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20, ++ (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20, + ih->hop_limit, +- (ntohl(*(__be32 *)ih) & 0x000fffff)); ++ (ntohl(net_hdr_word(ih)) & 0x000fffff)); + + fragment = 0; + ptr = ip6hoff + sizeof(struct ipv6hdr); +--- a/include/net/neighbour.h ++++ b/include/net/neighbour.h +@@ -262,8 +262,10 @@ static inline bool neigh_key_eq128(const + const u32 *n32 = (const u32 *)n->primary_key; + const u32 *p32 = pkey; + +- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) | +- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0; ++ return ((n32[0] ^ net_hdr_word(&p32[0])) | ++ (n32[1] ^ net_hdr_word(&p32[1])) | ++ (n32[2] ^ net_hdr_word(&p32[2])) | ++ (n32[3] ^ net_hdr_word(&p32[3]))) == 0; + } + + static inline struct neighbour *___neigh_lookup_noref( -- cgit v1.2.3