From f41c4f8d6770684f07544dfc1aaa880f82fe0260 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 11 Sep 2015 16:35:46 +0000 Subject: lantiq: Use the BAR0 base address in the ath PCI fixup code Fixes support for AR9287 on TP-Link TD-W8980 and possibly other devices which have an ath wifi chip at a PCI address other than 0xb8000000 (TD-W8980 for example has it's wifi chip at 0xbc000000). Signed-off-by: Geoffrey McRae Signed-off-by: Martin Blumenstingl git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46869 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch | 8 ++++---- .../0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'target') diff --git a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch index 094d16c5c9..ec769ccf63 100644 --- a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -431,8 +431,6 @@ Signed-off-by: John Crispin +#include +#include + -+#define LTQ_PCI_MEM_BASE 0x18000000 -+ +struct ath_fixup { + u16 *cal_data; + unsigned slot; @@ -448,6 +446,7 @@ Signed-off-by: John Crispin + u16 cmd; + u32 bar0; + u32 val; ++ u32 base; + unsigned i; + + for (i = 0; i < ath_num_fixups; i++) { @@ -471,14 +470,15 @@ Signed-off-by: John Crispin + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + -+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); ++ base = dev->resource[0].start; ++ mem = ioremap(base, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); diff --git a/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch index 04c2071f32..72ae1c92f3 100644 --- a/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ b/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -431,8 +431,6 @@ Signed-off-by: John Crispin +#include +#include + -+#define LTQ_PCI_MEM_BASE 0x18000000 -+ +struct ath_fixup { + u16 *cal_data; + unsigned slot; @@ -448,6 +446,7 @@ Signed-off-by: John Crispin + u16 cmd; + u32 bar0; + u32 val; ++ u32 base; + unsigned i; + + for (i = 0; i < ath_num_fixups; i++) { @@ -471,14 +470,15 @@ Signed-off-by: John Crispin + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + -+ mem = ioremap(LTQ_PCI_MEM_BASE, 0x10000); ++ base = dev->resource[0].start; ++ mem = ioremap(base, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, LTQ_PCI_MEM_BASE); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); -- cgit v1.2.3