From 588d69a7c7bdd5051d3bf1362eeef3b11a9ca901 Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Wed, 4 Jun 2008 13:51:17 +0000 Subject: add preliminary Marvell Orion support git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11352 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../004-make_window_setup_a_little_more_safe.patch | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 target/linux/orion/patches/004-make_window_setup_a_little_more_safe.patch (limited to 'target/linux/orion/patches/004-make_window_setup_a_little_more_safe.patch') diff --git a/target/linux/orion/patches/004-make_window_setup_a_little_more_safe.patch b/target/linux/orion/patches/004-make_window_setup_a_little_more_safe.patch new file mode 100644 index 0000000000..f5f1de4c2f --- /dev/null +++ b/target/linux/orion/patches/004-make_window_setup_a_little_more_safe.patch @@ -0,0 +1,79 @@ +Currently, Orion window setup uses hardcoded window indexes for each +of the boot/cs0/cs1/cs2/PCIe WA windows. The static window allocation +used can clash if board support code will ever attempt to configure +both a dev2 and a PCIe WA window, as both of those use CPU mbus window +#7 at present. + +This patch keeps track of the last used window, and opens subsequently +requested windows sequentially, starting from 4. (Windows 0-3 are used +as MEM/IO windows for the PCI/PCIe buses.) + +Signed-off-by: Lennert Buytenhek +--- + arch/arm/mach-orion5x/addr-map.c | 20 +++++++++++++++----- + 1 files changed, 15 insertions(+), 5 deletions(-) + +--- a/arch/arm/mach-orion5x/addr-map.c ++++ b/arch/arm/mach-orion5x/addr-map.c +@@ -70,6 +70,7 @@ + + + struct mbus_dram_target_info orion5x_mbus_dram_info; ++static int __initdata win_alloc_count; + + static int __init orion5x_cpu_win_can_remap(int win) + { +@@ -87,6 +88,9 @@ + static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) + { ++ if (win >= 8) ++ panic("setup_cpu_win: trying to allocate window %d\n", win); ++ + orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); + orion5x_write(CPU_WIN_CTRL(win), + ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); +@@ -128,6 +132,7 @@ + TARGET_PCIE, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, + TARGET_PCI, ATTR_PCI_MEM, -1); ++ win_alloc_count = 4; + + /* + * Setup MBUS dram target info. +@@ -156,25 +161,30 @@ + + void __init orion5x_setup_dev_boot_win(u32 base, u32 size) + { +- setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); ++ setup_cpu_win(win_alloc_count++, base, size, ++ TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); + } + + void __init orion5x_setup_dev0_win(u32 base, u32 size) + { +- setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); ++ setup_cpu_win(win_alloc_count++, base, size, ++ TARGET_DEV_BUS, ATTR_DEV_CS0, -1); + } + + void __init orion5x_setup_dev1_win(u32 base, u32 size) + { +- setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); ++ setup_cpu_win(win_alloc_count++, base, size, ++ TARGET_DEV_BUS, ATTR_DEV_CS1, -1); + } + + void __init orion5x_setup_dev2_win(u32 base, u32 size) + { +- setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); ++ setup_cpu_win(win_alloc_count++, base, size, ++ TARGET_DEV_BUS, ATTR_DEV_CS2, -1); + } + + void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) + { +- setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); ++ setup_cpu_win(win_alloc_count++, base, size, ++ TARGET_PCIE, ATTR_PCIE_WA, -1); + } -- cgit v1.2.3