From 5ced8bb7fd2b537a7273ade39d74971aaad1a3f7 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 18 Jan 2016 15:54:23 +0000 Subject: lantiq: drop linux 4.1 support Signed-off-by: Felix Fietkau git-svn-id: svn://svn.openwrt.org/openwrt/trunk@48323 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- ...023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch | 537 --------------------- 1 file changed, 537 deletions(-) delete mode 100644 target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch (limited to 'target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch') diff --git a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch deleted file mode 100644 index 3f50a3b262..0000000000 --- a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch +++ /dev/null @@ -1,537 +0,0 @@ -From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:15:36 +0200 -Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G - -Signed-off-by: John Crispin ---- - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 237 insertions(+) - create mode 100644 drivers/net/phy/lantiq.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -165,6 +165,11 @@ config RTL8306_PHY - tristate "Driver for Realtek RTL8306S switches" - select SWCONFIG - -+config LANTIQ_PHY -+ tristate "Driver for Lantiq PHYs" -+ ---help--- -+ Supports the 11G and 22E PHYs. -+ - config FIXED_PHY - tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" - depends on PHYLIB ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o - obj-$(CONFIG_DP83640_PHY) += dp83640.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_MICREL_PHY) += micrel.o -+obj-$(CONFIG_LANTIQ_PHY) += lantiq.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_AT803X_PHY) += at803x.o ---- /dev/null -+++ b/drivers/net/phy/lantiq.c -@@ -0,0 +1,278 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2012 Daniel Schwierzeck -+ */ -+ -+#include -+#include -+#include -+ -+#define MII_MMDCTRL 0x0d -+#define MII_MMDDATA 0x0e -+ -+#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */ -+#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */ -+ -+#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */ -+#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */ -+#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */ -+#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */ -+#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */ -+#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */ -+#define INT_VR9_11G_LSTC BIT(0) /* Link state change */ -+#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC) -+ -+#define ADVERTISED_MPD BIT(10) /* Multi-port device */ -+ -+#define MMD_DEVAD 0x1f -+#define MMD_ACTYPE_SHIFT 14 -+#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT) -+#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT) -+#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT) -+#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT) -+ -+static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev, -+ u16 regnum) -+{ -+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD); -+ phy_write(phydev, MII_MMDDATA, regnum); -+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD); -+ -+ return phy_read(phydev, MII_MMDDATA); -+} -+ -+static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev, -+ u16 regnum, u16 val) -+{ -+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD); -+ phy_write(phydev, MII_MMDDATA, regnum); -+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD); -+ phy_write(phydev, MII_MMDDATA, val); -+ -+ return 0; -+} -+ -+#if IS_ENABLED(CONFIG_OF_MDIO) -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ u32 tmp; -+ -+ /* store the led values if one was passed by the devicetree */ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledch", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e0, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledcl", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e1, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0h", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e2, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0l", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e3, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1h", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e4, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1l", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e5, tmp); -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2h", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e6, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2l", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e7, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3h", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e8, tmp); -+ -+ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3l", &tmp)) -+ vr9_gphy_mmd_write(phydev, 0x1e9, tmp); -+ -+ return 0; -+} -+#else -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+#endif /* CONFIG_OF_MDIO */ -+ -+static int vr9_gphy_config_init(struct phy_device *phydev) -+{ -+ int err; -+ -+ dev_dbg(&phydev->dev, "%s\n", __func__); -+ -+ /* Mask all interrupts */ -+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0); -+ if (err) -+ return err; -+ -+ /* Clear all pending interrupts */ -+ phy_read(phydev, MII_VR9_11G_ISTAT); -+ -+ vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5); -+ vr9_gphy_mmd_write(phydev, 0x1e1, 0x67); -+ vr9_gphy_mmd_write(phydev, 0x1e2, 0x42); -+ vr9_gphy_mmd_write(phydev, 0x1e3, 0x10); -+ vr9_gphy_mmd_write(phydev, 0x1e4, 0x70); -+ vr9_gphy_mmd_write(phydev, 0x1e5, 0x03); -+ vr9_gphy_mmd_write(phydev, 0x1e6, 0x20); -+ vr9_gphy_mmd_write(phydev, 0x1e7, 0x00); -+ vr9_gphy_mmd_write(phydev, 0x1e8, 0x40); -+ vr9_gphy_mmd_write(phydev, 0x1e9, 0x20); -+ -+ vr9_gphy_of_reg_init(phydev); -+ -+ return 0; -+} -+ -+static int vr9_gphy_config_aneg(struct phy_device *phydev) -+{ -+ int reg, err; -+ -+ /* Advertise as multi-port device */ -+ reg = phy_read(phydev, MII_CTRL1000); -+ reg |= ADVERTISED_MPD; -+ err = phy_write(phydev, MII_CTRL1000, reg); -+ if (err) -+ return err; -+ -+ return genphy_config_aneg(phydev); -+} -+ -+static int vr9_gphy_ack_interrupt(struct phy_device *phydev) -+{ -+ int reg; -+ -+ /* -+ * Possible IRQ numbers: -+ * - IM3_IRL18 for GPHY0 -+ * - IM3_IRL17 for GPHY1 -+ * -+ * Due to a silicon bug IRQ lines are not really independent from -+ * each other. Sometimes the two lines are driven at the same time -+ * if only one GPHY core raises the interrupt. -+ */ -+ -+ reg = phy_read(phydev, MII_VR9_11G_ISTAT); -+ -+ return (reg < 0) ? reg : 0; -+} -+ -+static int vr9_gphy_did_interrupt(struct phy_device *phydev) -+{ -+ int reg; -+ -+ reg = phy_read(phydev, MII_VR9_11G_ISTAT); -+ -+ return reg > 0; -+} -+ -+static int vr9_gphy_config_intr(struct phy_device *phydev) -+{ -+ int err; -+ -+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) -+ err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK); -+ else -+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0); -+ -+ return err; -+} -+ -+static struct phy_driver lantiq_phy[] = { -+ { -+ .phy_id = 0xd565a400, -+ .phy_id_mask = 0xfffffff8, -+ .name = "Lantiq XWAY PEF7071", -+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), -+ .flags = 0, /*PHY_HAS_INTERRUPT,*/ -+ .config_init = vr9_gphy_config_init, -+ .config_aneg = vr9_gphy_config_aneg, -+ .read_status = genphy_read_status, -+ .ack_interrupt = vr9_gphy_ack_interrupt, -+ .did_interrupt = vr9_gphy_did_interrupt, -+ .config_intr = vr9_gphy_config_intr, -+ .driver = { .owner = THIS_MODULE }, -+ }, { -+ .phy_id = 0x030260D0, -+ .phy_id_mask = 0xfffffff0, -+ .name = "Lantiq XWAY VR9 GPHY 11G v1.3", -+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), -+ .flags = 0, /*PHY_HAS_INTERRUPT,*/ -+ .config_init = vr9_gphy_config_init, -+ .config_aneg = vr9_gphy_config_aneg, -+ .read_status = genphy_read_status, -+ .ack_interrupt = vr9_gphy_ack_interrupt, -+ .did_interrupt = vr9_gphy_did_interrupt, -+ .config_intr = vr9_gphy_config_intr, -+ .driver = { .owner = THIS_MODULE }, -+ }, { -+ .phy_id = 0xd565a408, -+ .phy_id_mask = 0xfffffff8, -+ .name = "Lantiq XWAY VR9 GPHY 11G v1.4", -+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), -+ .flags = 0, /*PHY_HAS_INTERRUPT,*/ -+ .config_init = vr9_gphy_config_init, -+ .config_aneg = vr9_gphy_config_aneg, -+ .read_status = genphy_read_status, -+ .ack_interrupt = vr9_gphy_ack_interrupt, -+ .did_interrupt = vr9_gphy_did_interrupt, -+ .config_intr = vr9_gphy_config_intr, -+ .driver = { .owner = THIS_MODULE }, -+ }, { -+ .phy_id = 0xd565a418, -+ .phy_id_mask = 0xfffffff8, -+ .name = "Lantiq XWAY XRX PHY22F v1.4", -+ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), -+ .flags = 0, /*PHY_HAS_INTERRUPT,*/ -+ .config_init = vr9_gphy_config_init, -+ .config_aneg = vr9_gphy_config_aneg, -+ .read_status = genphy_read_status, -+ .ack_interrupt = vr9_gphy_ack_interrupt, -+ .did_interrupt = vr9_gphy_did_interrupt, -+ .config_intr = vr9_gphy_config_intr, -+ .driver = { .owner = THIS_MODULE }, -+ }, -+}; -+ -+static int __init ltq_phy_init(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) { -+ int err = phy_driver_register(&lantiq_phy[i]); -+ if (err) -+ pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name); -+ } -+ -+ return 0; -+} -+ -+static void __exit ltq_phy_exit(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) -+ phy_driver_unregister(&lantiq_phy[i]); -+} -+ -+module_init(ltq_phy_init); -+module_exit(ltq_phy_exit); -+ -+MODULE_DESCRIPTION("Lantiq PHY drivers"); -+MODULE_AUTHOR("Daniel Schwierzeck "); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt -@@ -0,0 +1,216 @@ -+Lanitq PHY binding -+============================================ -+ -+This devicetree binding controls the lantiq ethernet phys led functionality. -+ -+Example: -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "lantiq,xrx200-mdio"; -+ phy5: ethernet-phy@5 { -+ reg = <0x1>; -+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; -+ }; -+ phy11: ethernet-phy@11 { -+ reg = <0x11>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy12: ethernet-phy@12 { -+ reg = <0x12>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ phy13: ethernet-phy@13 { -+ reg = <0x13>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy14: ethernet-phy@14 { -+ reg = <0x14>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ }; -+ -+Register Description -+============================================ -+ -+LEDCH: -+ -+Name Hardware Reset Value -+LEDCH 0x00C5 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| FBF | SBF |RES | NACS | -+========================================= -+ -+Field Bits Type Description -+FBC 7:6 RW Fast Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+SBF 5:4 RW Slow Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+NACS 2:0 RW Inverse of Scan Function -+ --- -+ 0x0 (000b) NONE No Function -+ 0x1 (001b) LINK Complex function enabled when link is up -+ 0x2 (010b) PDOWN Complex function enabled when device is powered-down -+ 0x3 (011b) EEE Complex function enabled when device is in EEE mode -+ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running -+ 0x5 (101b) ABIST Complex function enabled when analog self-test is running -+ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running -+ 0x7 (111b) TEST Complex function enabled when test mode is running -+ -+LEDCL: -+ -+Name Hardware Reset Value -+LEDCL 0x0067 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+|RES | SCAN |RES | CBLINK | -+========================================= -+ -+Field Bits Type Description -+SCAN 6:4 RW Complex Scan Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+CBLINK 2:0 RW Complex Blinking Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+LEDxH: -+ -+Name Hardware Reset Value -+LED0H 0x0070 -+LED1H 0x0020 -+LED2H 0x0040 -+LED3H 0x0040 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| CON | BLINKF | -+========================================= -+ -+Field Bits Type Description -+CON 7:4 RW Constant On Configuration -+ --- -+ 0x0 (0000b) NONE LED does not light up constantly -+ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN LED is on when device is powered-down -+ 0x9 (1001b) EEE LED is on when device is in EEE mode -+ 0xA (1010b) ANEG LED is on when auto-negotiation is running -+ 0xB (1011b) ABIST LED is on when analog self-test is running -+ 0xC (1100b) CDIAG LED is on when cable diagnostics are running -+ -+BLINKF 3:0 RW Fast Blinking Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are running -+ -+LEDxL: -+ -+Name Hardware Reset Value -+LED0L 0x0003 -+LED1L 0x0000 -+LED2L 0x0000 -+LED3L 0x0020 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| BLINKS | PULSE | -+========================================= -+ -+Field Bits Type Description -+BLINKS 7:4 RW Slow Blinkin Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning -+ -+PULSE 3:0 RW Pulsing Configuration -+ The pulse field is a mask field by which certain events can be combined -+ --- -+ 0x0 (0000b) NONE No pulsing -+ 0x1 (0001b) TXACT Transmit activity -+ 0x2 (0010b) RXACT Receive activity -+ 0x4 (0100b) COL Collision -+ 0x8 (1000b) RES Reserved -- cgit v1.2.3