From e291d89f5c9c3d0de27c73d5f775964fc701aca6 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Tue, 29 Oct 2013 02:19:09 +0000 Subject: imx6: add initial 3.12 support Signed-off-by: Luka Perkov git-svn-id: svn://svn.openwrt.org/openwrt/trunk@38574 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- ...6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch (limited to 'target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch') diff --git a/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch new file mode 100644 index 0000000000..c8e4db1f89 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch @@ -0,0 +1,44 @@ +From 8d6a35fb13406f87d926fffeee0d70360ce3077d Mon Sep 17 00:00:00 2001 +From: Sean Cross +Date: Thu, 26 Sep 2013 11:24:46 +0800 +Subject: [PATCH] ARM: imx6q: Add PCIe bits to GPR syscon definition + +PCIe requires additional bits be defined for GPR8 and GPR12. + +Signed-off-by: Sean Cross +Signed-off-by: Shawn Guo +Signed-off-by: Bjorn Helgaas +--- + include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +index b6bdcd6..e00e9f3 100644 +--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h ++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +@@ -241,6 +241,12 @@ + + #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) + ++#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) ++#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) ++ + #define IMX6Q_GPR9_TZASC2_BYP BIT(1) + #define IMX6Q_GPR9_TZASC1_BYP BIT(0) + +@@ -273,7 +279,9 @@ + #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) + #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) + #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) ++#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) + #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) ++#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) + + #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) + #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) +-- +1.8.4.1 + -- cgit v1.2.3