From 8dc562dfaaeb61781b0e1be0b729ea7c708391f3 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Wed, 28 Mar 2012 20:42:15 +0000 Subject: bcm63xx: add missing bits from extirq support Add missing external IRQ code parts for older chips in the new code. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31128 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../patches-3.3/305-missing_ext_irq_bits.patch | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch (limited to 'target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch') diff --git a/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch b/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch new file mode 100644 index 0000000000..a350c4d554 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch @@ -0,0 +1,96 @@ +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -45,8 +45,8 @@ static void __internal_irq_unmask_64(uns + #define is_ext_irq_cascaded 0 + #define ext_irq_start 0 + #define ext_irq_end 0 +-#define ext_irq_count 0 +-#define ext_irq_cfg_reg1 0 ++#define ext_irq_count 4 ++#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345 + #define ext_irq_cfg_reg2 0 + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 +@@ -122,11 +122,15 @@ static void bcm63xx_init_irq(void) + irq_stat_addr += PERF_IRQSTAT_6338_REG; + irq_mask_addr += PERF_IRQMASK_6338_REG; + irq_bits = 32; ++ ext_irq_count = 4; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; + break; + case BCM6345_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6345_REG; + irq_mask_addr += PERF_IRQMASK_6345_REG; + irq_bits = 32; ++ ext_irq_count = 4; ++ ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; + break; + case BCM6348_CPU_ID: + irq_stat_addr += PERF_IRQSTAT_6348_REG; +@@ -413,7 +417,8 @@ static int bcm63xx_external_irq_set_type + reg = bcm_perf_readl(regaddr); + irq %= 4; + +- if (BCMCPU_IS_6348()) { ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM6348_CPU_ID: + if (levelsense) + reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); + else +@@ -426,9 +431,12 @@ static int bcm63xx_external_irq_set_type + reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); + else + reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); +- } ++ break; + +- if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { ++ case BCM6338_CPU_ID: ++ case BCM6345_CPU_ID: ++ case BCM6358_CPU_ID: ++ case BCM6368_CPU_ID: + if (levelsense) + reg |= EXTIRQ_CFG_LEVELSENSE(irq); + else +@@ -441,6 +449,9 @@ static int bcm63xx_external_irq_set_type + reg |= EXTIRQ_CFG_BOTHEDGE(irq); + else + reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); ++ break; ++ default: ++ BUG(); + } + + bcm_perf_writel(reg, regaddr); +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -71,6 +71,9 @@ void bcm63xx_machine_reboot(void) + case BCM6338_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; + break; ++ case BCM6345_CPU_ID: ++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345; ++ break; + case BCM6348_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348; + break; +@@ -80,6 +83,9 @@ void bcm63xx_machine_reboot(void) + } + + for (i = 0; i < 2; i++) { ++ if (!perf_regs[i]) ++ break; ++ + reg = bcm_perf_readl(perf_regs[i]); + if (BCMCPU_IS_6348()) { + reg &= ~EXTIRQ_CFG_MASK_ALL_6348; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -134,6 +134,7 @@ + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_6338 0x14 ++#define PERF_EXTIRQ_CFG_REG_6345 0x14 + #define PERF_EXTIRQ_CFG_REG_6348 0x14 + #define PERF_EXTIRQ_CFG_REG_6358 0x14 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 -- cgit v1.2.3