From 2dc1e11c688a439084692e0b86d20adc0310d42c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alvaro=20Fern=C3=A1ndez=20Rojas?= Date: Mon, 20 Jun 2016 23:24:50 +0200 Subject: As usual these patches were extracted from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- ...-Fix-the-name-of-the-VSYNCD_EVEN-register.patch | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 target/linux/brcm2708/patches-4.4/0291-drm-vc4-Fix-the-name-of-the-VSYNCD_EVEN-register.patch (limited to 'target/linux/brcm2708/patches-4.4/0291-drm-vc4-Fix-the-name-of-the-VSYNCD_EVEN-register.patch') diff --git a/target/linux/brcm2708/patches-4.4/0291-drm-vc4-Fix-the-name-of-the-VSYNCD_EVEN-register.patch b/target/linux/brcm2708/patches-4.4/0291-drm-vc4-Fix-the-name-of-the-VSYNCD_EVEN-register.patch new file mode 100644 index 0000000000..6d9e1c0039 --- /dev/null +++ b/target/linux/brcm2708/patches-4.4/0291-drm-vc4-Fix-the-name-of-the-VSYNCD_EVEN-register.patch @@ -0,0 +1,36 @@ +From e3f14344d3d427d0b9cdbf4e3039d88320836471 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Mon, 15 Feb 2016 17:06:02 -0800 +Subject: [PATCH 291/304] drm/vc4: Fix the name of the VSYNCD_EVEN register. + +It's used for delaying vsync in interlaced mode. + +Signed-off-by: Eric Anholt +(cherry picked from commit c31806fbdda910d337b60896040afa708bdfa2bd) +--- + drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- + drivers/gpu/drm/vc4/vc4_regs.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/vc4/vc4_crtc.c ++++ b/drivers/gpu/drm/vc4/vc4_crtc.c +@@ -88,7 +88,7 @@ static const struct { + } crtc_regs[] = { + CRTC_REG(PV_CONTROL), + CRTC_REG(PV_V_CONTROL), +- CRTC_REG(PV_VSYNCD), ++ CRTC_REG(PV_VSYNCD_EVEN), + CRTC_REG(PV_HORZA), + CRTC_REG(PV_HORZB), + CRTC_REG(PV_VERTA), +--- a/drivers/gpu/drm/vc4/vc4_regs.h ++++ b/drivers/gpu/drm/vc4/vc4_regs.h +@@ -187,7 +187,7 @@ + # define PV_VCONTROL_CONTINUOUS BIT(1) + # define PV_VCONTROL_VIDEN BIT(0) + +-#define PV_VSYNCD 0x08 ++#define PV_VSYNCD_EVEN 0x08 + + #define PV_HORZA 0x0c + # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) -- cgit v1.2.3