From b6854cf3b73274b692b042f211b0614a74a7820a Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 12 Dec 2015 11:27:51 +0000 Subject: ar71xx: add rx/tx delay definitons for qca955x's MAC This patch adds the rx/tx register offsets for the qca955x SoC. Signed-off-by: Chris R Blake git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47882 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch (limited to 'target/linux/ar71xx') diff --git a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch new file mode 100644 index 0000000000..2d89fd8a92 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay-defs.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -1098,5 +1098,11 @@ + + #define QCA955X_ETH_CFG_RGMII_EN BIT(0) + #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) ++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14) ++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14 ++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16) ++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3 ++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16 + + #endif /* __ASM_MACH_AR71XX_REGS_H */ -- cgit v1.2.3