From ab8c13df138bbaec1ee7e779f228c8dc0d10e7a8 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 20 Jun 2016 16:41:33 +0200 Subject: ar71xx: Fix TP-LINK Archer-C5/C7 v2 rfkill Fix ARCHER_C7_GPIO_BTN_RFKILL, which is attached to GPIO23 Signed-off-by: Lars Buerding --- target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c index fc1251303e..d93dab2849 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c @@ -50,7 +50,7 @@ #define ARCHER_C7_GPIO_LED_USB1 18 #define ARCHER_C7_GPIO_LED_USB2 19 -#define ARCHER_C7_GPIO_BTN_RFKILL 13 +#define ARCHER_C7_GPIO_BTN_RFKILL 23 #define ARCHER_C7_GPIO_BTN_RESET 16 #define ARCHER_C7_GPIO_USB1_POWER 22 -- cgit v1.2.3 From 1817b15e04a129b6ad633ec40c2a5225de41212d Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 20 Jun 2016 16:46:50 +0200 Subject: ar71xx: add proper support for Archer-C7 V2 This has minor differences to the V1 Signed-off-by: John Crispin --- .../ar71xx/files/arch/mips/ath79/mach-archer-c7.c | 44 ++++++++++++++++++++-- .../linux/ar71xx/files/arch/mips/ath79/machtypes.h | 1 + 2 files changed, 41 insertions(+), 4 deletions(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c index d93dab2849..f00998c669 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c @@ -50,7 +50,8 @@ #define ARCHER_C7_GPIO_LED_USB1 18 #define ARCHER_C7_GPIO_LED_USB2 19 -#define ARCHER_C7_GPIO_BTN_RFKILL 23 +#define ARCHER_C7_GPIO_BTN_RFKILL 13 +#define ARCHER_C7_V2_GPIO_BTN_RFKILL 23 #define ARCHER_C7_GPIO_BTN_RESET 16 #define ARCHER_C7_GPIO_USB1_POWER 22 @@ -122,6 +123,24 @@ static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = { }, }; +static struct gpio_keys_button archer_c7_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARCHER_C7_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARCHER_C7_V2_GPIO_BTN_RFKILL, + }, +}; + static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = { AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"), AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"), @@ -192,9 +211,6 @@ static void __init common_setup(bool pcie_slot) ath79_register_m25p80(&archer_c7_flash_data); ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), archer_c7_leds_gpio); - ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, - ARRAY_SIZE(archer_c7_gpio_keys), - archer_c7_gpio_keys); ath79_init_mac(tmpmac, mac, -1); ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); @@ -242,6 +258,9 @@ static void __init common_setup(bool pcie_slot) static void __init archer_c5_setup(void) { + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, + ARRAY_SIZE(archer_c7_gpio_keys), + archer_c7_gpio_keys); common_setup(true); } @@ -250,14 +269,31 @@ MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5", static void __init archer_c7_setup(void) { + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, + ARRAY_SIZE(archer_c7_gpio_keys), + archer_c7_gpio_keys); common_setup(true); } MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7", archer_c7_setup); +static void __init archer_c7_v2_setup(void) +{ + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, + ARRAY_SIZE(archer_c7_v2_gpio_keys), + archer_c7_v2_gpio_keys); + common_setup(true); +} + +MIPS_MACHINE(ATH79_MACH_ARCHER_C7_V2, "ARCHER-C7-V2", "TP-LINK Archer C7", + archer_c7_v2_setup); + static void __init tl_wdr4900_v2_setup(void) { + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, + ARRAY_SIZE(archer_c7_gpio_keys), + archer_c7_gpio_keys); common_setup(false); } diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index 4879255231..962511c23f 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -42,6 +42,7 @@ enum ath79_mach_type { ATH79_MACH_AP96, /* Atheros AP96 */ ATH79_MACH_ARCHER_C5, /* TP-LINK Archer C5 board */ ATH79_MACH_ARCHER_C7, /* TP-LINK Archer C7 board */ + ATH79_MACH_ARCHER_C7_V2, /* TP-LINK Archer C7 V2 board */ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */ ATH79_MACH_BHU_BXU2000N2_A1, /* BHU BXU2000n-2 A1 */ ATH79_MACH_BSB, /* Smart Electronics Black Swift board */ -- cgit v1.2.3 From d42ccc9f28aca96bdd7c83cfac43ae81d24bc5a2 Mon Sep 17 00:00:00 2001 From: Cezary Jackiewicz Date: Mon, 20 Jun 2016 16:47:34 +0200 Subject: ar71xx: add support for TP-LINK TL-WR842N/ND v3 - CPU QCA9531-BL3A - RAM: 64MB - flash: 16MB - USB AP143 platform, similar to tl-wr841n v10/v11, but with USB Signed-off-by: Cezary Jackiewicz --- .../ar71xx/files/arch/mips/ath79/Kconfig.openwrt | 15 ++-- .../files/arch/mips/ath79/mach-tl-wr841n-v9.c | 97 +++++++++++++++++++++- .../linux/ar71xx/files/arch/mips/ath79/machtypes.h | 1 + 3 files changed, 105 insertions(+), 8 deletions(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt index 0fb2df26d4..6cf7f830e1 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt +++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt @@ -1314,13 +1314,14 @@ config ATH79_MACH_TL_WR841N_V8 select ATH79_DEV_WMAC config ATH79_MACH_TL_WR841N_V9 - bool "TP-LINK TL-WR841N/ND v9 support" - select SOC_QCA953X - select ATH79_DEV_ETH - select ATH79_DEV_GPIO_BUTTONS - select ATH79_DEV_LEDS_GPIO - select ATH79_DEV_M25P80 - select ATH79_DEV_WMAC + bool "TP-LINK TL-WR841N/ND v9/TL-WR842N/ND v3 support" + select SOC_QCA953X + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC config ATH79_MACH_TL_WR941ND bool "TP-LINK TL-WR941ND support" diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c index 3e5c2a2522..02096031db 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c @@ -1,7 +1,8 @@ /* - * TP-LINK TL-WR841N/ND v9 + * TP-LINK TL-WR841N/ND v9/TL-WR842N/ND v3 * * Copyright (C) 2014 Matthias Schiffer + * Copyright (C) 2016 Cezary Jackiewicz * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -19,6 +20,7 @@ #include "dev-gpio-buttons.h" #include "dev-leds-gpio.h" #include "dev-m25p80.h" +#include "dev-usb.h" #include "dev-wmac.h" #include "machtypes.h" @@ -33,6 +35,20 @@ #define TL_WR841NV9_GPIO_BTN_RESET 12 #define TL_WR841NV9_GPIO_BTN_WIFI 17 +#define TL_WR842NV3_GPIO_LED_SYSTEM 2 +#define TL_WR842NV3_GPIO_LED_WLAN 3 +#define TL_WR842NV3_GPIO_LED_WAN_RED 4 +#define TL_WR842NV3_GPIO_LED_WAN_GREEN 11 +#define TL_WR842NV3_GPIO_LED_LAN1 12 +#define TL_WR842NV3_GPIO_LED_LAN2 13 +#define TL_WR842NV3_GPIO_LED_LAN3 14 +#define TL_WR842NV3_GPIO_LED_LAN4 15 +#define TL_WR842NV3_GPIO_LED_3G 16 +#define TL_WR842NV3_GPIO_LED_WPS 17 + +#define TL_WR842NV3_GPIO_BTN_RESET 1 +#define TL_WR842NV3_GPIO_BTN_WIFI 0 + #define TL_WR841NV9_KEYS_POLL_INTERVAL 20 /* msecs */ #define TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV9_KEYS_POLL_INTERVAL) @@ -95,6 +111,68 @@ static struct gpio_keys_button tl_wr841n_v9_gpio_keys[] __initdata = { } }; +static struct gpio_led tl_wr842n_v3_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR842NV3_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR842NV3_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR842NV3_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR842NV3_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR842NV3_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "tp-link:red:wan", + .gpio = TL_WR842NV3_GPIO_LED_WAN_RED, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR842NV3_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR842NV3_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:3g", + .gpio = TL_WR842NV3_GPIO_LED_3G, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR842NV3_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr842n_v3_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR842NV3_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WIFI button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR842NV3_GPIO_BTN_WIFI, + .active_low = 1, + } +}; + static void __init tl_ap143_setup(void) { @@ -142,3 +220,20 @@ static void __init tl_wr841n_v9_setup(void) MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9", tl_wr841n_v9_setup); + +static void __init tl_wr842n_v3_setup(void) +{ + tl_ap143_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr842n_v3_leds_gpio), + tl_wr842n_v3_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr842n_v3_gpio_keys), + tl_wr842n_v3_gpio_keys); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR842N_V3, "TL-WR842N-v3", "TP-LINK TL-WR842N/ND v3", + tl_wr842n_v3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index 962511c23f..d3e203eced 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -200,6 +200,7 @@ enum ath79_mach_type { ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */ ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */ ATH79_MACH_TL_WR842N_V2, /* TP-LINK TL-WR842N/ND v2 */ + ATH79_MACH_TL_WR842N_V3, /* TP-LINK TL-WR842N/ND v3 */ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ ATH79_MACH_TL_WR941ND_V5, /* TP-LINK TL-WR941ND v5 */ ATH79_MACH_TL_WR941ND_V6, /* TP-LINK TL-WR941ND v6 */ -- cgit v1.2.3 From b9cde0722a96d3cfce1784cf4659409058b08e36 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 20 Jun 2016 16:48:36 +0200 Subject: ar71xx: fix DDR write buffer flushing issues with 4.4 Signed-off-by: Felix Fietkau --- .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 89 ++++------------------ 1 file changed, 16 insertions(+), 73 deletions(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index b43c80a376..17dd3ac6b1 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -407,48 +407,14 @@ static void ath79_set_speed_dummy(int speed) { } -static void ath79_ddr_no_flush(void) -{ -} - static void ath79_ddr_flush_ge0(void) { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0); + ath79_ddr_wb_flush(0); } static void ath79_ddr_flush_ge1(void) { - ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1); -} - -static void ar724x_ddr_flush_ge0(void) -{ - ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0); -} - -static void ar724x_ddr_flush_ge1(void) -{ - ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1); -} - -static void ar91xx_ddr_flush_ge0(void) -{ - ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0); -} - -static void ar91xx_ddr_flush_ge1(void) -{ - ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1); -} - -static void ar933x_ddr_flush_ge0(void) -{ - ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0); -} - -static void ar933x_ddr_flush_ge1(void) -{ - ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1); + ath79_ddr_wb_flush(1); } static struct resource ath79_eth0_resources[] = { @@ -879,26 +845,25 @@ void __init ath79_register_eth(unsigned int id) return; } + if (id == 0) + pdata->ddr_flush = ath79_ddr_flush_ge0; + else + pdata->ddr_flush = ath79_ddr_flush_ge1; + switch (ath79_soc) { case ATH79_SOC_AR7130: - if (id == 0) { - pdata->ddr_flush = ath79_ddr_flush_ge0; + if (id == 0) pdata->set_speed = ath79_set_speed_ge0; - } else { - pdata->ddr_flush = ath79_ddr_flush_ge1; + else pdata->set_speed = ath79_set_speed_ge1; - } break; case ATH79_SOC_AR7141: case ATH79_SOC_AR7161: - if (id == 0) { - pdata->ddr_flush = ath79_ddr_flush_ge0; + if (id == 0) pdata->set_speed = ath79_set_speed_ge0; - } else { - pdata->ddr_flush = ath79_ddr_flush_ge1; + else pdata->set_speed = ath79_set_speed_ge1; - } pdata->has_gbit = 1; break; @@ -906,12 +871,10 @@ void __init ath79_register_eth(unsigned int id) if (id == 0) { pdata->reset_bit |= AR724X_RESET_GE0_MDIO | AR71XX_RESET_GE0_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge0; pdata->set_speed = ar7242_set_speed_ge0; } else { pdata->reset_bit |= AR724X_RESET_GE1_MDIO | AR71XX_RESET_GE1_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge1; pdata->set_speed = ath79_set_speed_dummy; } pdata->has_gbit = 1; @@ -934,13 +897,11 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR7240: if (id == 0) { pdata->reset_bit |= AR71XX_RESET_GE0_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge0; pdata->set_speed = ath79_set_speed_dummy; pdata->phy_mask = BIT(4); } else { pdata->reset_bit |= AR71XX_RESET_GE1_PHY; - pdata->ddr_flush = ar724x_ddr_flush_ge1; pdata->set_speed = ath79_set_speed_dummy; pdata->speed = SPEED_1000; @@ -962,27 +923,15 @@ void __init ath79_register_eth(unsigned int id) pdata->fifo_cfg3 = 0x01f00140; break; - case ATH79_SOC_AR9130: - if (id == 0) { - pdata->ddr_flush = ar91xx_ddr_flush_ge0; - pdata->set_speed = ar91xx_set_speed_ge0; - } else { - pdata->ddr_flush = ar91xx_ddr_flush_ge1; - pdata->set_speed = ar91xx_set_speed_ge1; - } - pdata->is_ar91xx = 1; - break; - case ATH79_SOC_AR9132: - if (id == 0) { - pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->has_gbit = 1; + /* fall through */ + case ATH79_SOC_AR9130: + if (id == 0) pdata->set_speed = ar91xx_set_speed_ge0; - } else { - pdata->ddr_flush = ar91xx_ddr_flush_ge1; + else pdata->set_speed = ar91xx_set_speed_ge1; - } pdata->is_ar91xx = 1; - pdata->has_gbit = 1; break; case ATH79_SOC_AR9330: @@ -990,14 +939,12 @@ void __init ath79_register_eth(unsigned int id) if (id == 0) { pdata->reset_bit = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO; - pdata->ddr_flush = ar933x_ddr_flush_ge0; pdata->set_speed = ath79_set_speed_dummy; pdata->phy_mask = BIT(4); } else { pdata->reset_bit = AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO; - pdata->ddr_flush = ar933x_ddr_flush_ge1; pdata->set_speed = ath79_set_speed_dummy; pdata->speed = SPEED_1000; @@ -1038,7 +985,6 @@ void __init ath79_register_eth(unsigned int id) ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; @@ -1073,7 +1019,6 @@ void __init ath79_register_eth(unsigned int id) ath79_switch_data.phy_poll_mask |= BIT(4); } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; @@ -1097,7 +1042,6 @@ void __init ath79_register_eth(unsigned int id) pdata->set_speed = qca955x_set_speed_sgmii; } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; @@ -1145,7 +1089,6 @@ void __init ath79_register_eth(unsigned int id) ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); } - pdata->ddr_flush = ath79_ddr_no_flush; pdata->has_gbit = 1; pdata->is_ar724x = 1; -- cgit v1.2.3 From 58d97c77333bb043c9e718f5f30c9b7712e76472 Mon Sep 17 00:00:00 2001 From: "P.Wassi" Date: Mon, 20 Jun 2016 16:54:16 +0200 Subject: ar71xx: Rename unifiac to unifiac-lite To avoid confusion with different unifiac devices, rename existing target "unifiac" to "unifiac-lite", before "unifiac-pro" is introduced. Signed-off-by: P.Wassi --- target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt | 2 +- .../linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c | 14 +++++++------- target/linux/ar71xx/files/arch/mips/ath79/machtypes.h | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt index 6cf7f830e1..715f389ca8 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt +++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt @@ -1443,7 +1443,7 @@ config ATH79_MACH_UBNT select ATH79_DEV_USB config ATH79_MACH_UBNT_UNIFIAC - bool "Ubiquiti UniFi AC (LITE) support" + bool "Ubiquiti UniFi AC (LITE/LR) support" select SOC_QCA956X select ATH79_DEV_AP9X_PCI if PCI select ATH79_DEV_ETH diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c index 072cf12a31..31cbe30d3f 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c @@ -73,7 +73,7 @@ static struct gpio_keys_button ubnt_unifiac_gpio_keys[] __initdata = { } }; -static void __init ubnt_unifiac_setup(void) +static void __init ubnt_unifiac_lite_setup(void) { u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); @@ -81,7 +81,7 @@ static void __init ubnt_unifiac_setup(void) ath79_init_mac(ath79_eth0_data.mac_addr, - eeprom + UNIFIAC_MAC0_OFFSET, 0); + eeprom + UNIFIAC_MAC0_OFFSET, 0); ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; @@ -99,12 +99,12 @@ static void __init ubnt_unifiac_setup(void) ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifiac_leds_gpio), - ubnt_unifiac_leds_gpio); + ubnt_unifiac_leds_gpio); ath79_register_gpio_keys_polled(-1, UNIFIAC_KEYS_POLL_INTERVAL, - ARRAY_SIZE(ubnt_unifiac_gpio_keys), - ubnt_unifiac_gpio_keys); + ARRAY_SIZE(ubnt_unifiac_gpio_keys), + ubnt_unifiac_gpio_keys); } -MIPS_MACHINE(ATH79_MACH_UBNT_UNIFIAC, "UBNT-UF-AC", "Ubiquiti UniFi-AC", - ubnt_unifiac_setup); +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFIAC_LITE, "UBNT-UF-AC-LITE", "Ubiquiti UniFi-AC-LITE", + ubnt_unifiac_lite_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index d3e203eced..2e8eb40a28 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -221,7 +221,7 @@ enum ath79_mach_type { ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */ ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ - ATH79_MACH_UBNT_UNIFIAC, /* Ubiquiti Unifi AC */ + ATH79_MACH_UBNT_UNIFIAC_LITE, /* Ubiquiti Unifi AC LITE/LR */ ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */ ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ -- cgit v1.2.3 From d354aaa58d046f343d024f4d0c0fa711c3dd1b2b Mon Sep 17 00:00:00 2001 From: "P.Wassi" Date: Mon, 20 Jun 2016 16:54:50 +0200 Subject: ar71xx: Add support for Ubiquiti UniFi AP AC PRO Add support for the Ubiquiti UniFi AP AC PRO Signed-off-by: P.Wassi --- .../ar71xx/files/arch/mips/ath79/Kconfig.openwrt | 3 +- .../files/arch/mips/ath79/mach-ubnt-unifiac.c | 69 ++++++++++++++++++++++ .../linux/ar71xx/files/arch/mips/ath79/machtypes.h | 1 + 3 files changed, 72 insertions(+), 1 deletion(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt index 715f389ca8..ac2cdaec3c 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt +++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt @@ -1443,7 +1443,7 @@ config ATH79_MACH_UBNT select ATH79_DEV_USB config ATH79_MACH_UBNT_UNIFIAC - bool "Ubiquiti UniFi AC (LITE/LR) support" + bool "Ubiquiti UniFi AC (LITE/LR/PRO) support" select SOC_QCA956X select ATH79_DEV_AP9X_PCI if PCI select ATH79_DEV_ETH @@ -1451,6 +1451,7 @@ config ATH79_MACH_UBNT_UNIFIAC select ATH79_DEV_LEDS_GPIO select ATH79_DEV_M25P80 select ATH79_DEV_WMAC + select ATH79_DEV_USB config ATH79_MACH_WEIO bool "WeIO board" diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c index 31cbe30d3f..9194bc1c07 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-unifiac.c @@ -21,6 +21,7 @@ #include #include +#include #include "common.h" #include "dev-ap9x-pci.h" @@ -29,6 +30,7 @@ #include "dev-leds-gpio.h" #include "dev-m25p80.h" #include "dev-wmac.h" +#include "dev-usb.h" #include "machtypes.h" @@ -108,3 +110,70 @@ static void __init ubnt_unifiac_lite_setup(void) MIPS_MACHINE(ATH79_MACH_UBNT_UNIFIAC_LITE, "UBNT-UF-AC-LITE", "Ubiquiti UniFi-AC-LITE", ubnt_unifiac_lite_setup); + +static struct ar8327_pad_cfg ubnt_unifiac_pro_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_platform_data ubnt_unifiac_pro_ar8327_data = { + .pad0_cfg = &ubnt_unifiac_pro_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + + +static struct mdio_board_info ubnt_unifiac_pro_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &ubnt_unifiac_pro_ar8327_data, + }, +}; + +static void __init ubnt_unifiac_pro_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(&ubnt_unifiac_flash_data); + + + ath79_init_mac(ath79_eth0_data.mac_addr, + eeprom + UNIFIAC_MAC0_OFFSET, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_mask = BIT(0); + + mdiobus_register_board_info(ubnt_unifiac_pro_mdio0_info, + ARRAY_SIZE(ubnt_unifiac_pro_mdio0_info)); + + ath79_register_mdio(0, 0x00); + ath79_register_eth(0); + + + ath79_register_usb(); + + + ath79_register_wmac(eeprom + UNIFIAC_WMAC_CALDATA_OFFSET, NULL); + + + ap91_pci_init(eeprom + UNIFIAC_PCI_CALDATA_OFFSET, NULL); + + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifiac_leds_gpio), + ubnt_unifiac_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UNIFIAC_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_unifiac_gpio_keys), + ubnt_unifiac_gpio_keys); +} + + +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFIAC_PRO, "UBNT-UF-AC-PRO", "Ubiquiti UniFi-AC-PRO", + ubnt_unifiac_pro_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index 2e8eb40a28..f53efff0b6 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -222,6 +222,7 @@ enum ath79_mach_type { ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ ATH79_MACH_UBNT_UNIFIAC_LITE, /* Ubiquiti Unifi AC LITE/LR */ + ATH79_MACH_UBNT_UNIFIAC_PRO, /* Ubiquiti Unifi AC PRO */ ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */ ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ -- cgit v1.2.3 From 9cb35e0499e49a24b480f14e4bab23f94a23aa87 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Tue, 21 Jun 2016 16:20:36 +0200 Subject: ar71xx/cpe510: enable LNA for CPE210/220/510/520 The LNA improves the rx path. Within a simple test setup it improved the signal from -60dbm to -40dbm. Signed-off-by: Alexander Couzens --- target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c index 8bf5c0f622..5cb052a84a 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c @@ -30,6 +30,9 @@ #define CPE510_GPIO_LED_L3 15 #define CPE510_GPIO_LED_L4 16 +#define CPE510_GPIO_EXTERNAL_LNA0 18 +#define CPE510_GPIO_EXTERNAL_LNA1 19 + #define CPE510_GPIO_BTN_RESET 4 #define CPE510_KEYS_POLL_INTERVAL 20 /* msecs */ @@ -93,6 +96,9 @@ static void __init cpe510_setup(void) ARRAY_SIZE(cpe510_gpio_keys), cpe510_gpio_keys); + ath79_wmac_set_ext_lna_gpio(0, CPE510_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, CPE510_GPIO_EXTERNAL_LNA1); + ath79_register_m25p80(NULL); ath79_register_mdio(1, 0); -- cgit v1.2.3 From 299c437ccd1fd605eef2e15f07397866864cf896 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Wed, 22 Jun 2016 14:12:09 +0200 Subject: ar71xx: update bomb ar71xx: split tp-link image building code into a separate file ar71xx: split legacy image building code into a separate file ar71xx: split ubnt image building code into a separate file ar71xx: move generic device image definitions to a separate file ar71xx: move nand device image definitions to a separate file ar71xx: Add support for initramfs images for OpenMesh devices ar71xx: Generate sysupgrade images for OpenMesh devices ar71xx: Move OpenMesh image target validation into subfunction ar71xx: Allow OpenMesh CE images with more than 3 files ar71xx: add kernel support for the OpenMesh OM2P-HSv3 ar71xx: add user-space support for the OpenMesh OM2P-HSv3 ar71xx: enable sysupgrade for the OpenMesh OM2P-HSv3 package/om-watchdog: add OpenMesh OM2P-HSv3 support package/uboot-envtools: add OpenMesh OM2P-HSv3 support ar71xx: add OM2P-HSv3 to the OM2P profile ar71xx: add kernel support for the OpenMesh MR1750v2 ar71xx: add user-space support for the OpenMesh MR1750v2 ar71xx: enable sysupgrade for the OpenMesh MR1750v2 package/om-watchdog: add OpenMesh MR1750v2 support package/uboot-envtools: add OpenMesh MR1750v2 support ar71xx: extract ath10k wifi board.bin for the OpenMesh MR1750v2 board ar71xx: add MR1750v2 to the MR1750 profile ar71xx/cpe510: split profile into 2 profiles cpe210 and cpe510 ar71xx/cpe510: use second wifi calibration table ar71xx: add GPIO pin for usb power switch for RouterBOARD 912 ar71xx: switch ordering and template to improve readability ar71xx: Fix TL-WR841N v11 LEDs, use separate machine Signed-off-by: Zoltan HERPAI --- .../ar71xx/files/arch/mips/ath79/mach-cpe510.c | 30 +++++++-- .../ar71xx/files/arch/mips/ath79/mach-mr1750.c | 1 + .../linux/ar71xx/files/arch/mips/ath79/mach-om2p.c | 1 + .../files/arch/mips/ath79/mach-tl-wr841n-v9.c | 71 +++++++++++++++++++++- .../linux/ar71xx/files/arch/mips/ath79/machtypes.h | 4 ++ 5 files changed, 100 insertions(+), 7 deletions(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c index 5cb052a84a..875589dde8 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c @@ -78,12 +78,8 @@ static struct gpio_keys_button cpe510_gpio_keys[] __initdata = { } }; - -static void __init cpe510_setup(void) +static void __init cpe_setup(u8 *mac) { - u8 *mac = (u8 *) KSEG1ADDR(0x1f830008); - u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); - /* Disable JTAG, enabling GPIOs 0-3 */ /* Configure OBS4 line, for GPIO 4*/ ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, @@ -105,9 +101,31 @@ static void __init cpe510_setup(void) ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_register_eth(1); +} + + +static void __init cpe210_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f830008); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + cpe_setup(mac); + + ath79_register_wmac(ee, mac); +} + +static void __init cpe510_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f830008); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff5000); + + cpe_setup(mac); ath79_register_wmac(ee, mac); } -MIPS_MACHINE(ATH79_MACH_CPE510, "CPE510", "TP-LINK CPE210/220/510/520", +MIPS_MACHINE(ATH79_MACH_CPE210, "CPE210", "TP-LINK CPE210/220", + cpe210_setup); + +MIPS_MACHINE(ATH79_MACH_CPE510, "CPE510", "TP-LINK CPE510/520", cpe510_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c index e3c04e7756..18101ce8e4 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c @@ -168,3 +168,4 @@ static void __init mr1750_setup(void) } MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup); +MIPS_MACHINE(ATH79_MACH_MR1750V2, "MR1750v2", "OpenMesh MR1750v2", mr1750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c index 6b0bdc3dcd..3b282a36ea 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c @@ -223,3 +223,4 @@ static void __init om2p_hs_setup(void) MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup); MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup); +MIPS_MACHINE(ATH79_MACH_OM2P_HSv3, "OM2P-HSv3", "OpenMesh OM2P HSv3", om2p_hs_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c index 02096031db..f806568f98 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c @@ -1,8 +1,9 @@ /* - * TP-LINK TL-WR841N/ND v9/TL-WR842N/ND v3 + * TP-LINK TL-WR841N/ND v9/v11 / TL-WR842N/ND v3 * * Copyright (C) 2014 Matthias Schiffer * Copyright (C) 2016 Cezary Jackiewicz + * Copyright (C) 2016 Stijn Segers * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -35,6 +36,19 @@ #define TL_WR841NV9_GPIO_BTN_RESET 12 #define TL_WR841NV9_GPIO_BTN_WIFI 17 +#define TL_WR841NV11_GPIO_LED_SYSTEM 1 +#define TL_WR841NV11_GPIO_LED_QSS 3 +#define TL_WR841NV11_GPIO_LED_WAN 4 +#define TL_WR841NV11_GPIO_LED_WAN_STATUS 2 +#define TL_WR841NV11_GPIO_LED_WLAN 13 +#define TL_WR841NV11_GPIO_LED_LAN1 16 +#define TL_WR841NV11_GPIO_LED_LAN2 15 +#define TL_WR841NV11_GPIO_LED_LAN3 14 +#define TL_WR841NV11_GPIO_LED_LAN4 11 + +#define TL_WR841NV11_GPIO_BTN_RESET 12 +#define TL_WR841NV11_GPIO_BTN_WIFI 17 + #define TL_WR842NV3_GPIO_LED_SYSTEM 2 #define TL_WR842NV3_GPIO_LED_WLAN 3 #define TL_WR842NV3_GPIO_LED_WAN_RED 4 @@ -111,6 +125,46 @@ static struct gpio_keys_button tl_wr841n_v9_gpio_keys[] __initdata = { } }; +static struct gpio_led tl_wr841n_v11_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR841NV9_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR841NV9_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR841NV9_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR841NV9_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841NV9_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR841NV11_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR841NV9_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wan_status", + .gpio = TL_WR841NV11_GPIO_LED_WAN_STATUS, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR841NV9_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + static struct gpio_led tl_wr842n_v3_leds_gpio[] __initdata = { { .name = "tp-link:green:lan1", @@ -221,6 +275,21 @@ static void __init tl_wr841n_v9_setup(void) MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9", tl_wr841n_v9_setup); +static void __init tl_wr841n_v11_setup(void) +{ + tl_ap143_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v11_leds_gpio), + tl_wr841n_v11_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v9_gpio_keys), + tl_wr841n_v9_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V11, "TL-WR841N-v11", "TP-LINK TL-WR841N/ND v11", + tl_wr841n_v11_setup); + static void __init tl_wr842n_v3_setup(void) { tl_ap143_setup(); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index f53efff0b6..fc02147e02 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -51,6 +51,7 @@ enum ath79_mach_type { ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */ ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */ ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */ + ATH79_MACH_CPE210, /* TP-LINK CPE210 */ ATH79_MACH_CPE510, /* TP-LINK CPE510 */ ATH79_MACH_CR3000, /* PowerCloud CR3000 */ ATH79_MACH_CR5000, /* PowerCloud CR5000 */ @@ -97,6 +98,7 @@ enum ath79_mach_type { ATH79_MACH_MR16, /* Cisco Meraki MR16 */ ATH79_MACH_MR18, /* Cisco Meraki MR18 */ ATH79_MACH_MR1750, /* OpenMesh MR1750 */ + ATH79_MACH_MR1750V2, /* OpenMesh MR1750v2 */ ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */ ATH79_MACH_MR600, /* OpenMesh MR600 */ ATH79_MACH_MR900, /* OpenMesh MR900 */ @@ -110,6 +112,7 @@ enum ath79_mach_type { ATH79_MACH_NBG6616, /* Zyxel NBG6616 */ ATH79_MACH_NBG6716, /* Zyxel NBG6716 */ ATH79_MACH_OM2P_HSv2, /* OpenMesh OM2P-HSv2 */ + ATH79_MACH_OM2P_HSv3, /* OpenMesh OM2P-HSv3 */ ATH79_MACH_OM2P_HS, /* OpenMesh OM2P-HS */ ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */ ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */ @@ -199,6 +202,7 @@ enum ath79_mach_type { ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */ ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */ ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */ + ATH79_MACH_TL_WR841N_V11, /* TP-LINK TL-WR841N/ND v11 */ ATH79_MACH_TL_WR842N_V2, /* TP-LINK TL-WR842N/ND v2 */ ATH79_MACH_TL_WR842N_V3, /* TP-LINK TL-WR842N/ND v3 */ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ -- cgit v1.2.3 From ab69c109ab81cbc1a438d983801a7813e32fb829 Mon Sep 17 00:00:00 2001 From: KeLei Liang Date: Wed, 22 Jun 2016 14:18:26 +0200 Subject: ar71xx: add WRTnode2Q support Signed-off-by: KeLei Liang --- .../ar71xx/files/arch/mips/ath79/Kconfig.openwrt | 10 ++ target/linux/ar71xx/files/arch/mips/ath79/Makefile | 1 + .../ar71xx/files/arch/mips/ath79/mach-wrtnode2q.c | 126 +++++++++++++++++++++ .../linux/ar71xx/files/arch/mips/ath79/machtypes.h | 1 + 4 files changed, 138 insertions(+) create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-wrtnode2q.c (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt index ac2cdaec3c..77415eb400 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt +++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt @@ -680,6 +680,16 @@ config ATH79_MACH_WRT400N select ATH79_DEV_LEDS_GPIO select ATH79_DEV_M25P80 +config ATH79_MACH_WRTNODE2Q + bool "WRTnode2Q board support" + select SOC_QCA953X + select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 + select ATH79_DEV_WMAC + config ATH79_MACH_R6100 bool "NETGEAR R6100 board support" select SOC_AR934X diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Makefile b/target/linux/ar71xx/files/arch/mips/ath79/Makefile index 6144e29157..ce6314d19b 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Makefile +++ b/target/linux/ar71xx/files/arch/mips/ath79/Makefile @@ -194,6 +194,7 @@ obj-$(CONFIG_ATH79_MACH_WPJ531) += mach-wpj531.o obj-$(CONFIG_ATH79_MACH_WPJ558) += mach-wpj558.o obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o +obj-$(CONFIG_ATH79_MACH_WRTNODE2Q) += mach-wrtnode2q.o obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrtnode2q.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrtnode2q.c new file mode 100644 index 0000000000..150a28b0d7 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrtnode2q.c @@ -0,0 +1,126 @@ +/* + * WRTnode2Q board support + * + * Copyright (c) 2013 The Linux Foundation. All rights reserved. + * Copyright (c) 2012 Gabor Juhos + * Copyright (c) 2015 Kelei + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define WRTNODE2Q_GPIO_LED_WLAN 12 +#define WRTNODE2Q_GPIO_LED_WPS 13 +#define WRTNODE2Q_GPIO_LED_STATUS 13 + +#define WRTNODE2Q_GPIO_LED_WAN 4 +#define WRTNODE2Q_GPIO_LED_LAN1 16 +#define WRTNODE2Q_GPIO_LED_LAN2 15 +#define WRTNODE2Q_GPIO_LED_LAN3 14 +#define WRTNODE2Q_GPIO_LED_LAN4 11 + +#define WRTNODE2Q_GPIO_BTN_WPS 17 + +#define WRTNODE2Q_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRTNODE2Q_KEYS_DEBOUNCE_INTERVAL (3 * WRTNODE2Q_KEYS_POLL_INTERVAL) + +#define WRTNODE2Q_MAC0_OFFSET 0 +#define WRTNODE2Q_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led wrtnode2q_leds_gpio[] __initdata = { + { + .name = "wrtnode2q:green:status", + .gpio = WRTNODE2Q_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "wrtnode2q:green:wlan", + .gpio = WRTNODE2Q_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wrtnode2q_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRTNODE2Q_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRTNODE2Q_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void __init wrtnode2q_gpio_led_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrtnode2q_leds_gpio), + wrtnode2q_leds_gpio); + ath79_register_gpio_keys_polled(-1, WRTNODE2Q_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrtnode2q_gpio_keys), + wrtnode2q_gpio_keys); +} + +static void __init wrtnode2q_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1f040000); + + ath79_register_m25p80(NULL); + + wrtnode2q_gpio_led_setup(); + + ath79_register_pci(); + ath79_register_usb(); + + ath79_register_wmac(art + WRTNODE2Q_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WRTNODE2Q_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + WRTNODE2Q_MAC0_OFFSET, 1); + + /* LAN ports */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_switch_data.phy4_mii_en = 1; + ath79_register_eth(1); + + /* WAN port */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(4); + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_WRTNODE2Q, "WRTNODE2Q", "WRTnode2Q board", + wrtnode2q_setup); \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index fc02147e02..441c227da6 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -255,6 +255,7 @@ enum ath79_mach_type { ATH79_MACH_WPJ558, /* Compex WPJ558 */ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */ ATH79_MACH_WRT400N, /* Linksys WRT400N */ + ATH79_MACH_WRTNODE2Q, /* WRTnode2Q */ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */ -- cgit v1.2.3 From bebdc8766a78b738039c4137e7315560cf0d52a6 Mon Sep 17 00:00:00 2001 From: Allan Nick Pedrana Date: Wed, 22 Jun 2016 14:22:05 +0200 Subject: ar71xx: add support for OpenEmbed SOM9331 This patch adds the target profile SOM9331 and configures hardware functionality for the 3x Eth Ports & corresponding LED's, the USB Host, the USART to USB bridge and the System LED. Signed-off-by: Allan Nick Pedrana --- .../ar71xx/files/arch/mips/ath79/Kconfig.openwrt | 10 ++ target/linux/ar71xx/files/arch/mips/ath79/Makefile | 1 + .../ar71xx/files/arch/mips/ath79/mach-som9331.c | 125 +++++++++++++++++++++ .../linux/ar71xx/files/arch/mips/ath79/machtypes.h | 1 + 4 files changed, 137 insertions(+) create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-som9331.c (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt index 77415eb400..52b9b5527e 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt +++ b/target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt @@ -249,6 +249,16 @@ config ATH79_MACH_ESR1750 select ATH79_DEV_USB select ATH79_DEV_WMAC +config ATH79_MACH_SOM9331 + bool "SOM9331 support" + select SOC_AR933X + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + config ATH79_MACH_WHR_HP_G300N bool "Buffalo WHR-HP-G300N board support" select SOC_AR724X diff --git a/target/linux/ar71xx/files/arch/mips/ath79/Makefile b/target/linux/ar71xx/files/arch/mips/ath79/Makefile index ce6314d19b..f8b0b2bb5a 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/Makefile +++ b/target/linux/ar71xx/files/arch/mips/ath79/Makefile @@ -135,6 +135,7 @@ obj-$(CONFIG_ATH79_MACH_RB2011) += mach-rb2011.o obj-$(CONFIG_ATH79_MACH_RBSXTLITE) += mach-rbsxtlite.o obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o obj-$(CONFIG_ATH79_MACH_SMART_300) += mach-smart-300.o +obj-$(CONFIG_ATH79_MACH_SOM9331) += mach-som9331.o obj-$(CONFIG_ATH79_MACH_TELLSTICK_ZNET_LITE) += mach-tellstick-znet-lite.o obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-som9331.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-som9331.c new file mode 100644 index 0000000000..eef5bcedc2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-som9331.c @@ -0,0 +1,125 @@ +/* + * OpenEmbed SOM9331 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * 5/27/2016 - Modified by Allan Nick Pedrana + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define SOM9331_GPIO_LED_WLAN 27 +#define SOM9331_GPIO_LED_SYSTEM 0 +#define SOM9331_GPIO_LED_2 13 +#define SOM9331_GPIO_LED_3 14 +#define SOM9331_GPIO_LED_5 16 +#define SOM9331_GPIO_LED_WAN SOM9331_GPIO_LED_2 +#define SOM9331_GPIO_LED_LAN1 SOM9331_GPIO_LED_3 +#define SOM9331_GPIO_LED_LAN2 SOM9331_GPIO_LED_5 +#define SOM9331_GPIO_BTN_RESET 11 + +#define SOM9331_KEYS_POLL_INTERVAL 20 /* msecs */ +#define SOM9331_KEYS_DEBOUNCE_INTERVAL (3 * SOM9331_KEYS_POLL_INTERVAL) + +static const char *som9331_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data som9331_flash_data = { + .part_probes = som9331_part_probes, +}; + +static struct gpio_led som9331_leds_gpio[] __initdata = { + { + .name = "som9331:red:wlan", + .gpio = SOM9331_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "som9331:orange:wan", + .gpio = SOM9331_GPIO_LED_WAN, + .active_low = 0, + }, + { + .name = "som9331:orange:lan1", + .gpio = SOM9331_GPIO_LED_LAN1, + .active_low = 0, + }, + { + .name = "som9331:orange:lan2", + .gpio = SOM9331_GPIO_LED_LAN2, + .active_low = 0, + }, + { + .name = "som9331:blue:system", + .gpio = SOM9331_GPIO_LED_SYSTEM, + .active_low = 0, + }, +}; + +static struct gpio_keys_button som9331_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = SOM9331_KEYS_DEBOUNCE_INTERVAL, + .gpio = SOM9331_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init som9331_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(&som9331_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(som9331_leds_gpio), + som9331_leds_gpio); + ath79_register_gpio_keys_polled(-1, SOM9331_KEYS_POLL_INTERVAL, + ARRAY_SIZE(som9331_gpio_keys), + som9331_gpio_keys); + + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_SOM9331, "SOM9331", "OpenEmbed SOM9331", som9331_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h index 441c227da6..f40b4a43b5 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h +++ b/target/linux/ar71xx/files/arch/mips/ath79/machtypes.h @@ -153,6 +153,7 @@ enum ath79_mach_type { ATH79_MACH_RB_SXTLITE5ND, /* Mikrotik RouterBOARD SXT Lite 5nD */ ATH79_MACH_RW2458N, /* Redwave RW2458N */ ATH79_MACH_SMART_300, /* NC-LINK SMART-300 */ + ATH79_MACH_SOM9331, /* OpenEmbed SOM9331 */ ATH79_MACH_TELLSTICK_ZNET_LITE, /* TellStick ZNet Lite */ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */ -- cgit v1.2.3 From fca52fb7f382d25307d8633d1ed171f79989f65d Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 22 Jun 2016 14:23:15 +0200 Subject: ar71xx: enable flow control for ethernet MACs with built-in switch Should fix LAN speed issues on some devices Signed-off-by: Felix Fietkau --- .../files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c index 38226cf22e..d5253609cd 100644 --- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -453,9 +453,17 @@ static void ag71xx_hw_stop(struct ag71xx *ag) static void ag71xx_hw_setup(struct ag71xx *ag) { struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct ag71xx_mdio_platform_data *mpdata; + u32 init = MAC_CFG1_INIT; + + if (pdata->mii_bus_dev && ag->pdev->id == 0) { + mpdata = pdata->mii_bus_dev->platform_data; + if (mpdata && mpdata->builtin_switch) + init |= MAC_CFG1_TFC | MAC_CFG1_RFC; + } /* setup MAC configuration registers */ - ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); + ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); -- cgit v1.2.3 From 51d20b495fc6c0cdd1efdf4d56c99169c18ec01b Mon Sep 17 00:00:00 2001 From: Arne Zachlod Date: Wed, 22 Jun 2016 14:24:06 +0200 Subject: ar71xx: mach-ubnt-xm.c convert patches to mach file Signed-off-by: Arne Zachlod --- .../ar71xx/files/arch/mips/ath79/mach-ubnt-xm.c | 700 +++++++++++++++++++++ 1 file changed, 700 insertions(+) create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-xm.c (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-xm.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-xm.c new file mode 100644 index 0000000000..622c81f107 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt-xm.c @@ -0,0 +1,700 @@ +/* + * Ubiquiti Networks XM (rev 1.0) board support + * + * Copyright (C) 2011 René Bolldorf + * + * Derived from: mach-pb44.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define UBNT_XM_GPIO_LED_L1 0 +#define UBNT_XM_GPIO_LED_L2 1 +#define UBNT_XM_GPIO_LED_L3 11 +#define UBNT_XM_GPIO_LED_L4 7 + +#define UBNT_XM_GPIO_BTN_RESET 12 + +#define UBNT_XM_KEYS_POLL_INTERVAL 20 +#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +#define UBNT_XM_EEPROM_ADDR 0x1fff1000 + +static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { + .name = "ubnt:red:link1", + .gpio = UBNT_XM_GPIO_LED_L1, + .active_low = 0, + }, { + .name = "ubnt:orange:link2", + .gpio = UBNT_XM_GPIO_LED_L2, + .active_low = 0, + }, { + .name = "ubnt:green:link3", + .gpio = UBNT_XM_GPIO_LED_L3, + .active_low = 0, + }, { + .name = "ubnt:green:link4", + .gpio = UBNT_XM_GPIO_LED_L4, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, + .gpio = UBNT_XM_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define UBNT_M_WAN_PHYMASK BIT(4) + +static void __init ubnt_xm_init(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + + ath79_register_m25p80(NULL); + ap91_pci_init(eeprom, NULL); + + ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_XM, + "UBNT-XM", + "Ubiquiti Networks XM (rev 1.0) board", + ubnt_xm_init); + +MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", + ubnt_xm_init); + +static void __init ubnt_rocket_m_setup(void) +{ + ubnt_xm_init(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", + ubnt_rocket_m_setup); + +static void __init ubnt_nano_m_setup(void) +{ + ubnt_xm_init(); + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", + ubnt_nano_m_setup); + +static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = { + { + .name = "ubnt:green:globe", + .gpio = 0, + .active_low = 1, + }, { + .name = "ubnt:green:power", + .gpio = 11, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static void __init ubnt_airrouter_setup(void) +{ + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(NULL); + ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1); + + ath79_register_eth(1); + ath79_register_eth(0); + ath79_register_usb(); + + ap91_pci_init(ee, NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio), + ubnt_airrouter_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter", + ubnt_airrouter_setup); + +static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = { + { + .name = "ubnt:orange:dome", + .gpio = 1, + .active_low = 0, + }, { + .name = "ubnt:green:dome", + .gpio = 0, + .active_low = 0, + } +}; + +static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = { + { + .name = "ubnt:orange:front", + .gpio = 1, + .active_low = 0, + }, { + .name = "ubnt:green:front", + .gpio = 0, + .active_low = 0, + } +}; + +static struct gpio_led ubnt_unifi_outdoor_plus_leds_gpio[] __initdata = { + { + .name = "ubnt:white:front", + .gpio = 1, + .active_low = 0, + }, { + .name = "ubnt:blue:front", + .gpio = 0, + .active_low = 0, + } +}; + + +static void __init ubnt_unifi_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_register_eth(0); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio), + ubnt_unifi_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi", + ubnt_unifi_setup); + + +#define UBNT_UNIFIOD_PRI_PHYMASK BIT(4) +#define UBNT_UNIFIOD_2ND_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +static void __init ubnt_unifi_outdoor_setup(void) +{ + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK | + UBNT_UNIFIOD_2ND_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio), + ubnt_unifi_outdoor_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20", + "Ubiquiti UniFiAP Outdoor", + ubnt_unifi_outdoor_setup); + + +static void __init ubnt_unifi_outdoor_plus_setup(void) +{ + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK | + UBNT_UNIFIOD_2ND_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_plus_leds_gpio), + ubnt_unifi_outdoor_plus_leds_gpio); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, "UBNT-UOP", + "Ubiquiti UniFiAP Outdoor+", + ubnt_unifi_outdoor_plus_setup); + + +static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = { + { + .name = "ubnt:white:dome", + .gpio = 12, + }, { + .name = "ubnt:blue:dome", + .gpio = 13, + } +}; + +static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, + .gpio = 17, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data uap_pro_ar8327_data = { + .pad0_cfg = &uap_pro_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info uap_pro_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &uap_pro_ar8327_data, + }, +}; + +#define UAP_PRO_MAC0_OFFSET 0x0000 +#define UAP_PRO_MAC1_OFFSET 0x0006 +#define UAP_PRO_WMAC_CALDATA_OFFSET 0x1000 +#define UAP_PRO_PCI_CALDATA_OFFSET 0x5000 + +static void __init ubnt_uap_pro_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds), + ubnt_uap_pro_gpio_leds); + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(uap_pro_gpio_keys), + uap_pro_gpio_keys); + + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); + + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(uap_pro_mdio0_info, + ARRAY_SIZE(uap_pro_mdio0_info)); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + ath79_init_mac(ath79_eth0_data.mac_addr, + eeprom + UAP_PRO_MAC0_OFFSET, 0); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro", + ubnt_uap_pro_setup); + +#define UBNT_XW_GPIO_LED_L1 11 +#define UBNT_XW_GPIO_LED_L2 16 +#define UBNT_XW_GPIO_LED_L3 13 +#define UBNT_XW_GPIO_LED_L4 14 + +static struct gpio_led ubnt_xw_leds_gpio[] __initdata = { + { + .name = "ubnt:red:link1", + .gpio = UBNT_XW_GPIO_LED_L1, + .active_low = 1, + }, { + .name = "ubnt:orange:link2", + .gpio = UBNT_XW_GPIO_LED_L2, + .active_low = 1, + }, { + .name = "ubnt:green:link3", + .gpio = UBNT_XW_GPIO_LED_L3, + .active_low = 1, + }, { + .name = "ubnt:green:link4", + .gpio = UBNT_XW_GPIO_LED_L4, + .active_low = 1, + }, +}; + +#define UBNT_ROCKET_TI_GPIO_LED_L1 16 +#define UBNT_ROCKET_TI_GPIO_LED_L2 17 +#define UBNT_ROCKET_TI_GPIO_LED_L3 18 +#define UBNT_ROCKET_TI_GPIO_LED_L4 19 +#define UBNT_ROCKET_TI_GPIO_LED_L5 20 +#define UBNT_ROCKET_TI_GPIO_LED_L6 21 +static struct gpio_led ubnt_rocket_ti_leds_gpio[] __initdata = { + { + .name = "ubnt:green:link1", + .gpio = UBNT_ROCKET_TI_GPIO_LED_L1, + .active_low = 1, + }, { + .name = "ubnt:green:link2", + .gpio = UBNT_ROCKET_TI_GPIO_LED_L2, + .active_low = 1, + }, { + .name = "ubnt:green:link3", + .gpio = UBNT_ROCKET_TI_GPIO_LED_L3, + .active_low = 1, + }, { + .name = "ubnt:green:link4", + .gpio = UBNT_ROCKET_TI_GPIO_LED_L4, + .active_low = 0, + }, { + .name = "ubnt:green:link5", + .gpio = UBNT_ROCKET_TI_GPIO_LED_L5, + .active_low = 0, + }, { + .name = "ubnt:green:link6", + .gpio = UBNT_ROCKET_TI_GPIO_LED_L6, + .active_low = 0, + }, +}; + +static void __init ubnt_xw_init(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio), + ubnt_xw_leds_gpio); + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); + + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0_SLAVE); + ath79_init_mac(ath79_eth0_data.mac_addr, + eeprom + UAP_PRO_MAC0_OFFSET, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; +} + +static void __init ubnt_nano_m_xw_setup(void) +{ + ubnt_xw_init(); + + /* GMAC0 is connected to an AR8326 switch */ + ath79_register_mdio(0, ~(BIT(0) | BIT(1) | BIT(5))); + ath79_eth0_data.phy_mask = (BIT(0) | BIT(1) | BIT(5)); + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_register_eth(0); +} + +static void __init ubnt_loco_m_xw_setup(void) +{ + ubnt_xw_init(); + + ath79_register_mdio(0, ~BIT(1)); + ath79_eth0_data.phy_mask = BIT(1); + ath79_register_eth(0); +} + +static void __init ubnt_rocket_m_xw_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio), + ubnt_xw_leds_gpio); + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + ath79_init_mac(ath79_eth0_data.mac_addr, + eeprom + UAP_PRO_MAC0_OFFSET, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_mdio(0, ~BIT(4)); + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +static struct at803x_platform_data ubnt_rocket_m_ti_at803_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; +static struct mdio_board_info ubnt_rocket_m_ti_mdio_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 4, + .platform_data = &ubnt_rocket_m_ti_at803_data, + }, +}; + +static void __init ubnt_rocket_m_ti_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rocket_ti_leds_gpio), + ubnt_rocket_ti_leds_gpio); + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + + ap91_pci_init(eeprom + 0x1000, NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + ath79_setup_ar934x_eth_rx_delay(3, 3); + ath79_init_mac(ath79_eth0_data.mac_addr, + eeprom + UAP_PRO_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, + eeprom + UAP_PRO_MAC1_OFFSET, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; + + mdiobus_register_board_info(ubnt_rocket_m_ti_mdio_info, + ARRAY_SIZE(ubnt_rocket_m_ti_mdio_info)); + ath79_register_mdio(0, 0x0); + + + ath79_eth0_data.phy_mask = BIT(4); + /* read out from vendor */ + ath79_eth0_pll_data.pll_1000 = 0x2000000; + ath79_eth0_pll_data.pll_10 = 0x1313; + ath79_register_eth(0); + + ath79_register_mdio(1, 0x0); + ath79_eth1_data.phy_mask = BIT(3); + ath79_register_eth(1); +} + + +MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M_XW, "UBNT-NM-XW", "Ubiquiti Nanostation M XW", + ubnt_nano_m_xw_setup); + +MIPS_MACHINE(ATH79_MACH_UBNT_LOCO_M_XW, "UBNT-LOCO-XW", "Ubiquiti Loco M XW", + ubnt_loco_m_xw_setup); + +MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_XW, "UBNT-RM-XW", "Ubiquiti Rocket M XW", + ubnt_rocket_m_xw_setup); + +MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_TI, "UBNT-RM-TI", "Ubiquiti Rocket M TI", + ubnt_rocket_m_ti_setup); + +static struct gpio_led ubnt_airgateway_gpio_leds[] __initdata = { + { + .name = "ubnt:blue:wlan", + .gpio = 0, + }, { + .name = "ubnt:white:status", + .gpio = 1, + }, +}; + +static struct gpio_keys_button airgateway_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 1, + } +}; + +static void __init ubnt_airgateway_setup(void) +{ + u32 t; + u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_gpio_leds), + ubnt_airgateway_gpio_leds); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(airgateway_gpio_keys), + airgateway_gpio_keys); + + ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, NULL); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_AIRGW, "UBNT-AGW", "Ubiquiti AirGateway", + ubnt_airgateway_setup); + +static struct gpio_led ubnt_airgateway_pro_gpio_leds[] __initdata = { + { + .name = "ubnt:blue:wlan", + .gpio = 13, + }, { + .name = "ubnt:white:status", + .gpio = 17, + }, +}; + + +static struct gpio_keys_button airgateway_pro_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 1, + } +}; + +static void __init ubnt_airgateway_pro_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_pro_gpio_leds), + ubnt_airgateway_pro_gpio_leds); + + ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, + ARRAY_SIZE(airgateway_pro_gpio_keys), + airgateway_pro_gpio_keys); + + ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); + ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); + + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* GMAC0 is left unused in this configuration */ + + /* GMAC1 is connected to MAC0 on the internal switch */ + /* The PoE/WAN port connects to port 5 on the internal switch */ + /* The LAN port connects to port 4 on the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + +} + +MIPS_MACHINE(ATH79_MACH_UBNT_AIRGWP, "UBNT-AGWP", "Ubiquiti AirGateway Pro", + ubnt_airgateway_pro_setup); -- cgit v1.2.3