From 32631c6efcd2835d7fcb8b077402a5cb88100b34 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Tue, 7 Jul 2015 08:05:55 +0000 Subject: ar71xx: rework patch for qca953x/956x Patch cherry-picked from the following location: https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e Changelist, - add more register defines - add EHCI support - fix GPIO pin count to 18 - fix chained irq disabled - fix GMAC0/GMAC1 initial - fix WMAC irq number to 47 - merge the changes of dev-eth.c from the patch to file. Signed-off-by: Miaoqing Pan Signed-off-by: Matthias Schiffer git-svn-id: svn://svn.openwrt.org/openwrt/trunk@46207 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'target/linux/ar71xx/files/arch/mips/ath79') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index ae3db4c3ef..ff94e2ec37 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: mdio_dev = &ath79_mdio1_device; mdio_data = &ath79_mdio1_data; break; @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) break; case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: mdio_data->builtin_switch = 1; break; @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_QCA9533: case ATH79_SOC_QCA9556: case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pll_10 = AR934X_PLL_VAL_10; pll_100 = AR934X_PLL_VAL_100; pll_1000 = AR934X_PLL_VAL_1000; @@ -627,6 +633,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; break; @@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: - case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; break; @@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: switch (pdata->phy_if_mode) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: if (id == 0) { pdata->reset_bit = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO; @@ -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id) pdata->fifo_cfg3 = 0x01f00140; break; - case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: if (id == 0) { pdata->reset_bit = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO; @@ -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: pdata->mii_bus_dev = &ath79_mdio1_device.dev; break; -- cgit v1.2.3