diff options
Diffstat (limited to 'target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2')
9 files changed, 0 insertions, 5606 deletions
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt deleted file mode 100644 index 85bfa612cd..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt +++ /dev/null @@ -1,4 +0,0 @@ -Global HAL Version: FEROCEON_HAL_3_1_7
-Unit HAL Version: 3.1.3
-Description: This component includes an implementation of the unit HAL drivers
-
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c deleted file mode 100644 index d1b8a3d378..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c +++ /dev/null @@ -1,1479 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include "ddr1_2/mvDram.h" -#include "boardEnv/mvBoardEnvLib.h" - -#undef MV_DEBUG -#ifdef MV_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, - MV_DRAM_BANK_INFO *pBankInfo); -static MV_U32 cas2ps(MV_U8 spd_byte); -/******************************************************************************* -* mvDramBankGet - Get the DRAM bank paramters. -* -* DESCRIPTION: -* This function retrieves DRAM bank parameters as described in -* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -* from it. Otherwise, if the DRAM is soldered on board, the function -* should insert its bank information into MV_DRAM_BANK_INFO struct. -* -* INPUT: -* bankNum - Board DRAM bank number. -* -* OUTPUT: -* pBankInfo - DRAM bank information struct. -* -* RETURN: -* MV_FAIL - Bank parameters could not be read. -* -*******************************************************************************/ -MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -{ - MV_DIMM_INFO dimmInfo; - - DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); - /* zero pBankInfo structure */ - memset(pBankInfo, 0, sizeof(*pBankInfo)); - - if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) - { - DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); - return MV_BAD_PARAM; - } - if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) - { - DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); - return MV_FAIL; - } - if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) - { - DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); - return MV_FAIL; - } - - /* convert Dimm info to Bank info */ - cpyDimm2BankInfo(&dimmInfo, pBankInfo); - - return MV_OK; -} - -/******************************************************************************* -* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -* -* DESCRIPTION: -* Convert a Dimm info struct into a bank info struct. -* -* INPUT: -* pDimmInfo - DIMM information structure. -* -* OUTPUT: -* pBankInfo - DRAM bank information struct. -* -* RETURN: -* None. -* -*******************************************************************************/ -static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, - MV_DRAM_BANK_INFO *pBankInfo) -{ - pBankInfo->memoryType = pDimmInfo->memoryType; - - /* DIMM dimensions */ - pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; - pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; - pBankInfo->dataWidth = pDimmInfo->dataWidth; - pBankInfo->errorCheckType = pDimmInfo->errorCheckType; - pBankInfo->sdramWidth = pDimmInfo->sdramWidth; - pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; - pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; - pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; - pBankInfo->refreshInterval = pDimmInfo->refreshInterval; - - /* DIMM timing parameters */ - pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; - pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = - pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; - pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = - pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; - - pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; - pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; - pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; - pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; - pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; - pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; - pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; - pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; - - /* Parameters calculated from the extracted DIMM information */ - pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; - pBankInfo->deviceDensity = pDimmInfo->deviceDensity; - pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / - pDimmInfo->numOfModuleBanks; - - /* DIMM attributes (MV_TRUE for yes) */ - - if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || - (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) - { - if (pDimmInfo->dimmAttributes & BIT1) - pBankInfo->registeredAddrAndControlInputs = MV_TRUE; - else - pBankInfo->registeredAddrAndControlInputs = MV_FALSE; - } - else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ - { - if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) - pBankInfo->registeredAddrAndControlInputs = MV_TRUE; - else - pBankInfo->registeredAddrAndControlInputs = MV_FALSE; - } - - return; -} - -/******************************************************************************* -* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -* -* DESCRIPTION: -* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -* -*******************************************************************************/ -MV_STATUS dimmSpdCpy(MV_VOID) -{ - MV_U32 i; - MV_U32 spdChecksum; - - MV_TWSI_SLAVE twsiSlave; - MV_U8 data[SPD_SIZE]; - - /* zero dimmInfo structure */ - memset(data, 0, SPD_SIZE); - - /* read the dimm eeprom */ - DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); - twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; - twsiSlave.slaveAddr.type = ADDR7_BIT; - twsiSlave.validOffset = MV_TRUE; - twsiSlave.offset = 0; - twsiSlave.moreThen256 = MV_FALSE; - - if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, - &twsiSlave, data, SPD_SIZE) ) - { - DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); - return MV_FAIL; - } - DB(puts("DRAM: Reading dimm info succeded.\n")); - - /* calculate SPD checksum */ - spdChecksum = 0; - - for(i = 0 ; i <= 62 ; i++) - { - spdChecksum += data[i]; - } - - if ((spdChecksum & 0xff) != data[63]) - { - DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", - (MV_U32)(spdChecksum & 0xff), data[63])); - } - else - { - DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); - } - - /* copy the SPD content 1:1 into the DIMM 1 SPD */ - twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; - twsiSlave.slaveAddr.type = ADDR7_BIT; - twsiSlave.validOffset = MV_TRUE; - twsiSlave.offset = 0; - twsiSlave.moreThen256 = MV_FALSE; - - for(i = 0 ; i < SPD_SIZE ; i++) - { - twsiSlave.offset = i; - if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, - &twsiSlave, &data[i], 1) ) - { - mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); - return MV_FAIL; - } - mvOsDelay(5); - } - - DB(puts("DRAM: Reading dimm info succeded.\n")); - return MV_OK; -} - -/******************************************************************************* -* dimmSpdGet - Get the SPD parameters. -* -* DESCRIPTION: -* Read the DIMM SPD parameters into given struct parameter. -* -* INPUT: -* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -* -* OUTPUT: -* pDimmInfo - DIMM information structure. -* -* RETURN: -* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -* -*******************************************************************************/ -MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -{ - MV_U32 i; - MV_U32 density = 1; - MV_U32 spdChecksum; - - MV_TWSI_SLAVE twsiSlave; - MV_U8 data[SPD_SIZE]; - - if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) - { - DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); - return MV_BAD_PARAM; - } - - /* zero dimmInfo structure */ - memset(data, 0, SPD_SIZE); - - /* read the dimm eeprom */ - DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); - twsiSlave.slaveAddr.address = (dimmNum == 0) ? - MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; - twsiSlave.slaveAddr.type = ADDR7_BIT; - twsiSlave.validOffset = MV_TRUE; - twsiSlave.offset = 0; - twsiSlave.moreThen256 = MV_FALSE; - - if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, - &twsiSlave, data, SPD_SIZE) ) - { - DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); - return MV_FAIL; - } - DB(puts("DRAM: Reading dimm info succeded.\n")); - - /* calculate SPD checksum */ - spdChecksum = 0; - - for(i = 0 ; i <= 62 ; i++) - { - spdChecksum += data[i]; - } - - if ((spdChecksum & 0xff) != data[63]) - { - DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", - (MV_U32)(spdChecksum & 0xff), data[63])); - } - else - { - DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); - } - - /* copy the SPD content 1:1 into the dimmInfo structure*/ - for(i = 0 ; i < SPD_SIZE ; i++) - { - pDimmInfo->spdRawData[i] = data[i]; - DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); - } - - DB(mvOsPrintf("DRAM SPD Information:\n")); - - /* Memory type (DDR / SDRAM) */ - switch (data[DIMM_MEM_TYPE]) - { - case (DIMM_MEM_TYPE_SDRAM): - pDimmInfo->memoryType = MEM_TYPE_SDRAM; - DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); - break; - case (DIMM_MEM_TYPE_DDR1): - pDimmInfo->memoryType = MEM_TYPE_DDR1; - DB(mvOsPrintf("DRAM Memeory type DDR1\n")); - break; - case (DIMM_MEM_TYPE_DDR2): - pDimmInfo->memoryType = MEM_TYPE_DDR2; - DB(mvOsPrintf("DRAM Memeory type DDR2\n")); - break; - default: - mvOsPrintf("ERROR: Undefined memory type!\n"); - return MV_ERROR; - } - - - /* Number Of Row Addresses */ - pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; - DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); - - /* Number Of Column Addresses */ - pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; - DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); - - /* Number Of Module Banks */ - pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; - DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", - pDimmInfo->numOfModuleBanks)); - - /* Number of module banks encoded differently for DDR2 */ - if (pDimmInfo->memoryType == MEM_TYPE_DDR2) - pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; - - /* Data Width */ - pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; - DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); - - /* Minimum Cycle Time At Max CasLatancy */ - pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); - - /* Error Check Type */ - pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; - DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", - pDimmInfo->errorCheckType)); - - /* Refresh Interval */ - pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; - DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", - pDimmInfo->refreshInterval)); - - /* Sdram Width */ - pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; - DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); - - /* Error Check Data Width */ - pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; - DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", - pDimmInfo->errorCheckDataWidth)); - - /* Burst Length Supported */ - /* SDRAM/DDR1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * - *********************************************************/ - /* DDR2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * - *********************************************************/ - - pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; - DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", - pDimmInfo->burstLengthSupported)); - - /* Number Of Banks On Each Device */ - pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; - DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", - pDimmInfo->numOfBanksOnEachDevice)); - - /* Suported Cas Latencies */ - - /* SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - - /* DDR 1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - *********************************************************/ - - /* DDR 2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * - *********************************************************/ - - pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; - DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", - pDimmInfo->suportedCasLatencies)); - - /* For DDR2 only, get the DIMM type information */ - if (pDimmInfo->memoryType == MEM_TYPE_DDR2) - { - pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; - DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", - pDimmInfo->dimmTypeInfo)); - } - - /* SDRAM Modules Attributes */ - pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; - DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", - pDimmInfo->dimmAttributes)); - - /* Minimum Cycle Time At Max CasLatancy Minus 1*/ - pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = - cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); - - /* Minimum Cycle Time At Max CasLatancy Minus 2*/ - pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = - cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); - - pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; - DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", - pDimmInfo->minRowPrechargeTime)); - pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; - DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", - pDimmInfo->minRowActiveToRowActive)); - pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; - DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", - pDimmInfo->minRasToCasDelay)); - pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; - DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", - pDimmInfo->minRasPulseWidth)); - - /* DIMM Bank Density */ - pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; - DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", - pDimmInfo->dimmBankDensity)); - - /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ - pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; - DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", - pDimmInfo->minWriteRecoveryTime)); - - /* Only DDR2 includes Internal Write To Read Command Delay field. */ - pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; - DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", - pDimmInfo->minWriteToReadCmdDelay)); - - /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ - pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; - DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", - pDimmInfo->minReadToPrechCmdDelay)); - - /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ - pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; - DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", - pDimmInfo->minRefreshToActiveCmd)); - - /* calculating the sdram density. Representing device density from */ - /* bit 20 to allow representation of 4GB and above. */ - /* For example, if density is 512Mbit 0x20000000, will be represent in */ - /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ - /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ - density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); - pDimmInfo->deviceDensity = density * - pDimmInfo->numOfBanksOnEachDevice * - pDimmInfo->sdramWidth; - DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); - - /* Number of devices includeing Error correction */ - pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * - pDimmInfo->numOfModuleBanks; - DB(mvOsPrintf("DRAM numberOfDevices %d\n", - pDimmInfo->numberOfDevices)); - - pDimmInfo->size = 0; - - /* Note that pDimmInfo->size is in MB units */ - if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) - { - if (pDimmInfo->dimmBankDensity & BIT0) - pDimmInfo->size += 1024; /* Equal to 1GB */ - else if (pDimmInfo->dimmBankDensity & BIT1) - pDimmInfo->size += 8; /* Equal to 8MB */ - else if (pDimmInfo->dimmBankDensity & BIT2) - pDimmInfo->size += 16; /* Equal to 16MB */ - else if (pDimmInfo->dimmBankDensity & BIT3) - pDimmInfo->size += 32; /* Equal to 32MB */ - else if (pDimmInfo->dimmBankDensity & BIT4) - pDimmInfo->size += 64; /* Equal to 64MB */ - else if (pDimmInfo->dimmBankDensity & BIT5) - pDimmInfo->size += 128; /* Equal to 128MB */ - else if (pDimmInfo->dimmBankDensity & BIT6) - pDimmInfo->size += 256; /* Equal to 256MB */ - else if (pDimmInfo->dimmBankDensity & BIT7) - pDimmInfo->size += 512; /* Equal to 512MB */ - } - else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) - { - if (pDimmInfo->dimmBankDensity & BIT0) - pDimmInfo->size += 1024; /* Equal to 1GB */ - else if (pDimmInfo->dimmBankDensity & BIT1) - pDimmInfo->size += 2048; /* Equal to 2GB */ - else if (pDimmInfo->dimmBankDensity & BIT2) - pDimmInfo->size += 16; /* Equal to 16MB */ - else if (pDimmInfo->dimmBankDensity & BIT3) - pDimmInfo->size += 32; /* Equal to 32MB */ - else if (pDimmInfo->dimmBankDensity & BIT4) - pDimmInfo->size += 64; /* Equal to 64MB */ - else if (pDimmInfo->dimmBankDensity & BIT5) - pDimmInfo->size += 128; /* Equal to 128MB */ - else if (pDimmInfo->dimmBankDensity & BIT6) - pDimmInfo->size += 256; /* Equal to 256MB */ - else if (pDimmInfo->dimmBankDensity & BIT7) - pDimmInfo->size += 512; /* Equal to 512MB */ - } - else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ - { - if (pDimmInfo->dimmBankDensity & BIT0) - pDimmInfo->size += 1024; /* Equal to 1GB */ - else if (pDimmInfo->dimmBankDensity & BIT1) - pDimmInfo->size += 2048; /* Equal to 2GB */ - else if (pDimmInfo->dimmBankDensity & BIT2) - pDimmInfo->size += 4096; /* Equal to 4GB */ - else if (pDimmInfo->dimmBankDensity & BIT3) - pDimmInfo->size += 8192; /* Equal to 8GB */ - else if (pDimmInfo->dimmBankDensity & BIT4) - pDimmInfo->size += 16384; /* Equal to 16GB */ - else if (pDimmInfo->dimmBankDensity & BIT5) - pDimmInfo->size += 128; /* Equal to 128MB */ - else if (pDimmInfo->dimmBankDensity & BIT6) - pDimmInfo->size += 256; /* Equal to 256MB */ - else if (pDimmInfo->dimmBankDensity & BIT7) - pDimmInfo->size += 512; /* Equal to 512MB */ - } - - pDimmInfo->size *= pDimmInfo->numOfModuleBanks; - - DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); - - return MV_OK; -} - -/******************************************************************************* -* dimmSpdPrint - Print the SPD parameters. -* -* DESCRIPTION: -* Print the Dimm SPD parameters. -* -* INPUT: -* pDimmInfo - DIMM information structure. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -MV_VOID dimmSpdPrint(MV_U32 dimmNum) -{ - MV_DIMM_INFO dimmInfo; - MV_U32 i, temp = 0; - MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; - MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; - MV_U32 busClkPs; - MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, - temp_buf[40], *spdRawData; - - busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ - - spdRawData = dimmInfo.spdRawData; - - if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) - { - mvOsOutput("ERROR: Could not read SPD information!\n"); - return; - } - - /* find Manufactura of Dimm Module */ - mvOsOutput("\nManufacturer's JEDEC ID Code: "); - for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) - { - mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); - } - mvOsOutput("\n"); - - /* Manufacturer's Specific Data */ - for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) - { - temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; - } - mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); - - /* Module Part Number */ - for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) - { - temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; - } - mvOsOutput("Module Part Number: %s\n", temp_buf); - - /* Module Serial Number */ - for(i = 0; i < sizeof(MV_U32); i++) - { - temp |= spdRawData[95+i] << 8*i; - } - mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, - (long)temp); - - /* find Manufac-Data of Dimm Module */ - mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", - ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), - ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); - /* find modul_revision of Dimm Module */ - mvOsOutput("Module Revision: %d.%d\n", - spdRawData[91], spdRawData[92]); - - /* find manufac_place of Dimm Module */ - mvOsOutput("manufac_place: %d\n", spdRawData[72]); - - /* go over the first 35 I2C data bytes */ - for(i = 2 ; i <= 35 ; i++) - switch(i) - { - case 2: /* Memory type (DDR1/2 / SDRAM) */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - mvOsOutput("Dram Type is: SDRAM\n"); - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - mvOsOutput("Dram Type is: SDRAM DDR1\n"); - else if (dimmInfo.memoryType == MEM_TYPE_DDR2) - mvOsOutput("Dram Type is: SDRAM DDR2\n"); - else - mvOsOutput("Dram Type unknown\n"); - break; -/*----------------------------------------------------------------------------*/ - - case 3: /* Number Of Row Addresses */ - mvOsOutput("Module Number of row addresses: %d\n", - dimmInfo.numOfRowAddr); - break; -/*----------------------------------------------------------------------------*/ - - case 4: /* Number Of Column Addresses */ - mvOsOutput("Module Number of col addresses: %d\n", - dimmInfo.numOfColAddr); - break; -/*----------------------------------------------------------------------------*/ - - case 5: /* Number Of Module Banks */ - mvOsOutput("Number of Banks on Mod.: %d\n", - dimmInfo.numOfModuleBanks); - break; -/*----------------------------------------------------------------------------*/ - - case 6: /* Data Width */ - mvOsOutput("Module Data Width: %d bit\n", - dimmInfo.dataWidth); - break; -/*----------------------------------------------------------------------------*/ - - case 8: /* Voltage Interface */ - switch(spdRawData[i]) - { - case 0x0: - mvOsOutput("Module is TTL_5V_TOLERANT\n"); - break; - case 0x1: - mvOsOutput("Module is LVTTL\n"); - break; - case 0x2: - mvOsOutput("Module is HSTL_1_5V\n"); - break; - case 0x3: - mvOsOutput("Module is SSTL_3_3V\n"); - break; - case 0x4: - mvOsOutput("Module is SSTL_2_5V\n"); - break; - case 0x5: - if (dimmInfo.memoryType != MEM_TYPE_SDRAM) - { - mvOsOutput("Module is SSTL_1_8V\n"); - break; - } - default: - mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); - break; - } - break; -/*----------------------------------------------------------------------------*/ - - case 9: /* Minimum Cycle Time At Max CasLatancy */ - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - rightOfPoint = (spdRawData[i] & 0x0f) * 10; - - /* DDR2 addition of right of point */ - if ((spdRawData[i] & 0x0f) == 0xA) - { - rightOfPoint = 25; - } - if ((spdRawData[i] & 0x0f) == 0xB) - { - rightOfPoint = 33; - } - if ((spdRawData[i] & 0x0f) == 0xC) - { - rightOfPoint = 66; - } - if ((spdRawData[i] & 0x0f) == 0xD) - { - rightOfPoint = 75; - } - mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 10: /* Clock To Data Out */ - div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - mvOsOutput("Clock To Data Out: %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 11: /* Error Check Type */ - mvOsOutput("Error Check Type (0=NONE): %d\n", - dimmInfo.errorCheckType); - break; -/*----------------------------------------------------------------------------*/ - - case 12: /* Refresh Interval */ - mvOsOutput("Refresh Rate: %x\n", - dimmInfo.refreshInterval); - break; -/*----------------------------------------------------------------------------*/ - - case 13: /* Sdram Width */ - mvOsOutput("Sdram Width: %d bits\n", - dimmInfo.sdramWidth); - break; -/*----------------------------------------------------------------------------*/ - - case 14: /* Error Check Data Width */ - mvOsOutput("Error Check Data Width: %d bits\n", - dimmInfo.errorCheckDataWidth); - break; -/*----------------------------------------------------------------------------*/ - - case 15: /* Minimum Clock Delay is unsupported */ - if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || - (dimmInfo.memoryType == MEM_TYPE_DDR1)) - { - mvOsOutput("Minimum Clk Delay back to back: %d\n", - spdRawData[i]); - } - break; -/*----------------------------------------------------------------------------*/ - - case 16: /* Burst Length Supported */ - /* SDRAM/DDR1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * - *********************************************************/ - /* DDR2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * - *********************************************************/ - mvOsOutput("Burst Length Supported: "); - if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || - (dimmInfo.memoryType == MEM_TYPE_DDR1)) - { - if (dimmInfo.burstLengthSupported & BIT0) - mvOsOutput("1, "); - if (dimmInfo.burstLengthSupported & BIT1) - mvOsOutput("2, "); - } - if (dimmInfo.burstLengthSupported & BIT2) - mvOsOutput("4, "); - if (dimmInfo.burstLengthSupported & BIT3) - mvOsOutput("8, "); - - mvOsOutput(" Bit \n"); - break; -/*----------------------------------------------------------------------------*/ - - case 17: /* Number Of Banks On Each Device */ - mvOsOutput("Number Of Banks On Each Chip: %d\n", - dimmInfo.numOfBanksOnEachDevice); - break; -/*----------------------------------------------------------------------------*/ - - case 18: /* Suported Cas Latencies */ - - /* SDRAM: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * - ********************************************************/ - - /* DDR 1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - *********************************************************/ - - /* DDR 2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * - *********************************************************/ - - mvOsOutput("Suported Cas Latencies: (CL) "); - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - for (k = 0; k <=7; k++) - { - if (dimmInfo.suportedCasLatencies & (1 << k)) - mvOsOutput("%d, ", k+1); - } - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if (dimmInfo.suportedCasLatencies & BIT0) - mvOsOutput("1, "); - if (dimmInfo.suportedCasLatencies & BIT1) - mvOsOutput("1.5, "); - if (dimmInfo.suportedCasLatencies & BIT2) - mvOsOutput("2, "); - if (dimmInfo.suportedCasLatencies & BIT3) - mvOsOutput("2.5, "); - if (dimmInfo.suportedCasLatencies & BIT4) - mvOsOutput("3, "); - if (dimmInfo.suportedCasLatencies & BIT5) - mvOsOutput("3.5, "); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR2) - { - if (dimmInfo.suportedCasLatencies & BIT2) - mvOsOutput("2, "); - if (dimmInfo.suportedCasLatencies & BIT3) - mvOsOutput("3, "); - if (dimmInfo.suportedCasLatencies & BIT4) - mvOsOutput("4, "); - if (dimmInfo.suportedCasLatencies & BIT5) - mvOsOutput("5, "); - } - else - mvOsOutput("?.?, "); - mvOsOutput("\n"); - break; -/*----------------------------------------------------------------------------*/ - - case 20: /* DDR2 DIMM type info */ - if (dimmInfo.memoryType == MEM_TYPE_DDR2) - { - if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) - mvOsOutput("Registered DIMM (RDIMM)\n"); - else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) - mvOsOutput("Unbuffered DIMM (UDIMM)\n"); - else - mvOsOutput("Unknown DIMM type.\n"); - } - - break; -/*----------------------------------------------------------------------------*/ - - case 21: /* SDRAM Modules Attributes */ - mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); - - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - if (dimmInfo.dimmAttributes & BIT0) - mvOsOutput(" Buffered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Buffered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT1) - mvOsOutput(" Registered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Registered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT2) - mvOsOutput(" On-Card PLL (clock): Yes \n"); - else - mvOsOutput(" On-Card PLL (clock): No \n"); - - if (dimmInfo.dimmAttributes & BIT3) - mvOsOutput(" Bufferd DQMB Input: Yes \n"); - else - mvOsOutput(" Bufferd DQMB Inputs: No \n"); - - if (dimmInfo.dimmAttributes & BIT4) - mvOsOutput(" Registered DQMB Inputs: Yes \n"); - else - mvOsOutput(" Registered DQMB Inputs: No \n"); - - if (dimmInfo.dimmAttributes & BIT5) - mvOsOutput(" Differential Clock Input: Yes \n"); - else - mvOsOutput(" Differential Clock Input: No \n"); - - if (dimmInfo.dimmAttributes & BIT6) - mvOsOutput(" redundant Row Addressing: Yes \n"); - else - mvOsOutput(" redundant Row Addressing: No \n"); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if (dimmInfo.dimmAttributes & BIT0) - mvOsOutput(" Buffered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Buffered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT1) - mvOsOutput(" Registered Addr/Control Input: Yes\n"); - else - mvOsOutput(" Registered Addr/Control Input: No\n"); - - if (dimmInfo.dimmAttributes & BIT2) - mvOsOutput(" On-Card PLL (clock): Yes \n"); - else - mvOsOutput(" On-Card PLL (clock): No \n"); - - if (dimmInfo.dimmAttributes & BIT3) - mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); - else - mvOsOutput(" FET Switch On-Card Enabled: No \n"); - - if (dimmInfo.dimmAttributes & BIT4) - mvOsOutput(" FET Switch External Enabled: Yes \n"); - else - mvOsOutput(" FET Switch External Enabled: No \n"); - - if (dimmInfo.dimmAttributes & BIT5) - mvOsOutput(" Differential Clock Input: Yes \n"); - else - mvOsOutput(" Differential Clock Input: No \n"); - } - else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ - { - mvOsOutput(" Number of Active Registers on the DIMM: %d\n", - (dimmInfo.dimmAttributes & 0x3) + 1); - - mvOsOutput(" Number of PLLs on the DIMM: %d\n", - ((dimmInfo.dimmAttributes) >> 2) & 0x3); - - if (dimmInfo.dimmAttributes & BIT4) - mvOsOutput(" FET Switch External Enabled: Yes \n"); - else - mvOsOutput(" FET Switch External Enabled: No \n"); - - if (dimmInfo.dimmAttributes & BIT6) - mvOsOutput(" Analysis probe installed: Yes \n"); - else - mvOsOutput(" Analysis probe installed: No \n"); - } - - break; -/*----------------------------------------------------------------------------*/ - - case 22: /* Suported AutoPreCharge */ - mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - if ( spdRawData[i] & BIT0 ) - mvOsOutput(" Early Ras Precharge: Yes \n"); - else - mvOsOutput(" Early Ras Precharge: No \n"); - - if ( spdRawData[i] & BIT1 ) - mvOsOutput(" AutoPreCharge: Yes \n"); - else - mvOsOutput(" AutoPreCharge: No \n"); - - if ( spdRawData[i] & BIT2 ) - mvOsOutput(" Precharge All: Yes \n"); - else - mvOsOutput(" Precharge All: No \n"); - - if ( spdRawData[i] & BIT3 ) - mvOsOutput(" Write 1/ReadBurst: Yes \n"); - else - mvOsOutput(" Write 1/ReadBurst: No \n"); - - if ( spdRawData[i] & BIT4 ) - mvOsOutput(" lower VCC tolerance: 5%%\n"); - else - mvOsOutput(" lower VCC tolerance: 10%%\n"); - - if ( spdRawData[i] & BIT5 ) - mvOsOutput(" upper VCC tolerance: 5%%\n"); - else - mvOsOutput(" upper VCC tolerance: 10%%\n"); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if ( spdRawData[i] & BIT0 ) - mvOsOutput(" Supports Weak Driver: Yes \n"); - else - mvOsOutput(" Supports Weak Driver: No \n"); - - if ( !(spdRawData[i] & BIT4) ) - mvOsOutput(" lower VCC tolerance: 0.2V\n"); - - if ( !(spdRawData[i] & BIT5) ) - mvOsOutput(" upper VCC tolerance: 0.2V\n"); - - if ( spdRawData[i] & BIT6 ) - mvOsOutput(" Concurrent Auto Preharge: Yes \n"); - else - mvOsOutput(" Concurrent Auto Preharge: No \n"); - - if ( spdRawData[i] & BIT7 ) - mvOsOutput(" Supports Fast AP: Yes \n"); - else - mvOsOutput(" Supports Fast AP: No \n"); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR2) - { - if ( spdRawData[i] & BIT0 ) - mvOsOutput(" Supports Weak Driver: Yes \n"); - else - mvOsOutput(" Supports Weak Driver: No \n"); - } - break; -/*----------------------------------------------------------------------------*/ - - case 23: - /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - rightOfPoint = (spdRawData[i] & 0x0f) * 10; - - /* DDR2 addition of right of point */ - if ((spdRawData[i] & 0x0f) == 0xA) - { - rightOfPoint = 25; - } - if ((spdRawData[i] & 0x0f) == 0xB) - { - rightOfPoint = 33; - } - if ((spdRawData[i] & 0x0f) == 0xC) - { - rightOfPoint = 66; - } - if ((spdRawData[i] & 0x0f) == 0xD) - { - rightOfPoint = 75; - } - - mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" - "(0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint ); - break; -/*----------------------------------------------------------------------------*/ - - case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ - div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / div; - rightOfPoint = time_tmp % div; - mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 25: - /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - leftOfPoint = (spdRawData[i] & 0xfc) >> 2; - rightOfPoint = (spdRawData[i] & 0x3) * 25; - } - else /* DDR1 or DDR2 */ - { - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - rightOfPoint = (spdRawData[i] & 0x0f) * 10; - - /* DDR2 addition of right of point */ - if ((spdRawData[i] & 0x0f) == 0xA) - { - rightOfPoint = 25; - } - if ((spdRawData[i] & 0x0f) == 0xB) - { - rightOfPoint = 33; - } - if ((spdRawData[i] & 0x0f) == 0xC) - { - rightOfPoint = 66; - } - if ((spdRawData[i] & 0x0f) == 0xD) - { - rightOfPoint = 75; - } - } - mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" - "(0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint ); - break; -/*----------------------------------------------------------------------------*/ - - case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - leftOfPoint = (spdRawData[i] & 0xfc) >> 2; - rightOfPoint = (spdRawData[i] & 0x3) * 25; - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = 0; - rightOfPoint = time_tmp; - } - mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", - leftOfPoint, rightOfPoint ); - break; -/*----------------------------------------------------------------------------*/ - - case 27: /* Minimum Row Precharge Time */ - shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; - maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0xff : 0xfc; - maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0x00 : 0x03; - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; - temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ - trp_clocks = (temp + (busClkPs-1)) / busClkPs; - mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " - "in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 28: /* Minimum Row Active to Row Active Time */ - shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; - maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0xff : 0xfc; - maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0x00 : 0x03; - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; - temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ - trrd_clocks = (temp + (busClkPs-1)) / busClkPs; - mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " - "%d.%d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 29: /* Minimum Ras-To-Cas Delay */ - shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; - maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0xff : 0xfc; - maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? - 0x00 : 0x03; - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); - rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; - temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ - trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; - mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " - "in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 30: /* Minimum Ras Pulse Width */ - tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; - mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " - "in Clk cycles %d\n", spdRawData[i], tras_clocks); - break; -/*----------------------------------------------------------------------------*/ - - case 31: /* Module Bank Density */ - mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); - - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - if (dimmInfo.dimmBankDensity & BIT0) - mvOsOutput("1GB, "); - if (dimmInfo.dimmBankDensity & BIT1) - mvOsOutput("8MB, "); - if (dimmInfo.dimmBankDensity & BIT2) - mvOsOutput("16MB, "); - if (dimmInfo.dimmBankDensity & BIT3) - mvOsOutput("32MB, "); - if (dimmInfo.dimmBankDensity & BIT4) - mvOsOutput("64MB, "); - if (dimmInfo.dimmBankDensity & BIT5) - mvOsOutput("128MB, "); - if (dimmInfo.dimmBankDensity & BIT6) - mvOsOutput("256MB, "); - if (dimmInfo.dimmBankDensity & BIT7) - mvOsOutput("512MB, "); - } - else if (dimmInfo.memoryType == MEM_TYPE_DDR1) - { - if (dimmInfo.dimmBankDensity & BIT0) - mvOsOutput("1GB, "); - if (dimmInfo.dimmBankDensity & BIT1) - mvOsOutput("2GB, "); - if (dimmInfo.dimmBankDensity & BIT2) - mvOsOutput("16MB, "); - if (dimmInfo.dimmBankDensity & BIT3) - mvOsOutput("32MB, "); - if (dimmInfo.dimmBankDensity & BIT4) - mvOsOutput("64MB, "); - if (dimmInfo.dimmBankDensity & BIT5) - mvOsOutput("128MB, "); - if (dimmInfo.dimmBankDensity & BIT6) - mvOsOutput("256MB, "); - if (dimmInfo.dimmBankDensity & BIT7) - mvOsOutput("512MB, "); - } - else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ - { - if (dimmInfo.dimmBankDensity & BIT0) - mvOsOutput("1GB, "); - if (dimmInfo.dimmBankDensity & BIT1) - mvOsOutput("2GB, "); - if (dimmInfo.dimmBankDensity & BIT2) - mvOsOutput("4GB, "); - if (dimmInfo.dimmBankDensity & BIT3) - mvOsOutput("8GB, "); - if (dimmInfo.dimmBankDensity & BIT4) - mvOsOutput("16GB, "); - if (dimmInfo.dimmBankDensity & BIT5) - mvOsOutput("128MB, "); - if (dimmInfo.dimmBankDensity & BIT6) - mvOsOutput("256MB, "); - if (dimmInfo.dimmBankDensity & BIT7) - mvOsOutput("512MB, "); - } - mvOsOutput("\n"); - break; -/*----------------------------------------------------------------------------*/ - - case 32: /* Address And Command Setup Time (measured in ns/1000) */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 33: /* Address And Command Hold Time */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 34: /* Data Input Setup Time */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 35: /* Data Input Hold Time */ - if (dimmInfo.memoryType == MEM_TYPE_SDRAM) - { - rightOfPoint = (spdRawData[i] & 0x0f); - leftOfPoint = (spdRawData[i] & 0xf0) >> 4; - if(leftOfPoint > 7) - { - leftOfPoint *= -1; - } - } - else /* DDR1 or DDR2 */ - { - time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + - ((spdRawData[i] & 0x0f)); - leftOfPoint = time_tmp / 100; - rightOfPoint = time_tmp % 100; - } - mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - - case 36: /* Relevant for DDR2 only: Write Recovery Time */ - leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); - rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; - mvOsOutput("Write Recovery Time [ns]: %d.%d\n", - leftOfPoint, rightOfPoint); - break; -/*----------------------------------------------------------------------------*/ - } - -} - - -/* - * translate ns.ns/10 coding of SPD timing values - * into ps unit values - */ -/******************************************************************************* -* cas2ps - Translate x.y ns parameter to pico-seconds values -* -* DESCRIPTION: -* This function translates x.y nano seconds to its value in pico seconds. -* For example 3.75ns will return 3750. -* -* INPUT: -* spd_byte - DIMM SPD byte. -* -* OUTPUT: -* None. -* -* RETURN: -* value in pico seconds. -* -*******************************************************************************/ -static MV_U32 cas2ps(MV_U8 spd_byte) -{ - MV_U32 ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - if( ns10 < 10 ) { - ns10 *= 10; - } - else if( ns10 == 10 ) - ns10 = 25; - else if( ns10 == 11 ) - ns10 = 33; - else if( ns10 == 12 ) - ns10 = 66; - else if( ns10 == 13 ) - ns10 = 75; - else - { - mvOsOutput("cas2ps Err. unsupported cycle time.\n"); - } - - return (ns*1000 + ns10*10); -} - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h deleted file mode 100644 index 678e22456d..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h +++ /dev/null @@ -1,191 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCmvDram -#define __INCmvDram - -#include "ddr1_2/mvDramIf.h" -#include "twsi/mvTwsi.h" - -#define MAX_DIMM_NUM 2 -#define SPD_SIZE 128 - -/* Dimm spd offsets */ -#define DIMM_MEM_TYPE 2 -#define DIMM_ROW_NUM 3 -#define DIMM_COL_NUM 4 -#define DIMM_MODULE_BANK_NUM 5 -#define DIMM_DATA_WIDTH 6 -#define DIMM_VOLT_IF 8 -#define DIMM_MIN_CC_AT_MAX_CAS 9 -#define DIMM_ERR_CHECK_TYPE 11 -#define DIMM_REFRESH_INTERVAL 12 -#define DIMM_SDRAM_WIDTH 13 -#define DIMM_ERR_CHECK_DATA_WIDTH 14 -#define DIMM_MIN_CLK_DEL 15 -#define DIMM_BURST_LEN_SUP 16 -#define DIMM_DEV_BANK_NUM 17 -#define DIMM_SUP_CAL 18 -#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -#define DIMM_BUF_ADDR_CONT_IN 21 -#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -#define DIMM_MIN_RAS_PULSE_WIDTH 30 -#define DIMM_BANK_DENSITY 31 -#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 - -/* Dimm Memory Type values */ -#define DIMM_MEM_TYPE_SDRAM 0x4 -#define DIMM_MEM_TYPE_DDR1 0x7 -#define DIMM_MEM_TYPE_DDR2 0x8 - -#define DIMM_MODULE_MANU_OFFS 64 -#define DIMM_MODULE_MANU_SIZE 8 -#define DIMM_MODULE_VEN_OFFS 73 -#define DIMM_MODULE_VEN_SIZE 25 -#define DIMM_MODULE_ID_OFFS 99 -#define DIMM_MODULE_ID_SIZE 18 - -/* enumeration for voltage levels. */ -typedef enum _mvDimmVoltageIf -{ - TTL_5V_TOLERANT, - LVTTL, - HSTL_1_5V, - SSTL_3_3V, - SSTL_2_5V, - VOLTAGE_UNKNOWN, -} MV_DIMM_VOLTAGE_IF; - - -/* enumaration for SDRAM CAS Latencies. */ -typedef enum _mvDimmSdramCas -{ - SD_CL_1 =1, - SD_CL_2, - SD_CL_3, - SD_CL_4, - SD_CL_5, - SD_CL_6, - SD_CL_7, - SD_FAULT -}MV_DIMM_SDRAM_CAS; - - -/* DIMM information structure */ -typedef struct _mvDimmInfo -{ - MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ - - MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ - - /* DIMM dimensions */ - MV_U32 numOfRowAddr; - MV_U32 numOfColAddr; - MV_U32 numOfModuleBanks; - MV_U32 dataWidth; - MV_U32 errorCheckType; /* ECC , PARITY..*/ - MV_U32 sdramWidth; /* 4,8,16 or 32 */ - MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ - MV_U32 burstLengthSupported; - MV_U32 numOfBanksOnEachDevice; - MV_U32 suportedCasLatencies; - MV_U32 refreshInterval; - MV_U32 dimmBankDensity; - MV_U32 dimmTypeInfo; /* DDR2 only */ - MV_U32 dimmAttributes; - - /* DIMM timing parameters */ - MV_U32 minCycleTimeAtMaxCasLatPs; - MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; - MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; - MV_U32 minRowPrechargeTime; - MV_U32 minRowActiveToRowActive; - MV_U32 minRasToCasDelay; - MV_U32 minRasPulseWidth; - MV_U32 minWriteRecoveryTime; /* DDR2 only */ - MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ - MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ - MV_U32 minRefreshToActiveCmd; /* DDR2 only */ - - /* Parameters calculated from the extracted DIMM information */ - MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ - MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ - MV_U32 numberOfDevices; - -} MV_DIMM_INFO; - - -MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -MV_VOID dimmSpdPrint(MV_U32 dimmNum); -MV_STATUS dimmSpdCpy(MV_VOID); - -#endif /* __INCmvDram */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c deleted file mode 100644 index 12fb26ad0e..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c +++ /dev/null @@ -1,1599 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -/* includes */ -#include "ddr1_2/mvDramIf.h" -#include "ctrlEnv/sys/mvCpuIf.h" - - - -#ifdef MV_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -/* DRAM bank presence encoding */ -#define BANK_PRESENT_CS0 0x1 -#define BANK_PRESENT_CS0_CS1 0x3 -#define BANK_PRESENT_CS0_CS2 0x5 -#define BANK_PRESENT_CS0_CS1_CS2 0x7 -#define BANK_PRESENT_CS0_CS2_CS3 0xd -#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf - -/* locals */ -static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -#if defined(MV_INC_BOARD_DDIM) -static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -static MV_U32 sdramModeRegCalc(MV_U32 minCas); -static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, - MV_U32 forcedCl); -static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, - MV_U32 minCas, MV_U32 busClk); -static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, - MV_U32 busClk); - -/******************************************************************************* -* mvDramIfDetect - Prepare DRAM interface configuration values. -* -* DESCRIPTION: -* This function implements the full DRAM detection and timing -* configuration for best system performance. -* Since this routine runs from a ROM device (Boot Flash), its stack -* resides on RAM, that might be the system DRAM. Changing DRAM -* configuration values while keeping vital data in DRAM is risky. That -* is why the function does not preform the configuration setting but -* prepare those in predefined 32bit registers (in this case IDMA -* registers are used) for other routine to perform the settings. -* The function will call for board DRAM SPD information for each DRAM -* chip select. The function will then analyze those SPD parameters of -* all DRAM banks in order to decide on DRAM configuration compatible -* for all DRAM banks. -* The function will set the CPU DRAM address decode registers. -* Note: This routine prepares values that will overide configuration of -* mvDramBasicAsmInit(). -* -* INPUT: -* forcedCl - Forced CAL Latency. If equal to zero, do not force. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ -MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -{ - MV_U32 retVal = MV_OK; /* return value */ - MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; - MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; - MV_U8 minCas; - MV_DRAM_DEC_WIN dramDecWin; - - dramDecWin.addrWin.baseHigh = 0; - - busClk = mvBoardSysClkGet(); - - if (0 == busClk) - { - mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); - return MV_ERROR; - } - - /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -#if defined(MV_INCLUDE_SDRAM_CS1) - for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) - mvCpuIfTargetWinEnable(i, MV_FALSE); -#endif - - /* we will use bank 0 as the representative of the all the DRAM banks, */ - /* since bank 0 must exist. */ - for(i = 0; i < MV_DRAM_MAX_CS; i++) - { - /* if Bank exist */ - if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) - { - /* check it isn't SDRAM */ - if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) - { - mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); - return MV_ERROR; - } - /* All banks must support registry in order to activate it */ - if(bankInfo[i].registeredAddrAndControlInputs != - bankInfo[0].registeredAddrAndControlInputs) - { - mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); - return MV_ERROR; - } - - /* Init the CPU window decode */ - /* Note that the size in Bank info is in MB units */ - /* Note that the Dimm width might be different then the device DRAM width */ - temp = MV_REG_READ(SDRAM_CONFIG_REG); - - deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; - dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); - size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); - - /* We can not change DRAM window settings while excecuting */ - /* code from it. That is why we skip the DRAM CS[0], saving */ - /* it to the ROM configuration routine */ - if(i == SDRAM_CS0) - { - MV_U32 sizeToReg; - - /* Translate the given window size to register format */ - sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); - - /* Size parameter validity check. */ - if (-1 == sizeToReg) - { - mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" - ,i); - return MV_BAD_PARAM; - } - - /* Size is located at upper 16 bits */ - sizeToReg <<= SCSR_SIZE_OFFS; - - /* enable it */ - sizeToReg |= SCSR_WIN_EN; - - MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); - } - else - { - dramDecWin.addrWin.baseLow = base; - dramDecWin.addrWin.size = size; - dramDecWin.enable = MV_TRUE; - - if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) - { - mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", - SDRAM_CS0 + i); - return MV_ERROR; - } - } - - base += size; - - /* update the suportedCasLatencies mask */ - bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; - - } - else - { - if( i == 0 ) /* bank 0 doesn't exist */ - { - mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); - return MV_ERROR; - } - else - { - DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); - bankInfo[i].size = 0; /* Mark this bank as non exist */ - } - } - } - - /* calculate minimum CAS */ - minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); - if (0 == minCas) - { - mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", - (busClk / 1000000)); - - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - minCas = DDR2_CL_4; /* Continue with this CAS */ - mvOsPrintf("Set default CAS latency 4\n"); - } - else - { - minCas = DDR1_CL_3; /* Continue with this CAS */ - mvOsPrintf("Set default CAS latency 3\n"); - } - } - - /* calc SDRAM_CONFIG_REG and save it to temp register */ - temp = sdramConfigRegCalc(&bankInfo[0], busClk); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG1, temp); - - /* calc SDRAM_MODE_REG and save it to temp register */ - temp = sdramModeRegCalc(minCas); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG2, temp); - - /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ - temp = sdramExtModeRegCalc(&bankInfo[0]); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG10, temp); - - /* calc D_UNIT_CONTROL_LOW and save it to temp register */ - temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG3, temp); - - /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ - temp = sdramAddrCtrlRegCalc(&bankInfo[0]); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG4, temp); - - /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ - temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG5, temp); - - /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ - temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); - if(-1 == temp) - { - mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); - return MV_ERROR; - } - MV_REG_WRITE(DRAM_BUF_REG6, temp); - - /* Config DDR2 On Die Termination (ODT) registers */ - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - sdramDDr2OdtConfig(bankInfo); - } - - /* Note that DDR SDRAM Address/Control and Data pad calibration */ - /* settings is done in mvSdramIfConfig.s */ - - return retVal; -} - -/******************************************************************************* -* minCasCalc - Calculate the Minimum CAS latency which can be used. -* -* DESCRIPTION: -* Calculate the minimum CAS latency that can be used, base on the DRAM -* parameters and the SDRAM bus Clock freq. -* -* INPUT: -* busClk - the DRAM bus Clock. -* pBankInfo - bank info parameters. -* -* OUTPUT: -* None -* -* RETURN: -* The minimum CAS Latency. The function returns 0 if max CAS latency -* supported by banks is incompatible with system bus clock frequancy. -* -*******************************************************************************/ -static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, - MV_U32 forcedCl) -{ - MV_U32 count = 1, j; - MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ - MV_U32 startBit, stopBit; - - /* DDR 1: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * - *********************************************************/ - - /* DDR 2: - *******-******-******-******-******-******-******-******* - * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * - *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * - *********************************************************/ - - - /* If we are asked to use the forced CAL */ - if (forcedCl) - { - mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), - (forcedCl % 10)); - - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - if (forcedCl == 30) - pBankInfo->suportedCasLatencies = 0x08; - else if (forcedCl == 40) - pBankInfo->suportedCasLatencies = 0x10; - else - { - mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", - (forcedCl / 10), (forcedCl % 10)); - pBankInfo->suportedCasLatencies = 0x10; - } - } - else - { - if (forcedCl == 15) - pBankInfo->suportedCasLatencies = 0x02; - else if (forcedCl == 20) - pBankInfo->suportedCasLatencies = 0x04; - else if (forcedCl == 25) - pBankInfo->suportedCasLatencies = 0x08; - else if (forcedCl == 30) - pBankInfo->suportedCasLatencies = 0x10; - else if (forcedCl == 40) - pBankInfo->suportedCasLatencies = 0x40; - else - { - mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", - (forcedCl / 10), (forcedCl % 10)); - pBankInfo->suportedCasLatencies = 0x10; - } - } - - return pBankInfo->suportedCasLatencies; - } - - /* go over the supported cas mask from Max Cas down and check if the */ - /* SysClk stands in its time requirments. */ - - - DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", - pBankInfo->suportedCasLatencies,busClkPs )); - for(j = 7; j > 0; j--) - { - if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) - { - /* Reset the bits for CL incompatible for the sysClk */ - switch (count) - { - case 1: - if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - case 2: - if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - case 3: - if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - count++; - break; - default: - pBankInfo->suportedCasLatencies &= ~(BIT0 << j); - break; - } - } - } - - DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", - pBankInfo->suportedCasLatencies )); - - /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ - /* SDRAM DDR2 controller supports CL 3 to 5 */ - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ - stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ - } - else - { - startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ - stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ - } - - for(j = startBit; j <= stopBit ; j++) - { - if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) - { - DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); - return (BIT0 << j); - } - } - - return 0; -} - -/******************************************************************************* -* sdramConfigRegCalc - Calculate sdram config register -* -* DESCRIPTION: Calculate sdram config register optimized value based -* on the bank info parameters. -* -* INPUT: -* pBankInfo - sdram bank parameters -* -* OUTPUT: -* None -* -* RETURN: -* sdram config reg value. -* -*******************************************************************************/ -static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -{ - MV_U32 sdramConfig = 0; - MV_U32 refreshPeriod; - - busClk /= 1000000; /* we work with busClk in MHz */ - - sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); - - /* figure out the memory refresh internal */ - switch (pBankInfo->refreshInterval & 0xf) - { - case 0x0: /* refresh period is 15.625 usec */ - refreshPeriod = 15625; - break; - case 0x1: /* refresh period is 3.9 usec */ - refreshPeriod = 3900; - break; - case 0x2: /* refresh period is 7.8 usec */ - refreshPeriod = 7800; - break; - case 0x3: /* refresh period is 31.3 usec */ - refreshPeriod = 31300; - break; - case 0x4: /* refresh period is 62.5 usec */ - refreshPeriod = 62500; - break; - case 0x5: /* refresh period is 125 usec */ - refreshPeriod = 125000; - break; - default: /* refresh period undefined */ - mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); - return -1; - } - - /* Now the refreshPeriod is in register format value */ - refreshPeriod = (busClk * refreshPeriod) / 1000; - - DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", - refreshPeriod)); - - /* make sure the refresh value is only 14 bits */ - if(refreshPeriod > SDRAM_REFRESH_MAX) - { - refreshPeriod = SDRAM_REFRESH_MAX; - DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", - refreshPeriod)); - } - - /* Clear the refresh field */ - sdramConfig &= ~SDRAM_REFRESH_MASK; - - /* Set new value to refresh field */ - sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); - - /* registered DRAM ? */ - if ( pBankInfo->registeredAddrAndControlInputs ) - { - /* it's registered DRAM, so set the reg. DRAM bit */ - sdramConfig |= SDRAM_REGISTERED; - mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); - } - - /* set DDR SDRAM devices configuration */ - sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ - - switch (pBankInfo->sdramWidth) - { - case 8: /* memory is x8 */ - sdramConfig |= SDRAM_DCFG_X8_DEV; - DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); - break; - case 16: - sdramConfig |= SDRAM_DCFG_X16_DEV; - DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); - break; - default: /* memory width unsupported */ - mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); - return -1; - } - - /* Set static default settings */ - sdramConfig |= SDRAM_CONFIG_DV; - - DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", - sdramConfig)); - - return sdramConfig; -} - -/******************************************************************************* -* sdramModeRegCalc - Calculate sdram mode register -* -* DESCRIPTION: Calculate sdram mode register optimized value based -* on the bank info parameters and the minCas. -* -* INPUT: -* minCas - minimum CAS supported. -* -* OUTPUT: -* None -* -* RETURN: -* sdram mode reg value. -* -*******************************************************************************/ -static MV_U32 sdramModeRegCalc(MV_U32 minCas) -{ - MV_U32 sdramMode; - - sdramMode = MV_REG_READ(SDRAM_MODE_REG); - - /* Clear CAS Latency field */ - sdramMode &= ~SDRAM_CL_MASK; - - mvOsPrintf("DRAM CAS Latency "); - - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - switch (minCas) - { - case DDR2_CL_3: - sdramMode |= SDRAM_DDR2_CL_3; - mvOsPrintf("3.\n"); - break; - case DDR2_CL_4: - sdramMode |= SDRAM_DDR2_CL_4; - mvOsPrintf("4.\n"); - break; - case DDR2_CL_5: - sdramMode |= SDRAM_DDR2_CL_5; - mvOsPrintf("5.\n"); - break; - default: - mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); - return -1; - } - sdramMode |= DDR2_MODE_REG_DV; - } - else /* DDR1 */ - { - switch (minCas) - { - case DDR1_CL_1_5: - sdramMode |= SDRAM_DDR1_CL_1_5; - mvOsPrintf("1.5\n"); - break; - case DDR1_CL_2: - sdramMode |= SDRAM_DDR1_CL_2; - mvOsPrintf("2\n"); - break; - case DDR1_CL_2_5: - sdramMode |= SDRAM_DDR1_CL_2_5; - mvOsPrintf("2.5\n"); - break; - case DDR1_CL_3: - sdramMode |= SDRAM_DDR1_CL_3; - mvOsPrintf("3\n"); - break; - case DDR1_CL_4: - sdramMode |= SDRAM_DDR1_CL_4; - mvOsPrintf("4\n"); - break; - default: - mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); - return -1; - } - sdramMode |= DDR1_MODE_REG_DV; - } - - DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); - - return sdramMode; -} - -/******************************************************************************* -* sdramExtModeRegCalc - Calculate sdram Extended mode register -* -* DESCRIPTION: -* Return sdram Extended mode register value based -* on the bank info parameters and bank presence. -* -* INPUT: -* pBankInfo - sdram bank parameters -* -* OUTPUT: -* None -* -* RETURN: -* sdram Extended mode reg value. -* -*******************************************************************************/ -static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -{ - MV_U32 populateBanks = 0; - int bankNum; - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - /* Represent the populate banks in binary form */ - for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - if (0 != pBankInfo[bankNum].size) - { - populateBanks |= (1 << bankNum); - } - } - - switch(populateBanks) - { - case(BANK_PRESENT_CS0): - return DDR_SDRAM_EXT_MODE_CS0_DV; - - case(BANK_PRESENT_CS0_CS1): - return DDR_SDRAM_EXT_MODE_CS0_DV; - - case(BANK_PRESENT_CS0_CS2): - return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; - - case(BANK_PRESENT_CS0_CS1_CS2): - return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; - - case(BANK_PRESENT_CS0_CS2_CS3): - return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; - - case(BANK_PRESENT_CS0_CS2_CS3_CS4): - return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; - - default: - mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); - return -1; - } - } - return 0; -} - -/******************************************************************************* -* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -* -* DESCRIPTION: Calculate sdram dunit control low register optimized value based -* on the bank info parameters and the minCas. -* -* INPUT: -* pBankInfo - sdram bank parameters -* minCas - minimum CAS supported. -* -* OUTPUT: -* None -* -* RETURN: -* sdram dunit control low reg value. -* -*******************************************************************************/ -static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -{ - MV_U32 dunitCtrlLow; - - dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); - - /* Clear StBurstDel field */ - dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; - -#ifdef MV_88W8660 - /* Clear address/control output timing field */ - dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -#endif /* MV_88W8660 */ - - DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); - - /* For proper sample of read data set the Dunit Control register's */ - /* stBurstDel bits [27:24] */ - /********-********-********-********-********-********* - * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * - *********-********-********-********-********-********* -Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * - *********-********-********-********-********-********* -Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * - *********-********-********-********-********-*********/ - - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - switch (minCas) - { - case DDR2_CL_3: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; - break; - case DDR2_CL_4: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; - break; - default: - mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", - minCas); - return -1; - } - } - else /* DDR1 */ - { - switch (minCas) - { - case DDR1_CL_1_5: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; - break; - case DDR1_CL_2: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; - break; - case DDR1_CL_2_5: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; - break; - case DDR1_CL_3: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; - break; - case DDR1_CL_4: - /* registerd DDR SDRAM? */ - if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) - dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; - else - dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; - break; - default: - mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", - minCas); - return -1; - } - - } - DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); - - return dunitCtrlLow; -} - -/******************************************************************************* -* sdramAddrCtrlRegCalc - Calculate sdram address control register -* -* DESCRIPTION: Calculate sdram address control register optimized value based -* on the bank info parameters and the minCas. -* -* INPUT: -* pBankInfo - sdram bank parameters -* -* OUTPUT: -* None -* -* RETURN: -* sdram address control reg value. -* -*******************************************************************************/ -static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -{ - MV_U32 addrCtrl = 0; - - /* Set Address Control register static configuration bits */ - addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); - - /* Set address control default value */ - addrCtrl |= SDRAM_ADDR_CTRL_DV; - - /* Clear DSize field */ - addrCtrl &= ~SDRAM_DSIZE_MASK; - - /* Note that density is in MB units */ - switch (pBankInfo->deviceDensity) - { - case 128: /* 128 Mbit */ - DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); - addrCtrl |= SDRAM_DSIZE_128Mb; - break; - case 256: /* 256 Mbit */ - DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); - addrCtrl |= SDRAM_DSIZE_256Mb; - break; - case 512: /* 512 Mbit */ - DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); - addrCtrl |= SDRAM_DSIZE_512Mb; - break; - default: - mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", - pBankInfo->deviceDensity); - return -1; - } - - /* SDRAM address control */ - DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); - - return addrCtrl; -} - -/******************************************************************************* -* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -* -* DESCRIPTION: -* This function calculates sdram timing control low register -* optimized value based on the bank info parameters and the minCas. -* -* INPUT: -* pBankInfo - sdram bank parameters -* busClk - Bus clock -* -* OUTPUT: -* None -* -* RETURN: -* sdram timinf control low reg value. -* -*******************************************************************************/ -static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, - MV_U32 minCas, MV_U32 busClk) -{ - MV_U32 tRp = 0; - MV_U32 tRrd = 0; - MV_U32 tRcd = 0; - MV_U32 tRas = 0; - MV_U32 tWr = 0; - MV_U32 tWtr = 0; - MV_U32 tRtp = 0; - - MV_U32 bankNum; - - busClk = busClk / 1000000; /* In MHz */ - - /* Scan all DRAM banks to find maximum timing values */ - for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); - tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); - tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); - tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); - } - - /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ - /* by shifting the data two bits right. */ - tRp = tRp >> 2; /* For example 0x50 -> 20ns */ - tRrd = tRrd >> 2; - tRcd = tRcd >> 2; - - /* Extract clock cycles from time parameter. We need to round up */ - tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); - /* Micron work around for 133MHz */ - if (busClk == 133) - tRp += 1; - DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); - tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); - /* JEDEC min reqeirments tRrd = 2 */ - if (tRrd < 2) - tRrd = 2; - DB(mvOsPrintf("tRrd = %d ", tRrd)); - tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); - DB(mvOsPrintf("tRcd = %d ", tRcd)); - tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); - DB(mvOsPrintf("tRas = %d ", tRas)); - - /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - /* Scan all DRAM banks to find maximum timing values */ - for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); - tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); - tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); - } - - /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ - /* part by shifting the data two bits right. */ - tWr = tWr >> 2; /* For example 0x50 -> 20ns */ - tWtr = tWtr >> 2; - tRtp = tRtp >> 2; - - /* Extract clock cycles from time parameter. We need to round up */ - tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); - DB(mvOsPrintf("tWr = %d ", tWr)); - tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); - /* JEDEC min reqeirments tWtr = 2 */ - if (tWtr < 2) - tWtr = 2; - DB(mvOsPrintf("tWtr = %d ", tWtr)); - tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); - /* JEDEC min reqeirments tRtp = 2 */ - if (tRtp < 2) - tRtp = 2; - DB(mvOsPrintf("tRtp = %d ", tRtp)); - } - else - { - tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); - - if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) - { - tWtr = 2; - } - else - { - tWtr = 1; - } - - tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ - } - - DB(mvOsPrintf("tWtr = %d\n", tWtr)); - - /* Note: value of 0 in register means one cycle, 1 means two and so on */ - return (((tRp - 1) << SDRAM_TRP_OFFS) | - ((tRrd - 1) << SDRAM_TRRD_OFFS) | - ((tRcd - 1) << SDRAM_TRCD_OFFS) | - ((tRas - 1) << SDRAM_TRAS_OFFS) | - ((tWr - 1) << SDRAM_TWR_OFFS) | - ((tWtr - 1) << SDRAM_TWTR_OFFS) | - ((tRtp - 1) << SDRAM_TRTP_OFFS)); -} - -/******************************************************************************* -* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -* -* DESCRIPTION: -* This function calculates sdram timing control high register -* optimized value based on the bank info parameters and the bus clock. -* -* INPUT: -* pBankInfo - sdram bank parameters -* busClk - Bus clock -* -* OUTPUT: -* None -* -* RETURN: -* sdram timinf control high reg value. -* -*******************************************************************************/ -static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, - MV_U32 busClk) -{ - MV_U32 tRfc; - MV_U32 timeNs = 0; - int bankNum; - MV_U32 sdramTw2wCyc = 0; - - busClk = busClk / 1000000; /* In MHz */ - - /* tRfc is different for DDR1 and DDR2. */ - if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) - { - MV_U32 bankNum; - - /* Scan all DRAM banks to find maximum timing values */ - for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); - } - else - { - if (pBankInfo[0].deviceDensity == _1G) - { - timeNs = SDRAM_TRFC_1G; - } - else - { - if (200 == busClk) - { - timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; - } - else - { - timeNs = SDRAM_TRFC_64_512M; - } - } - } - - tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); - - DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); - - - /* Represent the populate banks in binary form */ - for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - if (0 != pBankInfo[bankNum].size) - sdramTw2wCyc++; - } - - /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ - if (sdramTw2wCyc > 1) - sdramTw2wCyc = 1; - else - sdramTw2wCyc = 0; - - /* Note: value of 0 in register means one cycle, 1 means two and so on */ - return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | - ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | - ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | - (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | - (sdramTw2wCyc << SDRAM_TW2W_OFFS)); - -} - -/******************************************************************************* -* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -* -* DESCRIPTION: -* This function config DDR2 On Die Termination (ODT) registers. -* ODT configuration is done according to DIMM presence: -* -* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -* -* INPUT: -* pBankInfo - bank info parameters. -* -* OUTPUT: -* None -* -* RETURN: -* None -*******************************************************************************/ -static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -{ - MV_U32 populateBanks = 0; - MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; - int bankNum; - - /* Represent the populate banks in binary form */ - for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - if (0 != pBankInfo[bankNum].size) - { - populateBanks |= (1 << bankNum); - } - } - - switch(populateBanks) - { - case(BANK_PRESENT_CS0): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; - break; - case(BANK_PRESENT_CS0_CS1): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; - break; - case(BANK_PRESENT_CS0_CS2): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; - break; - case(BANK_PRESENT_CS0_CS1_CS2): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; - break; - case(BANK_PRESENT_CS0_CS2_CS3): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; - break; - case(BANK_PRESENT_CS0_CS2_CS3_CS4): - odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; - odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; - dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; - break; - default: - mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); - return; - } - MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); - MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); - MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); - return; -} -#endif /* defined(MV_INC_BOARD_DDIM) */ - -/******************************************************************************* -* mvDramIfWinSet - Set DRAM interface address decode window -* -* DESCRIPTION: -* This function sets DRAM interface address decode window. -* -* INPUT: -* target - System target. Use only SDRAM targets. -* pAddrDecWin - SDRAM address window structure. -* -* OUTPUT: -* None -* -* RETURN: -* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -* otherwise. -*******************************************************************************/ -MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -{ - MV_U32 baseReg=0,sizeReg=0; - MV_U32 baseToReg=0 , sizeToReg=0; - - /* Check parameters */ - if (!MV_TARGET_IS_DRAM(target)) - { - mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); - return MV_BAD_PARAM; - } - - /* Check if the requested window overlaps with current enabled windows */ - if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) - { - mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); - return MV_BAD_PARAM; - } - - /* check if address is aligned to the size */ - if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) - { - mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ - "\nAddress 0x%08x is unaligned to size 0x%x.\n", - target, - pAddrDecWin->addrWin.baseLow, - pAddrDecWin->addrWin.size); - return MV_ERROR; - } - - /* read base register*/ - baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); - - /* read size register */ - sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); - - /* BaseLow[31:16] => base register [31:16] */ - baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; - - /* Write to address decode Base Address Register */ - baseReg &= ~SCBAR_BASE_MASK; - baseReg |= baseToReg; - - /* Translate the given window size to register format */ - sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); - - /* Size parameter validity check. */ - if (-1 == sizeToReg) - { - mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); - return MV_BAD_PARAM; - } - - /* set size */ - sizeReg &= ~SCSR_SIZE_MASK; - /* Size is located at upper 16 bits */ - sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); - - /* enable/Disable */ - if (MV_TRUE == pAddrDecWin->enable) - { - sizeReg |= SCSR_WIN_EN; - } - else - { - sizeReg &= ~SCSR_WIN_EN; - } - - /* 3) Write to address decode Base Address Register */ - MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); - - /* Write to address decode Size Register */ - MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); - - return MV_OK; -} -/******************************************************************************* -* mvDramIfWinGet - Get DRAM interface address decode window -* -* DESCRIPTION: -* This function gets DRAM interface address decode window. -* -* INPUT: -* target - System target. Use only SDRAM targets. -* -* OUTPUT: -* pAddrDecWin - SDRAM address window structure. -* -* RETURN: -* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -* otherwise. -*******************************************************************************/ -MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -{ - MV_U32 baseReg,sizeReg; - MV_U32 sizeRegVal; - - /* Check parameters */ - if (!MV_TARGET_IS_DRAM(target)) - { - mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); - return MV_ERROR; - } - - /* Read base and size registers */ - sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); - baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); - - sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; - - pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, - SCSR_SIZE_ALIGNMENT); - - /* Check if ctrlRegToSize returned OK */ - if (-1 == pAddrDecWin->addrWin.size) - { - mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); - return MV_ERROR; - } - - /* Extract base address */ - /* Base register [31:16] ==> baseLow[31:16] */ - pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; - - pAddrDecWin->addrWin.baseHigh = 0; - - - if (sizeReg & SCSR_WIN_EN) - { - pAddrDecWin->enable = MV_TRUE; - } - else - { - pAddrDecWin->enable = MV_FALSE; - } - - return MV_OK; -} -/******************************************************************************* -* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -* -* DESCRIPTION: -* This function enable/Disable SDRAM address decode window. -* -* INPUT: -* target - System target. Use only SDRAM targets. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -* -*******************************************************************************/ -MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -{ - MV_DRAM_DEC_WIN addrDecWin; - - /* Check parameters */ - if (!MV_TARGET_IS_DRAM(target)) - { - mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); - return MV_ERROR; - } - - if (enable == MV_TRUE) - { /* First check for overlap with other enabled windows */ - if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) - { - mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", - target); - return MV_ERROR; - } - /* Check for overlapping */ - if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) - { - /* No Overlap. Enable address decode winNum window */ - MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); - } - else - { /* Overlap detected */ - mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", - target); - return MV_ERROR; - } - } - else - { /* Disable address decode winNum window */ - MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); - } - - return MV_OK; -} - -/******************************************************************************* -* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -* -* DESCRIPTION: -* This function scan each SDRAM address decode window to test if it -* overlapps the given address windoow -* -* INPUT: -* target - SDRAM target where the function skips checking. -* pAddrDecWin - The tested address window for overlapping with -* SDRAM windows. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_TRUE if the given address window overlaps any enabled address -* decode map, MV_FALSE otherwise. -* -*******************************************************************************/ -static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -{ - MV_TARGET targetNum; - MV_DRAM_DEC_WIN addrDecWin; - - for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) - { - /* don't check our winNum or illegal targets */ - if (targetNum == target) - { - continue; - } - - /* Get window parameters */ - if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) - { - mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); - return MV_ERROR; - } - - /* Do not check disabled windows */ - if (MV_FALSE == addrDecWin.enable) - { - continue; - } - - if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) - { - mvOsPrintf( - "sdramIfWinOverlap: Required target %d overlap winNum %d\n", - target, targetNum); - return MV_TRUE; - } - } - - return MV_FALSE; -} - -/******************************************************************************* -* mvDramIfBankSizeGet - Get DRAM interface bank size. -* -* DESCRIPTION: -* This function returns the size of a given DRAM bank. -* -* INPUT: -* bankNum - Bank number. -* -* OUTPUT: -* None. -* -* RETURN: -* DRAM bank size. If bank is disabled the function return '0'. In case -* or paramter is invalid, the function returns -1. -* -*******************************************************************************/ -MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -{ - MV_DRAM_DEC_WIN addrDecWin; - - /* Check parameters */ - if (!MV_TARGET_IS_DRAM(bankNum)) - { - mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); - return -1; - } - /* Get window parameters */ - if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) - { - mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); - return -1; - } - - if (MV_TRUE == addrDecWin.enable) - { - return addrDecWin.addrWin.size; - } - else - { - return 0; - } -} - - -/******************************************************************************* -* mvDramIfSizeGet - Get DRAM interface total size. -* -* DESCRIPTION: -* This function get the DRAM total size. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* DRAM total size. In case or paramter is invalid, the function -* returns -1. -* -*******************************************************************************/ -MV_32 mvDramIfSizeGet(MV_VOID) -{ - MV_U32 totalSize = 0, bankSize = 0, bankNum; - - for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) - { - bankSize = mvDramIfBankSizeGet(bankNum); - - if (-1 == bankSize) - { - mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); - return -1; - } - else - { - totalSize += bankSize; - } - } - - DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); - - return totalSize; -} - -/******************************************************************************* -* mvDramIfBankBaseGet - Get DRAM interface bank base. -* -* DESCRIPTION: -* This function returns the 32 bit base address of a given DRAM bank. -* -* INPUT: -* bankNum - Bank number. -* -* OUTPUT: -* None. -* -* RETURN: -* DRAM bank size. If bank is disabled or paramter is invalid, the -* function returns -1. -* -*******************************************************************************/ -MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -{ - MV_DRAM_DEC_WIN addrDecWin; - - /* Check parameters */ - if (!MV_TARGET_IS_DRAM(bankNum)) - { - mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); - return -1; - } - /* Get window parameters */ - if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) - { - mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); - return -1; - } - - if (MV_TRUE == addrDecWin.enable) - { - return addrDecWin.addrWin.baseLow; - } - else - { - return -1; - } -} - - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h deleted file mode 100644 index 8bfa3e8838..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h +++ /dev/null @@ -1,179 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -#ifndef __INCmvDramIfh -#define __INCmvDramIfh - -/* includes */ -#include "ddr1_2/mvDramIfRegs.h" -#include "ddr1_2/mvDramIfConfig.h" -#include "ctrlEnv/mvCtrlEnvLib.h" - -/* defines */ -/* DRAM Timing parameters */ -#define SDRAM_TWR 15 /* ns tWr */ -#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ - -/* typedefs */ - -/* enumeration for memory types */ -typedef enum _mvMemoryType -{ - MEM_TYPE_SDRAM, - MEM_TYPE_DDR1, - MEM_TYPE_DDR2 -}MV_MEMORY_TYPE; - -/* enumeration for DDR1 supported CAS Latencies */ -typedef enum _mvDimmDdr1Cas -{ - DDR1_CL_1_5 = 0x02, - DDR1_CL_2 = 0x04, - DDR1_CL_2_5 = 0x08, - DDR1_CL_3 = 0x10, - DDR1_CL_4 = 0x40, - DDR1_CL_FAULT -} MV_DIMM_DDR1_CAS; - -/* enumeration for DDR2 supported CAS Latencies */ -typedef enum _mvDimmDdr2Cas -{ - DDR2_CL_3 = 0x08, - DDR2_CL_4 = 0x10, - DDR2_CL_5 = 0x20, - DDR2_CL_FAULT -} MV_DIMM_DDR2_CAS; - - -typedef struct _mvDramBankInfo -{ - MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ - - /* DIMM dimensions */ - MV_U32 numOfRowAddr; - MV_U32 numOfColAddr; - MV_U32 dataWidth; - MV_U32 errorCheckType; /* ECC , PARITY..*/ - MV_U32 sdramWidth; /* 4,8,16 or 32 */ - MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ - MV_U32 burstLengthSupported; - MV_U32 numOfBanksOnEachDevice; - MV_U32 suportedCasLatencies; - MV_U32 refreshInterval; - - /* DIMM timing parameters */ - MV_U32 minCycleTimeAtMaxCasLatPs; - MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; - MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; - MV_U32 minRowPrechargeTime; - MV_U32 minRowActiveToRowActive; - MV_U32 minRasToCasDelay; - MV_U32 minRasPulseWidth; - MV_U32 minWriteRecoveryTime; /* DDR2 only */ - MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ - MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ - MV_U32 minRefreshToActiveCmd; /* DDR2 only */ - - /* Parameters calculated from the extracted DIMM information */ - MV_U32 size; - MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ - MV_U32 numberOfDevices; - - /* DIMM attributes (MV_TRUE for yes) */ - MV_BOOL registeredAddrAndControlInputs; - -}MV_DRAM_BANK_INFO; - -/* This structure describes CPU interface address decode window */ -typedef struct _mvDramIfDecWin -{ - MV_ADDR_WIN addrWin; /* An address window*/ - MV_BOOL enable; /* Address decode window is enabled/disabled */ -}MV_DRAM_DEC_WIN; - -#include "ddr1_2/mvDram.h" - -/* mvDramIf.h API list */ -MV_VOID mvDramIfBasicAsmInit(MV_VOID); -MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -MV_VOID _mvDramIfConfig(MV_VOID); - -MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -MV_32 mvDramIfSizeGet(MV_VOID); - -#if 0 -MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -#endif - -#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S deleted file mode 100644 index f2a9365c0b..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S +++ /dev/null @@ -1,988 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#define MV_ASMLANGUAGE -#include "mvSysHwConfig.h" -#include "mvOsAsm.h" -#include "mvBoardEnvSpec.h" -#include "mvCpuIfRegs.h" -#include "mvDramIfConfig.h" -#include "mvDramIfRegs.h" -#include "pex/mvPexRegs.h" -#include "pci/mvPciRegs.h" -#include "mvCtrlEnvSpec.h" -#include "mvCtrlEnvAsm.h" -#include "cpu/mvCpuArm.h" -#include "mvCommon.h" - -/* defines */ - -#if !defined(MV_INC_BOARD_DDIM) -.globl dramBoot1 -dramBoot1: - .word 0 - -/****************************************************************************** -* -* -* -* -*******************************************************************************/ -#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) - -/* PEX_PCI and PRPMC boards 256 MB*/ -#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 -#define STATIC_SDRAM_CONFIG 0x03248400 -#define STATIC_SDRAM_MODE 0x62 -#define STATIC_DUNIT_CTRL_LOW 0x4041000 -#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F -#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -#define STATIC_SDRAM_EXT_MODE 0x0 - -#elif defined(DB_FPGA) - -/* FPGA DC boards 256 MB*/ -#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 -#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ -#define STATIC_SDRAM_MODE 0x22 -#define STATIC_DUNIT_CTRL_LOW 0x03041000 -#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D -#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -#define STATIC_SDRAM_EXT_MODE 0x1 - -#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) - -/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ -#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 -#define STATIC_SDRAM_CONFIG 0x03158400 -#define STATIC_SDRAM_MODE 0x452 -#define STATIC_DUNIT_CTRL_LOW 0x06041000 -#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 -#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 -#define STATIC_SDRAM_EXT_MODE 0x00000440 - - -#elif defined(RD_88F6183AP) - -/* DDR2 1 devices 512Mbit by 16 bit */ -#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 -#define STATIC_SDRAM_CONFIG 0x1f154400 -#define STATIC_SDRAM_MODE 0x432 -#define STATIC_DUNIT_CTRL_LOW 0x04041000 -#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 -#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 -#define STATIC_SDRAM_EXT_MODE 0x00000440 - -/* 6082L MARVELL DIMM */ -#elif defined(DB_88F6082LBP) -#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 -#define STATIC_SDRAM_CONFIG 0x7f158400 -#define STATIC_SDRAM_MODE 0x432 -#define STATIC_DUNIT_CTRL_LOW 0x04041040 -#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 -#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 -#define STATIC_SDRAM_EXT_MODE 0x00000440 - -#elif defined(RD_88W8660_AP82S) - -/* Shark RD */ - -#if defined(MV_DRAM_32M) -#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x00000010 -#elif defined(MV_DRAM_16M) - -#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x00000000 - -#else -#error "NO DDR size selected" -#endif - -#define STATIC_SDRAM_CONFIG 0x03144400 -#define STATIC_SDRAM_MODE 0x62 -#define STATIC_DUNIT_CTRL_LOW 0x4041000 - -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b -#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -#define STATIC_SDRAM_EXT_MODE 0x0 - -#elif defined(RD_88W8660) - -/* Shark RD */ -#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 -#define STATIC_SDRAM_CONFIG 0x03144400 -#define STATIC_SDRAM_MODE 0x62 -#define STATIC_DUNIT_CTRL_LOW 0x4041000 -#define STATIC_SDRAM_ADDR_CTRL 0x00000010 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b -#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -#define STATIC_SDRAM_EXT_MODE 0x0 - -#else /* NAS */ - - -#if defined(RD_88F5182) - -#if defined(MV_88F5082) -#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x20 -#else -#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x20 -#endif - -#elif defined(RD_88F5182_3) - -#if defined(MV_88F5082) -#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x20 -#else -#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x20 -#endif - -#else - -#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 -#define STATIC_SDRAM_ADDR_CTRL 0x0 - -#endif - -#if defined(MV_88F5082) -#define STATIC_SDRAM_CONFIG 0x3144400 -#else -#define STATIC_SDRAM_CONFIG 0x3148400 -#endif -#define STATIC_SDRAM_MODE 0x62 -#define STATIC_DUNIT_CTRL_LOW 0x4041000 -#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -#define STATIC_SDRAM_TIME_CTRL_HI 0x40c -#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -#define STATIC_SDRAM_EXT_MODE 0x0 - -#endif - - .globl _mvDramIfStaticInit -_mvDramIfStaticInit: - - mov r11, LR /* Save link register */ - mov r10, r2 - - /* If we boot from NAND jump to DRAM sddress */ - - mov r5, #1 - ldr r6, =dramBoot1 - str r5, [r6] /* We started executing from DRAM */ - - ldr r6, dramBoot1 - cmp r6, #0 - bne 1f - - - /* set all dram windows to 0 */ - mov r6, #0 - MV_REG_WRITE_ASM(r6, r5, 0x1504) - MV_REG_WRITE_ASM(r6, r5, 0x150c) - MV_REG_WRITE_ASM(r6, r5, 0x1514) - MV_REG_WRITE_ASM(r6, r5, 0x151c) - - /* set all dram configuration in temp registers */ - ldr r6, = STATIC_SDRAM0_BANK0_SIZE - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) - ldr r6, = STATIC_SDRAM_CONFIG - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) - ldr r6, = STATIC_SDRAM_MODE - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) - ldr r6, = STATIC_DUNIT_CTRL_LOW - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) - ldr r6, = STATIC_SDRAM_ADDR_CTRL - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) - ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) - ldr r6, = STATIC_SDRAM_TIME_CTRL_HI - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) - ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) - ldr r6, = STATIC_SDRAM_ODT_CTRL_HI - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) - ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) - ldr r6, = STATIC_SDRAM_EXT_MODE - MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) - - mov sp, #0 - bl _mvDramIfConfig -1: - mov r2, r10 - mov PC, r11 /* r11 is saved link register */ - -#else /* #if !defined(MV_INC_BOARD_DDIM) */ - -.globl dramBoot1 -dramBoot1: - .word 0 - -/******************************************************************************* -* mvDramIfBasicInit - Basic initialization of DRAM interface -* -* DESCRIPTION: -* The function will initialize the DRAM for basic usage. The function -* will use the TWSI assembly API to extract DIMM parameters according -* to which DRAM interface will be initialized. -* The function referes to the following DRAM parameters: -* 1) DIMM is registered or not. -* 2) DIMM width detection. -* 3) DIMM density. -* -* INPUT: -* r3 - required size for initial DRAM. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -* Note: -* r4 holds I2C EEPROM address -* r5 holds SDRAM register base address -* r7 holds returned values -* r8 holds SDRAM various configuration registers value. -* r11 holds return function address. -*******************************************************************************/ -/* Setting the offsets of the I2C registers */ -#define NUM_OF_ROWS_OFFSET 3 -#define NUM_OF_COLS_OFFSET 4 -#define NUM_OF_RANKS 5 -#define SDRAM_WIDTH_OFFSET 13 -#define NUM_OF_BANKS_OFFSET 17 -#define SUPPORTED_CL_OFFSET 18 -#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ -#define SDRAM_MODULES_ATTR_OFFSET 21 - -#define DRAM_DEV_DENSITY_128M 0x080 -#define DRAM_DEV_DENSITY_256M 0x100 -#define DRAM_DEV_DENSITY_512M 0x200 - .globl _mvDramIfBasicInit - .extern _i2cInit - -_mvDramIfBasicInit: - - mov r11, LR /* Save link register */ - - mov r5, #1 - ldr r8, =dramBoot1 - str r5, [r8] /* We started executing from DRAM */ - - /* If we boot from NAND jump to DRAM sddress */ - ldr r8, dramBoot1 - cmp r8, #0 - movne pc, r11 - - - - bl _i2cInit /* Initialize TWSI master */ - - /* Get default SDRAM Config values */ - MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) - bic r8, r8, #SDRAM_DCFG_MASK - - - /* Read device ID */ - MV_CTRL_MODEL_GET_ASM(r4, r5); - - /* Return if OrionN */ - ldr r5, =MV_5180_DEV_ID - cmp r4, r5 - beq cat_through_end - - /* Return if Orion1 */ - ldr r5, =MV_5181_DEV_ID - cmp r4, r5 - beq cat_through_end - - /* Return if Nas */ - ldr r5, =MV_5182_DEV_ID - cmp r4, r5 - beq cat_through_end - - /* Return if Shark */ - ldr r5, =MV_8660_DEV_ID - cmp r4, r5 - beq cat_through_end - - /* goto calcConfigReg if bigger than Orion2*/ - ldr r5, =MV_5281_DEV_ID - cmp r4, r5 - bne cat_through - -cat_through: - /* set cat through - for better performance - in orion2 b0 and higher*/ - orr r8, r8, #SDRAM_CATTHR_EN - -cat_through_end: - - - /* Get registered/non registered info from DIMM */ - bl _is_Registered - beq nonRegistered - -setRegistered: - orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ - -nonRegistered: - /* Get SDRAM width */ - bl _get_width - - orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ - cmp r7, #16 - beq setConfigReg - - orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ - cmp r7, #8 - beq setConfigReg - - /* This is an error. return */ - b exit_ddrAutoConfig - -setConfigReg: - mov r8, r6 - ldr r6, =SDRAM_CONFIG_DV - orr r8, r8, r6 /* Add default settings */ - mov r6, r8 /* Do not swap r8 content */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) - - /* Set maximum CL supported by DIMM */ - bl _get_CAL - - /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ - clz r6, r7 - rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ - - /* Check the DDR version */ - tst r8, #SDRAM_DTYPE_DDR2 - bne casDdr2 - -casDdr1: - ldr r7, =3 /* stBurstDel field value */ - ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ - cmp r6, #1 /* If CL = 1.5 break */ - beq setModeReg - - ldr r7, =3 /* stBurstDel field value */ - ldr r8, =0x22 /* Assuming MAX CL = 2 */ - cmp r6, #2 /* If CL = 2 break */ - beq setModeReg - - ldr r7, =4 /* stBurstDel field value */ - ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ - cmp r6, #3 /* If CL = 2.5 break */ - beq setModeReg - - ldr r7, =4 /* stBurstDel field value */ - ldr r8, =0x32 /* Assuming MAX CL = 3 */ - cmp r6, #4 /* If CL = 3 break */ - beq setModeReg - - ldr r7, =5 /* stBurstDel field value */ - ldr r8, =0x42 /* Assuming MAX CL = 4 */ - cmp r6, #6 /* If CL = 4 break */ - b setModeReg - - b exit_ddrAutoConfig /* This is an error !! */ - -casDdr2: - ldr r7, =4 /* stBurstDel field value */ - ldr r8, =0x32 /* Assuming MAX CL = 3 */ - cmp r6, #3 /* If CL = 3 break */ - beq casDdr2Cont - - ldr r7, =5 /* stBurstDel field value */ - ldr r8, =0x42 /* Assuming MAX CL = 4 */ - cmp r6, #4 /* If CL = 4 break */ - beq casDdr2Cont - - /* CL 5 currently unsupported. We use CL 4 instead */ - ldr r7, =5 /* stBurstDel field value */ - ldr r8, =0x42 /* Assuming MAX CL = 5 */ - cmp r6, #5 /* If CL = 5 break */ - beq casDdr2Cont - - b exit_ddrAutoConfig /* This is an error !! */ -casDdr2Cont: - /* Write recovery for auto-precharge relevant only in DDR2 */ - orr r8, r8, #0x400 /* Default value */ - -setModeReg: - /* The CPU must not attempt to change the SDRAM Mode register setting */ - /* prior to DRAM controller completion of the DRAM initialization */ - /* sequence. To guarantee this restriction, it is recommended that */ - /* the CPU sets the SDRAM Operation register to NOP command, performs */ - /* read polling until the register is back in Normal operation value, */ - /* and then sets SDRAM Mode register to it's new value. */ - - /* write 'nop' to SDRAM operation */ - mov r6, #0x5 /* 'NOP' command */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll1: - ldr r6, [r5] - cmp r6, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll1 - - /* Now its safe to write new value to SDRAM Mode register */ - MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) - - /* Make the Dunit write the DRAM its new mode */ - mov r6, #0x3 /* Mode Register Set command */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll2: - ldr r6, [r5] - cmp r6, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll2 - - /* Set Dunit control register according to max CL detected */ - /* If we use registered DIMM, add 1 to stBurstDel */ - MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) - tst r6, #SDRAM_REGISTERED - beq setDunitReg - add r7, r7, #1 - -setDunitReg: - ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV - orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS - MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) - - - /* DIMM density configuration*/ - /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ -Density: - bl _getDensity - mov r8, r7 - mov r8, r8, LSR #20 /* Move density 20 bits to the right */ - /* For example 0x10000000 --> 0x1000 */ - - mov r6, #0x00 - cmp r8, #DRAM_DEV_DENSITY_128M - beq densCont - - mov r6, #0x10 - cmp r8, #DRAM_DEV_DENSITY_256M - beq densCont - - mov r6, #0x20 - cmp r8, #DRAM_DEV_DENSITY_512M - beq densCont - - /* This is an error. return */ - b exit_ddrAutoConfig - -densCont: - MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) - - /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ - MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) - tst r8, #SDRAM_DTYPE_DDR2 - beq _extModeODTEnd - - - /* Set DDR Extended Mode register for working with CS[0] */ - /* write 'nop' to SDRAM operation */ - mov r6, #0x5 /* 'NOP' command */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll3: - ldr r6, [r5] - cmp r6, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll3 - - /* Now its safe to write new value to SDRAM Extended Mode register */ - ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV - MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) - - /* Make the Dunit write the DRAM its new extended mode */ - mov r6, #0x4 /* Extended Mode Register Set command */ - MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll4: - ldr r6, [r5] - cmp r6, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll4 - - /* ODT configuration is done for single bank CS[0] only */ - /* Config DDR2 On Die Termination (ODT) registers */ - ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV - MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) - - ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV - MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) - - ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV - MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) - - - /* we will check what device we are running and perform - Initialization according to device value */ - -_extModeODTEnd: - - /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ - /* Does Not Work for Address/Control and Data Pads. */ - /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ - - /* Read device ID */ - MV_CTRL_MODEL_GET_ASM(r6, r5); - /* Read device revision */ - MV_CTRL_REV_GET_ASM(r8, r5); - - /* Continue if OrionN */ - ldr r5, =MV_5180_DEV_ID - cmp r6, r5 - bne 1f - b glMem2End -1: - - /* Continue if Orion1 and device revision B1 */ - ldr r5, =MV_5181_DEV_ID - cmp r6, r5 - bne 1f - - cmp r8, #MV_5181_B1_REV - bge glMem2End - b glMem2Start -1: - - /* Orion NAS */ - ldr r5, =MV_5182_DEV_ID - cmp r6, r5 - beq glMem2Start - - /* Orion Shark */ - ldr r5, =MV_8660_DEV_ID - cmp r6, r5 - beq glMem2Start - - b glMem2End - -glMem2Start: - - /* DDR SDRAM Address/Control Pads Calibration */ - MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - /* Set Bit [31] to make the register writable */ - orr r8, r6, #SDRAM_WR_EN - - MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ - bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ - bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */ - bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */ - - /* Get the final N locked value of driving strength [22:17] */ - mov r5, r6 - mov r5, r5, LSL #9 - mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */ - orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */ - - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r6, r6, r5 - - MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - - /* DDR SDRAM Data Pads Calibration */ - MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) - - /* Set Bit [31] to make the register writable */ - orr r8, r6, #SDRAM_WR_EN - - MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) - - bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ - bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ - bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */ - bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */ - - /* Get the final N locked value of driving strength [22:17] */ - mov r5, r6 - mov r5, r5, LSL #9 - mov r5, r5, LSR #26 - orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */ - - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r6, r6, r5 - - MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) - -glMem2End: - /* Implement Guideline (GL# MEM-3) Drive Strength Value */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - - /* Get SDRAM Config value */ - MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) - - /* Get DIMM type */ - tst r8, #SDRAM_DTYPE_DDR2 - beq ddr1StrengthVal - -ddr2StrengthVal: - ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV - ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV - b setDrvStrength -ddr1StrengthVal: - ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV - ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV - -setDrvStrength: - /* DDR SDRAM Address/Control Pads Calibration */ - MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ - - MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) - HTOLL(r6,r5) - - bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ - bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK - orr r6, r4, r6 /* Set default value for DDR */ - - MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - - /* DDR SDRAM Data Pads Calibration */ - MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) - - orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ - - MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) - HTOLL(r6,r5) - - bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ - bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK - orr r6, r8, r6 /* Set default value for DDR */ - - MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) - - - /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - /* Get the "sample on reset" register for the DDR frequancy */ - -#if defined(MV_RUN_FROM_FLASH) - /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ - ldr r7, = _cpuARMDDRCLK - ldr r4, =_start - ldr r4, [r4] - sub r7, r7, r4 - ldr r4, = Lrom_start_of_data - ldr r4, [r4] - add r7, r4, r7 -#else - /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ - ldr r7, = _cpuARMDDRCLK - ldr r4, =_start - sub r7, r7, r4 - add r7, r7, #CFG_MONITOR_BASE -#endif - /* Get the "sample on reset" register for the DDR frequancy */ - MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) - ldr r5, =MSAR_ARMDDRCLCK_MASK - and r5, r4, r5 -#if 0 /* YOTAM TO BE FIX */ - mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS -#endif - - /* Read device ID */ - MV_CTRL_MODEL_GET_ASM(r6, r8); - - /* Continue if TC90 */ - ldr r8, =MV_1281_DEV_ID - cmp r6, r6 - beq armClkMsb - - /* Continue if Orion2 */ - ldr r8, =MV_5281_DEV_ID - cmp r6, r8 -#if 0 /* YOTAM TO BE FIX */ - bne 1f -#endif - -armClkMsb: -#if 0 /* YOTAM TO BE FIX */ - tst r4, #MSAR_ARMDDRCLCK_H_MASK - beq 1f - orr r5, r5, #BIT4 -1: - ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE - mul r5, r4, r5 - add r7, r7, r5 - add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF - ldr r5, [r7] -#endif - - /* Get SDRAM Config value */ - MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) - - /* Get DIMM type */ - tst r8, #SDRAM_DTYPE_DDR2 - beq ddr1FtdllVal - -ddr2FtdllVal: - ldr r4, =FTDLL_DDR2_250MHZ - ldr r7, =_250MHz - cmp r5, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_200MHZ - ldr r7, =_200MHz - cmp r5, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_166MHZ - ldr r7, =_166MHz - cmp r5, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_133MHZ - b setFtdllReg - -ddr1FtdllVal: - ldr r4, =FTDLL_DDR1_200MHZ - ldr r7, =_200MHz - cmp r5, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR1_166MHZ - ldr r7, =_166MHz - cmp r5, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR1_133MHZ - ldr r7, =_133MHz - cmp r5, r7 - beq setFtdllReg - ldr r4, =0 - -setFtdllReg: - -#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) - MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) - orr r8, r8, r4 - MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) - bic r8, r8, #1 - MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ - - -setTimingReg: - /* Set default Timing parameters */ - MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) - tst r8, #SDRAM_DTYPE_DDR2 - bne ddr2TimeParam - -ddr1TimeParam: - ldr r6, =DDR1_TIMING_LOW_DV - MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) - ldr r6, =DDR1_TIMING_HIGH_DV - MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) - b timeParamDone - -ddr2TimeParam: - ldr r6, =DDR2_TIMING_LOW_DV - MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) - ldr r6, =DDR2_TIMING_HIGH_DV - MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) - -timeParamDone: - /* Open CS[0] window to requested size and enable it. Disable other */ - /* windows */ - ldr r6, =SCBAR_BASE_MASK - sub r3, r3, #1 - and r3, r3, r6 - orr r3, r3, #1 /* Enable bank */ - MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) - ldr r6, =0 - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) - MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) - -exit_ddrAutoConfig: - mov PC, r11 /* r11 is saved link register */ - - -/***************************************************************************************/ -/* r4 holds I2C EEPROM address - * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value - * r8 holds SDRAM various configuration registers value. - * r13 holds Link register - */ -/**************************/ -_getDensity: - mov r13, LR /* Save link register */ - - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ - bl _i2cRead - mov r8, r7 /* r8 save number of rows */ - - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ - bl _i2cRead - add r8, r8, r7 /* r8 = number of rows + number of col */ - - mov r7, #0x1 - mov r8, r7, LSL r8 /* r8 = (1 << r8) */ - - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ - bl _i2cRead - mul r8, r7, r8 - - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ - bl _i2cRead - mul r7, r8, r7 - - mov PC, r13 - -/**************************/ -_get_width: - mov r13, LR /* Save link register */ - - /* Get SDRAM width (SPD offset 13) */ - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #SDRAM_WIDTH_OFFSET - bl _i2cRead /* result in r7 */ - - mov PC, r13 - -/**************************/ -_get_CAL: - mov r13, LR /* Save link register */ - - /* Set maximum CL supported by DIMM */ - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ - bl _i2cRead - - mov PC, r13 - -/**************************/ -/* R8 - sdram configuration register. - * Return value in flag if no-registered then Z-flag is set - */ -_is_Registered: - mov r13, LR /* Save link register */ - - /* Get registered/non registered info from DIMM */ - tst r8, #SDRAM_DTYPE_DDR2 - bne regDdr2 - -regDdr1: - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #SDRAM_MODULES_ATTR_OFFSET - bl _i2cRead /* result in r7 */ - tst r7, #0x2 - b exit -regDdr2: - mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ - mov r7, #DIMM_TYPE_INFO_OFFSET - bl _i2cRead /* result in r7 */ - tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ - /* or Mini-RDIMM (0x10) */ -exit: - mov PC, r13 - - -#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S deleted file mode 100644 index e34ebbf298..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S +++ /dev/null @@ -1,668 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -/******************************************************************************* -* mvDramIfBasicAsm.s -* -* DESCRIPTION: -* Memory full detection and best timing configuration is done in -* C code. C runtime environment requires a stack. This module API -* initialize DRAM interface chip select 0 for basic functionality for -* the use of stack. -* The module API assumes DRAM information is stored in I2C EEPROM reside -* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM -* internal data structure is assumed to be orgenzied in common DRAM -* vendor SPD structure. -* NOTE: DFCDL values are assumed to be already initialized prior to -* this module API activity. -* -* -* DEPENDENCIES: -* None. -* -*******************************************************************************/ - -/* includes */ -#define MV_ASMLANGUAGE -#include "mvOsAsm.h" -#include "mvSysHwConfig.h" -#include "mvDramIfRegs.h" -#include "mvDramIfConfig.h" -#include "mvCpuIfRegs.h" -#include "pex/mvPexRegs.h" -#include "pci/mvPciRegs.h" -#include "mvCtrlEnvSpec.h" -#include "mvCtrlEnvAsm.h" -#include "cpu/mvCpuArm.h" -#include "mvCommon.h" - -/* defines */ - -/* locals */ -.data -.globl _mvDramIfConfig - -.text - -/******************************************************************************* -* _mvDramIfConfig - Basic DRAM interface initialization. -* -* DESCRIPTION: -* The function will initialize the following DRAM parameters using the -* values prepared by mvDramIfDetect routine. Values are located -* in predefined registers. -* -* INPUT: -* None. -* -* OUTPUT: -* None. -* -* RETURN: -* None. -* -*******************************************************************************/ - -_mvDramIfConfig: - - /* Save register on stack */ - cmp sp, #0 - beq no_stack_s -save_on_stack: - stmdb sp!, {r1, r2, r3, r4, r7, r11} -no_stack_s: - - /* 1) Write to SDRAM coniguration register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) - str r4, [r1] - - /* 2) Write Dunit control low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) - str r4, [r1] - - /* 3) Write SDRAM address control register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) - str r4, [r1] - - /* 4) Write SDRAM bank 0 size register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) - str r4, [r1] - - /* 5) Write SDRAM open pages control register */ - ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) - ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV - str r4, [r1] - - /* 6) Write SDRAM timing Low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) - str r4, [r1] - - /* 7) Write SDRAM timing High register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) - str r4, [r1] - - /* 8) Write SDRAM mode register */ - /* The CPU must not attempt to change the SDRAM Mode register setting */ - /* prior to DRAM controller completion of the DRAM initialization */ - /* sequence. To guarantee this restriction, it is recommended that */ - /* the CPU sets the SDRAM Operation register to NOP command, performs */ - /* read polling until the register is back in Normal operation value, */ - /* and then sets SDRAM Mode register to it’s new value. */ - - /* 8.1 write 'nop' to SDRAM operation */ - mov r4, #0x5 /* 'NOP' command */ - MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) - - /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll1: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll1 - - /* 8.3 Now its safe to write new value to SDRAM Mode register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) - str r4, [r1] - - /* 8.4 Make the Dunit write the DRAM its new mode */ - mov r4, #0x3 /* Mode Register Set command */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) - - /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll2: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll2 - -#ifndef DB_FPGA - /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ - MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) - tst r4, #SDRAM_DTYPE_DDR2 - beq _extModeODTEnd -#endif /* DB_FPGA */ - - /* 9) Write SDRAM Extended mode register This operation should be */ - /* done for each memory bank */ - /* write 'nop' to SDRAM operation */ - mov r4, #0x5 /* 'NOP' command */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll3: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll3 - - /* Now its safe to write new value to SDRAM Extended Mode register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) - str r4, [r1] - - /* Go over each of the Banks */ - ldr r3, =0 /* r3 = DRAM bank Num */ - -extModeLoop: - /* Set the SDRAM Operation Control to each of the DRAM banks */ - mov r2, r3 /* Do not swap the bank counter value */ - MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) - - /* Make the Dunit write the DRAM its new mode */ - mov r4, #0x4 /* Extended Mode Register Set command */ - MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) - - /* poll SDRAM operation. Make sure its back to normal operation */ -_sdramOpPoll4: - ldr r4, [r1] - cmp r4, #0 /* '0' = Normal SDRAM Mode */ - bne _sdramOpPoll4 -#ifndef DB_FPGA - add r3, r3, #1 - cmp r3, #4 /* 4 = Number of banks */ - bne extModeLoop - -extModeEnd: - /* Config DDR2 On Die Termination (ODT) registers */ - /* Write SDRAM DDR2 ODT control low register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) - str r4, [r1] - - /* Write SDRAM DDR2 ODT control high register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) - str r4, [r1] - - /* Write SDRAM DDR2 Dunit ODT control register */ - ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) - ldr r4, [r1] - ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) - str r4, [r1] - -#endif /* DB_FPGA */ -_extModeODTEnd: -#ifndef DB_FPGA - /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ - /* Does Not Work for Address/Control and Data Pads. */ - /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ - - /* Read device ID */ - MV_CTRL_MODEL_GET_ASM(r3, r1); - /* Read device revision */ - MV_CTRL_REV_GET_ASM(r2, r1); - - /* Continue if OrionN */ - ldr r1, =MV_5180_DEV_ID - cmp r3, r1 - bne 1f - b glMem2End -1: - /* Continue if Orion1 and device revision B1 */ - ldr r1, =MV_5181_DEV_ID - cmp r3, r1 - bne 1f - - cmp r2, #MV_5181_B1_REV - bge glMem2End - b glMem2Start -1: - - /* Orion NAS */ - ldr r1, =MV_5182_DEV_ID - cmp r3, r1 - beq glMem2Start - - /* Orion NAS */ - ldr r1, =MV_5082_DEV_ID - cmp r3, r1 - beq glMem2Start - - /* Orion Shark */ - ldr r1, =MV_8660_DEV_ID - cmp r3, r1 - beq glMem2Start - - b glMem2End - -glMem2Start: - - /* DDR SDRAM Address/Control Pads Calibration */ - MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - /* Set Bit [31] to make the register writable */ - orr r2, r3, #SDRAM_WR_EN - - MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ - bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ - bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */ - bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */ - - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r3 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ - orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ - - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r3, r3, r1 - - MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - - /* DDR SDRAM Data Pads Calibration */ - MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) - - /* Set Bit [31] to make the register writable */ - orr r2, r3, #SDRAM_WR_EN - - MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) - - bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ - bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ - bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */ - bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */ - - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r3 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 - orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ - - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ - orr r3, r3, r1 - - MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) - -glMem2End: - - - /* Implement Guideline (GL# MEM-3) Drive Strength Value */ - /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ - /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ - - /* Get SDRAM Config value */ - MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) - - /* Get DIMM type */ - tst r2, #SDRAM_DTYPE_DDR2 - beq ddr1StrengthVal - -ddr2StrengthVal: - ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV - ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV - b setDrvStrength -ddr1StrengthVal: - ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV - ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV - -setDrvStrength: - /* DDR SDRAM Address/Control Pads Calibration */ - MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ - - MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) - HTOLL(r3,r1) - - bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ - bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK - orr r3, r4, r3 /* Set default value for DDR */ - - MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) - - - /* DDR SDRAM Data Pads Calibration */ - MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) - - orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ - - MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) - HTOLL(r3,r1) - - bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ - bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK - orr r3, r2, r3 /* Set default value for DDR */ - - MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) - -#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) - /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ - /* 88F5082, 88F5181L, 88F6082/L */ - - /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ - ldr r7, = _cpuARMDDRCLK - ldr r4, =_start - sub r7, r7, r4 - add r7, r7, #CFG_MONITOR_BASE - - /* Get the "sample on reset" register for the DDR frequancy */ - MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) - ldr r1, =MSAR_ARMDDRCLCK_MASK - and r1, r4, r1 -#if 0 /* YOTAM TO BE FIX */ - mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS -#endif - - /* Read device ID */ - MV_CTRL_MODEL_GET_ASM(r3, r2); - - /* Continue if TC90 */ - ldr r2, =MV_1281_DEV_ID - cmp r3, r2 - beq armClkMsb - - /* Continue if Orion2 */ - ldr r2, =MV_5281_DEV_ID - cmp r3, r2 -#if 0 /* YOTAM TO BE FIX */ - bne 1f -#endif - -armClkMsb: -#if 0 /* YOTAM TO BE FIX */ - tst r4, #MSAR_ARMDDRCLCK_H_MASK - beq 1f - orr r1, r1, #BIT4 -1: - ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE - mul r1, r4, r1 - add r7, r7, r1 - add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF - ldr r1, [r7] -#endif - - /* Get SDRAM Config value */ - MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) - - /* Get DIMM type */ - tst r2, #SDRAM_DTYPE_DDR2 - beq ddr1FtdllVal - -ddr2FtdllVal: - ldr r2, =MV_5281_DEV_ID - cmp r3, r2 - bne 2f - MV_CTRL_REV_GET_ASM(r3, r2) - cmp r3, #MV_5281_D0_REV - beq orin2_d0_ddr2_ftdll_val - cmp r3, #MV_5281_D1_REV - beq orin2_d1_ddr2_ftdll_val - cmp r3, #MV_5281_D2_REV - beq orin2_d1_ddr2_ftdll_val - b ddr2_default_val - -/* Set Orion 2 D1 ftdll values for DDR2 */ -orin2_d1_ddr2_ftdll_val: - ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 - ldr r7, =_250MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 - ldr r7, =_200MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg - b ddr2_default_val - -/* Set Orion 2 D0 ftdll values for DDR2 */ -orin2_d0_ddr2_ftdll_val: - ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 - ldr r7, =_250MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 - ldr r7, =_200MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg - b ddr2_default_val -2: - ldr r2, =MV_5182_DEV_ID - cmp r3, r2 - bne 3f - -/* Set Orion nas ftdll values for DDR2 */ -orin_nas_ftdll_val: - ldr r4, =FTDLL_DDR2_166MHZ_5182 - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg - -/* default values for all other devices */ -3: -ddr2_default_val: - ldr r4, =FTDLL_DDR2_250MHZ - ldr r7, =_250MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_200MHZ - ldr r7, =_200MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_166MHZ - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR2_133MHZ - ldr r7, =_133MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =0 - b setFtdllReg - -ddr1FtdllVal: - ldr r2, =MV_5281_DEV_ID - cmp r3, r2 - bne 2f - MV_CTRL_REV_GET_ASM(r3, r2) - cmp r3, #MV_5281_D0_REV - bge orin2_ddr1_ftdll_val - b ddr1_default_val - -/* Set Orion 2 D0 and above ftdll values for DDR1 */ -orin2_ddr1_ftdll_val: - ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 - ldr r7, =_200MHz - cmp r1, r7 - beq setFtdllReg - ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg - b ddr1_default_val -2: - ldr r2, =MV_5181_DEV_ID - cmp r3, r2 - bne 3f - MV_CTRL_REV_GET_ASM(r3, r2) - cmp r3, #MV_5181_B1_REV - bge orin1_ddr1_ftdll_val - b ddr1_default_val - -/* Set Orion 1 ftdll values for DDR1 */ -orin1_ddr1_ftdll_val: - ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg -3: -ddr1_default_val: - ldr r4, =FTDLL_DDR1_133MHZ - ldr r7, =_133MHz - cmp r1, r7 - beq setFtdllReg - - ldr r4, =FTDLL_DDR1_166MHZ - ldr r7, =_166MHz - cmp r1, r7 - beq setFtdllReg - - ldr r4, =FTDLL_DDR1_200MHZ - ldr r7, =_200MHz - cmp r1, r7 - beq setFtdllReg - - ldr r4, =0 - -setFtdllReg: - - MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) - HTOLL(r4,r1) - bic r4, r4, #1 - MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) - -#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ -#endif /* DB_FPGA */ - -restoreTmpRegs: - /* Restore the registers we used to save the DDR detect values */ - - ldr r4, =DRAM_BUF_REG0_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) - - ldr r4, =DRAM_BUF_REG1_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) - - ldr r4, =DRAM_BUF_REG2_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) - - ldr r4, =DRAM_BUF_REG3_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) - - ldr r4, =DRAM_BUF_REG4_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) - - ldr r4, =DRAM_BUF_REG5_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) - - ldr r4, =DRAM_BUF_REG6_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) - - ldr r4, =DRAM_BUF_REG7_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) - - ldr r4, =DRAM_BUF_REG8_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) - - ldr r4, =DRAM_BUF_REG9_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) - - ldr r4, =DRAM_BUF_REG10_DV - MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) - - - /* Restore registers */ - /* Save register on stack */ - cmp sp, #0 - beq no_stack_l -load_from_stack: - ldmia sp!, {r1, r2, r3, r4, r7, r11} -no_stack_l: - - mov pc, lr - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h deleted file mode 100644 index a7c66444ac..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h +++ /dev/null @@ -1,192 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - - -#ifndef __INCmvDramIfConfigh -#define __INCmvDramIfConfigh - -/* includes */ - -/* defines */ - -/* registers defaults values */ - -#define SDRAM_CONFIG_DV \ - (SDRAM_PERR_WRITE | \ - SDRAM_SRMODE | \ - SDRAM_SRCLK_GATED) - -#define SDRAM_DUNIT_CTRL_LOW_DV \ - (SDRAM_CTRL_POS_RISE | \ - SDRAM_CLK1DRV_NORMAL | \ - SDRAM_LOCKEN_ENABLE) - -#define SDRAM_ADDR_CTRL_DV 0 - -#define SDRAM_TIMING_CTRL_LOW_REG_DV \ - ((0x2 << SDRAM_TRCD_OFFS) | \ - (0x2 << SDRAM_TRP_OFFS) | \ - (0x1 << SDRAM_TWR_OFFS) | \ - (0x0 << SDRAM_TWTR_OFFS) | \ - (0x5 << SDRAM_TRAS_OFFS) | \ - (0x1 << SDRAM_TRRD_OFFS)) -/* TRFC 0x27, TW2W 0x1 */ -#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ - ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ - ( 0x1 << SDRAM_TW2W_OFFS)) - -#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN - -/* DDR2 ODT default register values */ - -/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ - -#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 - -#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 - - -/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ - (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ - (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) - - -#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ - (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ - (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) - -/* DDR SDRAM Mode Register default value */ -#define DDR1_MODE_REG_DV 0x00000000 -#define DDR2_MODE_REG_DV 0x00000400 - -/* DDR SDRAM Timing parameter default values */ -#define DDR1_TIMING_LOW_DV 0x11602220 -#define DDR1_TIMING_HIGH_DV 0x0000000d - -#define DDR2_TIMING_LOW_DV 0x11812220 -#define DDR2_TIMING_HIGH_DV 0x0000030f - -/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ - (0x7F<< 12) | \ - (0x1 << 22)) - -#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ - -#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ - (0x1 << 12) | \ - (0x3 << 14) | \ - (0x1 << 18) | \ - (0x1 << 22)) - - -#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ - (0x1 << 12) | \ - (0x1 << 14) | \ - (0x1 << 16) | \ - (0x1 << 19) | \ - (0xF << 20)) - -#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ - -#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ - (0x1 << 12) | \ - (0x1 << 14) | \ - (0x1 << 16) | \ - (0x1 << 19) | \ - (0xF << 20)) - -#define FTDLL_DDR2_250MHZ 0x445001 - -/* Orion 1 B1 and above */ -#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 - -/* Orion nas */ -#define FTDLL_DDR2_166MHZ_5182 0x597001 - -/* Orion 2 D0 and above */ -#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 - -#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h deleted file mode 100644 index e9cd7c4e5d..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h +++ /dev/null @@ -1,306 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCmvDramIfRegsh -#define __INCmvDramIfRegsh - - -/* DDR SDRAM Controller Address Decode Registers */ -/* SDRAM CSn Base Address Register (SCBAR) */ -#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -#define SCBAR_BASE_OFFS 16 -#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -#define SCBAR_BASE_ALIGNMENT 0x10000 - -/* SDRAM CSn Size Register (SCSR) */ -#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -#define SCSR_WIN_EN BIT0 -#define SCSR_SIZE_OFFS 16 -#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -#define SCSR_SIZE_ALIGNMENT 0x10000 - -/* configuration register */ -#define SDRAM_CONFIG_REG 0x1400 -#define SDRAM_REFRESH_OFFS 0 -#define SDRAM_REFRESH_MAX 0x3000 -#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -#define SDRAM_DWIDTH_OFFS 14 -#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -#define SDRAM_DTYPE_OFFS 16 -#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -#define SDRAM_REGISTERED (1 << 17) -#define SDRAM_PERR_OFFS 18 -#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -#define SDRAM_DCFG_OFFS 20 -#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -#define SDRAM_SRMODE (1 << 24) -#define SDRAM_SRCLK_OFFS 25 -#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -#define SDRAM_CATTH_OFFS 26 -#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) - - -/* dunit control register */ -#define SDRAM_DUNIT_CTRL_REG 0x1404 -#define SDRAM_CTRL_POS_OFFS 6 -#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -#define SDRAM_CLK1DRV_OFFS 12 -#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -#define SDRAM_LOCKEN_OFFS 18 -#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -#define SDRAM_ST_BURST_DEL_OFFS 24 -#define SDRAM_ST_BURST_DEL_MAX 0xf -#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX<<SDRAM_ST_BURST_DEL_OFFS) - -/* sdram timing control low register */ -#define SDRAM_TIMING_CTRL_LOW_REG 0x1408 -#define SDRAM_TRCD_OFFS 4 -#define SDRAM_TRCD_MASK (0xF << SDRAM_TRCD_OFFS) -#define SDRAM_TRP_OFFS 8 -#define SDRAM_TRP_MASK (0xF << SDRAM_TRP_OFFS) -#define SDRAM_TWR_OFFS 12 -#define SDRAM_TWR_MASK (0xF << SDRAM_TWR_OFFS) -#define SDRAM_TWTR_OFFS 16 -#define SDRAM_TWTR_MASK (0xF << SDRAM_TWTR_OFFS) -#define SDRAM_TRAS_OFFS 20 -#define SDRAM_TRAS_MASK (0xF << SDRAM_TRAS_OFFS) -#define SDRAM_TRRD_OFFS 24 -#define SDRAM_TRRD_MASK (0xF << SDRAM_TRRD_OFFS) -#define SDRAM_TRTP_OFFS 28 -#define SDRAM_TRTP_MASK (0xF << SDRAM_TRTP_OFFS) - -/* sdram timing control high register */ -#define SDRAM_TIMING_CTRL_HIGH_REG 0x140c -#define SDRAM_TRFC_OFFS 0 -#define SDRAM_TRFC_MASK (0xF << SDRAM_TRFC_OFFS) -#define SDRAM_TR2R_OFFS 4 -#define SDRAM_TR2R_MASK (0x3 << SDRAM_TR2R_OFFS) -#define SDRAM_TR2W_W2R_OFFS 6 -#define SDRAM_TR2W_W2R_MASK (0x3 << SDRAM_TR2W_W2R_OFFS) -#define SDRAM_TRFC_EXT_OFFS 8 -#define SDRAM_TRFC_EXT_MASK (0x1 << SDRAM_TRFC_EXT_OFFS) -#define SDRAM_TW2W_OFFS 10 -#define SDRAM_TW2W_MASK (0x1 << SDRAM_TW2W_OFFS) - -/* address control register */ -#define SDRAM_ADDR_CTRL_REG 0x1410 -#define SDRAM_DSIZE_OFFS 4 -#define SDRAM_DSIZE_MASK (0x3 << SDRAM_DSIZE_OFFS) -#define SDRAM_DSIZE_128Mb (0x0 << SDRAM_DSIZE_OFFS) -#define SDRAM_DSIZE_256Mb (0x1 << SDRAM_DSIZE_OFFS) -#define SDRAM_DSIZE_512Mb (0x2 << SDRAM_DSIZE_OFFS) - -/* SDRAM Open Pages Control registers */ -#define SDRAM_OPEN_PAGE_CTRL_REG 0x1414 -#define SDRAM_OPEN_PAGE_EN (0 << 0) -#define SDRAM_OPEN_PAGE_DIS (1 << 0) - -/* sdram opertion register */ -#define SDRAM_OPERATION_REG 0x1418 -#define SDRAM_CMD_OFFS 0 -#define SDRAM_CMD_MASK (0x7 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_NORMAL (0x0 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_PRECHARGE_ALL (0x1 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_REFRESH_ALL (0x2 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_REG_SET_CMD (0x3 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_EXT_MODE_SET (0x4 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_NOP (0x5 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_SLF_RFRSH (0x7 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_EMRS2_CMD (0x8 << SDRAM_CMD_OFFS) -#define SDRAM_CMD_EMRS3_CMD (0x9 << SDRAM_CMD_OFFS) - -/* sdram mode register */ -#define SDRAM_MODE_REG 0x141c -#define SDRAM_BURST_LEN_OFFS 0 -#define SDRAM_BURST_LEN_MASK (0x7 << SDRAM_BURST_LEN_OFFS) -#define SDRAM_BURST_LEN_4 (0x2 << SDRAM_BURST_LEN_OFFS) -#define SDRAM_CL_OFFS 4 -#define SDRAM_CL_MASK (0x7 << SDRAM_CL_OFFS) -#define SDRAM_DDR1_CL_2 (0x2 << SDRAM_CL_OFFS) -#define SDRAM_DDR1_CL_3 (0x3 << SDRAM_CL_OFFS) -#define SDRAM_DDR1_CL_4 (0x4 << SDRAM_CL_OFFS) -#define SDRAM_DDR1_CL_1_5 (0x5 << SDRAM_CL_OFFS) -#define SDRAM_DDR1_CL_2_5 (0x6 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_3 (0x3 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_4 (0x4 << SDRAM_CL_OFFS) -#define SDRAM_DDR2_CL_5 (0x5 << SDRAM_CL_OFFS) -#define SDRAM_TM_OFFS 7 -#define SDRAM_TM_MASK (1 << SDRAM_TM_OFFS) -#define SDRAM_TM_NORMAL (0 << SDRAM_TM_OFFS) -#define SDRAM_TM_TEST_MODE (1 << SDRAM_TM_OFFS) -#define SDRAM_DLL_OFFS 8 -#define SDRAM_DLL_MASK (1 << SDRAM_DLL_OFFS) -#define SDRAM_DLL_NORMAL (0 << SDRAM_DLL_OFFS) -#define SDRAM_DLL_RESET (1 << SDRAM_DLL_OFFS) -#define SDRAM_WR_OFFS 11 -#define SDRAM_WR_MAX 7 -#define SDRAM_WR_MASK (SDRAM_WR_MAX << SDRAM_WR_OFFS) -#define SDRAM_PD_OFFS 12 -#define SDRAM_PD_MASK (1 << SDRAM_PD_OFFS) -#define SDRAM_PD_FAST_EXIT (0 << SDRAM_PD_OFFS) -#define SDRAM_PD_SLOW_EXIT (1 << SDRAM_PD_OFFS) - -/* DDR SDRAM Extended Mode register (DSEMR) */ -#define SDRAM_EXTENDED_MODE_REG 0x1420 -#define DSEMR_DLL_ENABLE (1 << 0) -#define DSEMR_DS_OFFS 1 -#define DSEMR_DS_MASK (1 << DSEMR_DS_OFFS) -#define DSEMR_DS_NORMAL (0 << DSEMR_DS_OFFS) -#define DSEMR_DS_REDUCED (1 << DSEMR_DS_OFFS) -#define DSEMR_RTT0_OFFS 2 -#define DSEMR_RTT1_OFFS 6 -#define DSEMR_RTT_ODT_DISABLE ((0 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS)) -#define DSEMR_RTT_ODT_75_OHM ((1 << DSEMR_RTT0_OFFS)||(0 << DSEMR_RTT1_OFFS)) -#define DSEMR_RTT_ODT_150_OHM ((0 << DSEMR_RTT0_OFFS)||(1 << DSEMR_RTT1_OFFS)) -#define DSEMR_OCD_OFFS 7 -#define DSEMR_OCD_MASK (0x7 << DSEMR_OCD_OFFS) -#define DSEMR_OCD_EXIT_CALIB (0 << DSEMR_OCD_OFFS) -#define DSEMR_OCD_DRIVE1 (1 << DSEMR_OCD_OFFS) -#define DSEMR_OCD_DRIVE0 (2 << DSEMR_OCD_OFFS) -#define DSEMR_OCD_ADJUST_MODE (4 << DSEMR_OCD_OFFS) -#define DSEMR_OCD_CALIB_DEFAULT (7 << DSEMR_OCD_OFFS) -#define DSEMR_DQS_OFFS 10 -#define DSEMR_DQS_MASK (1 << DSEMR_DQS_OFFS) -#define DSEMR_DQS_DIFFERENTIAL (0 << DSEMR_DQS_OFFS) -#define DSEMR_DQS_SINGLE_ENDED (0 << DSEMR_DQS_OFFS) -#define DSEMR_RDQS_ENABLE (1 << 11) -#define DSEMR_QOFF_OUTPUT_BUFF_EN (1 << 12) - -/* DDR SDRAM Operation Control Register */ -#define SDRAM_OPERATION_CTRL_REG 0x142c - -/* Dunit FTDLL Configuration Register */ -#define SDRAM_FTDLL_CONFIG_REG 0x1484 - -/* Pads Calibration register */ -#define SDRAM_ADDR_CTRL_PADS_CAL_REG 0x14c0 -#define SDRAM_DATA_PADS_CAL_REG 0x14c4 -#define SDRAM_DRVN_OFFS 0 -#define SDRAM_DRVN_MASK (0x3F << SDRAM_DRVN_OFFS) -#define SDRAM_DRVP_OFFS 6 -#define SDRAM_DRVP_MASK (0x3F << SDRAM_DRVP_OFFS) -#define SDRAM_PRE_DRIVER_STRENGTH_OFFS 12 -#define SDRAM_PRE_DRIVER_STRENGTH_MASK (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -#define SDRAM_TUNE_EN BIT16 -#define SDRAM_LOCK_OFFS 17 -#define SDRAM_LOCK_MAKS (0x1F << SDRAM_LOCK_OFFS) -#define SDRAM_LOCKN_OFFS 17 -#define SDRAM_LOCKN_MAKS (0x3F << SDRAM_LOCKN_OFFS) -#define SDRAM_LOCKP_OFFS 23 -#define SDRAM_LOCKP_MAKS (0x3F << SDRAM_LOCKP_OFFS) -#define SDRAM_WR_EN (1 << 31) - -/* DDR2 SDRAM ODT Control (Low) Register (DSOCLR) */ -#define DDR2_SDRAM_ODT_CTRL_LOW_REG 0x1494 -#define DSOCLR_ODT_RD_OFFS(odtNum) (odtNum * 4) -#define DSOCLR_ODT_RD_MASK(odtNum) (0xf << DSOCLR_ODT_RD_OFFS(odtNum)) -#define DSOCLR_ODT_RD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_RD_OFFS(odtNum)) -#define DSOCLR_ODT_WR_OFFS(odtNum) (16 + (odtNum * 4)) -#define DSOCLR_ODT_WR_MASK(odtNum) (0xf << DSOCLR_ODT_WR_OFFS(odtNum)) -#define DSOCLR_ODT_WD(odtNum, bank) ((1 << bank) << DSOCLR_ODT_WR_OFFS(odtNum)) - -/* DDR2 SDRAM ODT Control (High) Register (DSOCHR) */ -#define DDR2_SDRAM_ODT_CTRL_HIGH_REG 0x1498 -/* Optional control values to DSOCHR_ODT_EN macro */ -#define DDR2_ODT_CTRL_DUNIT 0 -#define DDR2_ODT_CTRL_NEVER 1 -#define DDR2_ODT_CTRL_ALWAYS 3 -#define DSOCHR_ODT_EN_OFFS(odtNum) (odtNum * 2) -#define DSOCHR_ODT_EN_MASK(odtNum) (0x3 << DSOCHR_ODT_EN_OFFS(odtNum)) -#define DSOCHR_ODT_EN(odtNum, ctrl) ((1 << ctrl) << DSOCHR_ODT_RD_OFFS(odtNum)) - -/* DDR2 Dunit ODT Control Register (DDOCR)*/ -#define DDR2_DUNIT_ODT_CONTROL_REG 0x149c -#define DDOCR_ODT_RD_OFFS 0 -#define DDOCR_ODT_RD_MASK (0xf << DDOCR_ODT_RD_OFFS) -#define DDOCR_ODT_RD(bank) ((1 << bank) << DDOCR_ODT_RD_OFFS) -#define DDOCR_ODT_WR_OFFS 4 -#define DDOCR_ODT_WR_MASK (0xf << DDOCR_ODT_WR_OFFS) -#define DDOCR_ODT_WR(bank) ((1 << bank) << DDOCR_ODT_WR_OFFS) -#define DSOCR_ODT_EN_OFFS 8 -#define DSOCR_ODT_EN_MASK (0x3 << DSOCR_ODT_EN_OFFS) -#define DSOCR_ODT_EN(ctrl) ((1 << ctrl) << DSOCR_ODT_EN_OFFS) -#define DSOCR_ODT_SEL_OFFS 10 -#define DSOCR_ODT_SEL_MASK (0x3 << DSOCR_ODT_SEL_OFFS) - -/* DDR SDRAM Initialization Control Register (DSICR) */ -#define DDR_SDRAM_INIT_CTRL_REG 0x1480 -#define DSICR_INIT_EN (1 << 0) - -#endif /* __INCmvDramIfRegsh */ |