diff options
19 files changed, 3181 insertions, 172 deletions
diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index d411072558..eeb695d775 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -98,6 +98,10 @@ define uboot/orangepi_plus TITLE:=U-Boot for Orange Pi Plus (H3) endef +define uboot/orangepi_2 + TITLE:=U-Boot for Orange Pi 2 (H3) +endef + UBOOTS:= \ A10-OLinuXino-Lime \ A13-OLinuXino \ @@ -115,6 +119,7 @@ UBOOTS:= \ Linksprite_pcDuino3 \ Lamobo_R1 \ orangepi_plus \ + orangepi_2 \ pangolin define Package/uboot/template diff --git a/package/boot/uboot-sunxi/patches/004-add-orange-pi-2.patch b/package/boot/uboot-sunxi/patches/004-add-orange-pi-2.patch new file mode 100644 index 0000000000..593e92f081 --- /dev/null +++ b/package/boot/uboot-sunxi/patches/004-add-orange-pi-2.patch @@ -0,0 +1,20 @@ +--- /dev/null ++++ b/configs/orangepi_2_defconfig +@@ -0,0 +1,17 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC0_CD_PIN="PF6" ++CONFIG_USB1_VBUS_PIN="PG13" ++# CONFIG_VIDEO is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SY8106A_POWER=y ++CONFIG_USB_EHCI_HCD=y diff --git a/package/boot/uboot-sunxi/patches/011-dt-sync-dts-files-with-kernel.patch b/package/boot/uboot-sunxi/patches/011-dt-sync-dts-files-with-kernel.patch index 1b7a059311..30b58add71 100644 --- a/package/boot/uboot-sunxi/patches/011-dt-sync-dts-files-with-kernel.patch +++ b/package/boot/uboot-sunxi/patches/011-dt-sync-dts-files-with-kernel.patch @@ -93,8 +93,6 @@ Acked-by: Ian Campbell <ijc@hellion.org.uk> create mode 100644 arch/arm/dts/sun8i-a83t-cubietruck-plus.dts create mode 100644 arch/arm/dts/sunxi-itead-core-common.dtsi -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 578038b..0cea4b4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -126,6 +126,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ @@ -125,17 +123,17 @@ index 578038b..0cea4b4 100644 sun7i-a20-lamobo-r1.dtb \ sun7i-a20-m3.dtb \ sun7i-a20-m5.dtb \ -@@ -189,6 +194,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ +@@ -189,8 +194,10 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ + sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-sinovoip-bpi-m3.dtb dtb-$(CONFIG_MACH_SUN8I_H3) += \ ++ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-pc.dtb \ -diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi -new file mode 100644 -index 0000000..0cfec50 + sun8i-h3-orangepi-plus.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ --- /dev/null +++ b/arch/arm/dts/axp22x.dtsi @@ -0,0 +1,145 @@ @@ -284,8 +282,6 @@ index 0000000..0cfec50 + }; + }; +}; -diff --git a/arch/arm/dts/sun4i-a10-a1000.dts b/arch/arm/dts/sun4i-a10-a1000.dts -index 2630d78..97570cb 100644 --- a/arch/arm/dts/sun4i-a10-a1000.dts +++ b/arch/arm/dts/sun4i-a10-a1000.dts @@ -93,6 +93,10 @@ @@ -299,8 +295,6 @@ index 2630d78..97570cb 100644 &ehci0 { status = "okay"; }; -diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts -index 1430568..023b03e 100644 --- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts +++ b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts @@ -45,6 +45,7 @@ @@ -339,8 +333,6 @@ index 1430568..023b03e 100644 &lradc { vref-supply = <®_vcc3v0>; status = "okay"; -diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts -index 046a84d..710e2ef 100644 --- a/arch/arm/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/dts/sun4i-a10-cubieboard.dts @@ -83,6 +83,10 @@ @@ -354,8 +346,6 @@ index 046a84d..710e2ef 100644 &cpu0 { cpu-supply = <®_dcdc2>; }; -diff --git a/arch/arm/dts/sun4i-a10-gemei-g9.dts b/arch/arm/dts/sun4i-a10-gemei-g9.dts -index 570754d..ac64781 100644 --- a/arch/arm/dts/sun4i-a10-gemei-g9.dts +++ b/arch/arm/dts/sun4i-a10-gemei-g9.dts @@ -47,6 +47,7 @@ @@ -470,8 +460,6 @@ index 570754d..ac64781 100644 ®_usb1_vbus { status = "okay"; }; -diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts -index 487ce63..e09053b 100644 --- a/arch/arm/dts/sun4i-a10-inet1.dts +++ b/arch/arm/dts/sun4i-a10-inet1.dts @@ -47,6 +47,7 @@ @@ -562,8 +550,6 @@ index 487ce63..e09053b 100644 ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -diff --git a/arch/arm/dts/sun4i-a10-inet97fv2.dts b/arch/arm/dts/sun4i-a10-inet97fv2.dts -index 6c927a8..04b0d2d 100644 --- a/arch/arm/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/dts/sun4i-a10-inet97fv2.dts @@ -47,6 +47,8 @@ @@ -737,8 +723,6 @@ index 6c927a8..04b0d2d 100644 usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; }; -diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts -index 8446465..bba4f9c 100644 --- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts @@ -59,6 +59,159 @@ @@ -949,8 +933,6 @@ index 8446465..bba4f9c 100644 usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH4"; allwinner,function = "gpio_in"; -diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts -index 985e155..4e798f0 100644 --- a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts +++ b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts @@ -1,5 +1,6 @@ @@ -1085,8 +1067,6 @@ index 985e155..4e798f0 100644 - usb2_vbus-supply = <®_usb2_vbus>; - status = "okay"; -}; -diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/dts/sun4i-a10-jesurun-q5.dts -index dc2f2ae..7afc7a6 100644 --- a/arch/arm/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/dts/sun4i-a10-jesurun-q5.dts @@ -156,6 +156,10 @@ @@ -1126,8 +1106,6 @@ index dc2f2ae..7afc7a6 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun4i-a10-marsboard.dts b/arch/arm/dts/sun4i-a10-marsboard.dts -index 02158bc..8e50723 100644 --- a/arch/arm/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/dts/sun4i-a10-marsboard.dts @@ -91,6 +91,10 @@ @@ -1182,8 +1160,6 @@ index 02158bc..8e50723 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun4i-a10-mk802.dts b/arch/arm/dts/sun4i-a10-mk802.dts -index 3c7eebe..ee46ea8 100644 --- a/arch/arm/dts/sun4i-a10-mk802.dts +++ b/arch/arm/dts/sun4i-a10-mk802.dts @@ -44,6 +44,7 @@ @@ -1260,8 +1236,6 @@ index 3c7eebe..ee46ea8 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts -index 28e32ad..b350448 100644 --- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts @@ -124,6 +124,18 @@ @@ -1283,8 +1257,6 @@ index 28e32ad..b350448 100644 &mdio { status = "okay"; -diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts -index 4e3e1b9..39034aa 100644 --- a/arch/arm/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/dts/sun4i-a10-pcduino.dts @@ -104,6 +104,10 @@ @@ -1386,9 +1358,6 @@ index 4e3e1b9..39034aa 100644 + usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */ status = "okay"; }; -diff --git a/arch/arm/dts/sun4i-a10-pcduino2.dts b/arch/arm/dts/sun4i-a10-pcduino2.dts -new file mode 100644 -index 0000000..de483a1 --- /dev/null +++ b/arch/arm/dts/sun4i-a10-pcduino2.dts @@ -0,0 +1,78 @@ @@ -1470,8 +1439,6 @@ index 0000000..de483a1 + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; -diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts -index 223515e..ea90634 100644 --- a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts @@ -47,6 +47,7 @@ @@ -1589,8 +1556,6 @@ index 223515e..ea90634 100644 ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi -index 463bacd..2c8f5e6 100644 --- a/arch/arm/dts/sun4i-a10.dtsi +++ b/arch/arm/dts/sun4i-a10.dtsi @@ -45,6 +45,7 @@ @@ -1840,8 +1805,6 @@ index 463bacd..2c8f5e6 100644 sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; -diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts -index 2b3511e..a790ec8 100644 --- a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts @@ -86,6 +86,20 @@ @@ -1865,8 +1828,6 @@ index 2b3511e..a790ec8 100644 &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>; -diff --git a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts -index 5a422c1..86d046a 100644 --- a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts @@ -111,7 +111,7 @@ @@ -1878,8 +1839,6 @@ index 5a422c1..86d046a 100644 pagesize = <16>; reg = <0x50>; read-only; -diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts -index 7fbb0b0..6efbba6 100644 --- a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts @@ -123,7 +123,7 @@ @@ -1920,8 +1879,6 @@ index 7fbb0b0..6efbba6 100644 allwinner,pins = "PG0"; allwinner,function = "gpio_in"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; -diff --git a/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts -index 6d466a2..1b11ec9 100644 --- a/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts +++ b/arch/arm/dts/sun5i-a13-inet-98v-rev2.dts @@ -123,21 +123,6 @@ @@ -1976,8 +1933,6 @@ index 6d466a2..1b11ec9 100644 + usb1_vbus-supply = <®_ldo3>; status = "okay"; }; -diff --git a/arch/arm/dts/sun5i-a13-utoo-p66.dts b/arch/arm/dts/sun5i-a13-utoo-p66.dts -index eb793d5..fa9ddfd 100644 --- a/arch/arm/dts/sun5i-a13-utoo-p66.dts +++ b/arch/arm/dts/sun5i-a13-utoo-p66.dts @@ -47,11 +47,21 @@ @@ -2043,8 +1998,6 @@ index eb793d5..fa9ddfd 100644 ®_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; -diff --git a/arch/arm/dts/sun5i-q8-common.dtsi b/arch/arm/dts/sun5i-q8-common.dtsi -index 0641d68..a78e189 100644 --- a/arch/arm/dts/sun5i-q8-common.dtsi +++ b/arch/arm/dts/sun5i-q8-common.dtsi @@ -41,11 +41,21 @@ @@ -2069,8 +2022,6 @@ index 0641d68..a78e189 100644 chosen { stdout-path = "serial0:115200n8"; }; -diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts -index abf3ccb..6ad19e2 100644 --- a/arch/arm/dts/sun5i-r8-chip.dts +++ b/arch/arm/dts/sun5i-r8-chip.dts @@ -64,6 +64,26 @@ @@ -2151,8 +2102,6 @@ index abf3ccb..6ad19e2 100644 ®_ldo5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; -diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi -index 9ffee9b..59a9426 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -44,6 +44,7 @@ @@ -2214,8 +2163,6 @@ index 9ffee9b..59a9426 100644 sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; -diff --git a/arch/arm/dts/sun6i-a31-colombus.dts b/arch/arm/dts/sun6i-a31-colombus.dts -index 0d0b6f2..f9cf368 100644 --- a/arch/arm/dts/sun6i-a31-colombus.dts +++ b/arch/arm/dts/sun6i-a31-colombus.dts @@ -60,6 +60,16 @@ @@ -2263,8 +2210,6 @@ index 0d0b6f2..f9cf368 100644 }; ®_usb2_vbus { -diff --git a/arch/arm/dts/sun6i-a31-hummingbird.dts b/arch/arm/dts/sun6i-a31-hummingbird.dts -index d0cfada..9a74637 100644 --- a/arch/arm/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/dts/sun6i-a31-hummingbird.dts @@ -54,6 +54,8 @@ @@ -2454,8 +2399,6 @@ index d0cfada..9a74637 100644 ®_usb1_vbus { gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */ status = "okay"; -diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi -index 44f889f..1867af2 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -61,7 +61,7 @@ @@ -2600,8 +2543,6 @@ index 44f889f..1867af2 100644 #size-cells = <0>; #gpio-cells = <3>; -diff --git a/arch/arm/dts/sun6i-a31s-primo81.dts b/arch/arm/dts/sun6i-a31s-primo81.dts -index cfdc03e..379746a 100644 --- a/arch/arm/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/dts/sun6i-a31s-primo81.dts @@ -1,16 +1,57 @@ @@ -2871,9 +2812,6 @@ index cfdc03e..379746a 100644 + usb1_vbus-supply = <®_dldo1>; status = "okay"; }; -diff --git a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi -new file mode 100644 -index 0000000..4ec0c86 --- /dev/null +++ b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi @@ -0,0 +1,142 @@ @@ -3019,9 +2957,6 @@ index 0000000..4ec0c86 + status = "okay"; +}; + -diff --git a/arch/arm/dts/sun6i-a31s-sina31s.dts b/arch/arm/dts/sun6i-a31s-sina31s.dts -new file mode 100644 -index 0000000..6ead2f5 --- /dev/null +++ b/arch/arm/dts/sun6i-a31s-sina31s.dts @@ -0,0 +1,153 @@ @@ -3178,9 +3113,6 @@ index 0000000..6ead2f5 +&usbphy { + status = "okay"; +}; -diff --git a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts -new file mode 100644 -index 0000000..360adfb --- /dev/null +++ b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -0,0 +1,205 @@ @@ -3389,8 +3321,6 @@ index 0000000..360adfb + usb2_vbus-supply = <®_dc1sw>; + status = "okay"; +}; -diff --git a/arch/arm/dts/sun7i-a20-bananapi.dts b/arch/arm/dts/sun7i-a20-bananapi.dts -index 9f7b472..67c8a76 100644 --- a/arch/arm/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/dts/sun7i-a20-bananapi.dts @@ -92,6 +92,24 @@ @@ -3511,8 +3441,6 @@ index 9f7b472..67c8a76 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-cubieboard2.dts b/arch/arm/dts/sun7i-a20-cubieboard2.dts -index 39a51d5..1fa832d 100644 --- a/arch/arm/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/dts/sun7i-a20-cubieboard2.dts @@ -84,6 +84,10 @@ @@ -3572,8 +3500,6 @@ index 39a51d5..1fa832d 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts -index e6b0192..8da939a 100644 --- a/arch/arm/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/dts/sun7i-a20-cubietruck.dts @@ -101,6 +101,10 @@ @@ -3587,9 +3513,6 @@ index e6b0192..8da939a 100644 &cpu0 { cpu-supply = <®_dcdc2>; }; -diff --git a/arch/arm/dts/sun7i-a20-icnova-swac.dts b/arch/arm/dts/sun7i-a20-icnova-swac.dts -new file mode 100644 -index 0000000..f5b5325 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-icnova-swac.dts @@ -0,0 +1,169 @@ @@ -3762,9 +3685,6 @@ index 0000000..f5b5325 + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; -diff --git a/arch/arm/dts/sun7i-a20-itead-ibox.dts b/arch/arm/dts/sun7i-a20-itead-ibox.dts -new file mode 100644 -index 0000000..661c21d --- /dev/null +++ b/arch/arm/dts/sun7i-a20-itead-ibox.dts @@ -0,0 +1,125 @@ @@ -3893,8 +3813,6 @@ index 0000000..661c21d +®_ahci_5v { + status = "okay"; +}; -diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts -index 975b0b2..5ee43d8 100644 --- a/arch/arm/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts @@ -97,16 +97,6 @@ @@ -3914,8 +3832,6 @@ index 975b0b2..5ee43d8 100644 }; &ehci0 { -diff --git a/arch/arm/dts/sun7i-a20-mk808c.dts b/arch/arm/dts/sun7i-a20-mk808c.dts -index 4f432f8..90ff4a2 100644 --- a/arch/arm/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/dts/sun7i-a20-mk808c.dts @@ -53,6 +53,7 @@ @@ -3986,8 +3902,6 @@ index 4f432f8..90ff4a2 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts -index 6904dbd..23aacce 100644 --- a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts @@ -1,5 +1,6 @@ @@ -4155,8 +4069,6 @@ index 6904dbd..23aacce 100644 usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; -diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts -index 0423708..35ad700 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts @@ -117,6 +117,18 @@ @@ -4178,8 +4090,6 @@ index 0423708..35ad700 100644 &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; -diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts -index 8acff78..d5c796c 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts @@ -170,6 +170,12 @@ @@ -4265,8 +4175,6 @@ index 8acff78..d5c796c 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts -index c5d70ca..7e3006f 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts @@ -125,6 +125,12 @@ @@ -4282,8 +4190,6 @@ index c5d70ca..7e3006f 100644 }; &i2c2 { -diff --git a/arch/arm/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/dts/sun7i-a20-orangepi-mini.dts -index 73cd81e..2be04c4 100644 --- a/arch/arm/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/dts/sun7i-a20-orangepi-mini.dts @@ -95,6 +95,10 @@ @@ -4349,8 +4255,6 @@ index 73cd81e..2be04c4 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-orangepi.dts b/arch/arm/dts/sun7i-a20-orangepi.dts -index 55a06ce..71125bf 100644 --- a/arch/arm/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/dts/sun7i-a20-orangepi.dts @@ -141,7 +141,18 @@ @@ -4405,8 +4309,6 @@ index 55a06ce..71125bf 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts -index 5361fce..ddac732 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts @@ -82,6 +82,14 @@ @@ -4527,8 +4429,6 @@ index 5361fce..ddac732 100644 + usb2_vbus-supply = <®_usb1_vbus>; status = "okay"; }; -diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts -index afc9ece..1a8b39b 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -111,6 +111,14 @@ @@ -4638,8 +4538,6 @@ index afc9ece..1a8b39b 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts -index 83c6d3f..2f6b21a 100644 --- a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts +++ b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts @@ -48,6 +48,7 @@ @@ -4787,8 +4685,6 @@ index 83c6d3f..2f6b21a 100644 usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; -diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts -index e7d84fe..dc31d47 100644 --- a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -1,13 +1,52 @@ @@ -5012,8 +4908,6 @@ index e7d84fe..dc31d47 100644 + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; -diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi -index 71ab6b8..0940a78 100644 --- a/arch/arm/dts/sun7i-a20.dtsi +++ b/arch/arm/dts/sun7i-a20.dtsi @@ -47,6 +47,7 @@ @@ -5220,8 +5114,6 @@ index 71ab6b8..0940a78 100644 sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; -diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi -index 9c4a55c..7e05e09 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -56,7 +56,7 @@ @@ -5364,8 +5256,6 @@ index 9c4a55c..7e05e09 100644 + }; }; }; -diff --git a/arch/arm/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/dts/sun8i-a23-gt90h-v4.dts -index 1aeb06c..b2ce284 100644 --- a/arch/arm/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/dts/sun8i-a23-gt90h-v4.dts @@ -47,15 +47,26 @@ @@ -5535,8 +5425,6 @@ index 1aeb06c..b2ce284 100644 + usb1_vbus-supply = <®_dldo1>; status = "okay"; }; -diff --git a/arch/arm/dts/sun8i-a23.dtsi b/arch/arm/dts/sun8i-a23.dtsi -index 2cc27c7..92e6616 100644 --- a/arch/arm/dts/sun8i-a23.dtsi +++ b/arch/arm/dts/sun8i-a23.dtsi @@ -50,6 +50,31 @@ @@ -5571,8 +5459,6 @@ index 2cc27c7..92e6616 100644 mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun8i-a23-mbus-clk"; -diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts -index 1d5390d..fef6abc 100644 --- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -68,7 +68,7 @@ @@ -5692,8 +5578,6 @@ index 1d5390d..fef6abc 100644 &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; -diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi -index faa7d3c..001d840 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -72,6 +72,41 @@ @@ -5755,9 +5639,6 @@ index faa7d3c..001d840 100644 usb_otg: usb@01c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; -diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts -new file mode 100644 -index 0000000..88b1e09 --- /dev/null +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts @@ -0,0 +1,65 @@ @@ -5826,8 +5707,6 @@ index 0000000..88b1e09 + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; -diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi -index 245b819..d3473f8 100644 --- a/arch/arm/dts/sun8i-a83t.dtsi +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -52,12 +52,6 @@ @@ -6039,8 +5918,6 @@ index 245b819..d3473f8 100644 + }; }; }; -diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts -index 4b25dcc..30ccca0 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -45,6 +45,7 @@ @@ -6140,8 +6017,6 @@ index 4b25dcc..30ccca0 100644 &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts -index 1cb6c66..900ec4f 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -45,6 +45,7 @@ @@ -6221,8 +6096,6 @@ index 1cb6c66..900ec4f 100644 }; &ehci1 { -diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi -index 0faa38a..c2f63c5 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -83,12 +83,6 @@ @@ -6478,17 +6351,40 @@ index 0faa38a..c2f63c5 100644 phys = <&usbphy 3>; phy-names = "usb"; status = "disabled"; -@@ -469,7 +499,7 @@ +@@ -469,7 +499,18 @@ gpio-controller; #gpio-cells = <3>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; ++ ++ rgmii_pins: rgmii_pins { ++ allwinner,pins = "PD0", "PD1", "PD2", "PD3", ++ "PD4", "PD5", "PD7", ++ "PD8", "PD9", "PD10", ++ "PD12", "PD13", "PD15", ++ "PD16", "PD17"; ++ allwinner,function = "emac"; ++ allwinner,drive = <SUN4I_PINCTRL_40_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; uart0_pins_a: uart0@0 { allwinner,pins = "PA4", "PA5"; -@@ -502,10 +532,22 @@ +@@ -500,12 +541,34 @@ + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; ++ ++ mmc2_8bit_pins: mmc2_8bit { ++ allwinner,pins = "PC5", "PC6", "PC8", ++ "PC9", "PC10", "PC11", ++ "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ allwinner,function = "mmc2"; ++ allwinner,drive = <SUN4I_PINCTRL_30_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; }; - bus_rst: reset@01c202c0 { @@ -6513,7 +6409,7 @@ index 0faa38a..c2f63c5 100644 }; timer@01c20c00 { -@@ -529,7 +571,7 @@ +@@ -529,7 +592,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 112>; @@ -6522,7 +6418,7 @@ index 0faa38a..c2f63c5 100644 dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; -@@ -542,7 +584,7 @@ +@@ -542,7 +605,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 113>; @@ -6531,7 +6427,7 @@ index 0faa38a..c2f63c5 100644 dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; -@@ -555,7 +597,7 @@ +@@ -555,7 +618,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 114>; @@ -6540,7 +6436,7 @@ index 0faa38a..c2f63c5 100644 dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; -@@ -568,7 +610,7 @@ +@@ -568,12 +631,26 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&bus_gates 115>; @@ -6549,7 +6445,26 @@ index 0faa38a..c2f63c5 100644 dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; -@@ -591,5 +633,40 @@ + }; + ++ emac: ethernet@01c30000 { ++ compatible = "allwinner,sun8i-h3-emac"; ++ reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; ++ reg-names = "emac", "syscon"; ++ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; ++ resets = <&ahb_rst 17>, <&ahb_rst 66>; ++ reset-names = "ahb", "ephy"; ++ clocks = <&bus_gates 17>, <&bus_gates 128>; ++ clock-names = "ahb", "ephy"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +@@ -591,5 +668,40 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; }; @@ -6590,8 +6505,6 @@ index 0faa38a..c2f63c5 100644 + }; }; }; -diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi -index 07cd268..346a49d 100644 --- a/arch/arm/dts/sun8i-q8-common.dtsi +++ b/arch/arm/dts/sun8i-q8-common.dtsi @@ -41,11 +41,23 @@ @@ -6718,8 +6631,6 @@ index 07cd268..346a49d 100644 +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; -diff --git a/arch/arm/dts/sun9i-a80-cubieboard4.dts b/arch/arm/dts/sun9i-a80-cubieboard4.dts -index 6484dcf..eb2ccd0 100644 --- a/arch/arm/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/dts/sun9i-a80-cubieboard4.dts @@ -62,9 +62,31 @@ @@ -6775,8 +6686,6 @@ index 6484dcf..eb2ccd0 100644 status = "okay"; }; -diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts -index 6ce4b5e..d7a20d9 100644 --- a/arch/arm/dts/sun9i-a80-optimus.dts +++ b/arch/arm/dts/sun9i-a80-optimus.dts @@ -65,7 +65,7 @@ @@ -6870,8 +6779,6 @@ index 6ce4b5e..d7a20d9 100644 }; &usbphy1 { -diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi -index a43ad77..f68b324 100644 --- a/arch/arm/dts/sun9i-a80.dtsi +++ b/arch/arm/dts/sun9i-a80.dtsi @@ -128,6 +128,17 @@ @@ -7196,9 +7103,6 @@ index a43ad77..f68b324 100644 + }; }; }; -diff --git a/arch/arm/dts/sunxi-itead-core-common.dtsi b/arch/arm/dts/sunxi-itead-core-common.dtsi -new file mode 100644 -index 0000000..2565d51 --- /dev/null +++ b/arch/arm/dts/sunxi-itead-core-common.dtsi @@ -0,0 +1,136 @@ @@ -7338,8 +7242,6 @@ index 0000000..2565d51 + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; -diff --git a/arch/arm/dts/sunxi-q8-common.dtsi b/arch/arm/dts/sunxi-q8-common.dtsi -index 17b26ff..b824146 100644 --- a/arch/arm/dts/sunxi-q8-common.dtsi +++ b/arch/arm/dts/sunxi-q8-common.dtsi @@ -75,3 +75,9 @@ @@ -7352,3 +7254,205 @@ index 17b26ff..b824146 100644 + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts +@@ -0,0 +1,199 @@ ++/* ++ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++#include <dt-bindings/pinctrl/sun4i-a10.h> ++ ++/ { ++ model = "Xunlong Orange Pi 2"; ++ compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_opc>, <&leds_r_opc>; ++ ++ status_led { ++ label = "orangepi:red:status"; ++ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ pwr_led { ++ label = "orangepi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ r_gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sw_r_opc>; ++ ++ sw2 { ++ label = "sw2"; ++ linux,code = <BTN_1>; ++ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sw4 { ++ label = "sw4"; ++ linux,code = <BTN_0>; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_pwrseq_pin_orangepi>; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_pins_a>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&pio { ++ leds_opc: led_pins@0 { ++ allwinner,pins = "PA15"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++}; ++ ++&r_pio { ++ leds_r_opc: led_pins@0 { ++ allwinner,pins = "PL10"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ sw_r_opc: key_pins@0 { ++ allwinner,pins = "PL3", "PL4"; ++ allwinner,function = "gpio_in"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { ++ allwinner,pins = "PL7"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++}; ++ ++®_usb1_vbus { ++ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usb1_vbus_pin_a { ++ allwinner,pins = "PG13"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy = <&phy1>; ++ status = "okay"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ diff --git a/package/kernel/mwlwifi/Makefile b/package/kernel/mwlwifi/Makefile index 880803e55e..f59943d296 100644 --- a/package/kernel/mwlwifi/Makefile +++ b/package/kernel/mwlwifi/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=mwlwifi -PKG_VERSION:=10.3.0.17-20160617 +PKG_VERSION:=10.3.0.18-20160804 PKG_RELEASE=1 PKG_LICENSE:=ISC @@ -17,7 +17,7 @@ PKG_LICENSE_FILES:= PKG_SOURCE_URL:=https://github.com/kaloz/mwlwifi PKG_SOURCE_PROTO:=git PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE_VERSION:=b7aff3c2839b048407d716d1cb9326122ee401f8 +PKG_SOURCE_VERSION:=d48847cc83954930fdcd98818bbf33e75707b8e1 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz PKG_MAINTAINER:=Imre Kaloz <kaloz@openwrt.org> diff --git a/package/network/services/uhttpd/files/uhttpd.config b/package/network/services/uhttpd/files/uhttpd.config index e14b9fefd7..bdc0675099 100644 --- a/package/network/services/uhttpd/files/uhttpd.config +++ b/package/network/services/uhttpd/files/uhttpd.config @@ -103,6 +103,11 @@ config uhttpd main # except for development and debug purposes! # option no_ubusauth 0 + # For this instance of uhttpd use the listed httpauth + # sections to require Basic auth to the specified + # resources. +# list httpauth prefix_user + # Certificate defaults for px5g key generator config cert px5g @@ -120,3 +125,8 @@ config cert px5g # Common name option commonname OpenWrt + +# config httpauth prefix_user +# option prefix /protected/url/path +# option username user +# option password 'plaintext_or_md5_or_$p$user_for_system_user'
\ No newline at end of file diff --git a/package/network/services/uhttpd/files/uhttpd.init b/package/network/services/uhttpd/files/uhttpd.init index 4ca6c8d626..d411d2aaf5 100755 --- a/package/network/services/uhttpd/files/uhttpd.init +++ b/package/network/services/uhttpd/files/uhttpd.init @@ -53,6 +53,21 @@ generate_keys() { } } +create_httpauth() { + local cfg="$1" + local prefix username password + + config_get prefix "$cfg" prefix + config_get username "$cfg" username + config_get password "$cfg" password + + if [ -z "$prefix" ] || [ -z "$username" ] || [ -z "$password" ]; then + return + fi + echo "${prefix}:${username}:${password}" >>$httpdconf + haveauth=1 +} + start_instance() { UHTTPD_CERT="" @@ -60,13 +75,25 @@ start_instance() local cfg="$1" local realm="$(uci_get system.@system[0].hostname)" - local listen http https interpreter indexes path handler + local listen http https interpreter indexes path handler httpdconf haveauth procd_open_instance procd_set_param respawn procd_set_param stderr 1 procd_set_param command "$UHTTPD_BIN" -f + config_get config "$cfg" config + if [ -z "$config" ]; then + mkdir -p /var/etc/uhttpd + httpdconf="/var/etc/uhttpd/httpd.${cfg}.conf" + rm -f ${httpdconf} + config_list_foreach "$cfg" httpauth create_httpauth + if [ "$haveauth" = "1" ]; then + procd_append_param command -c ${httpdconf} + [ -r /etc/httpd.conf ] && cat /etc/httpd.conf >>/var/etc/uhttpd/httpd.${cfg}.conf + fi + fi + append_arg "$cfg" home "-h" append_arg "$cfg" realm "-r" "${realm:-OpenWrt}" append_arg "$cfg" config "-c" diff --git a/target/linux/brcm2708/bcm2708/profiles/RaspberryPi.mk b/target/linux/brcm2708/bcm2708/profiles/RaspberryPi.mk new file mode 100644 index 0000000000..9f698a711d --- /dev/null +++ b/target/linux/brcm2708/bcm2708/profiles/RaspberryPi.mk @@ -0,0 +1,14 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RaspberryPi + NAME:=Raspberry Pi Models B/B+/CM +endef +define Profile/RaspberryPi/Description + Raspberry Pi Models B/B+/CM +endef +$(eval $(call Profile,RaspberryPi)) diff --git a/target/linux/brcm2708/bcm2709/profiles/RaspberryPi2.mk b/target/linux/brcm2708/bcm2709/profiles/RaspberryPi2.mk new file mode 100644 index 0000000000..ef7483d841 --- /dev/null +++ b/target/linux/brcm2708/bcm2709/profiles/RaspberryPi2.mk @@ -0,0 +1,14 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RaspberryPi_2 + NAME:=Raspberry Pi 2 Model B +endef +define Profile/RaspberryPi_2/Description + Raspberry Pi 2 Model B +endef +$(eval $(call Profile,RaspberryPi_2)) diff --git a/target/linux/brcm2708/bcm2710/profiles/RaspberryPi3.mk b/target/linux/brcm2708/bcm2710/profiles/RaspberryPi3.mk new file mode 100644 index 0000000000..c39cf5257b --- /dev/null +++ b/target/linux/brcm2708/bcm2710/profiles/RaspberryPi3.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2016 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RaspberryPi_3 + NAME:=Raspberry Pi 3 Model B + PACKAGES:=brcmfmac43430-firmware-sdio kmod-brcmfmac wpad-mini +endef +define Profile/RaspberryPi_3/Description + Raspberry Pi 3 Model B +endef +$(eval $(call Profile,RaspberryPi_3)) diff --git a/target/linux/brcm2708/image/Makefile b/target/linux/brcm2708/image/Makefile index 35f51204f0..e7089c6a19 100644 --- a/target/linux/brcm2708/image/Makefile +++ b/target/linux/brcm2708/image/Makefile @@ -1,4 +1,4 @@ -# +# # Copyright (C) 2012-2015 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. @@ -42,39 +42,45 @@ define Build/sdcard-img $(if $(CONFIG_TARGET_IMAGES_GZIP),gzip -9n -c $@ > $(BIN_DIR)/$(notdir $@).gz) endef -### Devices ### +### Device macros ### define Device/Default FILESYSTEMS := ext4 + PROFILES = Default $$(DEVICE_PROFILE) KERNEL := kernel-bin | kernel-img IMAGES := sdcard.img IMAGE/sdcard.img := boot-img | sdcard-img + DEVICE_PROFILE := DEVICE_DTS := endef -DEVICE_VARS += DEVICE_DTS +DEVICE_VARS += DEVICE_PROFILE DEVICE_DTS -define Device/rpi - DEVICE_TITLE := Raspberry Pi B/B+/CM/Zero - DEVICE_DTS := bcm2708-rpi-b bcm2708-rpi-b-plus bcm2708-rpi-cm +# $(1) = profile +# $(2) = image name +# $(3) = dts +define bcm27xx + define Device/$(2) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + endef + TARGET_DEVICES += $(2) endef + +### BCM2708/BCM2835 ### ifeq ($(SUBTARGET),bcm2708) - TARGET_DEVICES += rpi + # Raspberry Pi Models B/B+/CM + $(eval $(call bcm27xx,RaspberryPi,rpi,bcm2708-rpi-b bcm2708-rpi-b-plus bcm2708-rpi-cm)) endif -define Device/rpi-2 - DEVICE_TITLE := Raspberry Pi 2 B - DEVICE_DTS := bcm2709-rpi-2-b -endef +### BCM2709/BCM2836 ### ifeq ($(SUBTARGET),bcm2709) - TARGET_DEVICES += rpi-2 + # Raspberry Pi 2 Model B + $(eval $(call bcm27xx,RaspberryPi_2,rpi-2,bcm2709-rpi-2-b)) endif -define Device/rpi-3 - DEVICE_TITLE := Raspberry Pi 3 B - DEVICE_DTS := bcm2710-rpi-3-b - DEVICE_PACKAGES := brcmfmac43430-firmware-sdio kmod-brcmfmac wpad-mini -endef +### BCM2710/BCM2837 ### ifeq ($(SUBTARGET),bcm2710) - TARGET_DEVICES += rpi-3 + # Raspberry Pi 3 Model B + $(eval $(call bcm27xx,RaspberryPi_3,rpi-3,bcm2710-rpi-3-b)) endif $(eval $(call BuildImage)) diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile index bda690e39c..0525e08ed9 100644 --- a/target/linux/sunxi/image/Makefile +++ b/target/linux/sunxi/image/Makefile @@ -111,6 +111,10 @@ define Image/Build/Profile/orangepi_plus $(call Image/Build/SDCard,$(1),sun8i-h3-orangepi-plus) endef +define Image/Build/Profile/orangepi_2 + $(call Image/Build/SDCard,$(1),sun8i-h3-orangepi-2) +endef + define Image/Build $(call Image/Build/$(1),$(1)) $(call Image/Build/Profile/$(PROFILE),$(1)) diff --git a/target/linux/sunxi/patches-4.4/210-dt-sun8i-add-orangepi-2.patch b/target/linux/sunxi/patches-4.4/210-dt-sun8i-add-orangepi-2.patch new file mode 100644 index 0000000000..5f40cec3d4 --- /dev/null +++ b/target/linux/sunxi/patches-4.4/210-dt-sun8i-add-orangepi-2.patch @@ -0,0 +1,302 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -662,6 +662,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-q8-tablet.dtb \ + sun8i-a33-sinlinx-sina33.dtb \ ++ sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-plus.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +@@ -0,0 +1,186 @@ ++/* ++ * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++#include <dt-bindings/pinctrl/sun4i-a10.h> ++ ++/ { ++ model = "Xunlong Orange Pi 2"; ++ compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&leds_opc>, <&leds_r_opc>; ++ ++ status_led { ++ label = "orangepi:red:status"; ++ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ pwr_led { ++ label = "orangepi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ r_gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sw_r_opc>; ++ ++ sw2 { ++ label = "sw2"; ++ linux,code = <BTN_1>; ++ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ sw4 { ++ label = "sw4"; ++ linux,code = <BTN_0>; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_pwrseq_pin_orangepi>; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_pins_a>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&pio { ++ leds_opc: led_pins@0 { ++ allwinner,pins = "PA15"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++}; ++ ++&r_pio { ++ leds_r_opc: led_pins@0 { ++ allwinner,pins = "PL10"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ sw_r_opc: key_pins@0 { ++ allwinner,pins = "PL3", "PL4"; ++ allwinner,function = "gpio_in"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ ++ wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { ++ allwinner,pins = "PL7"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++}; ++ ++®_usb1_vbus { ++ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usb1_vbus_pin_a { ++ allwinner,pins = "PG13"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/sun8i-h3.dtsi ++++ b/arch/arm/boot/dts/sun8i-h3.dtsi +@@ -288,6 +288,33 @@ + clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clock-output-names = "mbus"; + }; ++ ++ apb0: apb0_clk { ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ clocks = <&osc24M>; ++ clock-output-names = "apb0"; ++ }; ++ ++ apb0_gates: clk@01f01428 { ++ compatible = "allwinner,sun8i-h3-apb0-gates-clk", ++ "allwinner,sun4i-a10-gates-clk"; ++ reg = <0x01f01428 0x4>; ++ #clock-cells = <1>; ++ clocks = <&apb0>; ++ clock-indices = <0>, <1>; ++ clock-output-names = "apb0_pio", "apb0_ir"; ++ }; ++ ++ ir_clk: ir_clk@01f01454 { ++ compatible = "allwinner,sun4i-a10-mod0-clk"; ++ reg = <0x01f01454 0x4>; ++ #clock-cells = <0>; ++ clocks = <&osc32k>, <&osc24M>; ++ clock-output-names = "ir"; ++ }; + }; + + soc { +@@ -472,7 +499,7 @@ + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; +- #interrupt-cells = <2>; ++ #interrupt-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PA4", "PA5"; +@@ -503,6 +530,16 @@ + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; ++ ++ mmc2_8bit_pins: mmc2_8bit { ++ allwinner,pins = "PC5", "PC6", "PC8", ++ "PC9", "PC10", "PC11", ++ "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ allwinner,function = "mmc2"; ++ allwinner,drive = <SUN4I_PINCTRL_30_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; + }; + + ahb_rst: reset@01c202c0 { +@@ -606,5 +643,40 @@ + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; ++ ++ apb0_reset: reset@01f014b0 { ++ reg = <0x01f014b0 0x4>; ++ compatible = "allwinner,sun6i-a31-clock-reset"; ++ #reset-cells = <1>; ++ }; ++ ++ ir: ir@01f02000 { ++ compatible = "allwinner,sun5i-a13-ir"; ++ clocks = <&apb0_gates 1>, <&ir_clk>; ++ clock-names = "apb", "ir"; ++ resets = <&apb0_reset 1>; ++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; ++ reg = <0x01f02000 0x40>; ++ status = "disabled"; ++ }; ++ ++ r_pio: pinctrl@01f02c00 { ++ compatible = "allwinner,sun8i-h3-r-pinctrl"; ++ reg = <0x01f02c00 0x400>; ++ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&apb0_gates 0>; ++ resets = <&apb0_reset 0>; ++ gpio-controller; ++ #gpio-cells = <3>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ ++ ir_pins_a: ir@0 { ++ allwinner,pins = "PL11"; ++ allwinner,function = "s_cir_rx"; ++ allwinner,drive = <SUN4I_PINCTRL_10_MA>; ++ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; ++ }; ++ }; + }; + }; diff --git a/target/linux/sunxi/profiles/orangepi_2.mk b/target/linux/sunxi/profiles/orangepi_2.mk new file mode 100644 index 0000000000..a398921879 --- /dev/null +++ b/target/linux/sunxi/profiles/orangepi_2.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2016 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/orangepi_2 + NAME:=orangepi_2 + PACKAGES:=\ + kmod-rtc-sunxi uboot-sunxi-orangepi_2 +endef + +define Profile/orangepi_2/Description + Package set optimized for the OrangePi 2 (H3) +endef + +$(eval $(call Profile,orangepi_2)) diff --git a/target/linux/zynq/config-4.4 b/target/linux/zynq/config-4.4 index f8e080d5f9..a011a33c5a 100644 --- a/target/linux/zynq/config-4.4 +++ b/target/linux/zynq/config-4.4 @@ -602,6 +602,7 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_SERIO=y CONFIG_SERIO_LIBPS2=y CONFIG_SERIO_SERPORT=y +CONFIG_XILINX_DEVCFG=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y CONFIG_SND=y diff --git a/target/linux/zynq/patches/100-dt-sync-dts-files-with-kernel.patch b/target/linux/zynq/patches/100-dt-sync-dts-files-with-kernel.patch new file mode 100644 index 0000000000..47959bd1db --- /dev/null +++ b/target/linux/zynq/patches/100-dt-sync-dts-files-with-kernel.patch @@ -0,0 +1,17 @@ +--- a/arch/arm/boot/dts/zynq-zed.dts ++++ b/arch/arm/boot/dts/zynq-zed.dts +@@ -32,10 +32,12 @@ + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; +- + usb_phy0: phy0 { +- compatible = "usb-nop-xceiv"; ++ compatible = "ulpi-phy"; + #phy-cells = <0>; ++ reg = <0xe0002000 0x1000>; ++ view-port = <0x0170>; ++ drv-vbus; + }; + }; + diff --git a/target/linux/zynq/patches/110-add-platform-driver-support-for-ulpi-phys.patch b/target/linux/zynq/patches/110-add-platform-driver-support-for-ulpi-phys.patch new file mode 100644 index 0000000000..b2eb6aa5b7 --- /dev/null +++ b/target/linux/zynq/patches/110-add-platform-driver-support-for-ulpi-phys.patch @@ -0,0 +1,146 @@ +--- a/drivers/usb/phy/Kconfig ++++ b/drivers/usb/phy/Kconfig +@@ -202,6 +202,7 @@ config USB_RCAR_PHY + config USB_ULPI + bool "Generic ULPI Transceiver Driver" + depends on ARM || ARM64 ++ depends on USB_PHY + select USB_ULPI_VIEWPORT + help + Enable this to support ULPI connected USB OTG transceivers which +--- a/drivers/usb/phy/phy-ulpi.c ++++ b/drivers/usb/phy/phy-ulpi.c +@@ -26,9 +26,16 @@ + #include <linux/kernel.h> + #include <linux/slab.h> + #include <linux/export.h> ++#include <linux/module.h> ++#include <linux/of.h> ++#include <linux/io.h> ++#include <linux/of_address.h> ++#include <linux/of_device.h> ++#include <linux/platform_device.h> + #include <linux/usb.h> + #include <linux/usb/otg.h> + #include <linux/usb/ulpi.h> ++#include <linux/usb/phy.h> + + + struct ulpi_info { +@@ -52,6 +59,13 @@ static struct ulpi_info ulpi_ids[] = { + ULPI_INFO(ULPI_ID(0x0451, 0x1507), "TI TUSB1210"), + }; + ++struct ulpi_phy { ++ struct usb_phy *usb_phy; ++ void __iomem *regs; ++ unsigned int vp_offset; ++ unsigned int flags; ++}; ++ + static int ulpi_set_otg_flags(struct usb_phy *phy) + { + unsigned int flags = ULPI_OTG_CTRL_DP_PULLDOWN | +@@ -253,6 +267,23 @@ static int ulpi_set_vbus(struct usb_otg + return usb_phy_io_write(phy, flags, ULPI_OTG_CTRL); + } + ++static int usbphy_set_vbus(struct usb_phy *phy, int on) ++{ ++ unsigned int flags = usb_phy_io_read(phy, ULPI_OTG_CTRL); ++ ++ flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT); ++ ++ if (on) { ++ if (phy->flags & ULPI_OTG_DRVVBUS) ++ flags |= ULPI_OTG_CTRL_DRVVBUS; ++ ++ if (phy->flags & ULPI_OTG_DRVVBUS_EXT) ++ flags |= ULPI_OTG_CTRL_DRVVBUS_EXT; ++ } ++ ++ return usb_phy_io_write(phy, flags, ULPI_OTG_CTRL); ++} ++ + struct usb_phy * + otg_ulpi_create(struct usb_phy_io_ops *ops, + unsigned int flags) +@@ -275,6 +306,7 @@ otg_ulpi_create(struct usb_phy_io_ops *o + phy->io_ops = ops; + phy->otg = otg; + phy->init = ulpi_init; ++ phy->set_vbus = usbphy_set_vbus; + + otg->usb_phy = phy; + otg->set_host = ulpi_set_host; +@@ -284,3 +316,70 @@ otg_ulpi_create(struct usb_phy_io_ops *o + } + EXPORT_SYMBOL_GPL(otg_ulpi_create); + ++static int ulpi_phy_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct resource *res; ++ struct ulpi_phy *uphy; ++ bool flag; ++ int ret; ++ ++ uphy = devm_kzalloc(&pdev->dev, sizeof(*uphy), GFP_KERNEL); ++ if (!uphy) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ uphy->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); ++ if (IS_ERR(uphy->regs)) ++ return PTR_ERR(uphy->regs); ++ ++ ret = of_property_read_u32(np, "view-port", &uphy->vp_offset); ++ if (IS_ERR(uphy->regs)) { ++ dev_err(&pdev->dev, "view-port register not specified\n"); ++ return PTR_ERR(uphy->regs); ++ } ++ ++ flag = of_property_read_bool(np, "drv-vbus"); ++ if (flag) ++ uphy->flags |= ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT; ++ ++ uphy->usb_phy = otg_ulpi_create(&ulpi_viewport_access_ops, uphy->flags); ++ ++ uphy->usb_phy->dev = &pdev->dev; ++ ++ uphy->usb_phy->io_priv = uphy->regs + uphy->vp_offset; ++ ++ ret = usb_add_phy_dev(uphy->usb_phy); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int ulpi_phy_remove(struct platform_device *pdev) ++{ ++ struct ulpi_phy *uphy = platform_get_drvdata(pdev); ++ ++ usb_remove_phy(uphy->usb_phy); ++ ++ return 0; ++} ++ ++static const struct of_device_id ulpi_phy_table[] = { ++ { .compatible = "ulpi-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, ulpi_phy_table); ++ ++static struct platform_driver ulpi_phy_driver = { ++ .probe = ulpi_phy_probe, ++ .remove = ulpi_phy_remove, ++ .driver = { ++ .name = "ulpi-phy", ++ .of_match_table = ulpi_phy_table, ++ }, ++}; ++module_platform_driver(ulpi_phy_driver); ++ ++MODULE_DESCRIPTION("ULPI PHY driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/zynq/patches/111-use-usb2-phy-for-zynq-platform.patch b/target/linux/zynq/patches/111-use-usb2-phy-for-zynq-platform.patch new file mode 100644 index 0000000000..356dd0f872 --- /dev/null +++ b/target/linux/zynq/patches/111-use-usb2-phy-for-zynq-platform.patch @@ -0,0 +1,13 @@ +--- a/drivers/usb/chipidea/ci_hdrc_usb2.c ++++ b/drivers/usb/chipidea/ci_hdrc_usb2.c +@@ -59,6 +59,10 @@ static int ci_hdrc_usb2_probe(struct pla + if (match && match->data) { + /* struct copy */ + *ci_pdata = *(struct ci_hdrc_platform_data *)match->data; ++ ci_pdata->usb_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", ++ 0); ++ if (IS_ERR(ci_pdata->usb_phy)) ++ return PTR_ERR(ci_pdata->usb_phy); + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); diff --git a/target/linux/zynq/patches/112-add-support-for-vbus-control-with-phy.patch b/target/linux/zynq/patches/112-add-support-for-vbus-control-with-phy.patch new file mode 100644 index 0000000000..5dca10032a --- /dev/null +++ b/target/linux/zynq/patches/112-add-support-for-vbus-control-with-phy.patch @@ -0,0 +1,62 @@ +--- a/drivers/usb/chipidea/ci_hdrc_usb2.c ++++ b/drivers/usb/chipidea/ci_hdrc_usb2.c +@@ -33,6 +33,7 @@ static const struct ci_hdrc_platform_dat + + static struct ci_hdrc_platform_data ci_zynq_pdata = { + .capoffset = DEF_CAPOFFSET, ++ .flags = CI_HDRC_PHY_VBUS_CONTROL, + }; + + static const struct of_device_id ci_hdrc_usb2_of_match[] = { +--- a/drivers/usb/chipidea/host.c ++++ b/drivers/usb/chipidea/host.c +@@ -66,6 +66,14 @@ static int ehci_ci_portpower(struct usb_ + } + } + ++ if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL && ++ ci->usb_phy && ci->usb_phy->set_vbus) { ++ if (enable) ++ ci->usb_phy->set_vbus(ci->usb_phy, 1); ++ else ++ ci->usb_phy->set_vbus(ci->usb_phy, 0); ++ } ++ + if (enable && (ci->platdata->phy_mode == USBPHY_INTERFACE_MODE_HSIC)) { + /* + * Marvell 28nm HSIC PHY requires forcing the port to HS mode. +--- a/drivers/usb/chipidea/otg_fsm.c ++++ b/drivers/usb/chipidea/otg_fsm.c +@@ -456,6 +456,11 @@ static void ci_otg_drv_vbus(struct otg_f + return; + } + } ++ ++ if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL && ++ ci->usb_phy && ci->usb_phy->set_vbus) ++ ci->usb_phy->set_vbus(ci->usb_phy, 1); ++ + /* Disable data pulse irq */ + hw_write_otgsc(ci, OTGSC_DPIE, 0); + +@@ -465,6 +470,10 @@ static void ci_otg_drv_vbus(struct otg_f + if (ci->platdata->reg_vbus) + regulator_disable(ci->platdata->reg_vbus); + ++ if (ci->platdata->flags & CI_HDRC_PHY_VBUS_CONTROL && ++ ci->usb_phy && ci->usb_phy->set_vbus) ++ ci->usb_phy->set_vbus(ci->usb_phy, 0); ++ + fsm->a_bus_drop = 1; + fsm->a_bus_req = 0; + } +--- a/include/linux/usb/chipidea.h ++++ b/include/linux/usb/chipidea.h +@@ -55,6 +55,7 @@ struct ci_hdrc_platform_data { + #define CI_HDRC_OVERRIDE_AHB_BURST BIT(9) + #define CI_HDRC_OVERRIDE_TX_BURST BIT(10) + #define CI_HDRC_OVERRIDE_RX_BURST BIT(11) ++#define CI_HDRC_PHY_VBUS_CONTROL BIT(12) + enum usb_dr_mode dr_mode; + #define CI_HDRC_CONTROLLER_RESET_EVENT 0 + #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 diff --git a/target/linux/zynq/patches/113-add-xilinx-devcfg-char-node.patch b/target/linux/zynq/patches/113-add-xilinx-devcfg-char-node.patch new file mode 100644 index 0000000000..9dddecb68d --- /dev/null +++ b/target/linux/zynq/patches/113-add-xilinx-devcfg-char-node.patch @@ -0,0 +1,2231 @@ +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -387,6 +387,13 @@ config XILINX_HWICAP + + If unsure, say N. + ++config XILINX_DEVCFG ++ tristate "Xilinx Device Configuration" ++ depends on ARCH_ZYNQ ++ help ++ This option enables support for the Xilinx device configuration driver. ++ If unsure, say N ++ + config R3964 + tristate "Siemens R3964 line discipline" + depends on TTY +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_GEN_RTC) += genrtc.o + obj-$(CONFIG_EFI_RTC) += efirtc.o + obj-$(CONFIG_DS1302) += ds1302.o + obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/ ++obj-$(CONFIG_XILINX_DEVCFG) += xilinx_devcfg.o + ifeq ($(CONFIG_GENERIC_NVRAM),y) + obj-$(CONFIG_NVRAM) += generic_nvram.o + else +--- /dev/null ++++ b/drivers/char/xilinx_devcfg.c +@@ -0,0 +1,2105 @@ ++/* ++ * Xilinx Zynq Device Config driver ++ * ++ * Copyright (c) 2011 - 2013 Xilinx Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++ ++#include <linux/cdev.h> ++#include <linux/clk.h> ++#include <linux/delay.h> ++#include <linux/dma-mapping.h> ++#include <linux/fs.h> ++#include <linux/init.h> ++#include <linux/interrupt.h> ++#include <linux/io.h> ++#include <linux/ioport.h> ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/mutex.h> ++#include <linux/of.h> ++#include <linux/platform_device.h> ++#include <linux/slab.h> ++#include <linux/string.h> ++#include <linux/sysctl.h> ++#include <linux/types.h> ++#include <linux/uaccess.h> ++ ++extern void zynq_slcr_init_preload_fpga(void); ++extern void zynq_slcr_init_postload_fpga(void); ++ ++#define DRIVER_NAME "xdevcfg" ++#define XDEVCFG_DEVICES 1 ++ ++/* An array, which is set to true when the device is registered. */ ++static DEFINE_MUTEX(xdevcfg_mutex); ++ ++/* Constant Definitions */ ++#define XDCFG_CTRL_OFFSET 0x00 /* Control Register */ ++#define XDCFG_LOCK_OFFSET 0x04 /* Lock Register */ ++#define XDCFG_INT_STS_OFFSET 0x0C /* Interrupt Status Register */ ++#define XDCFG_INT_MASK_OFFSET 0x10 /* Interrupt Mask Register */ ++#define XDCFG_STATUS_OFFSET 0x14 /* Status Register */ ++#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /* DMA Source Address Register */ ++#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /* DMA Destination Address Reg */ ++#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /* DMA Source Transfer Length */ ++#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /* DMA Destination Transfer */ ++#define XDCFG_UNLOCK_OFFSET 0x34 /* Unlock Register */ ++#define XDCFG_MCTRL_OFFSET 0x80 /* Misc. Control Register */ ++ ++/* Control Register Bit definitions */ ++#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /* Program signal to ++ * Reset FPGA */ ++#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /* Enable PCAP for PR */ ++#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /* Enable PCAP */ ++#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /* Enable PCAP Quad Rate */ ++#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /* AES Enable Mask */ ++#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /* SEU Enable Mask */ ++#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /* Secure Non Invasive ++ * Debug Enable */ ++#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /* Secure Invasive ++ * Debug Enable */ ++#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /* Non-Invasive Debug ++ * Enable */ ++#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /* Invasive Debug ++ * Enable */ ++#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /* DAP Enable Mask */ ++ ++/* Lock register bit definitions */ ++ ++#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /* Lock AES_EN update */ ++#define XDCFG_LOCK_SEU_MASK 0x00000004 /* Lock SEU_En update */ ++#define XDCFG_LOCK_DBG_MASK 0x00000001 /* This bit locks ++ * security config ++ * including: DAP_En, ++ * DBGEN,NIDEN, SPNIEN */ ++ ++/* Miscellaneous Control Register bit definitions */ ++#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /* Internal PCAP loopback */ ++ ++/* Status register bit definitions */ ++#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /* FPGA init status */ ++ ++/* Interrupt Status/Mask Register Bit definitions */ ++#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /* DMA Command Done */ ++#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /* DMA and PCAP Cmd Done */ ++#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /* FPGA programmed */ ++#define XDCFG_IXR_ERROR_FLAGS_MASK 0x00F0F860 ++#define XDCFG_IXR_ALL_MASK 0xF8F7F87F ++/* Miscellaneous constant values */ ++#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /* Invalid DMA address */ ++ ++static const char * const fclk_name[] = { ++ "fclk0", ++ "fclk1", ++ "fclk2", ++ "fclk3" ++}; ++#define NUMFCLKS ARRAY_SIZE(fclk_name) ++ ++/** ++ * struct xdevcfg_drvdata - Device Configuration driver structure ++ * ++ * @dev: Pointer to the device structure ++ * @cdev: Instance of the cdev structure ++ * @devt: Pointer to the dev_t structure ++ * @class: Pointer to device class ++ * @fclk_class: Pointer to fclk device class ++ * @dma_done: The dma_done status bit for the DMA command completion ++ * @error_status: The error status captured during the DMA transfer ++ * @irq: Interrupt number ++ * @clk: Peripheral clock for devcfg ++ * @fclk: Array holding references to the FPGA clocks ++ * @fclk_exported: Flag inidcating whether an FPGA clock is exported ++ * @is_open: The status bit to indicate whether the device is opened ++ * @sem: Instance for the mutex ++ * @lock: Instance of spinlock ++ * @base_address: The virtual device base address of the device registers ++ * @is_partial_bitstream: Status bit to indicate partial/full bitstream ++ */ ++struct xdevcfg_drvdata { ++ struct device *dev; ++ struct cdev cdev; ++ dev_t devt; ++ struct class *class; ++ struct class *fclk_class; ++ int irq; ++ struct clk *clk; ++ struct clk *fclk[NUMFCLKS]; ++ u8 fclk_exported[NUMFCLKS]; ++ volatile bool dma_done; ++ volatile int error_status; ++ bool is_open; ++ struct mutex sem; ++ spinlock_t lock; ++ void __iomem *base_address; ++ int ep107; ++ bool is_partial_bitstream; ++ bool endian_swap; ++ char residue_buf[3]; ++ int residue_len; ++}; ++ ++/** ++ * struct fclk_data - FPGA clock data ++ * @clk: Pointer to clock ++ * @enable: Flag indicating enable status of the clock ++ * @rate_rnd: Rate to be rounded for round rate operation ++ */ ++struct fclk_data { ++ struct clk *clk; ++ int enabled; ++ unsigned long rate_rnd; ++}; ++ ++/* Register read/write access routines */ ++#define xdevcfg_writereg(offset, val) __raw_writel(val, offset) ++#define xdevcfg_readreg(offset) __raw_readl(offset) ++ ++/** ++ * xdevcfg_reset_pl() - Reset the programmable logic. ++ * @base_address: The base address of the device. ++ * ++ * Must be called with PCAP clock enabled ++ */ ++static void xdevcfg_reset_pl(void __iomem *base_address) ++{ ++ /* ++ * Create a rising edge on PCFG_INIT. PCFG_INIT follows PCFG_PROG_B, ++ * so we need to * poll it after setting PCFG_PROG_B to make sure that ++ * the rising edge happens. ++ */ ++ xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET, ++ (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) | ++ XDCFG_CTRL_PCFG_PROG_B_MASK)); ++ while (!(xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) & ++ XDCFG_STATUS_PCFG_INIT_MASK)) ++ ; ++ ++ xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET, ++ (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) & ++ ~XDCFG_CTRL_PCFG_PROG_B_MASK)); ++ while (xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) & ++ XDCFG_STATUS_PCFG_INIT_MASK) ++ ; ++ ++ msleep(5); ++ xdevcfg_writereg(base_address + XDCFG_CTRL_OFFSET, ++ (xdevcfg_readreg(base_address + XDCFG_CTRL_OFFSET) | ++ XDCFG_CTRL_PCFG_PROG_B_MASK)); ++ while (!(xdevcfg_readreg(base_address + XDCFG_STATUS_OFFSET) & ++ XDCFG_STATUS_PCFG_INIT_MASK)) ++ ; ++} ++ ++/** ++ * xdevcfg_irq() - The main interrupt handler. ++ * @irq: The interrupt number. ++ * @data: Pointer to the driver data structure. ++ * returns: IRQ_HANDLED after the interrupt is handled. ++ **/ ++static irqreturn_t xdevcfg_irq(int irq, void *data) ++{ ++ u32 intr_status; ++ struct xdevcfg_drvdata *drvdata = data; ++ ++ spin_lock(&drvdata->lock); ++ ++ intr_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_INT_STS_OFFSET); ++ ++ /* Clear the interrupts */ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, ++ intr_status); ++ ++ if ((intr_status & XDCFG_IXR_D_P_DONE_MASK) == ++ XDCFG_IXR_D_P_DONE_MASK) ++ drvdata->dma_done = 1; ++ ++ if ((intr_status & XDCFG_IXR_ERROR_FLAGS_MASK) == ++ XDCFG_IXR_ERROR_FLAGS_MASK) ++ drvdata->error_status = 1; ++ ++ spin_unlock(&drvdata->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * xdevcfg_write() - The is the driver write function. ++ * ++ * @file: Pointer to the file structure. ++ * @buf: Pointer to the bitstream location. ++ * @count: The number of bytes to be written. ++ * @ppos: Pointer to the offset value ++ * returns: Success or error status. ++ **/ ++static ssize_t ++xdevcfg_write(struct file *file, const char __user *buf, size_t count, ++ loff_t *ppos) ++{ ++ char *kbuf; ++ int status; ++ unsigned long timeout; ++ u32 intr_reg, dma_len; ++ dma_addr_t dma_addr; ++ u32 transfer_length = 0; ++ struct xdevcfg_drvdata *drvdata = file->private_data; ++ size_t user_count = count; ++ int i; ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ status = mutex_lock_interruptible(&drvdata->sem); ++ ++ if (status) ++ goto err_clk; ++ ++ dma_len = count + drvdata->residue_len; ++ kbuf = dma_alloc_coherent(drvdata->dev, dma_len, &dma_addr, GFP_KERNEL); ++ if (!kbuf) { ++ status = -ENOMEM; ++ goto err_unlock; ++ } ++ ++ /* Collect stragglers from last time (0 to 3 bytes) */ ++ memcpy(kbuf, drvdata->residue_buf, drvdata->residue_len); ++ ++ /* Fetch user data, appending to stragglers */ ++ if (copy_from_user(kbuf + drvdata->residue_len, buf, count)) { ++ status = -EFAULT; ++ goto error; ++ } ++ ++ /* Include stragglers in total bytes to be handled */ ++ count += drvdata->residue_len; ++ ++ /* First block contains a header */ ++ if (*ppos == 0 && count > 4) { ++ /* Look for sync word */ ++ for (i = 0; i < count - 4; i++) { ++ if (memcmp(kbuf + i, "\x66\x55\x99\xAA", 4) == 0) { ++ pr_debug("Found normal sync word\n"); ++ drvdata->endian_swap = 0; ++ break; ++ } ++ if (memcmp(kbuf + i, "\xAA\x99\x55\x66", 4) == 0) { ++ pr_debug("Found swapped sync word\n"); ++ drvdata->endian_swap = 1; ++ break; ++ } ++ } ++ /* Remove the header, aligning the data on word boundary */ ++ if (i != count - 4) { ++ count -= i; ++ memmove(kbuf, kbuf + i, count); ++ } ++ } ++ ++ /* Save stragglers for next time */ ++ drvdata->residue_len = count % 4; ++ count -= drvdata->residue_len; ++ memcpy(drvdata->residue_buf, kbuf + count, drvdata->residue_len); ++ ++ /* Fixup endianess of the data */ ++ if (drvdata->endian_swap) { ++ for (i = 0; i < count; i += 4) { ++ u32 *p = (u32 *)&kbuf[i]; ++ *p = swab32(*p); ++ } ++ } ++ ++ /* Enable DMA and error interrupts */ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, ++ XDCFG_IXR_ALL_MASK); ++ ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, ++ (u32) (~(XDCFG_IXR_D_P_DONE_MASK | ++ XDCFG_IXR_ERROR_FLAGS_MASK))); ++ ++ drvdata->dma_done = 0; ++ drvdata->error_status = 0; ++ ++ /* Initiate DMA write command */ ++ if (count < 0x1000) ++ xdevcfg_writereg(drvdata->base_address + ++ XDCFG_DMA_SRC_ADDR_OFFSET, (u32)(dma_addr + 1)); ++ else ++ xdevcfg_writereg(drvdata->base_address + ++ XDCFG_DMA_SRC_ADDR_OFFSET, (u32) dma_addr); ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_ADDR_OFFSET, ++ (u32)XDCFG_DMA_INVALID_ADDRESS); ++ /* Convert number of bytes to number of words. */ ++ if (count % 4) ++ transfer_length = (count / 4 + 1); ++ else ++ transfer_length = count / 4; ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_LEN_OFFSET, ++ transfer_length); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_LEN_OFFSET, 0); ++ ++ timeout = jiffies + msecs_to_jiffies(1000); ++ ++ while (!drvdata->dma_done) { ++ if (time_after(jiffies, timeout)) { ++ status = -ETIMEDOUT; ++ goto error; ++ } ++ } ++ ++ if (drvdata->error_status) ++ status = drvdata->error_status; ++ ++ /* Disable the DMA and error interrupts */ ++ intr_reg = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_INT_MASK_OFFSET); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, ++ intr_reg | (XDCFG_IXR_D_P_DONE_MASK | ++ XDCFG_IXR_ERROR_FLAGS_MASK)); ++ ++ /* If we didn't write correctly, then bail out. */ ++ if (status) { ++ status = -EFAULT; ++ goto error; ++ } ++ ++ *ppos += user_count; ++ status = user_count; ++ ++error: ++ dma_free_coherent(drvdata->dev, dma_len, kbuf, dma_addr); ++err_unlock: ++ mutex_unlock(&drvdata->sem); ++err_clk: ++ clk_disable(drvdata->clk); ++ return status; ++} ++ ++ ++/** ++ * xdevcfg_read() - The is the driver read function. ++ * @file: Pointer to the file structure. ++ * @buf: Pointer to the bitstream location. ++ * @count: The number of bytes read. ++ * @ppos: Pointer to the offsetvalue ++ * returns: Success or error status. ++ */ ++static ssize_t ++xdevcfg_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) ++{ ++ u32 *kbuf; ++ int status; ++ unsigned long timeout; ++ dma_addr_t dma_addr; ++ struct xdevcfg_drvdata *drvdata = file->private_data; ++ u32 intr_reg; ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ status = mutex_lock_interruptible(&drvdata->sem); ++ if (status) ++ goto err_clk; ++ ++ /* Get new data from the ICAP, and return was requested. */ ++ kbuf = dma_alloc_coherent(drvdata->dev, count, &dma_addr, GFP_KERNEL); ++ if (!kbuf) { ++ status = -ENOMEM; ++ goto err_unlock; ++ } ++ ++ drvdata->dma_done = 0; ++ drvdata->error_status = 0; ++ ++ /* Enable DMA and error interrupts */ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, ++ XDCFG_IXR_ALL_MASK); ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, ++ (u32) (~(XDCFG_IXR_D_P_DONE_MASK | ++ XDCFG_IXR_ERROR_FLAGS_MASK))); ++ /* Initiate DMA read command */ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_ADDR_OFFSET, ++ (u32)XDCFG_DMA_INVALID_ADDRESS); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_ADDR_OFFSET, ++ (u32)dma_addr); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_SRC_LEN_OFFSET, 0); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_DMA_DEST_LEN_OFFSET, ++ count / 4); ++ ++ timeout = jiffies + msecs_to_jiffies(1000); ++ ++ while (!drvdata->dma_done) { ++ if (time_after(jiffies, timeout)) { ++ status = -ETIMEDOUT; ++ goto error; ++ } ++ } ++ ++ if (drvdata->error_status) ++ status = drvdata->error_status; ++ ++ /* Disable and clear DMA and error interrupts */ ++ intr_reg = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_INT_MASK_OFFSET); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_MASK_OFFSET, ++ intr_reg | (XDCFG_IXR_D_P_DONE_MASK | ++ XDCFG_IXR_ERROR_FLAGS_MASK)); ++ ++ ++ /* If we didn't read correctly, then bail out. */ ++ if (status) { ++ status = -EFAULT; ++ goto error; ++ } ++ ++ /* If we fail to return the data to the user, then bail out. */ ++ if (copy_to_user(buf, kbuf, count)) { ++ status = -EFAULT; ++ goto error; ++ } ++ ++ status = count; ++error: ++ dma_free_coherent(drvdata->dev, count, kbuf, dma_addr); ++err_unlock: ++ mutex_unlock(&drvdata->sem); ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++static void xdevcfg_enable_partial(struct xdevcfg_drvdata *drvdata) ++{ ++ u32 reg = xdevcfg_readreg(drvdata->base_address + XDCFG_CTRL_OFFSET); ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ reg | XDCFG_CTRL_PCAP_PR_MASK); ++} ++ ++static void xdevcfg_disable_partial(struct xdevcfg_drvdata *drvdata) ++{ ++ u32 reg = xdevcfg_readreg(drvdata->base_address + XDCFG_CTRL_OFFSET); ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ reg & ~XDCFG_CTRL_PCAP_PR_MASK); ++} ++ ++/** ++ * xdevcfg_open() - The is the driver open function. ++ * @inode: Pointer to the inode structure of this device. ++ * @file: Pointer to the file structure. ++ * returns: Success or error status. ++ */ ++static int xdevcfg_open(struct inode *inode, struct file *file) ++{ ++ struct xdevcfg_drvdata *drvdata; ++ int status; ++ ++ drvdata = container_of(inode->i_cdev, struct xdevcfg_drvdata, cdev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ status = mutex_lock_interruptible(&drvdata->sem); ++ if (status) ++ goto err_clk; ++ ++ if (drvdata->is_open) { ++ status = -EBUSY; ++ goto error; ++ } ++ ++ file->private_data = drvdata; ++ drvdata->is_open = 1; ++ drvdata->endian_swap = 0; ++ drvdata->residue_len= 0; ++ ++ /* ++ * If is_partial_bitstream is set, then PROG_B is not asserted ++ * (xdevcfg_reset_pl function) and also zynq_slcr_init_preload_fpga and ++ * zynq_slcr_init_postload_fpga functions are not invoked. ++ */ ++ if (drvdata->is_partial_bitstream) ++ xdevcfg_enable_partial(drvdata); ++ else ++ zynq_slcr_init_preload_fpga(); ++ ++ /* ++ * Only do the reset of the PL for Zynq as it causes problems on the ++ * EP107 and the issue is not understood, but not worth investigating ++ * as the emulation platform is very different than silicon and not a ++ * complete implementation. Also, do not reset if it is a partial ++ * bitstream. ++ */ ++ if ((!drvdata->ep107) && (!drvdata->is_partial_bitstream)) ++ xdevcfg_reset_pl(drvdata->base_address); ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_INT_STS_OFFSET, ++ XDCFG_IXR_PCFG_DONE_MASK); ++ ++error: ++ mutex_unlock(&drvdata->sem); ++err_clk: ++ clk_disable(drvdata->clk); ++ return status; ++} ++ ++/** ++ * xdevcfg_release() - The is the driver release function. ++ * @inode: Pointer to the inode structure of this device. ++ * @file: Pointer to the file structure. ++ * returns: Success. ++ */ ++static int xdevcfg_release(struct inode *inode, struct file *file) ++{ ++ struct xdevcfg_drvdata *drvdata = file->private_data; ++ ++ if (drvdata->is_partial_bitstream) ++ xdevcfg_disable_partial(drvdata); ++ else ++ zynq_slcr_init_postload_fpga(); ++ ++ ++ if (drvdata->residue_len) ++ printk("Did not transfer last %d bytes\n", ++ drvdata->residue_len); ++ ++ drvdata->is_open = 0; ++ ++ return 0; ++} ++ ++static const struct file_operations xdevcfg_fops = { ++ .owner = THIS_MODULE, ++ .write = xdevcfg_write, ++ .read = xdevcfg_read, ++ .open = xdevcfg_open, ++ .release = xdevcfg_release, ++}; ++ ++/* ++ * The following functions are the routines provided to the user to ++ * set/get the status bit value in the control/lock registers. ++ */ ++ ++/** ++ * xdevcfg_set_dap_en() - This function sets the DAP bits in the ++ * control register with the given value. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: negative error if the string could not be converted ++ * or the size of the buffer. ++ */ ++static ssize_t xdevcfg_set_dap_en(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ int status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_unlock; ++ ++ if (mask_bit > 7) { ++ status = -EINVAL; ++ goto err_unlock; ++ } ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | ++ (((u32)mask_bit) & XDCFG_CTRL_DAP_EN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_unlock: ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_dap_en_status() - The function returns the DAP_EN bits status in ++ * the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: Size of the buffer. ++ */ ++static ssize_t xdevcfg_show_dap_en_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 dap_en_status; ++ int status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ dap_en_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_DAP_EN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", dap_en_status); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_dap, 0644, xdevcfg_show_dap_en_status, ++ xdevcfg_set_dap_en); ++ ++/** ++ * xdevcfg_set_dbgen() - This function sets the DBGEN bit in the ++ * control register with the given value. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_dbgen(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ int status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | XDCFG_CTRL_DBGEN_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status & (~XDCFG_CTRL_DBGEN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_dbgen_status() - The function returns the DBGEN bit status in ++ * the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: Size of the buffer. ++ */ ++static ssize_t xdevcfg_show_dbgen_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 dbgen_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ dbgen_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_DBGEN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (dbgen_status >> 3)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_dbg_in, 0644, xdevcfg_show_dbgen_status, ++ xdevcfg_set_dbgen); ++ ++/** ++ * xdevcfg_set_niden() - This function sets the NIDEN bit in the ++ * control register with the given value. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_niden(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ int status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | XDCFG_CTRL_NIDEN_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status & (~XDCFG_CTRL_NIDEN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_niden_status() - The function returns the NIDEN bit status in ++ * the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: Size of the buffer. ++ */ ++static ssize_t xdevcfg_show_niden_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 niden_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ niden_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_NIDEN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (niden_status >> 4)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_dbg_nonin, 0644, xdevcfg_show_niden_status, ++ xdevcfg_set_niden); ++ ++/** ++ * xdevcfg_set_spiden() - This function sets the SPIDEN bit in the ++ * control register with the given value. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_spiden(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ int status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | XDCFG_CTRL_SPIDEN_MASK)); ++ else ++ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status & (~XDCFG_CTRL_SPIDEN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_spiden_status() - The function returns the SPIDEN bit status in ++ * the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: Size of the buffer. ++ */ ++static ssize_t xdevcfg_show_spiden_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 spiden_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ spiden_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SPIDEN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (spiden_status >> 5)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_sec_dbg_in, 0644, xdevcfg_show_spiden_status, ++ xdevcfg_set_spiden); ++ ++/** ++ * xdevcfg_set_spniden() - This function sets the SPNIDEN bit in the ++ * control register with the given value. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or the size of buffer ++ */ ++static ssize_t xdevcfg_set_spniden(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | XDCFG_CTRL_SPNIDEN_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status & (~XDCFG_CTRL_SPNIDEN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_spniden_status() - The function returns the SPNIDEN bit status ++ * in the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: Size of the buffer. ++ */ ++static ssize_t xdevcfg_show_spniden_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 spniden_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ spniden_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SPNIDEN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (spniden_status >> 6)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_sec_dbg_nonin, 0644, xdevcfg_show_spniden_status, ++ xdevcfg_set_spniden); ++ ++/** ++ * xdevcfg_set_seu() - This function sets the SEU_EN bit in the ++ * control register with the given value ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_seu(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | XDCFG_CTRL_SEU_EN_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status & (~XDCFG_CTRL_SEU_EN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_seu_status() - The function returns the SEU_EN bit status ++ * in the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_seu_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 seu_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ seu_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_SEU_EN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (seu_status > 8)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_seu, 0644, xdevcfg_show_seu_status, xdevcfg_set_seu); ++ ++/** ++ * xdevcfg_set_aes() - This function sets the AES_EN bits in the ++ * control register with either all 1s or all 0s. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ * ++ * The user must send only one bit in the buffer to notify whether he wants to ++ * either set or reset these bits. ++ */ ++static ssize_t xdevcfg_set_aes(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 ctrl_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ int status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ ctrl_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status < 0) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status | ++ XDCFG_CTRL_PCFG_AES_EN_MASK | ++ XDCFG_CTRL_PCAP_RATE_EN_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ++ (ctrl_reg_status & ++ ~(XDCFG_CTRL_PCFG_AES_EN_MASK | ++ XDCFG_CTRL_PCAP_RATE_EN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_aes_status() - The function returns the AES_EN bit status ++ * in the control register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_aes_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 aes_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ aes_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_CTRL_OFFSET) & XDCFG_CTRL_PCFG_AES_EN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (aes_status >> 9)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(enable_aes, 0644, xdevcfg_show_aes_status, xdevcfg_set_aes); ++ ++/** ++ * xdevcfg_set_aes_en_lock() - This function sets the LOCK_AES_EN bit in the ++ * lock register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_aes_en_lock(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 aes_en_lock_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ aes_en_lock_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_LOCK_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, ++ (aes_en_lock_status | XDCFG_LOCK_AES_EN_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, ++ (aes_en_lock_status & ++ (~XDCFG_LOCK_AES_EN_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_aes_en_lock_status() - The function returns the LOCK_AES_EN bit ++ * status in the lock register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_aes_en_lock_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 aes_en_lock_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ aes_en_lock_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_LOCK_OFFSET) & XDCFG_LOCK_AES_EN_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (aes_en_lock_status >> 3)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(aes_en_lock, 0644, xdevcfg_show_aes_en_lock_status, ++ xdevcfg_set_aes_en_lock); ++ ++/** ++ * xdevcfg_set_seu_lock() - This function sets the LOCK_SEU bit in the ++ * lock register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_seu_lock(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 seu_lock_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ seu_lock_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_LOCK_OFFSET); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, ++ (seu_lock_status | XDCFG_LOCK_SEU_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, ++ (seu_lock_status & (~XDCFG_LOCK_SEU_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_seu_lock_status() - The function returns the LOCK_SEU bit ++ * status in the lock register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_seu_lock_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 seu_lock_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ seu_lock_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_LOCK_OFFSET) & XDCFG_LOCK_SEU_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (seu_lock_status >> 2)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(seu_lock, 0644, xdevcfg_show_seu_lock_status, ++ xdevcfg_set_seu_lock); ++ ++/** ++ * xdevcfg_set_dbg_lock() - This function sets the LOCK_DBG bit in the ++ * lock register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_dbg_lock(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ u32 lock_reg_status; ++ unsigned long flags; ++ unsigned long mask_bit; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ lock_reg_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_LOCK_OFFSET); ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ goto err_clk; ++ ++ if (mask_bit > 1) { ++ status = -EINVAL; ++ goto err_clk; ++ } ++ ++ spin_lock_irqsave(&drvdata->lock, flags); ++ ++ if (mask_bit) ++ xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, ++ (lock_reg_status | XDCFG_LOCK_DBG_MASK)); ++ else ++ xdevcfg_writereg(drvdata->base_address + XDCFG_LOCK_OFFSET, ++ (lock_reg_status & (~XDCFG_LOCK_DBG_MASK))); ++ ++ spin_unlock_irqrestore(&drvdata->lock, flags); ++ ++ clk_disable(drvdata->clk); ++ ++ return size; ++ ++err_clk: ++ clk_disable(drvdata->clk); ++ ++ return status; ++} ++ ++/** ++ * xdevcfg_show_dbg_lock_status() - The function returns the LOCK_DBG bit ++ * status in the lock register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_dbg_lock_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 dbg_lock_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ dbg_lock_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_LOCK_OFFSET) & XDCFG_LOCK_DBG_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", dbg_lock_status); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(dbg_lock, 0644, xdevcfg_show_dbg_lock_status, ++ xdevcfg_set_dbg_lock); ++ ++/** ++ * xdevcfg_show_prog_done_status() - The function returns the PROG_DONE bit ++ * status in the interrupt status register. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_prog_done_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ u32 prog_done_status; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = clk_enable(drvdata->clk); ++ if (status) ++ return status; ++ ++ prog_done_status = xdevcfg_readreg(drvdata->base_address + ++ XDCFG_INT_STS_OFFSET) & XDCFG_IXR_PCFG_DONE_MASK; ++ ++ clk_disable(drvdata->clk); ++ ++ status = sprintf(buf, "%d\n", (prog_done_status >> 2)); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(prog_done, 0644, xdevcfg_show_prog_done_status, ++ NULL); ++ ++/** ++ * xdevcfg_set_is_partial_bitstream() - This function sets the ++ * is_partial_bitstream variable. If is_partial_bitstream is set, ++ * then PROG_B is not asserted (xdevcfg_reset_pl) and also ++ * zynq_slcr_init_preload_fpga and zynq_slcr_init_postload_fpga functions ++ * are not invoked. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * @size: The number of bytes used from the buffer ++ * returns: -EINVAL if invalid parameter is sent or size ++ */ ++static ssize_t xdevcfg_set_is_partial_bitstream(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ unsigned long mask_bit; ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = kstrtoul(buf, 10, &mask_bit); ++ ++ if (status) ++ return status; ++ ++ if (mask_bit > 1) ++ return -EINVAL; ++ ++ if (mask_bit) ++ drvdata->is_partial_bitstream = 1; ++ else ++ drvdata->is_partial_bitstream = 0; ++ ++ return size; ++} ++ ++/** ++ * xdevcfg_show_is_partial_bitstream_status() - The function returns the ++ * value of is_partial_bitstream variable. ++ * @dev: Pointer to the device structure. ++ * @attr: Pointer to the device attribute structure. ++ * @buf: Pointer to the buffer location for the configuration ++ * data. ++ * returns: size of the buffer. ++ */ ++static ssize_t xdevcfg_show_is_partial_bitstream_status(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ ssize_t status; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ status = sprintf(buf, "%d\n", drvdata->is_partial_bitstream); ++ ++ return status; ++} ++ ++static DEVICE_ATTR(is_partial_bitstream, 0644, ++ xdevcfg_show_is_partial_bitstream_status, ++ xdevcfg_set_is_partial_bitstream); ++ ++static const struct attribute *xdevcfg_attrs[] = { ++ &dev_attr_prog_done.attr, /* PCFG_DONE bit in Intr Status register */ ++ &dev_attr_dbg_lock.attr, /* Debug lock bit in Lock register */ ++ &dev_attr_seu_lock.attr, /* SEU lock bit in Lock register */ ++ &dev_attr_aes_en_lock.attr, /* AES EN lock bit in Lock register */ ++ &dev_attr_enable_aes.attr, /* AES EN bit in Control register */ ++ &dev_attr_enable_seu.attr, /* SEU EN bit in Control register */ ++ &dev_attr_enable_sec_dbg_nonin.attr, /*SPNIDEN bit in Control register*/ ++ &dev_attr_enable_sec_dbg_in.attr, /*SPIDEN bit in Control register */ ++ &dev_attr_enable_dbg_nonin.attr, /* NIDEN bit in Control register */ ++ &dev_attr_enable_dbg_in.attr, /* DBGEN bit in Control register */ ++ &dev_attr_enable_dap.attr, /* DAP_EN bits in Control register */ ++ &dev_attr_is_partial_bitstream.attr, /* Flag for partial bitstream */ ++ NULL, ++}; ++ ++ ++static const struct attribute_group xdevcfg_attr_group = { ++ .attrs = (struct attribute **) xdevcfg_attrs, ++}; ++ ++static ssize_t fclk_enable_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct fclk_data *pdata = dev_get_drvdata(dev); ++ ++ return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled); ++} ++ ++static ssize_t fclk_enable_store(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t count) ++{ ++ unsigned long enable; ++ int ret; ++ struct fclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &enable); ++ if (ret) ++ return -EINVAL; ++ ++ enable = !!enable; ++ if (enable == pdata->enabled) ++ return count; ++ ++ if (enable) ++ ret = clk_enable(pdata->clk); ++ else ++ clk_disable(pdata->clk); ++ ++ if (ret) ++ return ret; ++ ++ pdata->enabled = enable; ++ return count; ++} ++ ++static DEVICE_ATTR(enable, 0644, fclk_enable_show, fclk_enable_store); ++ ++static ssize_t fclk_set_rate_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct fclk_data *pdata = dev_get_drvdata(dev); ++ ++ return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->clk)); ++} ++ ++static ssize_t fclk_set_rate_store(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int ret = 0; ++ unsigned long rate; ++ struct fclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &rate); ++ if (ret) ++ return -EINVAL; ++ ++ rate = clk_round_rate(pdata->clk, rate); ++ ret = clk_set_rate(pdata->clk, rate); ++ ++ return ret ? ret : count; ++} ++ ++static DEVICE_ATTR(set_rate, 0644, fclk_set_rate_show, fclk_set_rate_store); ++ ++static ssize_t fclk_round_rate_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct fclk_data *pdata = dev_get_drvdata(dev); ++ ++ return scnprintf(buf, PAGE_SIZE, "%lu => %lu\n", pdata->rate_rnd, ++ clk_round_rate(pdata->clk, pdata->rate_rnd)); ++} ++ ++static ssize_t fclk_round_rate_store(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t count) ++{ ++ int ret = 0; ++ unsigned long rate; ++ struct fclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &rate); ++ if (ret) ++ return -EINVAL; ++ ++ pdata->rate_rnd = rate; ++ ++ return count; ++} ++ ++static DEVICE_ATTR(round_rate, 0644, fclk_round_rate_show, ++ fclk_round_rate_store); ++ ++static const struct attribute *fclk_ctrl_attrs[] = { ++ &dev_attr_enable.attr, ++ &dev_attr_set_rate.attr, ++ &dev_attr_round_rate.attr, ++ NULL, ++}; ++ ++static const struct attribute_group fclk_ctrl_attr_grp = { ++ .attrs = (struct attribute **)fclk_ctrl_attrs, ++}; ++ ++static ssize_t xdevcfg_fclk_export_store(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ int i, ret; ++ struct device *subdev; ++ struct fclk_data *fdata; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ for (i = 0; i < NUMFCLKS; i++) { ++ if (!strncmp(buf, fclk_name[i], strlen(fclk_name[i]))) ++ break; ++ } ++ ++ if (i < NUMFCLKS && !drvdata->fclk_exported[i]) { ++ drvdata->fclk_exported[i] = 1; ++ subdev = device_create(drvdata->fclk_class, dev, MKDEV(0, 0), ++ NULL, fclk_name[i]); ++ if (IS_ERR(subdev)) ++ return PTR_ERR(subdev); ++ ret = clk_prepare(drvdata->fclk[i]); ++ if (ret) ++ return ret; ++ fdata = kzalloc(sizeof(*fdata), GFP_KERNEL); ++ if (!fdata) { ++ ret = -ENOMEM; ++ goto err_unprepare; ++ } ++ fdata->clk = drvdata->fclk[i]; ++ dev_set_drvdata(subdev, fdata); ++ ret = sysfs_create_group(&subdev->kobj, &fclk_ctrl_attr_grp); ++ if (ret) ++ goto err_free; ++ } else { ++ return -EINVAL; ++ } ++ ++ return size; ++ ++err_free: ++ kfree(fdata); ++err_unprepare: ++ clk_unprepare(drvdata->fclk[i]); ++ ++ return ret; ++} ++ ++static ssize_t xdevcfg_fclk_export_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ int i; ++ ssize_t count = 0; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ for (i = 0; i < NUMFCLKS; i++) { ++ if (!drvdata->fclk_exported[i]) ++ count += scnprintf(buf + count, PAGE_SIZE - count, ++ "%s\n", fclk_name[i]); ++ } ++ return count; ++} ++ ++static DEVICE_ATTR(fclk_export, 0644, xdevcfg_fclk_export_show, ++ xdevcfg_fclk_export_store); ++ ++static int match_fclk(struct device *dev, const void *data) ++{ ++ struct fclk_data *fdata = dev_get_drvdata(dev); ++ ++ return fdata->clk == data; ++} ++ ++static ssize_t xdevcfg_fclk_unexport_store(struct device *dev, ++ struct device_attribute *attr, const char *buf, size_t size) ++{ ++ int i; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ for (i = 0; i < NUMFCLKS; i++) { ++ if (!strncmp(buf, fclk_name[i], strlen(fclk_name[i]))) ++ break; ++ } ++ ++ if (i < NUMFCLKS && drvdata->fclk_exported[i]) { ++ struct fclk_data *fdata; ++ struct device *subdev; ++ ++ drvdata->fclk_exported[i] = 0; ++ subdev = class_find_device(drvdata->fclk_class, NULL, ++ drvdata->fclk[i], match_fclk); ++ fdata = dev_get_drvdata(subdev); ++ if (fdata->enabled) ++ clk_disable(fdata->clk); ++ clk_unprepare(fdata->clk); ++ kfree(fdata); ++ device_unregister(subdev); ++ put_device(subdev); ++ } else { ++ return -EINVAL; ++ } ++ ++ return size; ++} ++ ++static ssize_t xdevcfg_fclk_unexport_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ int i; ++ ssize_t count = 0; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ for (i = 0; i < NUMFCLKS; i++) { ++ if (drvdata->fclk_exported[i]) ++ count += scnprintf(buf + count, PAGE_SIZE - count, ++ "%s\n", fclk_name[i]); ++ } ++ return count; ++} ++ ++static DEVICE_ATTR(fclk_unexport, 0644, xdevcfg_fclk_unexport_show, ++ xdevcfg_fclk_unexport_store); ++ ++static const struct attribute *fclk_exp_attrs[] = { ++ &dev_attr_fclk_export.attr, ++ &dev_attr_fclk_unexport.attr, ++ NULL, ++}; ++ ++static const struct attribute_group fclk_exp_attr_grp = { ++ .attrs = (struct attribute **)fclk_exp_attrs, ++}; ++ ++static void xdevcfg_fclk_init(struct device *dev) ++{ ++ int i; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ for (i = 0; i < NUMFCLKS; i++) { ++ drvdata->fclk[i] = clk_get(dev, fclk_name[i]); ++ if (IS_ERR(drvdata->fclk[i])) { ++ dev_warn(dev, "fclk not found\n"); ++ return; ++ } ++ } ++ ++ drvdata->fclk_class = class_create(THIS_MODULE, "fclk"); ++ if (IS_ERR(drvdata->fclk_class)) { ++ dev_warn(dev, "failed to create fclk class\n"); ++ return; ++ } ++ ++ if (sysfs_create_group(&dev->kobj, &fclk_exp_attr_grp)) ++ dev_warn(dev, "failed to create sysfs entries\n"); ++} ++ ++static void xdevcfg_fclk_remove(struct device *dev) ++{ ++ int i; ++ struct xdevcfg_drvdata *drvdata = dev_get_drvdata(dev); ++ ++ for (i = 0; i < NUMFCLKS; i++) { ++ if (drvdata->fclk_exported[i]) { ++ struct fclk_data *fdata; ++ struct device *subdev; ++ ++ drvdata->fclk_exported[i] = 0; ++ subdev = class_find_device(drvdata->fclk_class, NULL, ++ drvdata->fclk[i], match_fclk); ++ fdata = dev_get_drvdata(subdev); ++ if (fdata->enabled) ++ clk_disable(fdata->clk); ++ clk_unprepare(fdata->clk); ++ kfree(fdata); ++ device_unregister(subdev); ++ put_device(subdev); ++ ++ } ++ } ++ ++ class_destroy(drvdata->fclk_class); ++ sysfs_remove_group(&dev->kobj, &fclk_exp_attr_grp); ++ ++ return; ++} ++ ++/** ++ * xdevcfg_drv_probe - Probe call for the device. ++ * ++ * @pdev: handle to the platform device structure. ++ * Returns 0 on success, negative error otherwise. ++ * ++ * It does all the memory allocation and registration for the device. ++ */ ++static int xdevcfg_drv_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct xdevcfg_drvdata *drvdata; ++ dev_t devt; ++ int retval; ++ u32 ctrlreg; ++ struct device_node *np; ++ const void *prop; ++ int size; ++ struct device *dev; ++ ++ drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); ++ if (!drvdata) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ drvdata->base_address = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(drvdata->base_address)) ++ return PTR_ERR(drvdata->base_address); ++ ++ drvdata->irq = platform_get_irq(pdev, 0); ++ retval = devm_request_irq(&pdev->dev, drvdata->irq, &xdevcfg_irq, ++ 0, dev_name(&pdev->dev), drvdata); ++ if (retval) { ++ dev_err(&pdev->dev, "No IRQ available"); ++ return retval; ++ } ++ ++ platform_set_drvdata(pdev, drvdata); ++ spin_lock_init(&drvdata->lock); ++ mutex_init(&drvdata->sem); ++ drvdata->is_open = 0; ++ drvdata->is_partial_bitstream = 0; ++ drvdata->dma_done = 0; ++ drvdata->error_status = 0; ++ dev_info(&pdev->dev, "ioremap %pa to %p\n", ++ &res->start, drvdata->base_address); ++ ++ drvdata->clk = devm_clk_get(&pdev->dev, "ref_clk"); ++ if (IS_ERR(drvdata->clk)) { ++ dev_err(&pdev->dev, "input clock not found\n"); ++ return PTR_ERR(drvdata->clk); ++ } ++ ++ retval = clk_prepare_enable(drvdata->clk); ++ if (retval) { ++ dev_err(&pdev->dev, "unable to enable clock\n"); ++ return retval; ++ } ++ ++ /* ++ * Figure out from the device tree if this is running on the EP107 ++ * emulation platform as it doesn't match the silicon exactly and the ++ * driver needs to work accordingly. ++ */ ++ np = of_get_next_parent(pdev->dev.of_node); ++ np = of_get_next_parent(np); ++ prop = of_get_property(np, "compatible", &size); ++ ++ if (prop != NULL) { ++ if ((strcmp((const char *)prop, "xlnx,zynq-ep107")) == 0) ++ drvdata->ep107 = 1; ++ else ++ drvdata->ep107 = 0; ++ } ++ ++ /* Unlock the device */ ++ xdevcfg_writereg(drvdata->base_address + XDCFG_UNLOCK_OFFSET, ++ 0x757BDF0D); ++ ++ /* ++ * Set the configuration register with the following options ++ * - Reset FPGA ++ * - Enable the PCAP interface ++ * - Set the throughput rate for maximum speed ++ * - Set the CPU in user mode ++ */ ++ ctrlreg = xdevcfg_readreg(drvdata->base_address + XDCFG_CTRL_OFFSET); ++ ctrlreg &= ~XDCFG_CTRL_PCAP_PR_MASK; ++ ctrlreg |= XDCFG_CTRL_PCFG_PROG_B_MASK | XDCFG_CTRL_PCAP_MODE_MASK; ++ xdevcfg_writereg(drvdata->base_address + XDCFG_CTRL_OFFSET, ctrlreg); ++ ++ /* Ensure internal PCAP loopback is disabled */ ++ ctrlreg = xdevcfg_readreg(drvdata->base_address + XDCFG_MCTRL_OFFSET); ++ xdevcfg_writereg(drvdata->base_address + XDCFG_MCTRL_OFFSET, ++ (~XDCFG_MCTRL_PCAP_LPBK_MASK & ++ ctrlreg)); ++ ++ ++ retval = alloc_chrdev_region(&devt, 0, XDEVCFG_DEVICES, DRIVER_NAME); ++ if (retval < 0) ++ goto failed5; ++ ++ drvdata->devt = devt; ++ ++ cdev_init(&drvdata->cdev, &xdevcfg_fops); ++ drvdata->cdev.owner = THIS_MODULE; ++ retval = cdev_add(&drvdata->cdev, devt, 1); ++ if (retval) { ++ dev_err(&pdev->dev, "cdev_add() failed\n"); ++ goto failed6; ++ } ++ ++ drvdata->class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(drvdata->class)) { ++ dev_err(&pdev->dev, "failed to create class\n"); ++ goto failed6; ++ } ++ ++ dev = device_create(drvdata->class, &pdev->dev, devt, drvdata, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ dev_err(&pdev->dev, "unable to create device\n"); ++ goto failed7; ++ } ++ ++ /* create sysfs files for the device */ ++ retval = sysfs_create_group(&(pdev->dev.kobj), &xdevcfg_attr_group); ++ if (retval) { ++ dev_err(&pdev->dev, "Failed to create sysfs attr group\n"); ++ cdev_del(&drvdata->cdev); ++ goto failed8; ++ } ++ ++ xdevcfg_fclk_init(&pdev->dev); ++ ++ clk_disable(drvdata->clk); ++ ++ return 0; /* Success */ ++ ++failed8: ++ device_destroy(drvdata->class, drvdata->devt); ++failed7: ++ class_destroy(drvdata->class); ++failed6: ++ /* Unregister char driver */ ++ unregister_chrdev_region(devt, XDEVCFG_DEVICES); ++failed5: ++ clk_disable_unprepare(drvdata->clk); ++ ++ return retval; ++} ++ ++/** ++ * xdevcfg_drv_remove - Remove call for the device. ++ * ++ * @pdev: handle to the platform device structure. ++ * Returns 0 or error status. ++ * ++ * Unregister the device after releasing the resources. ++ */ ++static int xdevcfg_drv_remove(struct platform_device *pdev) ++{ ++ struct xdevcfg_drvdata *drvdata; ++ ++ drvdata = platform_get_drvdata(pdev); ++ ++ if (!drvdata) ++ return -ENODEV; ++ ++ unregister_chrdev_region(drvdata->devt, XDEVCFG_DEVICES); ++ ++ sysfs_remove_group(&pdev->dev.kobj, &xdevcfg_attr_group); ++ ++ xdevcfg_fclk_remove(&pdev->dev); ++ device_destroy(drvdata->class, drvdata->devt); ++ class_destroy(drvdata->class); ++ cdev_del(&drvdata->cdev); ++ clk_unprepare(drvdata->clk); ++ ++ return 0; /* Success */ ++} ++ ++static struct of_device_id xdevcfg_of_match[] = { ++ { .compatible = "xlnx,zynq-devcfg-1.0", }, ++ { /* end of table */} ++}; ++MODULE_DEVICE_TABLE(of, xdevcfg_of_match); ++ ++/* Driver Structure */ ++static struct platform_driver xdevcfg_platform_driver = { ++ .probe = xdevcfg_drv_probe, ++ .remove = xdevcfg_drv_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = DRIVER_NAME, ++ .of_match_table = xdevcfg_of_match, ++ }, ++}; ++ ++module_platform_driver(xdevcfg_platform_driver); ++ ++MODULE_AUTHOR("Xilinx, Inc"); ++MODULE_DESCRIPTION("Xilinx Device Config Driver"); ++MODULE_LICENSE("GPL"); +--- a/arch/arm/mach-zynq/common.h ++++ b/arch/arm/mach-zynq/common.h +@@ -33,6 +33,9 @@ extern int zynq_cpun_start(u32 address, + extern struct smp_operations zynq_smp_ops __initdata; + #endif + ++extern void zynq_slcr_init_preload_fpga(void); ++extern void zynq_slcr_init_postload_fpga(void); ++ + extern void __iomem *zynq_scu_base; + + void zynq_pm_late_init(void); +--- a/arch/arm/mach-zynq/slcr.c ++++ b/arch/arm/mach-zynq/slcr.c +@@ -24,10 +24,14 @@ + + /* register offsets */ + #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ ++ + #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ ++#define SLCR_FPGA_RST_CTRL_OFFSET 0x240 /* FPGA Software Reset Control */ + #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ + #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ + #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */ ++#define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */ ++#define SLCR_LVL_SHFTR_EN_OFFSET 0x900 /* Level Shifters Enable */ + + #define SLCR_UNLOCK_MAGIC 0xDF0D + #define SLCR_A9_CPU_CLKSTOP 0x10 +@@ -124,6 +128,35 @@ static struct notifier_block zynq_slcr_r + }; + + /** ++ * zynq_slcr_init_preload_fpga - Disable communication from the PL to PS. ++ */ ++void zynq_slcr_init_preload_fpga(void) ++{ ++ /* Assert FPGA top level output resets */ ++ zynq_slcr_write(0xF, SLCR_FPGA_RST_CTRL_OFFSET); ++ ++ /* Disable level shifters */ ++ zynq_slcr_write(0, SLCR_LVL_SHFTR_EN_OFFSET); ++ ++ /* Enable output level shifters */ ++ zynq_slcr_write(0xA, SLCR_LVL_SHFTR_EN_OFFSET); ++} ++EXPORT_SYMBOL(zynq_slcr_init_preload_fpga); ++ ++/** ++ * zynq_slcr_init_postload_fpga - Re-enable communication from the PL to PS. ++ */ ++void zynq_slcr_init_postload_fpga(void) ++{ ++ /* Enable level shifters */ ++ zynq_slcr_write(0xf, SLCR_LVL_SHFTR_EN_OFFSET); ++ ++ /* Deassert AXI interface resets */ ++ zynq_slcr_write(0, SLCR_FPGA_RST_CTRL_OFFSET); ++} ++EXPORT_SYMBOL(zynq_slcr_init_postload_fpga); ++ ++/** + * zynq_slcr_cpu_start - Start cpu + * @cpu: cpu number + */ +@@ -227,6 +260,9 @@ int __init zynq_early_slcr_init(void) + /* unlock the SLCR so that registers can be changed */ + zynq_slcr_unlock(); + ++ /* See AR#54190 design advisory */ ++ regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202); ++ + register_restart_handler(&zynq_slcr_restart_nb); + + pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); +--- a/arch/arm/boot/dts/zynq-7000.dtsi ++++ b/arch/arm/boot/dts/zynq-7000.dtsi +@@ -244,7 +244,7 @@ + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; +- fclk-enable = <0>; ++ fclk-enable = <0xf>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", +@@ -296,8 +296,8 @@ + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; +- clocks = <&clkc 12>; +- clock-names = "ref_clk"; ++ clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; ++ clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; + syscon = <&slcr>; + }; + |