From 0c1e8630dca36c2d5a9bf98a5f1f8c15f75d0253 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 12 Aug 2013 18:11:33 +0200 Subject: [PATCH 20/57] MIPS: ralink: update dts files Add the devicetree nodes needed to make the newly merged drivers work. Signed-off-by: John Crispin --- arch/mips/ralink/dts/mt7620a.dtsi | 135 +++++++++++++++++++++++ arch/mips/ralink/dts/rt3050.dtsi | 156 ++++++++++++++++++++++++++ arch/mips/ralink/dts/rt3883.dtsi | 219 +++++++++++++++++++++++++++++++++++++ 3 files changed, 510 insertions(+) diff --git a/arch/mips/ralink/dts/mt7620a.dtsi b/arch/mips/ralink/dts/mt7620a.dtsi index 08bf24f..df6cb79 100644 --- a/arch/mips/ralink/dts/mt7620a.dtsi +++ b/arch/mips/ralink/dts/mt7620a.dtsi @@ -29,10 +29,32 @@ reg = <0x0 0x100>; }; + timer@100 { + compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer"; + reg = <0x100 0x20>; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + + watchdog@120 { + compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt"; + reg = <0x120 0x10>; + + resets = <&rstctrl 8>; + reset-names = "wdt"; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + intc: intc@200 { compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; reg = <0x200 0x100>; + resets = <&rstctrl 19>; + reset-names = "intc"; + interrupt-controller; #interrupt-cells = <1>; @@ -43,16 +65,129 @@ memc@300 { compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; + + resets = <&rstctrl 20>; + reset-names = "mc"; + + interrupt-parent = <&intc>; + interrupts = <3>; + }; + + uart@500 { + compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0x500 0x100>; + + resets = <&rstctrl 12>; + reset-names = "uart"; + + interrupt-parent = <&intc>; + interrupts = <5>; + + reg-shift = <2>; + + status = "disabled"; + }; + + gpio0: gpio@600 { + compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; + reg = <0x600 0x34>; + + resets = <&rstctrl 13>; + reset-names = "pio"; + + interrupt-parent = <&intc>; + interrupts = <6>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <0>; + ralink,num-gpios = <24>; + ralink,register-map = [ 00 04 08 0c + 20 24 28 2c + 30 34 ]; + + status = "disabled"; + }; + + gpio1: gpio@638 { + compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; + reg = <0x638 0x24>; + + interrupt-parent = <&intc>; + interrupts = <6>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <24>; + ralink,num-gpios = <16>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + gpio2: gpio@660 { + compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; + reg = <0x660 0x24>; + + interrupt-parent = <&intc>; + interrupts = <6>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <40>; + ralink,num-gpios = <32>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + spi@b00 { + compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi"; + reg = <0xb00 0x100>; + + resets = <&rstctrl 18>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; }; uartlite@c00 { compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + resets = <&rstctrl 19>; + reset-names = "uartl"; + interrupt-parent = <&intc>; interrupts = <12>; reg-shift = <2>; }; + + systick@d00 { + compatible = "ralink,mt7620a-systick", "ralink,cevt-systick"; + reg = <0xd00 0x10>; + + resets = <&rstctrl 28>; + reset-names = "intc"; + + interrupt-parent = <&cpuintc>; + interrupts = <7>; + }; + }; + + rstctrl: rstctrl { + compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; + #reset-cells = <1>; }; }; diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi index e3203d4..49622d7 100644 --- a/arch/mips/ralink/dts/rt3050.dtsi +++ b/arch/mips/ralink/dts/rt3050.dtsi @@ -9,6 +9,10 @@ }; }; + chosen { + bootargs = "console=ttyS0,57600"; + }; + cpuintc: cpuintc@0 { #address-cells = <0>; #interrupt-cells = <1>; @@ -29,10 +33,32 @@ reg = <0x0 0x100>; }; + timer@100 { + compatible = "ralink,rt3052-timer", "ralink,rt2880-timer"; + reg = <0x100 0x20>; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + + watchdog@120 { + compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt"; + reg = <0x120 0x10>; + + resets = <&rstctrl 8>; + reset-names = "wdt"; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + intc: intc@200 { compatible = "ralink,rt3052-intc", "ralink,rt2880-intc"; reg = <0x200 0x100>; + resets = <&rstctrl 19>; + reset-names = "intc"; + interrupt-controller; #interrupt-cells = <1>; @@ -43,17 +69,144 @@ memc@300 { compatible = "ralink,rt3052-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; + + resets = <&rstctrl 20>; + reset-names = "mc"; + + interrupt-parent = <&intc>; + interrupts = <3>; + }; + + uart@500 { + compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0x500 0x100>; + + resets = <&rstctrl 12>; + reset-names = "uart"; + + interrupt-parent = <&intc>; + interrupts = <5>; + + reg-shift = <2>; + + status = "disabled"; + }; + + gpio0: gpio@600 { + compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio"; + reg = <0x600 0x34>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <0>; + ralink,num-gpios = <24>; + ralink,register-map = [ 00 04 08 0c + 20 24 28 2c + 30 34 ]; + + resets = <&rstctrl 13>; + reset-names = "pio"; + + interrupt-parent = <&intc>; + interrupts = <6>; + + status = "disabled"; + }; + + gpio1: gpio@638 { + compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio"; + reg = <0x638 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <24>; + ralink,num-gpios = <16>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + gpio2: gpio@660 { + compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio"; + reg = <0x660 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <40>; + ralink,num-gpios = <12>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + spi@b00 { + compatible = "ralink,rt3050-spi", "ralink,rt2880-spi"; + reg = <0xb00 0x100>; + + resets = <&rstctrl 18>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; }; uartlite@c00 { compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + resets = <&rstctrl 19>; + reset-names = "uartl"; + interrupt-parent = <&intc>; interrupts = <12>; reg-shift = <2>; }; + + }; + + rstctrl: rstctrl { + compatible = "ralink,rt3050-reset", "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + ethernet@10100000 { + compatible = "ralink,rt3050-eth"; + reg = <0x10100000 10000>; + + interrupt-parent = <&cpuintc>; + interrupts = <5>; + + status = "disabled"; + }; + + esw@10110000 { + compatible = "ralink,rt3050-esw"; + reg = <0x10110000 8000>; + + interrupt-parent = <&intc>; + interrupts = <17>; + + status = "disabled"; + }; + + wmac@10180000 { + compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac"; + reg = <0x10180000 40000>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + status = "disabled"; }; usb@101c0000 { @@ -63,6 +216,9 @@ interrupt-parent = <&intc>; interrupts = <18>; + resets = <&rstctrl 22>; + reset-names = "otg"; + status = "disabled"; }; }; diff --git a/arch/mips/ralink/dts/rt3883.dtsi b/arch/mips/ralink/dts/rt3883.dtsi index 3b131dd..4d092b1 100644 --- a/arch/mips/ralink/dts/rt3883.dtsi +++ b/arch/mips/ralink/dts/rt3883.dtsi @@ -29,10 +29,32 @@ reg = <0x0 0x100>; }; + timer@100 { + compatible = "ralink,rt3883-timer", "ralink,rt2880-timer"; + reg = <0x100 0x20>; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + + watchdog@120 { + compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt"; + reg = <0x120 0x10>; + + resets = <&rstctrl 8>; + reset-names = "wdt"; + + interrupt-parent = <&intc>; + interrupts = <1>; + }; + intc: intc@200 { compatible = "ralink,rt3883-intc", "ralink,rt2880-intc"; reg = <0x200 0x100>; + resets = <&rstctrl 19>; + reset-names = "intc"; + interrupt-controller; #interrupt-cells = <1>; @@ -43,16 +65,213 @@ memc@300 { compatible = "ralink,rt3883-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; + + resets = <&rstctrl 20>; + reset-names = "mc"; + + interrupt-parent = <&intc>; + interrupts = <3>; + }; + + uart@500 { + compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0x500 0x100>; + + resets = <&rstctrl 12>; + reset-names = "uart"; + + interrupt-parent = <&intc>; + interrupts = <5>; + + reg-shift = <2>; + + status = "disabled"; + }; + + gpio0: gpio@600 { + compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; + reg = <0x600 0x34>; + + resets = <&rstctrl 13>; + reset-names = "pio"; + + interrupt-parent = <&intc>; + interrupts = <6>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <0>; + ralink,num-gpios = <24>; + ralink,register-map = [ 00 04 08 0c + 20 24 28 2c + 30 34 ]; + + status = "disabled"; + }; + + gpio1: gpio@638 { + compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; + reg = <0x638 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <24>; + ralink,num-gpios = <16>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + gpio2: gpio@660 { + compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; + reg = <0x660 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <40>; + ralink,num-gpios = <32>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + gpio3: gpio@688 { + compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio"; + reg = <0x688 0x24>; + + gpio-controller; + #gpio-cells = <2>; + + ralink,gpio-base = <72>; + ralink,num-gpios = <24>; + ralink,register-map = [ 00 04 08 0c + 10 14 18 1c + 20 24 ]; + + status = "disabled"; + }; + + spi0: spi@b00 { + compatible = "ralink,rt3883-spi", "ralink,rt2880-spi"; + reg = <0xb00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + resets = <&rstctrl 18>; + reset-names = "spi"; + + status = "disabled"; }; uartlite@c00 { compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + resets = <&rstctrl 19>; + reset-names = "uartl"; + interrupt-parent = <&intc>; interrupts = <12>; reg-shift = <2>; }; }; + + rstctrl: rstctrl { + compatible = "ralink,rt3883-reset", "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + + pci@10140000 { + compatible = "ralink,rt3883-pci"; + reg = <0x10140000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; /* direct mapping */ + + status = "disabled"; + + pciintc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <4>; + }; + + host-bridge { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + device_type = "pci"; + + bus-range = <0 255>; + ranges = < + 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ + 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ + >; + + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 17 */ + 0x8800 0 0 1 &pciintc 18 + 0x8800 0 0 2 &pciintc 18 + 0x8800 0 0 3 &pciintc 18 + 0x8800 0 0 4 &pciintc 18 + /* IDSEL 18 */ + 0x9000 0 0 1 &pciintc 19 + 0x9000 0 0 2 &pciintc 19 + 0x9000 0 0 3 &pciintc 19 + 0x9000 0 0 4 &pciintc 19 + >; + + pci-bridge@1 { + reg = <0x0800 0 0 0 0>; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + status = "disabled"; + + ralink,pci-slot = <1>; + + interrupt-map-mask = <0x0 0 0 0>; + interrupt-map = <0x0 0 0 0 &pciintc 20>; + }; + + pci-slot@17 { + reg = <0x8800 0 0 0 0>; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ralink,pci-slot = <17>; + + status = "disabled"; + }; + + pci-slot@18 { + reg = <0x9000 0 0 0 0>; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + ralink,pci-slot = <18>; + + status = "disabled"; + }; + }; + }; }; -- 1.7.10.4