From b2ef79004dd8e26f3a4625610bff5362b70e956b Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 28 Jul 2013 18:06:39 +0200 Subject: [PATCH 14/31] MTD: lantiq: xway: the latched command should be persistent Signed-off-by: John Crispin --- drivers/mtd/nand/xway_nand.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c index 169a91d..7f2bdd1 100644 --- a/drivers/mtd/nand/xway_nand.c +++ b/drivers/mtd/nand/xway_nand.c @@ -54,6 +54,8 @@ #define NAND_CON_CSMUX (1 << 1) #define NAND_CON_NANDM 1 +static u32 xway_latchcmd; + static void xway_reset_chip(struct nand_chip *chip) { unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; @@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) unsigned long flags; if (ctrl & NAND_CTRL_CHANGE) { - nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR); if (ctrl & NAND_CLE) - nandaddr |= NAND_WRITE_CMD; - else - nandaddr |= NAND_WRITE_ADDR; - this->IO_ADDR_W = (void __iomem *) nandaddr; + xway_latchcmd = NAND_WRITE_CMD; + else if (ctrl & NAND_ALE) + xway_latchcmd = NAND_WRITE_ADDR; } if (cmd != NAND_CMD_NONE) { spin_lock_irqsave(&ebu_lock, flags); - writeb(cmd, this->IO_ADDR_W); + writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd)); while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) ; spin_unlock_irqrestore(&ebu_lock, flags); -- 1.7.10.4