From 55fb6f3a05deb4a8b5e600cc10bae9555a9f90be Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 23 Jun 2013 15:50:49 +0000 Subject: ralink: update patches Signed-off-by: John Crispin SVN-Revision: 37016 --- ...3-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 target/linux/ramips/patches-3.9/0163-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch (limited to 'target/linux/ramips/patches-3.9/0163-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch') diff --git a/target/linux/ramips/patches-3.9/0163-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch b/target/linux/ramips/patches-3.9/0163-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch new file mode 100644 index 0000000000..f7f6d32a68 --- /dev/null +++ b/target/linux/ramips/patches-3.9/0163-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch @@ -0,0 +1,48 @@ +From 7bb04eed36ee0b2f3148fc33db7f75d9b4c8548c Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 24 May 2013 21:28:08 +0200 +Subject: [PATCH 163/164] USB: MIPS: ralink: fix usb issue on mt7620 + +USB fails when frequency scaling is enabled. Increase the idle cpu speed when +scaled. + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-ralink/mt7620.h | 1 + + arch/mips/ralink/mt7620.c | 8 ++++++++ + 2 files changed, 9 insertions(+) + +diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h +index 9809972..d469c69 100644 +--- a/arch/mips/include/asm/mach-ralink/mt7620.h ++++ b/arch/mips/include/asm/mach-ralink/mt7620.h +@@ -20,6 +20,7 @@ + #define SYSC_REG_CHIP_REV 0x0c + #define SYSC_REG_SYSTEM_CONFIG0 0x10 + #define SYSC_REG_SYSTEM_CONFIG1 0x14 ++#define SYSC_REG_CPU_SYS_CLKCFG 0x3c + #define SYSC_REG_CPLL_CONFIG0 0x54 + #define SYSC_REG_CPLL_CONFIG1 0x58 + +diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c +index 4956d96..d76eb85 100644 +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -186,6 +186,14 @@ void __init ralink_clk_init(void) + ralink_clk_add("10000500.uart", 40000000); + ralink_clk_add("10000b00.spi", 40000000); + ralink_clk_add("10000c00.uartlite", 40000000); ++ ++#ifdef CONFIG_USB ++ /* ++ * When the CPU goes into sleep mode, the BUS clock will be too low for ++ * USB to function properly ++ */ ++ rt_sysc_m32(0x1f1f, 0x303, SYSC_REG_CPU_SYS_CLKCFG); ++#endif + } + + void __init ralink_of_remap(void) +-- +1.7.10.4 + -- cgit v1.2.3