From 271a348cda0688e41ee54d5d246a4b4674b4dc81 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sun, 17 Jan 2016 11:16:52 +0000 Subject: mpc85xx: Add PTP node for TL-WD4900 in device tree PTP requires at least one timer to be 1PPS so describe it. For testing, load kernel module gianfar_ptp and use ptp4l from linuxptp. Copied from FSL P1010RDB reference design. Signed-off-by: Wojciech Dubowik SVN-Revision: 48275 --- .../mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'target/linux/mpc85xx') diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts index 0d79dc0db2..2325006172 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts @@ -145,6 +145,19 @@ can1: can@1d000 { status = "disabled"; }; + + ptp_clock@b0e00 { + compatible = "fsl,etsec-ptp"; + reg = <0xb0e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; + fsl,cksel = <1>; + fsl,tclk-period = <5>; + fsl,tmr-prsc = <2>; + fsl,tmr-add = <0xcccccccd>; + fsl,tmr-fiper1 = <0x3b9ac9fb>; /* 1PPS */ + fsl,tmr-fiper2 = <0x00018696>; + fsl,max-adj = <249999999>; + }; }; pci0: pcie@ffe09000 { -- cgit v1.2.3