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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 47215
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kernel lock debugging unveiled that we should not call
of_reset_control_get inside a clock's enable operation (see below)
move of_reset_control_* previously used in pllb_clk_enable to new
pllb_clk_prepare and pllb_clk_unprepare functions.
use a container to carry runtime information.
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2742 lockdep_trace_alloc+0xb8/0xfc()
DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.26 #6
[<c001a6ac>] (unwind_backtrace) from [<c0016dec>] (show_stack+0x10/0x14)
[<c0016dec>] (show_stack) from [<c0194f68>] (dump_stack+0x7c/0x94)
[<c0194f68>] (dump_stack) from [<c0021b50>] (warn_slowpath_common+0x68/0x8c)
[<c0021b50>] (warn_slowpath_common) from [<c0021ba4>] (warn_slowpath_fmt+0x30/0x40)
[<c0021ba4>] (warn_slowpath_fmt) from [<c0061b30>] (lockdep_trace_alloc+0xb8/0xfc)
[<c0061b30>] (lockdep_trace_alloc) from [<c00cb740>] (kmem_cache_alloc+0x1c/0xf8)
[<c00cb740>] (kmem_cache_alloc) from [<c01d33c8>] (of_reset_control_get+0xe8/0x12c)
[<c01d33c8>] (of_reset_control_get) from [<c0269228>] (pllb_clk_enable+0x14/0xbc)
[<c0269228>] (pllb_clk_enable) from [<c0265738>] (__clk_enable+0x54/0xa0)
[<c0265738>] (__clk_enable) from [<c0265acc>] (clk_enable+0x18/0x2c)
[<c0265acc>] (clk_enable) from [<c04325f8>] (oxnas_pcie_probe+0x3b8/0x6a0)
[<c04325f8>] (oxnas_pcie_probe) from [<c01f2510>] (platform_drv_probe+0x18/0x48)
[<c01f2510>] (platform_drv_probe) from [<c01f1070>] (driver_probe_device+0xd8/0x24c)
[<c01f1070>] (driver_probe_device) from [<c01f1298>] (__driver_attach+0x70/0x94)
[<c01f1298>] (__driver_attach) from [<c01ef728>] (bus_for_each_dev+0x4c/0x98)
[<c01ef728>] (bus_for_each_dev) from [<c01f0818>] (bus_add_driver+0xcc/0x1e8)
[<c01f0818>] (bus_add_driver) from [<c01f169c>] (driver_register+0xa0/0xe8)
[<c01f169c>] (driver_register) from [<c01f2568>] (platform_driver_probe+0x20/0xa4)
[<c01f2568>] (platform_driver_probe) from [<c0013a3c>] (do_one_initcall+0x90/0x140)
[<c0013a3c>] (do_one_initcall) from [<c0421d38>] (kernel_init_freeable+0x1e4/0x2c0)
[<c0421d38>] (kernel_init_freeable) from [<c000c214>] (kernel_init+0x8/0x104)
[<c000c214>] (kernel_init) from [<c0008768>] (ret_from_fork+0x14/0x2c)
---[ end trace 5f17ed2f61e0683f ]---
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43787
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This is the oxnas target previously developed at
http://gitorious.org/openwrt-oxnas
Basically, this consolidates the changes and addtionas from
http://github.org/kref/linux-oxnas
into a new OpenWrt hardware target 'oxnas' adding support for
PLX Technology NAS7820/NAS7821/NAS7825/...
formally known as
Oxford Semiconductor OXE810SE/OXE815/OX820/...
For now there are 4 supported boards:
Cloud Engines Pogoplug V3 (without PCIe)
fully supported
Cloud Engines Pogoplug Pro (with PCIe)
fully supported
MitraStar STG-212
aka ZyXEL NSA-212,
aka Medion Akoya P89625 / P89636 / P89626 / P89630,
aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587
fully supported, see http://wiki.openwrt.org/toh/medion/md86587
Shuttle KD-20
partially supported (S-ATA driver lacks support for 2nd port)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43388
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