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Replace former uci-defaults.sh implementation with the uci-defaults-new.sh one
and update all users accordingly.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 47867
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Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 47744
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This removes calls to ucidef_set_interfaces_lan_wan() and
ucidef_set_interfaces_lan() on boards where all relevant info can be
inferred from the switch definition.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 47722
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This changes uci-defaults-new.sh, config_generate and all relevant board.d
files in order combine ucidef_add_switch() and ucidef_add_switch_ports() into
a single function.
Also removes now superfluous enable and reset arguments.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 47721
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Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
SVN-Revision: 47692
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According to the info from NVRAM we should use port 8 for the CPU (and
interface eth2). Unfortunately it doesn't work right now, so lets switch
to the port 5.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Forwardport of r46586 from 15.05
SVN-Revision: 47281
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This device seems to have switch port 7 connected to the CPU:
vlan1ports=1 2 3 5 7*
vlan2ports=0 7u
it should be handled by eth1 and NVRAM seems to confirm that (no
et0macaddr entry, existing et1macaddr & et1phyaddr entries).
One of the remaining ports (4/8?) may be connected to the Quantenna SoC.
Original firmware boot log contains following messages:
(0x00,0x5d)Port 5 States Override: 0xfb
(0x00,0x5f)Port 7 States Override: 0xfb
(0x00,0x0e)Port 8 States Override: 0x0a
(why does it force port 5 state?!)
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45692
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It has 3 Ethernet interfaces, each of them connected to separated switch
port. Default NVRAM uses switch port 8 as CPU which is connected to the
3rd interface (eth2).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45681
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Some devices have unsorted ports which may lead to broken config.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45575
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45458
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It seems to have few ports connected to CPU (only for CPU sending data?)
as part of "SMP dual core 3 GMAC setup" feature.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45403
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 43754
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This new argument is used right after starting regular preinit (which
happens if failsafe wasn't triggered). The main purpose of "preinit"
argument is to indicate that failsafe can be triggered, however we were
missing a way to inform user that we don't wait for a trigger anymore.
With this change it's clear when failsafe mode can be triggered.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 43715
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 43639
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Without running fixtrx the image will not boot at the second time,
because the CRC the boot loader check is invalid at that time.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 42639
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This scripts adds a default config for the switch.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 40565
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