| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ar71xx: use correct fractional dividers for {CPU,DDR}_PLL on QCA955x | Gabor Juhos | 2012-09-10 | 1 | -2/+2 |
| | | | | | SVN-Revision: 33362 | ||||
| * | ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x | Gabor Juhos | 2012-09-08 | 1 | -6/+6 |
| | | | | | SVN-Revision: 33335 | ||||
| * | ar71xx: add initial support for the QCA955X SoCs | Gabor Juhos | 2012-07-05 | 1 | -0/+167 |
| SVN-Revision: 32606 | |||||
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index : openwrt/em-br6478acv2/lede/master-31e0f0ae | |
| Edimax BR-6578AC V2 base from https://github.com/ulli-kroll/lede.git | James |
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path: root/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch